JP5842255B2 - Apparatus and method for generating logic circuit from logic circuit description in programming language - Google Patents

Description

  The present invention relates to a method for synthesizing a semiconductor integrated circuit, and more specifically, to an apparatus and method for synthesizing a logic circuit from a logic circuit description described using a programming language.

  Conventionally, in designing a logic circuit of an LSI (Large Scale Integrated Circuit), the design is performed with RTL (Register Transfer Level) description and data flow control is performed using a state transition diagram. RTL represents the abstraction level of logic circuit design, and RTL description is a kind of description method based on a hardware description language (HDL, Hardware Description Language) that describes the structure and operation of hardware. is there. In RTL, the flow of data is described in register units. The HDL source code described in RTL is converted into a logic gate level circuit description using software called a logic synthesis tool.

When designing a logic circuit using a state transition diagram, it is necessary to manually verify the flow of state transition after creating the state transition diagram. Therefore, when designing a logic circuit that requires complex data flow control, such as a high-performance LSI, such as for image processing applications, it may be due to omission of verification when verifying the flow of state transitions, bugs, etc. There is a problem that design quality is likely to deteriorate.
Therefore, in recent years, the following high-level synthesis technology has been introduced.

As a technique for designing a logic circuit in a short period of time, a high-level synthesis technique as shown in Non-Patent Document 1 is known. High-level synthesis technology is a design automation technology that automatically converts the behavioral description of a logic circuit (hereinafter referred to as “software description”) expressed using a procedural software programming language such as C language into an RTL description in HDL. is there. The process of automatically synthesizing an RTL description from a software description using such a high-level synthesis technique is as follows.
(1) Allocation process: The type and number of arithmetic units and memories mounted on the logic circuit to be synthesized are determined.
(2) Scheduling step: The execution time of each operation in the software description is determined. This process is based on a “parallelism analysis” function used in a parallel compiler technology for a VLIW (Very Long Instruction Word) processor capable of parallel computation by a plurality of arithmetic units.
(3) Binding step: Determines the assignment of each operation to an arithmetic unit, the assignment of intermediate processing data to a register, and the like.
(4) FSMD generation step: A control unit for executing processing operations equivalent to software description in a logic circuit is realized by FSM (Finite State Machine), and this control unit is used to calculate an arithmetic unit, a register, a memory, And an FSMD (Finite State Machine + Datapath) that drives an arithmetic processing circuit (Datapath) including a bus and the like. The finally generated FSMD is the output RTL description.
Among these processes, the process of multiplexing each arithmetic process in the software by “scheduling” in the time direction and the process of multiplexing each arithmetic process in the spatial direction by “binding” (assignment to the arithmetic unit) The “operation scheduling and binding process” is an important process that is the core of high-level synthesis technology.
Details of the high-level synthesis technique and the process thereof are described in, for example, Patent Document 1 (Japanese Patent Laid-Open No. 2003-077628), Patent Document 2 (Japanese Patent Laid-Open No. 2006-011878), and Non-Patent Document 1.

As another technique for designing a logic circuit in a short period of time, a method using SystemC as shown in Non-Patent Document 2 is also known. SystemC is a kind of HDL provided as a class definition and macro definition of C ++ language that provides an interface for event-driven simulation of a hardware system. In SystemC, it is possible to describe “hierarchy description”, “parallel operation process description / process activation condition (sensitivity list)” and “signal connection” necessary for hardware description. Can be described in RTL. In addition, system functions can be abstractly expressed by software description in C ++ language by a description method on SystemC that separates communication description and operation processing description called TLM (Transaction Level Modeling), and it is possible to express system functions at large scale. It is possible to perform a simulation.
Details of SystemC are described in Non-Patent Document 2, for example.

JP 2003-077628 A JP 2006-011878 A

Kazutoshi Wakabayashi, “High-level synthesis technology that synthesizes hardware descriptions from software programs”, IEICE Fundamental Review, 2012, Vol. 6, No. 1, p. 37-50 By Thorsten Groetker, Masaru Enomoto, Masamichi Kawarabayashi and Takashi Hasegawa, “System Design with SystemC”, Maruzen, 2003, ISBN 4-621-07144-0 C3055

High-level synthesis techniques have the following problems.
First, the high-level synthesis technology has a problem that technology construction and tool implementation for synthesizing high-performance and high-efficiency circuits are very complicated and large-scale. The program code to be input by the high-level synthesis technology has a fundamentally the same structure as the software program code executed by the CPU in that it represents a sequential processing procedure. The degree of freedom is very high. Since the processing performance of the synthesized circuit is determined by how many operations parallelism can be extracted from such a highly flexible software description, extremely complicated parallelism analysis technology (data dependency analysis, control dependency analysis, Loop analysis, sequence reference dependency analysis, etc.). As a result, the aforementioned “operation scheduling and binding process” becomes very complicated.

  Further, the high-level synthesis technique has a problem that it is very difficult to predict how the contents of the RTL description, that is, the state of the logic circuit will change due to the change of the contents of the software description to be input. As described above, since the “operation scheduling / binding process” is complicated, it is extremely difficult to predict the output circuit characteristics (circuit scale, processing time) from the input software description. Therefore, for example, if none of the characteristics of the generated synthesis circuit meet the performance requirements, the performance requirements can be met by changing the software description to increase the parallelism of operations and reduce the amount of memory transfer. Measures to be satisfied (reduction of processing time and circuit scale) are required, but it is difficult to predict how changes to the software description will affect the characteristics of the synthesized circuit. The work of modifying the description itself can be extremely difficult.

  Furthermore, the high-level synthesis technique has a problem that it is difficult to describe software that reflects the designer's architectural intent and know-how because the structure (architecture) of the logic circuit largely depends on the “operation scheduling and binding process”. For this reason, manual design (design method for describing a logical structure directly in a hardware description language) that does not rely on high-level synthesis technology is still mainstream in the design of processing function blocks that require high parallelism.

  On the other hand, the method using SystemC has the following problems. For one, in order to describe a logic circuit using SystemC in RTL, it is necessary to use an RTL description class defined in SystemC, and the amount of description is equal to or higher than that of a hardware description language. Therefore, the improvement in design productivity by RTL description is very limited. In addition, there is a tool that automatically converts a TLM description into an RTL description using the above-described high-level synthesis technique. However, when this tool is used, the problem of the high-level synthesis technique is applied as it is.

  The present invention has been made in order to solve such problems of the prior art, and describes a specific information processing function based on circuit implementation in a programming language, and an RTL description that can be logically synthesized from this description. An object of the present invention is to provide an apparatus, a method, and a computer program for automatically generating data.

  In the first aspect of the present invention, a logic circuit description is generated by taking a program including a top-level function to be generated as a logic circuit describing an operation description, which is a series of hardware processing flows for circuit design. This is a logic circuit generation device. The logic circuit generation device includes a control flow graph generation unit, a control flow degeneration conversion unit, a data flow graph generation unit, and a logic circuit description output unit.

  The control flow graph generation unit generates a control flow graph from a loop processing unit and a top-level function that does not include a function call instruction. The control flow degeneracy conversion unit removes all conditional branch instructions from the control flow graph including only one assignment instruction for each variable for each variable, thereby reducing a control flow degeneration program that is a program in which the control flow is degenerated. Generate. The data flow graph generation unit uses each instruction of the control flow degenerate program as a node from the control flow degenerate program, and adds a directional branch from an assignment instruction to each variable to an instruction that refers to the variable. Generate a graph. The logic circuit description output unit generates a logic circuit description representing a sequential circuit in which a directed edge of the data flow graph corresponds to a wiring of the logic circuit and a node of the data flow graph corresponds to an arithmetic unit of the logic circuit.

  The state variable representing the state of the sequential circuit is expressed in the program as a local variable or a static variable of a higher-level function that calls the top-level function, and the value of the state variable before the assignment instruction to the state variable is executed This represents the current state of the sequential circuit, and the value of the state variable after the assignment instruction to the state variable is executed represents the next state of the sequential circuit.

  In one embodiment, preferably, the logic circuit generation device further includes a static single assignment format conversion unit. The static single assignment format conversion unit inputs a control flow graph to the control flow degenerate conversion unit when the top-level function is not a static single assignment format including only one assignment instruction for a variable for each variable. Convert to static single assignment form before being done. The static single assignment format conversion unit includes a φ function instruction insertion unit, a variable name conversion unit, and a state variable name re-conversion unit. The φ-function instruction insertion unit selects the variable definition on the path that was actually executed from all the variable definitions that merge at the location where multiple definitions of the value for the same variable merge in the control flow graph. Insert φ function instruction. The variable name conversion unit converts the name of each variable included in the control flow graph so as to have a different name for each assignment instruction for the variable, so that the control flow graph assigns an instruction for each variable after the name conversion. Is converted to a static single assignment form containing only one. The state variable name reconverting unit converts the variable name again so that the variable name in the start block of the control flow graph matches the variable name reaching the end block of the state variable after the name conversion. Preferably, the control flow degeneracy conversion unit includes a φ function instruction materializing unit. The φ function instruction materializing unit converts the φ function instruction into a specific operation instruction.

  In one embodiment, preferably, the logic circuit generation device further includes a register / memory array access instruction decomposition unit. The register / memory array access instruction decomposer includes an array assignment instruction decomposer and an array reference instruction decomposer. The array assignment instruction decomposition unit adds a write data variable and a write address variable to the control flow graph for each array variable when the top-level function included in the program includes an array assignment instruction that is a write processing instruction for the array variable. Each array assignment instruction is determined by assigning an assignment value to an array element to the write data variable, an instruction to assign an array index value to the write address variable, and the write address variable as an array index. The instruction is divided into an instruction for assigning the value of the write data variable to the array element. The array reference instruction decomposition unit adds a read address variable to the control flow graph for each array variable when the top-level function included in the program includes an array reference instruction that is a read processing instruction for the array variable. Each array reference instruction is decomposed into an instruction for assigning an array index value to the read address variable and an instruction for referring to an array element determined by using the read address variable as an array index. Preferably, in the memory for holding each array element data in the logic circuit, the write data variable corresponds to the write data port of the memory, the write address variable corresponds to the write address port of the memory, and the read address variable corresponds to the memory of the memory. This corresponds to the read address port. The control flow graph generated by the control flow graph generation unit is processed by the register / memory array access instruction decomposition unit and then processed by the control flow degeneration conversion unit.

  In one embodiment, more preferably, the register / memory array access instruction decomposing unit further includes a write port number assigning unit and a read port number assigning unit. The write port number assigning unit calculates, for each array assignment instruction for each array variable in the control flow graph, a maximum value of the number of executions of the array assignment instruction to the array variable executed between the start point block and the array assignment instruction. The array assignment instruction is assigned as a write port number. The read port number assigning unit, for each array reference instruction for each array variable in the control flow graph, sets the maximum number of executions of the array reference instruction to the array variable executed between the start point block and the array reference instruction. Assigned to the array reference instruction as a read port number. Preferably, the array assignment instruction decomposition unit adds the write data variable and the write address variable to the control flow graph for each write port number for each array variable, and for each read port number, The read address variable is added to the control flow graph. Preferably, the memory for holding each array element data includes the same number of write ports as the number of write port numbers assigned to the array variable assignment instruction, and the read ports assigned to the array variable reference instructions. There are as many read ports as there are numbers.

  In one embodiment, more preferably, the logic circuit generation device further includes a write memory port number determination unit and a read memory port number determination unit. The write memory port number determination unit determines whether or not the number of write port numbers assigned by the write port number assignment unit is equal to or less than a predetermined write memory port number threshold. The read memory port number determining unit determines whether or not the number of read port numbers assigned by the read port number assigning unit is equal to or less than a predetermined read memory port number threshold. Preferably, the logic circuit generation device performs a process of generating a logic circuit description when the write memory port number determination unit determines “No” or when the read memory port number determination unit determines “No”. Stop.

  In one embodiment, the program input to the logic circuit generation device preferably includes an attribute description for assigning an attribute to each variable. The attribute is a bit width attribute that specifies the bit width of the data of the variable, a register attribute that specifies that the value of the variable is held in the register, and a memory that specifies that the value of the array element of the array variable is held in the memory Including attributes. Preferably, the logic circuit generation device generates a logic circuit description including a sequential circuit in which a state is expressed by using a variable having a register attribute or the memory attribute as a state variable.

  In one embodiment, more preferably, the logic circuit generation device further includes a bit width determination unit, an arithmetic unit circuit delay evaluation unit, and a pipeline boundary arrangement unit. The bit width determination unit, for a variable included in the data flow graph, calculates the variable from the bit width of the variable and / or constant referred to in the assignment instruction for the variable and the type of operation executed in the assignment instruction. Calculate the bit width. The arithmetic unit circuit delay evaluation unit calculates the signal propagation delay time of the arithmetic unit based on the bit width calculated for the variable included in the data flow graph. The pipeline boundary arrangement unit includes a pipeline constraint extraction unit and a pipeline stage number determination unit. The pipeline constraint extraction unit adds a pipeline boundary attribute to a directional branch between an arithmetic unit that executes an assignment instruction for a state variable in the data flow graph and an arithmetic unit that executes a reference instruction for the state variable. The pipeline stage number determination unit determines the pipeline stage number used to generate the circuit description of the clock synchronous pipeline circuit as the pipeline stage number lower limit value, which is the minimum required pipeline stage number determined by the constraint based on the pipeline boundary attribute. The number is determined according to the number of pipeline stages calculated from the designated clock cycle or the number of pipeline stages designated in advance.

  In one embodiment, preferably, the logic circuit generation device further includes a logic circuit input signal extraction unit and a logic circuit output signal extraction unit. The logic circuit input signal extraction unit extracts the input signal of the circuit to be described by the circuit description from the argument of the highest function and the global variable. The logic circuit output signal extraction unit extracts the output signal of the circuit to be described by the circuit description from the argument and return value of the highest function and the global variable.

  In one embodiment, preferably, the logic circuit generation device further includes a non-circular / non-hierarchical conversion unit. When the highest level function includes a function call instruction, the complete inline expansion unit converts the highest level function into a lowest layer function that does not include the function call instruction by performing inline expansion of each function call instruction. When the lowest layer function converted by the complete inline expansion unit includes a loop processing unit with a fixed number of iterations, the complete loop expansion unit loops the loop processing unit with each fixed number of iterations. , Convert to a non-circular bottom layer function that does not include a loop processing unit. Preferably, the program input to the logic circuit generation device is input to the control flow graph generation unit after being converted into a non-circular bottom layer function by the non-circular / non-hierarchical conversion unit.

  In one embodiment, more preferably, the complete inline expansion unit sets the function as the lowest function when the function call instruction is not fully expanded even if the inline expansion is repeated a predetermined number of times for the input function. The complete loop expansion unit is configured to stop processing upon determining that conversion is impossible, and when the input function includes a loop processing unit whose number of iterations is not a constant, the complete loop expansion unit is acyclic. It is configured to stop processing upon determining that the function cannot be converted into the lowest function of the type. Preferably, the logic circuit generation device stops the process of generating the logic circuit description when the complete inline expansion possibility determination unit stops processing or when the complete loop expansion possibility determination unit stops processing. .

  In one embodiment, preferably, the logic circuit generation device further includes a state variable instruction dependency determination unit. The state variable instruction dependency determining unit determines whether or not an assignment instruction, a reference instruction, and an assignment instruction are continuously executed in this order for the same state variable in the control flow graph. Preferably, the logic circuit generation device stops the process of generating the logic circuit description when the state variable instruction dependency determination unit determines “No”.

  In the second aspect of the present invention, a logic circuit description is generated by taking, as an input, a program including a top-level function to be generated as a logic circuit that describes an operation description that is a series of hardware processing flows for circuit design. A logic circuit generation method performed by the logic circuit generation device.

  According to a third aspect of the present invention, there is provided a program including a top-level function for generating a logic circuit describing an operation description that is a flow of a series of hardware processing for circuit design. A logic circuit generation computer program for causing a computer to execute each step of a logic circuit generation method performed by a logic circuit generation device that takes an input and generates a logic circuit description.

  According to the apparatus, method, and computer program of the present invention, an RTL description that can be logically synthesized can be automatically generated from a software description having a high degree of freedom of description. Can be designed, developed and verified in a short period of time and at a low cost.

It is an exemplary functional block diagram which shows the function of the logic circuit generation apparatus 1 which concerns on one Embodiment of this invention. 1 is a diagram illustrating an exemplary hardware configuration of a logic circuit generation device 1 according to an embodiment of the present invention. It is a figure which shows the example of a description of the alias definition of a data type in the software description of this invention. It is a figure which shows the example of a description which adds a variable attribute with respect to a data type in the software description of this invention. It is a figure which shows the example of a description of the program which calls the same function with the argument which has a different variable attribute in the software description of this invention, and the pipeline circuit diagram corresponding to the program. It is a figure which shows the example of description of the state transition of the sequential circuit which used the static variable in the software description of this invention, and the state transition diagram of the sequential circuit. It is a figure which shows the example of description of the line buffer for image processing and shift register circuit which used the memory attribute variable in the software description of this invention, and a corresponding pipeline circuit diagram. It is a figure which shows the RTL description in the software description by the software description of this invention, and the prior art which described the operation | movement of the line buffer update of FIG. It is a figure which shows the example of a description of a recursive function call. It is a figure which shows the result of having expanded the function shown in FIG. 9 in-line in the logic circuit generation apparatus and method of this invention. It is a figure which shows the result of applying the optimization by constant propagation to the function shown in FIG. 10 in the logic circuit generation apparatus and method of this invention. FIG. 10 is a diagram illustrating a result of a complete inline function expansion of the function shown in FIG. 9 in the process of the circuit generation method of the present invention. It is a figure which shows the specific example of complete loop expansion | deployment in the logic circuit generation apparatus and method of this invention. (A1) represents an example of a function including a loop processing unit that repeats a constant number of times. (A2) represents a control flow graph corresponding to the function of (a1). (B1) represents the result of complete loop expansion of the function of (a1). It is a figure which shows the specific example of decomposition | disassembly of a memory array access instruction in the logic circuit generation apparatus and method of this invention. (A) represents an example of a function including a memory array access instruction. (B) represents a software description as a result of decomposing the memory array access instruction included in (a) using a port variable. It is a figure which shows the specific example of the SSA conversion procedure in the logic circuit generation apparatus and method of this invention. (A) is an example of a software description, (b) is a control flow graph corresponding to the software description of (a), (c) is a control flow graph resulting from inserting a φ-function instruction, and (d) is a variable to be substituted. (E) is a control flow graph as a result of converting the variable name of the referenced variable, and (f) is a control flow graph as a result of reconverting the variable name of the state variable. Represents. It is a figure which shows the specific example of the control flow graph of the program containing a memory array access command in the logic circuit generation apparatus and method of this invention. (A) represents the control flow graph corresponding to the software description of FIG.14 (b). (B) represents the control flow graph after carrying out SSA conversion of the control flow graph of (a). FIG. 16 is a diagram showing a result of performing control flow degeneration conversion processing by materializing a φ function instruction in the logic circuit generation device and method of the present invention on the control flow graph of FIG. It is a figure which shows the specific example of the control flow degeneration conversion process containing the register / memory arrangement | sequence access instruction in the logic circuit generation apparatus and method of this invention. (A) represents the software description corresponding to the control flow graph of FIG.16 (b) which is a control flow graph after SSA conversion. (B) represents a software description as a result of performing control flow degeneration processing on the software description of (a). It is a figure which shows the data flow graph produced | generated from the control flow degeneration program of FIG. It is a figure which shows the data flow graph produced | generated from the control flow degeneracy program of FIG.18 (b). It is a figure which shows the specific example of the software description of the program accompanied by a constant multiplication. It is a figure which shows the specific example and result of decomposition | disassembly of the division in the logic circuit generation apparatus and method of this invention. It is a figure which shows the software description corresponding to the data flow graph of FIG. It is a figure which shows the specific example of the process of constant multiplication decomposition | disassembly, constant propagation, and common subexpression removal in the logic circuit generation apparatus and method of this invention. It is a figure which shows typically the relationship between the maximum signal propagation time of a logic circuit, and the input-output signal of the calculator included in a logic circuit. It is a figure which shows typically the arithmetic unit circuit delay model of the logic circuit generation apparatus and method of this invention. FIG. 6 is a diagram schematically showing the relationship between the propagation time of each input signal of the computing unit, the propagation delay of the computing unit, and the propagation time of the output signal in the computing unit circuit delay model of the logic circuit generation device and method of the present invention. is there. It is a figure which shows the relationship between the input signal of a 2 input 1 output multiplexer, and an output signal. It is a figure which shows the relationship between the circuit diagram of the Booth recorder, the determination method of an input signal, and an input signal and an output signal assumed in one Embodiment of the logic circuit generation apparatus and method of this invention. It is a circuit diagram which shows the equivalence comparison negator assumed in one Embodiment of the logic circuit generation apparatus and method of this invention. 1 is a circuit diagram of a shift computing unit and a diagram showing a relationship between an input signal and an output signal, which are assumed in an embodiment of a logic circuit generation device and method of the present invention. It is a figure which shows the specific example of the software description of the program containing the reference instruction before assignment of a register variable, and the reference instruction after assignment. FIG. 33 is a diagram illustrating a data flow graph representing a pipeline circuit generated from the program of FIG. 32. It is a figure which shows the data flow graph of the result of having performed the register variable update instruction node group grouping process with respect to the data flow graph of FIG. It is a flowchart which shows the flow of a pipeline circuit synthetic | combination process in the logic circuit generation apparatus and method of this invention. It is the figure which showed typically the example of the data flow graph in which three pipeline boundary branches exist on one path | route. It is a flowchart which shows the flow of control of the local change process of a pipeline boundary using SA method in the logic circuit generation apparatus and method of this invention. It is a figure which shows one Embodiment of the logic circuit generation apparatus of this invention. It is a figure which shows one Embodiment of the logic circuit generation apparatus of this invention. It is a figure which shows one Embodiment of the logic circuit generation apparatus of this invention. It is a figure which shows one Embodiment of the logic circuit generation apparatus of this invention. It is a figure which shows one Embodiment of the logic circuit generation apparatus of this invention. It is a figure which shows one Embodiment of the logic circuit generation apparatus of this invention. It is a figure which shows one Embodiment of the logic circuit generation apparatus of this invention.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings (FIGS. 1 to 37). FIG. 1 is an exemplary block diagram illustrating functions of a logic circuit generation device 1 according to an embodiment of the present invention. As shown in FIG. 1, the logic circuit generation device 1 can output a logic circuit description D representing a logic circuit using a program P including the highest function Ftop as a logic circuit generation target as an input. The logic circuit generation device 1
Acyclic / non-hierarchical conversion unit 21
Logic circuit input / output signal extraction unit 22
Control flow graph generation unit 23
State variable instruction dependency determination unit 24
Register / memory array access instruction decomposition unit 25
Memory port number determination unit 26
Static single assignment format conversion unit 27
Control flow degeneration conversion unit 28
Data flow graph generation unit 29
Data flow graph optimization unit 30
-Circuit delay of arithmetic unit-Circuit scale evaluation unit 31
Pipeline boundary arrangement part 32
RTL description output unit 33
Can be included. The outline of these will be described below, but the details of the processing performed in each unit will be described later with reference to FIGS.

  The non-circular / non-hierarchical conversion unit 21 converts the top-level function Ftop to be generated in the logic circuit included in the program P input to the logic circuit generation device 1 into an acyclic type that does not include a loop processing unit and a function call instruction. Convert to the lowest layer function Fexp.

  The logic circuit input / output signal extraction unit 22 extracts an input signal and an output signal of the logic circuit generated by the logic circuit generation device 1 from the argument of the acyclic bottom layer function Fexp and the global variable of the program P.

  The control flow graph generation unit 23 generates a control flow graph Fcfg from the acyclic bottom layer function Fexp.

  Whether or not the state variable instruction dependency determining unit 24 sequentially executes an assignment instruction, a reference instruction, and an assignment instruction in this order for the same state variable in the control flow graph Fcfg. Determine whether or not. When the state variable instruction dependency determining unit 24 determines “No”, the logic circuit generation device 1 can stop the process of generating the logic circuit description.

  The register / memory array access instruction decomposition unit 25 assigns a write port number to the array assignment instruction included in the control flow graph Fcfg, and adds a variable corresponding to the data input port and the address input port to the control flow graph Ffcf. Subdivide assignment instructions. The register / memory array access instruction decomposition unit 25 assigns a read port number to the array reference instruction, and subdivides the array reference instruction by adding a variable corresponding to the address input port to Fcfg.

  The memory port number determination unit 26 has threshold values in which the number of write port numbers assigned to the array assignment instruction and the number of read port numbers assigned to the array reference instruction in the register / memory array access instruction decomposition unit 25 are respectively determined in advance. It is determined whether or not: When the memory port number determination unit 26 determines “No”, the logic circuit generation device 1 can stop the process of generating the logic circuit description.

  The static single assignment format conversion unit 27 converts the control flow graph Fcfg to a static single assignment format that includes only one assignment instruction for each variable included therein.

  The control flow degeneration conversion unit 28 generates a control flow degeneration program Fdeg, which is a program in which the control flow is degenerated, by removing all conditional branch instructions from the control flow graph Fcfg in the static single assignment format.

  The data flow graph generation unit 29 generates a data flow graph Fdfg from the control flow degeneration program Fdeg.

  The data flow graph optimization unit 30 optimizes the data flow graph Fdfg.

  The circuit delay / circuit scale evaluation unit 31 of the arithmetic unit estimates the circuit delay and circuit evaluation of the logic circuit generated by the logic circuit generation device 1 based on the data flow graph Fdfg.

  The pipeline boundary arrangement unit 32 synthesizes the pipeline circuit data Fplc by arranging the pipeline boundary in the data flow graph Fdfg.

  The RTL description output unit 33 generates and outputs a logic circuit description D based on the pipeline circuit data Fplc. This logic circuit description D becomes the output of the logic circuit generation device 1.

  FIG. 2 shows an exemplary hardware configuration of the logic circuit generation device 1 according to an embodiment of the present invention. The logic circuit generation device 1 includes a central processing unit (CPU) 11, a storage device such as a RAM 12, a ROM 13, and a hard disk drive (HDD) 14 that store various programs and data executed by the central processing unit, and these devices. Can be realized using a general-purpose computer having a bus 10 that connects the two. Further, the logic circuit generation device 1 includes a drive device 15 for inputting / outputting data to / from an external recording medium such as a CD-ROM or a DVD-ROM, and an input device 16 such as a keyboard or a mouse as necessary. And an output device 17 such as a CRT, a liquid crystal display or a printer, and a communication interface 18 for communicating with another computer or a network may be connected.

  In one embodiment of the present invention, the logic circuit generation device 1 can input the program P from the drive device 15, the input device 16, or the communication interface 18. The program P input to the logic circuit generation device 1 can be stored in the RAM 12. The RAM 12 can further store another program 4 (not shown) for causing the CPU 11 to execute the function of each unit of the logic circuit generation device 1 shown in FIG. The CPU 11 can process the program P stored in the RAM 12 according to the program 4 and generate a logic circuit description D as a result. Various control data such as a control flow graph Fcfg, a control flow degeneration program Fdeg, a data flow graph Fdfg, and pipeline circuit data Flcd generated in the course of processing of the program P by the CPU, and a finally generated logic circuit description D are also provided. Can be stored in the RAM 12. The logic circuit description D stored in the RAM 12 can be output from the drive device 15, the output device 17, or the communication interface 18.

  Here, with reference to FIG. 3 to FIG. 7, the program P used as an input of the logic circuit generation device or the logic circuit generation method according to the present invention uses, as one embodiment, an example of a program described in C language. I will explain. In the present specification, a description of a program P used as an input of a logic circuit generation device or a logic circuit generation method according to the present invention, which describes an operation description that is a flow of a series of hardware processing for circuit design, It will be referred to as the software description of the invention.

Data type alias definition
In the C language, an alias data type for a defined data type can be defined using a typedef specifier. FIG. 3 is a diagram showing a description example of the alias definition of the data type in the software description of the present invention. In this example, INT10 type and INT12 type are alias data types for int type, and S_INT12 type and M_INT12 type are alias data types for INT12 type. The SA_T type is an alias data type for a structure having a (char type), b (INT10 type), and c (INT12 type) as member variables.

[Add variable attribute to data type]
FIG. 4 is a diagram showing a description example in which a variable attribute is added to a data type in the software description of the present invention. In this description example, the variable attribute is described in the C source code using the #pragma statement. However, in another embodiment, for example, a file describing the correspondence between the type name and the variable attribute Other methods may be used such as a method for reading information and a method for inputting such information through a user interface.

  Looking at FIG. 4 in more detail, a description for adding a bit width attribute, a memory attribute, and a register attribute, which are variable attributes, to the data type is shown. Specifically, a bit width attribute of 10 bits width is added to the INT10 type, a bit width attribute of 12 bit width to the INT12 type, a memory attribute to the M_INT12 type, and a register attribute to the S_INT12 type and ST_A type, respectively.

  Further, since the S_INT12 type and the M_INT12 type are alias names of the INT12 type, a 12-bit width attribute is implicitly added to the S_INT12 type and the M_INT12 type. Since ST_A type is a structure consisting of three member variables, char type a, INT12 type b, and INT10 type c, the register attributes explicitly added to ST_A type are those 3 It is also implicitly added to the two member variables a, b, and c. In this way, the variable attribute description method characterized by combining the data type alias definition means and the attribute information description means for each data type reduces the amount of various additional information required for logic circuit generation. It is possible to efficiently associate with the software description by the amount of description.

[Improve design reusability by adding bit width attribute to data type]
FIG. 5 is a diagram showing a description example of code for calling the same function with arguments having different variable attributes in the software description of the present invention, and a pipeline circuit diagram corresponding to the program. In this description example, the function top0 is a logic circuit generation target function, 10-bit width arguments a and b and 12-bit width argument c are supplied as inputs, and an INT12 type return value is output. A method for determining input and output will be described later. A 12-bit width attribute and a register attribute are added to the local variable d of the S_INT12 type. The argument given to the function func0 that is called twice inside the function top0 is 10 bits wide in the first call, but 12 bits wide in the second call. Can be expressed. When such a bit width adjustment is performed by a hardware description language or SystemC, an explicit bit width designation description is required. However, by using the variable attribute addition description method for a type according to the present invention, the bit width is reduced. Since it can be specified implicitly, the reusability of the design is greatly improved.

[Implicit specification of timing information by register attribute addition]
In the example of FIG. 5, the variable d has a register attribute. In general, the register attribute does not change the operation of the software description, but specifies that a variable having this attribute is implemented as a register in the logic circuit. The operation of the register in the logic circuit is characterized in that the register input signal propagates to the register output signal only at the rising edge of the clock signal (i.e., transition from 0 to 1). It becomes possible to hold the internal state of the sequential circuit as a state variable. For this reason, a variable having a register attribute requires at least one clock from the time a value is assigned until the value can be read. Therefore, in the description of FIG. 5, after the return value of func0 called for the first time is substituted into d, d can be referred to after one clock, and the result of the second func0 called using that value is The output is delayed by one clock. In this way, by adding a register attribute to a software description having no time concept, timing information important in the logic circuit operation can be implicitly added. Since variable c is input at the same time as variables a and b, it is necessary to synchronize argument c with argument d of the second func0. This is done automatically in the generation process. Thus, by adding the register attribute, the timing of the logic circuit operation can be freely adjusted without changing the software description.

[Description of sequential circuit using static variables]
FIG. 6 is a diagram showing a description example of state transition of a sequential circuit using static variables and a state transition diagram of the sequential circuit in the software description of the present invention. In this description example, a 2-bit width attribute and a register attribute are added to the static variable stt and used as a state variable of the sequential circuit. In order to express the behavior of the state variable of the sequential circuit in the software description, it is necessary to keep the value of this state variable after one execution of the function top1, so the state variable is declared as a static variable. There is a need. Further, by adding a register attribute to this state variable, it is specified that the state variable of this sequential circuit is implemented by a register. Initialization to 0 in the declaration statement of stt is performed only once before starting the program (at the time of reset operation in the logic circuit), and the value of variable stt is updated by the value of input a each time function top1 is executed. It will be done. The value of stt assigned to the variable prev_stt and the value of stt in the switch statement are the values before stt is updated. In this way, the state transition of the sequential circuit, which is one of the most important components in the logic circuit, can be described very simply by the static variable in the software description.

[Description including memory circuit using memory attribute variable]
FIG. 7 is a diagram showing a description example of a line buffer for image processing and a shift register circuit using a memory attribute variable, and a corresponding pipeline circuit diagram in the software description of the present invention. In this description example, the function top2 is a function that inputs an 8-bit data pin and outputs 3 × 3 array data pw [3] [3]. This function uses the line buffer (vertical “delay circuit” to store pixel data for one line in the horizontal direction) as peripheral pixel data necessary for spatial filter processing for raster scan image data, etc. It is generated by a shift register (a horizontal “delay circuit”).

  More specifically, the line buffer is realized by two memory attribute array variables lbuf1 [1024] and lbuf2 [1024], and a 10-bit wide state variable pos is used as a common index to these arrays. A memory attribute array reference such as lb1 = lbuf1 [pos] represents a memory read, and an assignment to a memory attribute array such as lbuf1 [pos] = pin represents a memory write. The shift register is realized by a series of instructions for shifting the state variable array pw [3] [3], such as pw [0] [2] = pw [0] [1]. On the other hand, variables lb1, lb2, etc. that do not have state attributes are used to represent signals that transfer data instantaneously.

  There are two types of memory, synchronous type and asynchronous type, depending on the presence or absence of clock synchronization. At present, synchronous type memory is mostly used because priority is given to high speed. FIG. 8 is a diagram showing the software description (upper part) of the present invention and the RTL description (lower part) in the prior art describing the line buffer update of FIG. More specifically, FIG. 8 shows the software description of the update processing (simultaneous read / write to the same address) portion of the two line buffers in FIG. 7 and the RTL description by the Verilog hardware description language of the same operation. In synchronous memory circuit operation, the read data becomes valid one clock later, so lbuf2 must be written (lbuf2 [pos] = lb1) one clock after lbuf1 read (lb1 = lbuf1 [pos]) There is. In the line buffer, since it is necessary to read and write to the same address at the same time, it is necessary to delay the reading of lbuf2 by one clock in accordance with the write timing. The read data of lbuf2 (lb2 = lbuf2 [pos]) becomes valid one clock later than lbuf1. Although such a timing shift affects the operation timing of the subsequent circuit that refers to these data, it is necessary to accurately represent the above timing in the RTL description. On the other hand, in the software description of the present invention, it is only necessary to express the data flow without worrying about such detailed timing. In other words, the logic circuit description method using the programming language, which is the technology of the present invention, is a description method that allows only the data flow to be expressed while hiding the detailed circuit operation timing. In this respect, design productivity is dramatically improved compared to the RTL description.

[Specify top-level function]
In the software description of the present invention, the part that is the target of logic circuit generation can be the entire software description, but can also be determined by specifying the highest-level function that is the target of logic circuit generation. In this embodiment, although not shown, the logic circuit generation target is determined by describing in the software description a #pragma statement for designating the highest function. In another embodiment, other methods such as a method of reading a file in which the function name of the top-level function is described, a method of specifying a target range of logic circuit generation by a user interface, and the like may be used.

  As described above, the features of the software description which is the description of the program P used as the input of the logic circuit generation device or the logic circuit generation method according to the present invention have been described using the example described in the C language. However, these features can be expressed. As long as the program P is used, the program P used as the input of the logic circuit generation apparatus or the logic circuit generation method according to the present invention can be obtained by various software description languages such as a procedural language other than the C language, a functional language, or an object-oriented language. Those skilled in the art will readily understand that the same can be described.

  Next, with reference to FIGS. 9 to 37, each part of the logic circuit generation device 1 in the present embodiment shown in FIG. 1 will be described in detail.

[Acyclic / non-hierarchical conversion unit 21]
The program P input to the logic circuit generation device 1 is first input to the acyclic / non-hierarchical conversion unit 21. The non-circular / non-hierarchical conversion unit 21 is a function that performs non-circular / non-hierarchical conversion on the top-level function Ftop that is a logic circuit generation target included in the program P and does not include a loop processing unit and a function call instruction The non-circular bottom layer function Fexp is output.

  More specifically, the acyclic / non-hierarchical conversion unit 21 includes a complete inline expansion unit 211 and a complete loop expansion unit 212 described below. The highest-order function Ftop input to the non-circular / non-hierarchical conversion unit 21 is first input to the complete inline expansion unit 211 and converted into a lowest-layer function that is a function that does not include a function call instruction. The lowest layer function is further input to the complete loop expansion unit 212 and converted into an acyclic bottom layer function.

  The complete inline expansion unit 211 converts the input function into a lowest layer function that is a function that does not include a function call instruction. The process of converting a function to the lowest layer function is called complete inline expansion. The complete inline expansion unit 211 repeats inline expansion of the function call instruction for the input function. This completely expands instructions that call non-recursive functions. Further, the complete inline expansion unit 211 performs optimization by constant propagation as necessary in the process of repeating inline expansion of function calls. As a result, even for a recursive function, if the upper limit of the number of recursive calls can be specified, the instruction for calling the function is completely expanded.

  The complete inline expansion unit 211 determines that the function cannot be converted into the lowest function when the function call instruction is not fully expanded even if the inline expansion is repeated a predetermined number of times, and stops the processing. Can be. In this case, for example, the logic circuit generation device 1 can output a warning message to the output device 17 and stop the logic circuit generation processing.

With reference to FIGS. 9 to 12, processing for completely inlining a function will be described using a specific example. FIG. 9 shows a description example of a recursive function call. In this example, the function funcB is a recursive function because it contains an instruction that calls the function funcB itself. The function funcA is a function including an instruction that calls the function funcB that is a recursive function. Consider the process of fully inlining the function funcA in this example. FIG. 10 shows a function funcA that is the result of inline expansion of the function call funcB (4) included in funcA. Here, the variable funcB_0 is a variable introduced to store the return value of the function call funcB (4). FIG. 11 shows the result of applying optimization by constant propagation to the function funcA of FIG. Specifically, in FIG. 10, the variable a is referred to in two places as it is after the constant 4 is assigned, so the reference of the variable a is replaced with the constant 4. This
{int a = 4; funcB_0 = (a == 1)? 1: funcB (a-1) + 1;}
Part of
{funcB_0 = (4 == 1)? 1: funcB (4-1) + 1;}
Is converted to Conditional expression on the right side of this assignment statement
(4 == 1)? 1: funcB (4-1) + 1
Since the conditional expression of (4 == 1) evaluates to false, the conditional expression is the third term, that is,
funcB (4-1) + 1
Furthermore, Equation 4-1 is simplified to Constant Equation 3. As a result, the function funcA in FIG. 11 is obtained. Further, inline expansion of the instruction that calls the function funcB and optimization by constant propagation are repeatedly applied to the obtained function funcA until the condition of a == 1 where no recursive call occurs is satisfied. As a result, as shown in FIG. 12, a function in a form that does not include a function call instruction, that is, a lowermost layer function is obtained.

  As described above, the complete inline expansion unit 211 converts the input function into a lowermost layer function that is a function that does not include a function call instruction. If the input function does not include a function call instruction, the complete inline expansion unit 211 outputs the input function as it is.

  The complete loop expansion unit 212 converts the input lowest layer function into an acyclic bottom layer function that does not include a loop processing unit. This is performed by expanding all the loop processing units included in the function, and this processing is called complete loop expansion.

With reference to FIG. 13, processing for converting the lowest layer function to the acyclic bottom layer function will be described using a specific example. The function funcD in FIG. 13A is a function including a loop processing unit. The number of loop iterations in this loop processing unit is three. In the first iteration, the value of variable i is the constant value 0. That is, the first iteration of this loop processing unit is
i = 0; a + = a * i + 1;
By applying constant propagation optimization to this
a + = a * 0 + 1;
Is obtained. Similarly in the second and third repetitions
a + = a * 1 + 1;
a + = a * 2 + 1;
Is obtained. As a result, as shown in FIG. 13B, a function funcD in a form not including the loop processing unit is obtained.

  As described above, the complete loop expansion unit 212 converts the input lowest layer function into an acyclic bottom layer function that does not include a loop processing unit. When the input lowest layer function does not include the loop processing unit, the complete loop expansion unit 212 outputs the input lowest layer function as it is.

  In another embodiment of the present invention, the logic circuit generation device 1 may not include the acyclic / non-hierarchical conversion unit 21. In this case, the logic circuit generation device 1 takes as input a program P in which the highest function Ftop is an acyclic bottom layer function.

[Logical circuit input / output signal extraction unit 22]
The program P including the highest function Ftop converted to the acyclic bottom layer function Fexp by the noncircular / nonhierarchical conversion unit 21 is then input to the logic circuit input / output signal extraction unit 22. The logic circuit input / output signal extraction unit 22 is expressed by a logic circuit description D output from the logic circuit generator 1 from the input arguments and return values of the acyclic bottom layer function Fexp and global variables included in the program P. The input signal and output signal of the logic circuit are extracted.

  More specifically, the logic circuit input / output signal extraction unit 22 includes a logic circuit input signal extraction unit 221 and a logic circuit output signal extraction unit 222 described below. The logic circuit input signal extraction unit 221 extracts an input signal from the argument of the acyclic bottom layer function Fexp and the global variable included in the program P, and the logic circuit output signal extraction unit 222 receives the input acyclic bottom layer The output signal is extracted from the argument and return value of the function Fexp and the global variable included in the program P.

The logic circuit input signal extraction unit 221 extracts an input signal from an argument of the acyclic bottom layer function Fexp and a global variable included in the program P. Specifically, the logic circuit input signal extraction unit 221 determines and extracts the following (1) to (3) as input signals. Here, the “argument” is an argument of the acyclic bottom layer function Fexp, and the “function” is the acyclic bottom layer function Fexp.
(1) Non-pointer type argument.
(2) An entity variable that is referred to by a pointer type argument that has a value reference through a pointer reference within the function and does not have a value assignment through a pointer reference.
(3) A global variable with a value reference inside the function and no value substitution.

The logic circuit output signal extraction unit 222 extracts an output signal from the input argument and return value of the acyclic bottom layer function Fexp and the global variable included in the program P. Specifically, the logic circuit output signal extraction unit 222 determines and extracts the following (1) to (3) as output signals. Here, the “argument” is an argument of the acyclic bottom layer function Fexp, and the “function” is the acyclic bottom layer function Fexp.
(1) Function return value.
(2) An entity variable that is referenced by a pointer type argument that has a value assignment via a pointer reference inside the function.
(3) A global variable with value substitution inside the function.

With reference to FIGS. 5 to 7, a process in which the logic circuit input signal extraction unit 221 and the logic circuit output signal extraction unit 222 extract the input signal and the output signal, respectively, will be described using specific examples.
In the function top0 in FIG. 5, arguments a, b, and c that are non-pointer types are determined as input signals, and a return value calculation formula is determined as an output signal. In this example, the return value is the variable e, but in general the return value of the function can be a general expression that is not a variable alone.
In the function top1 in FIG. 6, the argument a which is a non-pointer type is determined as an input signal, and prev_stt which is a return value calculation formula is determined as an output signal. Note that the intra-function static variable stt cannot be referred to from outside the function, so it is determined as a signal inside the logic circuit and not an input / output signal.
In the function top2 in FIG. 7, the non-pointer type argument pin is determined as an input signal. The argument pw is of the pointer type, and value assignment via pointer reference (pw [0] [0] = pin etc.) exists in the function, so that all nine array elements are determined as output signals. The variable containing the entity of the array referred to by this pointer type argument pw is specified by a function (not shown) that calls the function top2, which may be a static variable (including a global variable), or It may be a local variable of a higher-level function that calls the function top2 directly or indirectly.

[Control Flow Graph Generation Unit 23]
The control flow graph generation unit 23 generates the control flow graph Fcfg from the acyclic bottom layer function Fexp obtained by the acyclic / non-hierarchical conversion unit 21.
In general, a function control flow graph is a directed graph representing a path when a function is executed. The nodes (nodes) of the control flow graph include a basic block, a start point block, and an end point block. The basic block is a sequential instruction sequence having no branch destination other than the head instruction and no branch instruction other than the end instruction. The starting point block is a node corresponding to the function entrance, and the execution of the function is started from here. The end point block is a node corresponding to the function exit, and the execution of the function is terminated when it reaches here. An edge (branch) of the control flow graph is a directional branch that represents a direct transition between nodes for execution of a function.
Since the process of generating the control flow graph from the function is a known technique, the description of the specific method is omitted here. The control flow graph Fcfg generated from the non-circular lowest layer function Fexp by the control flow graph generation unit 23 does not include a loop structure (that is, a path that passes through one node a plurality of times does not exist in the graph). However, when a conditional branch instruction is included in the highest-level function Ftop, the control flow graph Fcfg includes a conditional branch of a path (and a confluence associated therewith).

[State variable instruction dependency determination unit 24]
The state variable instruction dependency determination unit 24 determines the possibility of logic circuit generation for the control flow graph Fcfg generated by the control flow graph generation unit 23 according to the logic circuit generation enable determination rules 1 and 2 described below. When the state variable instruction dependency determination unit 24 determines that the logic circuit generation is not possible by any of these rules, the logic circuit generation device 1 outputs a warning message to the output device 17, for example, The generation process can be stopped.

  The logic circuit generation possibility determination rule 1 allows generation of a logic circuit when the array index is a non-constant variable and the array variable does not have a register attribute or a memory attribute for an assignment instruction to each array variable. It is a rule that determines that it is not. When such a variable is included in the control flow graph Fcfg, the variable instruction dependency determining unit 24 determines that a logic circuit cannot be generated.

  The logic circuit generation possibility determination rule 2 is read-after-write of the variable X from the instruction A to the instruction B for each variable X that is a register / memory array variable (referred to as an array variable having a register attribute or a memory attribute). When there are instructions A, B, and C that have a dependency and have a write-after-read dependency of the variable X from the instruction B to the instruction C, it is determined that the logic circuit cannot be generated. It is a rule to do. In this case, the assignment to X by the instruction A, the reference to X by the instruction B, and the assignment to X by the instruction C are executed continuously. Such a software description is a circuit of one clock. Since it cannot be realized as an operation, it is determined that the logic circuit cannot be generated. If an instruction having such a relationship is included in the control flow graph Ffcfg, the variable instruction dependency determining unit 24 determines that a logic circuit cannot be generated.

  Note that in another embodiment of the present invention, the logic circuit generation device 1 may not include the state variable instruction dependency determination unit 24. In any case, the program P taken as an input by the logic circuit generation device 1 is limited to the one including the highest function Ftop converted to a control flow graph satisfying the logic circuit generation possibility determination rules 1 and 2 described above. .

[Register / Memory Array Access Instruction Decomposition Unit 25]
In order to execute a plurality of read instructions and a plurality of write instructions for each register / memory array variable (referred to as an array variable having a register attribute or a memory attribute) in one clock, a register array variable (an array variable having a register attribute). )) Using a multi-port register file, or a memory array variable (an array variable having a memory attribute) must be implemented using a multi-port memory. The register / memory array access instruction decomposition unit 25 assigns port numbers to the array assignment instruction and the array reference instruction, thereby associating a plurality of write ports with array assignment instructions on the software description, and a plurality of read ports. Corresponds to an array reference instruction on the software description. Further, the register / memory array access instruction decomposition unit 25 adds an array assignment instruction and an array reference by adding a variable corresponding to an input port of the register file circuit or the memory circuit generated corresponding to the register / memory array variable. Subdivide instructions.
More specifically, the register / memory array access instruction decomposing unit 25 in this embodiment includes a write port number assigning unit 251, a read port number assigning unit 252, an array assignment instruction decomposing unit 253, which will be described below. And an array reference instruction decomposing unit 254.

  The write port number assigning unit 251 assigns a write port number to each of the array assignment instructions to the register / memory array variable included in the control flow graph Fcfg, and determines the number of write ports of the register / memory array variable. More specifically, the write port number assigning unit 251 performs each of the array assignment instruction A to the register / memory array variable X included in the control flow graph Fcfx from the start point block to the instruction A in the control flow graph Ffcf. The number of array assignment instructions to the array variable X other than the instruction A existing on the path is counted, and the maximum value of the number is assigned to the instruction A as a write port number.

  The number of write port numbers assigned to the array / assignment instruction for the register / memory array variable X in this way is referred to as the number of write ports for the register / memory array variable X. That is, when the write port number is represented by Nw numbers from 0 to Nw−1 using a certain integer Nw, the number of write ports is Nw. The number of register array variable write ports is called the register file write port number, and the number of memory array variable write ports is called the memory write port number.

  The read port number assigning unit 252 assigns a read port number to each of array reference instructions for register / memory array variables included in the control flow graph Fcfg, and determines the number of read ports for the register / memory array variables. More specifically, the read port number assigning unit 252 performs each of the array reference instruction B to the register / memory array variable X included in the control flow graph Fcfg from the start point block to the instruction B in the control flow graph Ffcf. The number of array reference instructions to the array variable X other than the instruction B existing on the path is counted up, and the maximum value of the number is assigned to the instruction B as a read port number.

  The number of read port numbers assigned to the array / reference instruction of the register / memory array variable X in this way is referred to as the number of read ports of the register / memory array variable X. That is, when a read port number is represented by Nr numbers from 0 to Nr−1 using a certain integer Nr, the number of read ports is Nr. The number of read ports of the register array variable is called the number of register file read ports, and the number of read ports of the memory array variable is called the number of memory read ports.

  Any register file circuit or memory circuit that implements a register / memory array variable is used to write a value to the register / memory array variable and to read a value from the register / memory array variable. Read port. The write port includes a data input port and an address input port. The array assignment instruction decomposition unit 253 adds variables corresponding to these two input ports to the control flow graph Ffcf, and subdivides the array assignment instructions included in the control flow graph Fcfg. The read port includes an address input port. The array reference instruction decomposing unit 254 adds a variable corresponding to the input port to the control flow graph Fcff, and subdivides the array reference instruction included in the control flow graph Fcfg. Variables added corresponding to these ports are referred to as “register / memory array port variables” or simply “port variables”.

  With reference to FIG. 14, the processing of the register / memory array access instruction decomposition unit 25 described above will be described using a specific example. (A1) is a software description of a program including a function top3 including an array assignment instruction and an array reference instruction for the memory array variable A, and (a2) is a control flow graph of the function top3.

  The function top3 includes two array reference instructions v = A [a] and u = A [b] as shown in the 8th and 12th lines of (a1). These also appear as they are in the control flow graph of (a2). In (a2), there is no array reference instruction for the array variable A between the start point block top3: start and the instruction of the array reference instruction v = A [a] (that is, there are 0 array reference instructions). Therefore, the read port number assigning unit 252 assigns the read port number 0 to the array reference instruction v = A [a]. Further, between the start point block top3: start and the array reference instruction u = A [b], there are a path that passes through the array reference instruction v = A [a] and a path that does not pass through. Therefore, there are 0 or 1 array reference instructions on the path from the start block top3: start to the array reference instruction u = A [b], and the maximum value of the number is 1, so the read port number The assigning unit 252 assigns the read port number 1 to the array reference instruction u = A [b]. As described above, since the read port numbers assigned to the array reference instruction for the array variable A are two, 0 and 1, the read port number assigning unit 252 determines that the number of read ports for the array variable A is 2.

  Further, the function top3 has three array assignment instructions A [a] = V + 1, A [b] = u + 1, and as shown in the 9th, 13th and 16th lines of (a1). Includes A [0] = v + u. Among these, the processing for the array assignment instructions A [a] = V + 1 and A [b] = u + 1 is the same as the processing for the first and second array reference instructions. That is, the write port number assigning unit 251 assigns the write port number 0 to the array assignment instruction A [a] = V + 1 and assigns the write port number 1 to the array assignment instruction A [b] = u + 1. Between the start block top3: start and the array assignment instruction A [0] = v + u, there are paths that pass through the array assignment instruction A [a] = V + 1 and paths that do not pass. This path does not pass the array assignment command A [b] = u + 1. Therefore, there are 0 or 1 array assignment instructions on the path from the start point block top3: start to the array assignment instruction A [0] = v + u, and the maximum number is 1. The write port number assigning unit 251 assigns the write port number 1 to the third array assignment instruction. As described above, since the read port numbers assigned to the array assignment instruction for the array variable A are two, 0 and 1, the write port number assigning unit 251 determines that the number of write ports for the array variable A is 2.

As described above, write ports 0 and 1 are assigned to the array assignment instruction of array variable A, and read ports 0 and 1 are assigned to the array reference instruction. Therefore, the array assignment instruction decomposition unit 253 and the array reference instruction decomposition unit 254 add port variables corresponding to these ports to the control flow graph Fcfg as shown below.
Read address variable: A0r (port 0), A1r (port 1)
Write address variable: A0w (port 0), A1w (port 1)
Write data variable: A0d (port 0), A1d (port 1)
Here, the read address variable is a variable corresponding to the address input port in the read port, the write address variable is a variable corresponding to the address input port in the write port, and the write data variable corresponds to the data input port in the write port. Is a variable.

  Further, the array assignment instruction decomposing unit 253 and the array reference instruction decomposing unit 254 generate an instruction for assigning the expression of the array index to the write address variable and the read address variable, and assign an expression for calculating the assignment value to the write data variable. Generate instructions. As a result, the array assignment instruction decomposing unit 253 and the array reference instruction decomposing unit 254 convert the array assignment instruction and the array reference instruction included in the control flow graph Fcfg into subdivided instructions as shown in FIG. Convert. FIG. 14 (b1) is a representation of the control flow graph of FIG. 16 (a) re-expressed in software description to aid understanding.

  In another embodiment of the present invention, the register / memory array access instruction decomposing unit 25 may not include the write port number assigning unit 251 and the read port number assigning unit 252. In this case, the array assignment instruction decomposition unit 253 and the array reference instruction decomposition unit 254 may add a set of port variables to each array variable included in the control flow graph Fcfg. In another embodiment of the present invention, the logic circuit generation device 1 may not include the register / memory array access instruction decomposition unit 25. In this case, the logic circuit generation device 1 takes as input a program P that does not include a register / memory array variable.

[Memory Port Number Determination Unit 26]
The memory port number determination unit 26 is configured such that the number of register file write ports, the number of register file read ports, the number of memory write ports, and the number of memory read ports calculated by the register / memory array access instruction decomposition unit 25 are respectively set to predetermined threshold values. Determine whether or not The threshold value for the number of ports can be individually determined for four types of ports in advance according to technical factors such as circuit characteristics (for example, circuit scale, circuit operation speed, power consumption) and semiconductor manufacturing process. If any of these numbers of ports exceeds a predetermined threshold, the memory port number determination unit 26 determines that circuit synthesis is not possible. When the memory port number determination unit 26 determines that the logic circuit generation is not possible, the logic circuit generation device 1 outputs a warning message to the output device 17, for example, and stops the logic circuit generation processing. Can do.

  In another embodiment of the present invention, the logic circuit generation device 1 may not include the memory port number determination unit 26. In this case, the logic circuit generation device 1 performs a logic circuit generation process regardless of the number of ports.

[Static single assignment format conversion unit 27]
If it is determined by the memory port number determination unit 26 that the control flow graph Fcfg can be generated as a logic circuit, then the control flow graph Ffcf is input to the static single substitution format conversion unit 27. The static single assignment format conversion unit 27 converts the control flow graph Fcfg to a control flow graph in the static single assignment format.

  In general, the static single assignment form is one of the intermediate representation forms of the software compiler, and there is only one definition of the value of each variable (that is, the assignment of the value to each variable is in one place. Format). The static single assignment form is obtained by renaming a variable and adding an instruction called a φ function instruction at a control flow location where a plurality of value definitions for the same variable merge.

  More specifically, the static single assignment format conversion unit 27 includes a φ function instruction insertion unit 271, a variable name conversion unit 272, and a state variable name reconversion unit 273, which will be described next.

  The φ function instruction insertion unit 271 inserts a φ function instruction at a location where a plurality of value definitions for the same variable merge in the control flow graph. The φ-function instruction is an instruction for selecting a variable definition on the actually executed path from all the variable definitions (referred to as a value definition for the variable) that joins the location. The value defined by the variable definition selected by the φ function instruction is assigned to the same variable. Note that the materialization of the φ function instruction (which means converting the φ function instruction into a specific operation instruction) is performed by the control flow degeneration conversion unit 28 described later.

  The variable name conversion unit 272 replaces the definition of the value of the variable by each variable substitution instruction and each φ function instruction in the control flow graph with a variable name with a subscript unique to each variable. The variable name conversion unit 272 further, for each instruction that refers to a variable in the control flow graph, sets the variable name of each variable to be referred to, the value of the variable by each variable assignment instruction or each φ function instruction that reaches the instruction. Replace with the subscripted variable name corresponding to the definition of. By this processing, the control flow graph is converted into a static single substitution format.

  As an additional process for the control flow graph converted into the static single substitution format, the state variable name re-converting unit 273 performs an end point block corresponding to the exit of the function for each static variable (including global variables). Replace the subscripted variable name assigned to the definition of the value that reaches with the subscripted variable name in the starting block corresponding to the function entry. This is done so that the values of static variables and global variables at the function exit can be referred to at the function entry location in the next function execution.

  Referring to FIG. 15, a specific example of processing when static single assignment format conversion unit 27 converts a control flow graph Fcfg involving the merging of a plurality of variable definitions into a static single assignment format is used. explain. FIG. 15B is a control flow graph representing the control flow of the top-level function top4 included in the program shown in FIG. First, as shown in FIG. 15C, the φ function instruction insertion unit 271 inserts a φ function instruction at the beginning of the basic block where the variable definitions of the variables a, b, and c merge. Specifically, looking at the function argument variable a, the definition of the value at the function entry given as the value of the function argument and the value definition by the assignment instruction of a = b + 1 are the places where the φ function instruction is inserted. Join at. Looking at the global variable b, there are three definitions: the value definition at the function entry given as the value of the global variable, the value definition by the assignment instruction of b = b + 1, and the value definition by the assignment instruction of b = a. , Merge at the place where the φ function instruction is inserted. Looking at the local variable c, there are three definitions: a value definition with an assignment instruction of c = b-1, a value definition with an assignment instruction of c = c + 1, and a value definition with an assignment instruction of c = 0. Merge at the place where φ function instruction is inserted.

  Next, as illustrated in FIG. 15D, the variable name conversion unit 272 replaces the variable value definition by each variable assignment instruction and each φ function instruction with a variable name with a unique subscript for each variable. For example, the variable name c1 is the subscripted variable name assigned for the value definition by one assignment instruction for the variable c, and the variable name c2 is the subscripted variable assigned for the value definition by another assignment instruction for the same variable c. Name. Although the substitution variable name conversion unit 272 is not shown, the values of the function argument variable and the static variable (including the global variable) are defined in the start block top4: start of the control flow graph corresponding to the entry of the function top4. And assign variable names with subscripts to these variables. Specifically, the subscripted variable name a1 is assigned to the definition of the value of the variable a given as the value of the function argument. For the global variable b, the value at the time of function entry is regarded as a definition as it is, and the subscripted variable name b1 is assigned to the definition of the value.

  Further, as shown in FIG. 15E, the variable name conversion unit 272 converts the variable name of each referenced variable for each instruction referring to the variable, each variable assignment instruction reaching each instruction, or each φ Replace with the subscripted variable name corresponding to the definition of the value of the variable by the function instruction. Specifically, the global variable b is referred to in the instruction represented by the expression c1 = b−1 in FIG. 15D, but as described above, the value of the variable b reaching this instruction is defined. Since the subscripted variable name b1 is assigned, the variable name of the variable b in this instruction is replaced with b1 as shown in FIG. 15 (e). The same applies to other instructions that refer to variables.

  With the above processing, the control flow graph is converted into the static single assignment format. However, the state variable name reconverting unit 273 adds an additional control flow graph to the static single assignment format control flow graph thus created. Process. That is, as shown in FIG. 15F, for each static variable (including global variables), a subscript assigned to the definition of the value reaching the end point block top4: end corresponding to the exit of the function top4. Replace the subscripted variable name with the subscripted variable name in the start block top4: start corresponding to the entry of the function top4.

  In FIG. 16, processing for converting the control flow graph Fcfg to the static single substitution format is shown using another specific example. FIG. 16A is a control flow graph of the function top3 described by the software description shown in FIG. FIG. 16B shows the result of the static single assignment format conversion unit 27 converting the control flow graph of FIG. 16A into the static single assignment format. A specific method of conversion is as described above with reference to FIG. The function top3 in this example includes a register / memory array access instruction, and the register / memory array access instruction included in the control flow graph Ffcfg is registered by the register / memory array access instruction decomposition unit 25 described above. It is subdivided using port variables. The static single assignment format conversion unit 27 replaces the variable names of register / memory array port variables as well as other variables. However, the variable name is not replaced for the register / memory array variable itself.

  In another embodiment of the present invention, the logic circuit generation device 1 may not include the static single assignment format conversion unit 27. In this case, the logic circuit generation device 1 takes as input a program P that includes the highest function Ftop described in the software description in the static single substitution format.

[Control Flow Degeneration Conversion Unit 28]
The control flow graph Fcfg converted to the static single assignment format by the static single assignment format conversion unit 27 is then input to the control flow degeneration conversion unit 28. As described above, the control flow graph Fcfg does not include a loop structure, but may include a conditional branch of a path (and accompanying merging), and therefore is not suitable for use as data representing a logic circuit as it is. However, since the control flow graph Fcfg input to the control flow degeneration conversion unit 28 is converted into a static single assignment format including only one assignment to each variable, it is added to the control flow graph Ffcf. If the φ function instruction is materialized, the conditional operation is ignored and the instruction of all nodes in the control flow graph is executed normally. This is a very important fact in the method of generating a logic circuit from a software description.

  Therefore, the control flow degeneration conversion unit 28 is a program in which the control flow is degenerated by materializing the φ function instruction included in the input control flow graph Fcfx and removing all conditional branches from the control flow graph Fcffg. A control flow degeneration program Fdeg is generated. The control flow degeneracy program Fdeg represents the structure of the logic circuit more directly as compared with the control flow graph Fcfg including the conditional branch.

  More specifically, the control flow degeneracy conversion unit 28 in the present embodiment includes a φ function instruction instantiation unit 281, a basic block unification unit 282, and a register / memory array access instruction fusion unit 283 described below. Including.

  The φ function instruction instantiation unit 281 instantiates the φ function instruction included in the input control flow graph Fcfg (that is, converts the φ function instruction into a specific operation instruction). As described in the description of the static single assignment format conversion unit 27, the φ function instruction is inserted at a location in the control flow graph where a plurality of variable definitions are merged, and all of the merges at that location. This is an instruction for selecting a variable definition on the path actually executed from the variable definitions. The variable definition is selected based on the condition value in the conditional branch of the route. For example, there are two paths that branch conditionally depending on the truth value of the condition p. The variable definition a1 exists on the path that is executed when the condition p is true, and the condition p is executed when the condition p is false. Assume that a variable definition a2 exists on the path, and a φ function instruction φ (a1, a2) for selecting one of these variable definitions exists in the part after the merging of the two paths. Then the φ function instruction φ (a1, a2) is instantiated to select a1 if the condition p is true, and to select a2 otherwise (ie, the condition p is false). The More specifically, φ (a1, a2) is instantiated into the expression p? A1: a2.

  The basic block unification unit 282 removes all conditional branches from the control flow graph Fcfg in which the φ function instruction is instantiated by the φ function instruction instantiation unit 281, so that the control flow is a program in which the control flow is degenerated. A degenerate program Fdeg is generated.

  In general, in a control flow graph that does not include conditional branches, there is only one path, and all instructions are executed sequentially, so instructions (except for branch instructions) included in all basic blocks It is possible to combine all basic blocks into one basic block by combining them into one instruction sequence. A program represented by a control flow graph in which basic blocks are combined into one in this way is called a program in which the control flow is degenerated.

  By the way, as described above, the control flow graph Fcfg in which the φ-function instruction is materialized, which is input to the basic block unification unit 282, is normal even if the instruction of all nodes is executed ignoring the conditional branch. To work. Therefore, the basic block unification unit 282 combines all the basic blocks by combining instructions (other than branch instructions) included in all the basic blocks of the input control flow graph Fcfg into one instruction sequence. The program is combined with one basic block and the control flow is degenerated. At this time, the order of instructions in the instruction sequence of the combined basic blocks is based on the execution order of the original basic blocks. For example, consider a case where a path branches from the basic block B1 to the basic blocks B2 and B3 in the input control flow graph Fcfg, and then these paths merge at the basic block B4. At this time, since B1 is executed before B2 in the path passing through B1 and B2, the instruction included in B1 is arranged before the instruction included in B2 in the combined basic block. Like that. The same applies to the relationship between B1 and B3, the relationship between B2 and B4, and the relationship between B3 and B4. However, since there is no path that passes through both B2 and B3, the instruction included in B2 may be disposed before or after the instruction included in B3. As a result, the order of instructions in this part in the combined basic block is B1 → B2 → B3 → B4 or B1 → B3 → B2 → B4. In any case, the instruction included in B2 and the instruction included in B3 were executed exclusively in the input control flow graph Fcfg, but in the combined basic block Both will be executed.

  The register / memory array access instruction fusion unit 283 performs a conditionally executed process for fusing a register / memory array access instruction that is executed exclusively to the control flow degenerate program Fdeg in which the φ-function instruction is materialized. Processing for adding an execution conditional expression to the register / memory array access instruction to be executed.

With reference to FIG. 15F and FIG. 17, the process performed by the control flow degeneration conversion unit 28 will be described using a specific example. First, the φ function instruction instantiation unit 281 instantiates a φ function instruction included in the control flow graph Fcfg. The operation of each φ function instruction included in the control flow graph of FIG. 15F is specifically as follows based on the condition value in the conditional branch of the path. Here, the condition values are set as P1 = (a1 == 0) and P2 = (a1 <0).
φ (a1, a2) selects a2 if P1 is true, and a1 if P1 is false.
φ (b1, b2, b3) selects b2 if P1 is true, selects b3 if P1 is false and P2 is true, P1 is false, and P2 is If it is false, select b1.
φ (c1, c2, c3) selects c2 if P1 is true, selects c3 if P1 is false and P2 is true, P1 is false, and P2 is If it is false, select c1.
By expressing these by specific expressions, each φ function instruction is materialized as follows.
φ (a1, a2) = (P1)? a1: a2;
S_b3_b1 = (P2)? B3: b1;
φ (b1, b2, b3) = (P1)? b2: S_b3_b1;
S_c3_c1 = (P2)? C3: c1;
φ (c1, c2, c3) = (P1)? c2: S_c3_c1;

  Next, the basic block unification unit 282 combines instructions (except for branch instructions) of all the basic blocks included in the control flow graph Fcfg in which the φ function instruction is materialized into one instruction sequence. As a result, all conditional branches are removed, and the control flow degeneration program Fdeg shown in FIG. 17 is generated.

  As another specific example, processing performed by the control flow degeneration conversion unit 28 will be described with reference to FIGS. 16B and 18. FIG. 18A shows a control flow degenerate program Fdeg converted from the control flow graph Fcfg of FIG. 16B including a register / memory array access instruction. The specific processing method of this conversion is as described with reference to FIG. 15 (f) and FIG. The register / memory array access instruction fusion unit 283 performs a process of fusing a register / memory array access instruction that is executed exclusively to the control flow degeneration program Fdeg. Specifically, the array assignment instruction A [A1w1] = A1d1 shown in the 17th line of FIG. 18A and the array assignment instruction A [A1w2] = A1d2 shown in the 20th line are converted into the φ function instruction A1w3. = φ (A1w1, A1w2) and A1d3 = Merged into one array assignment instruction A [A1w3] = A1d3 shown in line 26 of Fig. 18 (b) using the result of materialization of φ (A1d1, A1d2) To do. Further, the register / memory array access instruction fusion unit 283 performs a process of adding an execution conditional expression to a conditionally executed register / memory array access instruction. Specifically, the array reference instruction v2 = A [A1r1] shown in the fifth line of FIG. 18A is assigned when the read address port variable assignment instruction A1r1 = a1 is executed when P1 is true. This array reference instruction is converted to if (P1) v2 = A [A1r1] as shown in the fifth line of FIG. Similarly, the array assignment instruction A [A1w1] = A1d1 write address port variable assignment instruction A1w1 = a1 and the write data port variable assignment instruction A1d1 = u2 + 1 shown in the eighth line of FIG. , P1 is executed when it is true, this array assignment instruction is converted to if (P1) v2 = A [A1r1] as shown in the fifth line of FIG. 18B. In addition, the write address port variable and write data port variable of array assignment instruction A [A1w3] = A1d3 are output by φ function instructions, and these φ function instructions are always on the control flow path to be executed. Is not added.

  As described above, the control flow degeneration conversion unit 28 generates the control flow degeneration program Fdeg, which is a program in which the control flow is degenerated, from the input control flow graph Ffcfg. In another embodiment, when the logic circuit generation device 1 does not include the φ function instruction insertion unit 271, the control flow graph Fcfg does not include the φ function instruction. The φ function instruction materializing unit 281 may not be included. In still another embodiment, when the logic circuit generation device 1 does not include the register / memory array access instruction decomposition 25, the control flow degeneration conversion unit 28 does not include the register / memory array access instruction fusion unit 283. Can be.

[Data Flow Graph Generation Unit 29]
The control flow degeneration program Fdeg generated by the control flow degeneration conversion unit 28 is then input to the data flow graph generation unit 29. The data flow graph generation unit 29 generates the data flow graph Fdfg from the control instruction branch included in the input control flow degeneration program Fdeg and the sequential instruction sequence without merging. In general, a data flow graph is a directed graph in which each instruction is a node in a sequential instruction sequence and a directional branch is connected between an instruction that defines a value of a variable and an instruction that refers to the definition. Since the process of generating the data flow graph from the sequential instruction sequence without branching and merging of the control flow can be easily implemented using a known technique, description of the specific method is omitted here. As a specific example, FIG. 19 shows a data flow graph generated from the control flow degeneration program of FIG. As another specific example, FIG. 20 shows a data flow graph generated from the control flow degeneration program of FIG.

[Data flow graph optimization unit 30]
The data flow graph Fdfg generated by the data flow graph generation unit 29 is then input to the data flow graph optimization unit 30. The data flow graph optimization unit 30 optimizes the input data flow graph Fdfg. More specifically, the data flow graph optimization unit 30 includes a bit width determination unit 301, a redundant comparison operation deletion unit 302, an operation decomposition unit 303, and a redundant operation deletion unit 304 described below.

  In the RTL description, it is necessary to clearly indicate the bit width of each data of the arithmetic circuit, but it is very complicated to explicitly specify the bit width of each data. Therefore, the bit width determination unit 301 automatically determines the bit widths of the intermediate data and the output data of the arithmetic circuit from the input data of the logic circuit and the bit width designation information for the register variable. In the present embodiment, a section of values that can be taken by these data is obtained, and the minimum bit width capable of expressing any value in the section is determined as the bit width of the data. Hereinafter, the process performed by the bit width determination unit 301 will be described in detail. In the following description, only integer values are considered as data, but it is clear that other types of values (eg, floating point numbers) can be considered as well. In the present embodiment, negative values are expressed in 2's complement notation.

  In the following description, the minimum value and the maximum value that can be taken by the data x are represented by x.L and x.H, respectively. In addition, the section [x.L, x.H] defined with these as both end points is called the data section of the data x. The data interval of the data whose possible value is the constant value c is [c, c].

The minimum bit width that can represent the part excluding the sign bit in the bit representation of the constant c is called the minimum bit width of c and is represented by min_bit (c). If c is non-negative, i.e. if c> = 0, then the value of min_bits (c) is the smallest integer n that satisfies 2 ⁿ -1> = c, and if c is negative, i.e. If c <0, the value of min_bits (c) is the smallest integer n that satisfies 2 ⁿ > =-c.

Using this min_bits (c), the minimum bit width bit_width ([xL, xH]) for representing the data x having the data section [xL, xH] is expressed as follows.
When the data x can take only non-negative values, that is, when xL> = 0, the data x is treated as unsigned data and is represented in bits by unsigned binary notation. In this case, since the bit width that can represent the maximum value that x can represent can represent any value that x can represent, the minimum bit width for representing the data x is
bit_width ([xL, xH]) = min_bits (xH);
It is expressed.
On the other hand, if the data x can take a negative value, that is, if xL <0, the data x is treated as signed data, and is represented as a bit by a signed binary number (two's complement for negative values). Is done. In this case, the minimum bit width for representing the data x is
bit_width ([xL, xH]) = max (min_bits (xL), min_bits (xH)) + 1;
It is expressed.

First, the bit width determination unit 301 calculates a range of values that each data can take from the bit width information and the data type for the input data and the state variable of the logic circuit, and sets it as an initial data section. To do.
The initial data interval of n-bit unsigned data x is
[xL, xH] = [0, 2 ⁿ -1];
Is set.
The initial data interval of n-bit signed data x is
[xL, xH] = [-2 ^n-1 , 2 ⁿ -1-1];
Is set.

  Next, the bit width determination unit 301 determines the data section of the calculation result based on the type of each calculation and the data section to be calculated. Below, the process which determines the data area of a calculation result for every kind of calculation is demonstrated.

(1) Data interval for binary operation
The data interval of the result of a binary operation of the form z = x op y
[zL, zH] = Range (op, [xL, xH], [yL, yH]);
Is written. Here, the operator op is a C language binary operator {+,-, *, /,%, <<, >>, &, |, ^, ==,! =, <,>, < A process for a binary operation that is any one of = and> =} will be described, but it is obvious that the same process can be performed for another binary operation such as a power. The data interval of the operation result in the binary operation is determined from the operator op and the data intervals [xL, xH] and [yL, yH] of the operation target data x and y. Hereinafter, specific processing for determining the data section of the calculation result for each type of binary calculation will be described.

(1.1) Data interval of monotone binary operation The binary operation when the operator op of the binary operation x op y is any of {+,-, *, <<, >>} Let us call this a monotone binary operation. In this case, the data interval of the calculation result of x op y is obtained using the minimum value xL, yL and the maximum value xH, yH. More specifically,
MRange (op, [xL, xH], [yL, yH]) = [min (z0, z1, z2, z3), max (z0, z1, z2, z3)];
(However, in the above formula
z0 = xL op yL;
z1 = xL op yH;
z2 = xH op yL;
z3 = xH op yH;
), This is the data section of the result of the monotonic binary operation,
Range (op, [xL, xH], [yL, yH]) = MRange (op, [xL, xH], [yL, yH]);
Is determined.

(1.2) Data interval of division When the binary operation x op y is division, that is, when op is /, the data interval [yL, yH] of the divisor y further increases as described below. Divide cases. Note that here y == 0 is not considered.
If y is only a non-negative value or y is only a non-positive value, ie yL> = 0 || yH <= 0, then y == 0 is removed from the valid divisor data interval, that is, the y data interval If the data interval is [y'.L, y'.H], its end points are
y'.L = (yL == 0)? 1: yL;
y'.H = (yH == 0)?-1: yH;
It is expressed. Using this, the calculation data interval in this case is
Range (/, [xL, xH], [yL, yH]) = MRange (/, [xL, xH], [y'.L, y'.H]);
Is determined.
In other cases, that is, when y takes a positive or negative value yL <0 &&yH> 0, when the divisor y is divided into a negative range and a positive range, and the divisor is limited to each range The data interval of the operation result is obtained and integrated to determine the data interval of the final operation result. Specifically, the data interval of the operation result when the divisor is limited to the negative range is [L0, H0], and the data interval of the operation result when the divisor is limited to the positive range is [L1, H1]. Then
[L0, H0] = MRange (/, [xL, xH], [yL,-1]);
[L1, H1] = MRange (/, [xL, xH], [1, yH]);
It is expressed. Therefore, the data section of the final calculation result in this case is integrated.
Range (/, [xL, xH], [yL, yH]) = [min (L0, L1), max (H0, H1)]
Is determined.

(1.3) Data interval of remainder operation When binary operation x op y is a remainder operation, that is, when op is%, it is as follows.
In general, if y! = 0 and x is negative, the minimum value of x% y is-(abs (y)-1) and the maximum value is 0. When x is non-negative, the minimum value of x% y is 0 and the maximum value is abs (y)-1. there,
y_abs_max = max (abs (yL), abs (yH));
z4 = (xL <0)?-(y_abs_max-1): 0;
z5 = (xH> = 0)? y_abs_max-1: 0;
By defining, the data interval of the operation result in the remainder operation is
Range (%, [xL, xH], [yL, yH]) = [min (z4, 0), max (z5, 0)];
Is determined.

(1.4) Data interval of logical operation Data interval of operation result when binary operation x op y is a bitwise logical operation, that is, when operator op is one of {&, |, ^} The process for determining the will be described below. In the description, the simple “logical operation” means a logical operation for each bit.

  In the case of calculating a data section of a logical operation, the concept of 2's complement is not applied unlike the case of an arithmetic operation. That is, since -1 and 0 are 111... 1 and 000... 0 in binary representation, respectively, the interval including both -1 and 0 is discontinuous in binary representation. In this way, a section that is discontinuous in binary representation including both negative and non-negative values is referred to as a binary discontinuous section. Conversely, a section taking only a negative value and a section taking only a non-negative value are called binary continuous sections.

For two integers x and y, each represented by two's complement notation, reinterpreted as an unsigned integer and compared, the maximum value is unsigned_max (x, y) and the minimum value is unsigned_min (x, y ) If these are specifically defined by formulas,
unsigned_max (x, y) = ((unsigned) x> (unsigned) y)? x: y;
unsigned_min (x, y) = ((unsigned) x <(unsigned) y)? x: y;
It becomes.
In other words, it is as follows. If the signs of x and y are equal, that is, ((x <0) == (y <0))
unsigned_max (x, y) = (x> y)? x: y;
unsigned_min (x, y) = (x <y)? x: y;
It is expressed. On the other hand, if the signs of x and y are different, that is, ((x <0)! = (Y <0)), the negative values are reinterpreted when they are reinterpreted and compared as unsigned integers. Because the value is larger than the reinterpreted non-negative value,
unsigned_max (x, y) = (x <0)? x: y;
unsigned_min (x, y) = (x> = 0)? x: y;
It is expressed.

Here, first, a case will be described in which all data sections to be calculated in a logical operation are binary continuous sections. That is, in a logical operation of the form z = x op y, both [xL, xH] and [yL, yH] are binary continuous intervals. In this case, the data interval [zL, zH]
[zL, zH] = C_Range (op, [xL, xH], [yL, yH]);
Is written. This is specifically obtained by the following calculation formula.
b = max (min_bits (xL), min_bits (xH), min_bits (yL), min_bits (yH));
x_sign = (xL <0); (Because it is a binary continuous interval, (xL <0) == (xH <0))
y_sign = (yL <0); (Because it is a binary continuous interval, (yL <0) == (yH <0))
min_range = (x_sign op y_sign)?-2 ^b : 0;
max_range = (x_sign op y_sign)?-1: 2 ^b -1;
C_Range (&, [xL, xH], [yL, yH]) = [min_range, unsigned_min (xH, yH)];
C_Range (|, [xL, xH], [yL, yH]) = [unsigned_max (xL, yL), max_range];
C_Range (^, [xL, xH], [yL, yH]) = [min_range, max_range];

  In the above equation, min_range and max_range are used to determine the end point of the section. However, depending on how the data section to be calculated is given, the actual calculation result range does not necessarily include the min_range or max_range value. There is a case. In another embodiment of the present invention, the data section of the calculation result may be obtained more strictly by analyzing the possible value of each bit from the data section to be calculated. Or, on the contrary, in still another embodiment, for example, only the bit width may be considered, and it may be simpler than this embodiment.

Next, a general case in the logical operation will be described. In the operation x op y, when the operator op is one of {&, |, ^}, for each data interval [xL, xH] and [yL, yH], the interval is binary discontinuous If it is a section, divide the section into two binary continuous sections, calculate the data section of the calculation results in each binary continuous section, and integrate the results to obtain the final calculation result Determine the data interval. This is expressed as follows using specific equations. First, it is determined whether each of the data sections [xL, xH] and [yL, yH] is a binary discontinuous section.
x_neg_pos = (xL <0 &&xH> = 0); ([xL, xH] is a binary discontinuous section)
y_neg_pos = (yL <0 &&yH> = 0); ([yL, yH] is a binary discontinuous section)
If x_neg_pos == 0 && y_neg_pos == 0, that is, if both sections are binary continuous sections, as described above
Range (op, [xL, xH], [yL, yH]) = C_Range (op, [xL, xH], [yL, yH]);
Is required.
If x_neg_pos == 0 && y_neg_pos == 1, by dividing the data interval [yL, yH], which is a binary discontinuous interval
[L0, H0] = C_Range (op, [xL, xH], [yL,-1]);
[L1, H1] = C_Range (op, [xL, xH], [0, yH]);
Range (op, [xL, xH], [yL, yH]) = [min (L0, L1), max (H0, H1)];
Is required.
If x_neg_pos == 1 && y_neg_pos == 0, by dividing the data interval [xL, xH], which is a binary discontinuous interval
[L2, H2] = C_Range (op, [xL,-1], [yL, y, H]);
[L3, H3] = C_Range (op, [0, xH], [yL, yH]);
Range (op, [xL, xH], [yL, yH]) = [min (L2, L3), max (H2, H3)];
Is required.
If x_neg_pos == 1 && y_neg_pos == 1, by dividing the data interval [xL, xH] and [yL, yH] together
[L4, H4] = C_Range (op, [xL,-1], [yL,-1]);
[L5, H5] = C_Range (op, [xL,-1], [0, yH]);
[L6, H6] = C_Range (op, [0, xH], [yL,-1]);
[L7, H7] = C_Range (op, [0, xH], [0, yH]);
Range (op, [xL, xH], [yL, yH]) = [min (L4, L5, L6, L7), max (H4, H5, H6, H7)];
Is required.
As described above, in all cases, the data section of the operation result in the logical operation is determined.

(1.5) Data interval of comparison operation When binary operation x op y is a comparison operation, that is, the operator op is one of {==,! =, <,>, <=,> =} The data interval of the calculation result in the case is either [0, 0], [1, 1], or [0, 1] The result of a comparison operation may be a constant 0 or 1 due to general constant propagation. In addition, as will be described later, there are cases where a constant is evaluated by data interval determination.
If the result of the comparison operation is not a constant, the data interval of the operation result is [0, 1]. That is,
Range (op, [xL, xH], [yL, yH]) = [0, 1];
Is determined.

  As described above, the data section of the calculation result in the binary calculation is determined by (1.1) to (1.5).

(2) Data Interval of Unary Operation Next, processing for determining a data interval of the operation result in unary operation will be described.
The data interval of the result of unary operation of the form u = op x
[uL, uH] = Range (op, [xL, xH])
Is written. Here, processing for a unary operation in which the operator op is one of {!, ~,-, +} Among C language unary operators will be described.
The data interval of the operation result in the unary operation is determined as follows from the operator op and the data interval [xL, xH] of the operation target data x.
Range (!, [xL, xH]) = [0, 1]; (logical negation)
Range (~, [xL, xH]) = [~ xH, ~ xL]; (bit inversion)
Range (-, [xL, xH]) = [-xH, -xL]; (minus operation)
Range (+, [xL, xH]) = [xL, xH]; (plus operation)

(3) Data Interval of Selection Operation Finally, a process for determining the data interval of the operation result in the selection operation (ternary operation) in the format of s = t? X: y will be described. The data interval of the calculation result in the selection calculation is determined by the relationship between the conditional expression t and the selected terms x and y. When the conditional expression t is a constant value, as will be described later, the selection operation is simplified to a simple substitution expression by the redundant comparison operation deletion unit 302, and therefore the data section of the operation result needs to be considered here. There is no. Therefore, hereinafter, a case will be described in which it is not clear that the conditional expression t is a constant value.

(3.1) When the conditional expression t is a comparison operation (<,>, <=,> =) between the variable w and the constant
The data section [wL, wH] of w is divided into a section where the conditional expression t is false and a section where it is true, and for each divided section, the data section of w included in the selected terms x and y is After evaluating the data sections of the selected terms x and y as being the divided sections, the data sections of the final calculation result are determined by integrating the data sections of both. At this time, depending on the format of the conditional expression t, one of the following processes (a) to (d) is selected to evaluate the data section of the selected terms x and y. In these, c represents a constant value.
(A) If the conditional expression t is of the form w <c, the data interval of the second term x is evaluated assuming that the data interval of w is [wL, c-1], and the data interval of w Evaluate the data interval of the third term y as if [c, wH].
(B) When conditional expression t is in the form of w> = c, conditional expression t is expressed as! (W <c). Therefore, conversely to (a) above, the data interval of w is The data interval of the second term x is evaluated as being [c, wH], and the data interval of the third term y is re-evaluated assuming that the data interval of w is [wL, c-1].
(C) If conditional expression t is in the form of w <= c, if c '= c + 1, then conditional expression t is expressed as w <c'. Based on (a) above, the data intervals of x and y are evaluated.
(D) When conditional expression t is in the form of w> c, if c '= c + 1, conditional expression t is expressed as w> = c', so this form of w> = c ' Based on the above, the data intervals of x and y are evaluated according to the above (a).
The data interval of the calculation result in the selection calculation is determined by integrating the data intervals of x and y evaluated by the above (a) to (d). That is, the data interval of x evaluated by (a) to (d) above is [x'.L, x'.H] and the data interval of y is [y'.L, y'.H]. When the data interval of the final calculation result is
[sL, sH] = [min (x'.L, y'.L), max (x'.H, y'.H)];
Is determined.

The determination of the selection operation data interval when the conditional expression t is a size comparison operation between the variable w and a constant will be described below using a specific example. As a first example,
s1 = (w> 127)? 127: w;
Consider the data interval [s1.L, s1.H] of the operation result in the equation. In this expression, the second term 127 is selected when w> 127, and the third term w is selected when w <= 127. Since it is assumed that the conditional expression w> 127 is not a constant value, wL <= 127 &&wH> 127 holds. Conditional expression w> 127 corresponds to the above (d) because it is expressed in the form of w> c using the constant value c. Therefore, the data interval [wL, wH] of w is divided into [wL, 127] and [128, wH], and the former is applied to the third term w and the latter is applied to the second term 127, respectively. As a result, the data interval of the second term 127 is [127, 127], and the data interval of the third term w is [wL, 127]. Therefore, the data interval of the calculation result is obtained by integrating these intervals.
[s1.L, s1.H] = [min (wL, 127), 127] = [wL, 127];
Is determined.

As a second example,
s2 = (w <0)?-w: w
Consider the data interval [s2.L, s2.H] of the operation result in In this equation, the second term -w is selected when w <0, and the third term w is selected when w> = 0. Since it is assumed that the conditional expression w <0 is not a constant value, wL <0 &&wH> = 0 holds. Since the conditional expression w <0 is expressed in the form of w <c using the constant value c, it corresponds to the above (a). Therefore, the data interval [wL, wH] of w is divided into [wL, -1] and [0, wH], and the former is applied to the second term -w and the latter is applied to the third term w. As a result, the data interval of the second term -w is Range (-, [wL, -1]) = [1, -wL], and the data interval of the third term w is [0, wH]. Therefore, the data interval of the calculation result is obtained by integrating these intervals.
[s2.L, s2.H] = [0, max (-wL, wH)]
Is determined.

(3.2) When the conditional expression t is not a magnitude comparison operation between the variable w and the constant The data area of the selected operation is determined by simply integrating the data sections of the selected terms x and y. That is,
[sL, sH] = [min (xL, yL), max (xH, yH)];
And

  As described above, the data section of the calculation result in the selection calculation is determined by (3.1) and (3.2). In the present embodiment, when the conditional expression t is not a magnitude comparison operation between the variable w and the constant, the data sections of the selected terms are simply integrated, but another implementation of the present invention. In the embodiment, the data section of the calculation result may be obtained more strictly by further analyzing the relationship between the conditional expression and the selected term. Or, on the contrary, in another embodiment, the data sections of the selected terms may be simply integrated without always considering the conditional expression, for example.

  As described above, by the processing described in (1) to (3), the bit width determination unit 301 determines the data section of the intermediate data and output data of the arithmetic circuit. The bit width of data is defined as the minimum bit width that can represent an arbitrary value in the data section.

  In another embodiment of the present invention, the data flow optimization unit 30 may not include the bit width determination unit 301. In this case, the logic circuit generation device 1 determines the bit widths of the intermediate data and output data of the arithmetic circuit according to the type of the data, or the software of the program P input to the logic circuit generation device 1 When the bit width of data is specified in the description, the specified bit width can be used as it is.

By determining the data interval of each data, it may become clear that the result of the comparison operation is evaluated to a constant value. A comparison operation that results in a constant value is called a redundant comparison operation. The redundancy comparison calculation deletion unit 302 determines a redundancy comparison calculation based on the data section of each data determined by the bit width determination unit 301 and replaces it with a constant value, and further performs optimization by constant propagation.
For example, if the interval of data x is [xL, xH] = [0, 63] and the interval of data y is [yL, yH] = [64, 200], the expression x <y must be 1 In this case, replace the expression x <y with the constant value 1 in this case.
As another example, when the interval of data x is [xL, xH] = [0, 63], the expression x <0 always evaluates to 0. In this case, the expression x <0 is defined. Replace with the number 0.

  With reference to FIG. 21, the data section determination processing by the bit width determination unit 301 and the processing of the redundancy comparison calculation deletion unit 302 will be described using a specific example. For convenience of illustration and description, the program in this example is expressed as a software description in C language, but the object processed by the bit determination unit 301 and the redundant comparison calculation deletion unit 302 is a data flow graph. In the description, it should be understood that the data flow graph corresponding to the software description is the actual processing target.

  In this example, the function funcF has the clipping process for variables cc and dd (specifically, the process of clipping to 0 if negative value) and the clipping process for variable r (specifically, the value exceeds 255) Processing to clip to 255). The function top6 defines the concrete values of the arrays c [3] and d [3].

First, the bit width determination unit 301 uses, as an initial data section, a data section of each element of the array x [3] at the entrance of the function top6 (in this case, expressed as xi for convenience) based on its type.
[xi, L, xi.H] = [0, 255]
And set.

The first expression of the function funcF, ie
c = x [0] * c [0] + x [1] * c [1] + x [2] * c [2];
Contains multiple operations and subdivides
tmp0 = x [0] * c [0];
tmp1 = x [1] * c [1];
tmp2 = x [2] * c [2];
tmp3 = tmp0 + tmp1;
cc = tmp3 + tmp2;
It is expressed. The bit width determination unit 301 applies the data section of each data when the elements of the array c [3] = {-1, 2, -1} are propagated constant to these expressions according to the above-described processing. ,
[tmp0.L, tmp0.H] = [-255, 0]
[tmp1.L, tmp1.H] = [0, 510]
[tmp2.L, tmp2.H] = [-255, 0]
[tmp3.L, tmp3.H] = [-255, 510]
[cc.L, cc.H] = [-510, 510]
Is determined.

Similarly, the second expression of the function funcF, ie
dd = x [0] * d [0] + x [1] * d [1] + x [2] * d [2];
And also subdivide
tmp4 = x [0] * d [0];
tmp5 = x [1] * d [1];
tmp6 = x [2] * d [2];
tmp7 = tmp4 + tmp5;
dd = tmp7 + tmp6;
It is expressed. The bit width determination unit 301 calculates the data interval of each data when the elements of the array d [3] = {1, 2, 1} are propagated constant.
[tmp4.L, tmp4.H] = [0, 255]
[tmp5.L, tmp5.H] = [0, 510]
[tmp6.L, tmp6.H] = [0, 255]
[tmp7.L, tmp7.H] = [0, 765]
[dd.L, dd.H] = [0, 1020]
Is determined.

Since the data section of variable cc is [cc.L, cc.H] = [-510, 510] as described above, the third expression of function funcF, that is,
cc_clip = (cc <0)? 0: cc;
The conditional expression cc <0 in the selection operation is not a redundant comparison operation. Therefore, the bit width determination unit 301 determines the data section of the calculation result in the selection calculation according to the above-described processing (3.1) (a) of the bit width determination unit 301.
[cc_clip.L, cc_clip.H] = [0, 510]
Is determined.

On the other hand, since the data interval of the variable dd is [dd.L, dd.H] = [0, 1020] as described above, the fourth expression of the function funcF, that is,
dd_clip = (dd <0)? 0: dd;
The conditional expression dd <0 in the selection operation is always a redundant comparison operation that evaluates to 0. Therefore, the redundant comparison calculation deletion unit 302 converts this equation into
dd_clip = dd;
And simplify. As a result, the bit width determination unit 301 determines the data interval of the operation result.
[dd_clip.L, dd_clip.H] = [dd.L, dd.H] = [0, 1020]
Is determined.

Similarly, the bit width determination unit 301
r = (cc_clip + dd_clip) >>2;
Data interval
[rL, rH] = [0, 382]
And
r_clip = (r> 255)? 255: r;
Data interval
[r_clip.L, r_clip.H] = [0, 255]
Is determined. As described above, all intermediate data and output data sections of the function funcF are determined, and therefore the bit width is determined.

  As described above, the redundant comparison calculation deletion unit 302 optimizes the data flow graph by removing the redundant comparison calculation. In another embodiment of the present invention, the data flow graph optimization unit 30 may not include the redundant comparison calculation deletion unit 302. In that case, since the comparison operation in the data flow graph Fdfg is not optimized, the logic circuit finally output by the logic circuit generation device 1 may be redundant as compared with the present embodiment. The object of the present invention is still achieved.

  As an additional process for optimizing the data flow graph Fdfg, the arithmetic decomposition unit 303 performs a process of converting a complex arithmetic operation into a simple arithmetic operation that is easy to logically synthesize. Specifically, as described below, (1) constant multiplication addition / shift decomposition and (2) division shift / trial subtraction decomposition are performed.

(1) Constant Multiplication Decomposition For operations in which one operation object (ie, multiplicand or multiplier) among the operations included in the data flow graph Fdfg is a constant, the operation decomposition unit 303 performs the multiplication on a constant bit string. Are replaced with a series of operations that shift the other operation target to each bit position and integrate them. This process is called constant multiplication decomposition. For example, the expression x * 5 is 101 when the multiplier 5 which is a constant is expressed in bits, so it can be replaced with the sum of x and a value obtained by shifting x to the left by 2 bits. Expressing this as an expression gives (x << 2) + x.

(2) Division decomposition The operation decomposition unit 303 decomposes division into shift and trial subtraction by a so-called writing method. This process is called division decomposition. Arithmetic in binary numbers is the same as general arithmetic in decimal numbers, but the value of the quotient bit obtained at each subtraction is 0 or 1, and the value of the reduction is 0 or divisor. Value. Therefore, at each subtraction, if the dividend is greater than or equal to the divisor, the quotient bit value is 1 and the divisor value is the divisor value.If not, the quotient bit is 0 and the divisor value is set. Set to 0. This process of comparison and subtraction is known as trial subtraction. Whether the divisor is greater than or equal to the divisor may be determined by the sign of the result of the actual subtraction by the divisor.

  With reference to FIG. 22, decomposition of operations of a = c / d and b = c% d in 8-bit unsigned data a, b, c, d will be described. In the upper part of the figure, as a specific example, the writing to obtain the quotient 12 and the remainder 2 when 254 is divided by 21 is expressed in binary and decimal numbers, respectively. In the binary drawing, for example, the value n3 of 000001111 is not greater than or equal to the divisor 00010101, so the value of the bit g3 of the corresponding quotient is 0 and the subtraction is also 0. On the other hand, since the value 000011111 of n4 is greater than or equal to the divisor, the value of the bit g4 of the corresponding quotient is 1 and the subtraction is 00010101. The lower part of the figure represents the calculation process as a series of expressions in C language. That is, in general, the operations of a = c / d and b = c% d in 8-bit unsigned data a, b, c, d are decomposed into this series of expressions. More generally, the number of trial subtractions depends on the bit width of the data c, but the bit width of the data c determined by the bit width determination unit 301 is used here.

  In another embodiment of the present invention, the arithmetic decomposition unit 303 performs other optimization processing for arithmetic operations generally known in the field of software or processing equipment in addition to the above (1) and (2). Can be. In still another embodiment of the present invention, the data flow graph optimization unit 30 may not include the arithmetic decomposition unit 303. In that case, since the above-described optimization is not performed for the operations included in the data flow graph Fdfg, the logic circuit finally output by the logic circuit generation device 1 becomes redundant as compared with the present embodiment. However, the object of the present invention is still achieved.

  The redundant operation deletion unit 304 performs constant propagation, common subexpression deletion, and dead code deletion processing as additional processing for optimizing the data flow graph Fdfg. Constant propagation is a process for replacing an expression that results in a constant value with a constant value (that is, propagating a constant). In addition, a process of simply replacing an expression represented by one variable with the variable is also performed. Common subexpression deletion is a process of combining a plurality of expressions that are clearly evaluated to the same value into one expression. Dead code elimination is a process of deleting a variable that is not referenced.

  With reference to FIGS. 23 and 24, constant multiplication decomposition by the arithmetic decomposition unit 303, constant propagation and common subexpression elimination by the redundant operation deletion unit 304 will be described using specific examples. In FIG. 23, (a) is a software description of the program P including the function top5 as the highest function, and (b) is expanded inline by the non-circular / non-hierarchical conversion unit 21 to become a non-circular bottom layer function. The function top5. In FIG. 24, (a) is a data flow graph of the function top5 expanded inline.

  In FIG. 24, (b) is a data flow graph as a result of applying constant propagation to (a). Specifically, variable b0 is replaced with constant value 3, and variable b1 is replaced with constant value 7. In addition, the variables a0 and a1 represented simply by the variable c are replaced with the variable c. (C) is a data flow graph as a result of applying constant multiplication decomposition to (b). Specifically, the expression c * 3 is decomposed into the expression (c << 1) + c, and the expression c * 7 is decomposed into the expression (c << 2) + (c << 1) + c. By introducing an intermediate variable (for example, tmp0) corresponding to the subexpression (for example, c << 1) and expressing the subexpression as a node for these decomposition result expressions, the data flow graph of (c) becomes can get. (D) is a data flow graph as a result of applying common subexpression elimination to (c). Specifically, since the variables tmp0 and tmp1 are the result of the operation of the expression c << 1, the common expression c << 1 is combined into one by replacing the reference to tmp1 with the reference to tmp0. (E) is a data flow graph resulting from further applying the common subexpression deletion to (d). (F) is a data flow graph as a result of applying dead code deletion to (e). Specifically, the tmp1 and tmp3 nodes that are not referenced by other nodes are deleted from the data flow graph.

  As described above, the redundant calculation deletion unit 304 performs constant propagation, common subexpression deletion, and dead code deletion processing as additional processing for optimizing the data flow graph Fdfg. In another embodiment of the present invention, the data flow graph optimization unit 30 can be configured not to include the redundant calculation deletion unit 304.

[Calculator circuit delay / circuit area evaluation unit 31]
The data flow graph Fdfg optimized by the data flow graph optimization unit 30 is then input to the circuit delay / circuit area evaluation unit 31 of the arithmetic unit. The circuit delay / circuit area evaluation unit 31 of the arithmetic unit calculates the circuit delay of the corresponding arithmetic unit (that is, from the input / output bit width of each arithmetic instruction determined by the bit width determination unit 301 and the type of each arithmetic operation) , Signal propagation delay time) and circuit area. By estimating the circuit delay of the arithmetic unit, it is possible to estimate the operation speed (that is, the maximum operation clock frequency) of the logic circuit finally generated by the logic circuit generation device 1. In addition, by predicting the circuit area of the arithmetic unit with a certain degree of accuracy, the program P input to the logic circuit generation device 1 in order to obtain a logic circuit with a smaller area or a logic circuit that operates at a higher speed. It is possible to improve the efficiency of tuning work for software descriptions. In this embodiment, as will be described later, the circuit delay of the arithmetic unit evaluated here is also used in processing for maximizing the operation clock frequency of the logic circuit as the pipeline circuit.

  Various approaches are possible for the calculation method of the circuit delay of the arithmetic unit. In order to calculate the circuit delay with high accuracy, a logic synthesis tool that is a tool for synthesizing a circuit using a circuit library for a specific semiconductor process from an RTL description is directly applied to each arithmetic unit, There is a method of storing the result of logic synthesis with a bit width of 2 and predicting a circuit delay with an actual bit width from several logic synthesis results. In the present embodiment, the circuit delay / circuit area evaluation unit 31 of the arithmetic unit estimates the circuit delay and circuit area of the arithmetic unit based on a simple arithmetic unit delay model and area model described below. According to these models, it is possible to estimate the circuit delay and the circuit area with a certain degree of accuracy without the support of an external tool such as a logic synthesis tool.

  As shown in FIG. 25, in the synchronous logic circuit, the maximum operation clock frequency of the logic circuit is determined by the maximum signal propagation time of the output signal of the logic circuit. When the input signal of the entire logic circuit and each register output signal that changes at the instant of clock rise (ie, transition from 0 to 1) are used as the signal propagation sources, the maximum signal propagation time is determined by these sources. This is the maximum time required for signal propagation from the other signal to other signals.

  A signal propagation delay factor is a circuit delay from the change of the input signal to the change of the output signal in each logic gate constituting the logic circuit. In the present embodiment, these circuit delays are modeled in units of arithmetic units. Similarly, the circuit area is also modeled on a computing unit basis. A complex arithmetic unit is hierarchically expressed using a simpler arithmetic unit. Correspondingly, a delay model and an area model of the arithmetic unit are also hierarchically expressed. As a result, it is possible to make the delay model and the area model correspond to all the arithmetic units that can be expressed in the software description, so that it is not necessary to depend on an external logic synthesis tool.

  In the circuit delay model of the arithmetic unit, the propagation time of each signal is represented by only two points of the MSB (most significant bit) and LSB (least significant bit) of the signal. This is much faster than calculating the propagation time individually for each bit of the signal. Also, since the signal propagation time difference between the MSB and the LSB is expressed, the circuit delay is calculated with high accuracy corresponding to the carry propagation structure included in the arithmetic operator (addition, subtraction, multiplication, etc.).

  In the following description, the LSB propagation time of the signal S is represented as S.TL, and the MSB propagation time is represented as S.TM. The signal propagation source (that is, the input signal and register output signal of the entire logic circuit) SI propagation time is SI.TL = SI.TM = 0. In addition, as shown in FIG. 26, the input signal at the port i of the computing unit is denoted as S (i), and the output signal via the input port i is denoted as SO ′ (i). Therefore, for example, the LSB propagation time of the input port i is expressed as S (i) .TL. Here, as further shown in FIG. 26, the following four notations are introduced to express the signal propagation delay between each input port and output port of the computing unit.

  L (i) (simple propagation delay) is the propagation delay from the LSB of the input port i to the LSB of the output port (LSB propagation delay), or the propagation delay from the MSB of the input port i to the MSB of the output port (MSB propagation delay) ). Here, a simple model is assumed in which the LSB propagation delay and the MSB propagation delay are the same.

  C (i) (carry propagation delay) indicates a signal propagation delay time from the LSB of the input port i to the MSB of the output port. This is mainly used to represent the carry delay of the adder. Examples of the arithmetic unit in which the carry propagation delay is considered (that is, C (i) is not 0) include an adder, a subtracter (including a unary minus operation), a multiplier, and a magnitude comparator.

  F (i) (input delay synchronization flag) indicates whether or not the signal propagation time of each of the input LSB and MSB is synchronized (that is, the signal is not synchronized). Let F (i) = 0 and F (i) = 1 denote the case where the signal is synchronized. Specifically, since the output of the equivalence comparator and logic negator is determined after all the bits of the input arrive, F (i) = 1 is set for all input ports i. The shift computing unit sets F (2) = 1 because the output is determined after all the bits of the input of the second input port that specify the shift amount arrive. In this model, as will be described later, since the LSB propagation time of one signal does not become slower than the MSB propagation time, when the signals are synchronized, the LSB propagation time is aligned with the MSB propagation time. Will be.

Although not shown, TL (i) represents the LSB propagation time of the input signal as a result of considering the signal synchronization selectively performed by F (i). That is, when F (i) == 0, signal synchronization is not performed, so TL (i) is S (i) .TL. On the other hand, when F (i) == 1, signal synchronization is performed and the LSB propagation time is aligned with the MSB propagation time, so TL (i) is S (i) .TM. Expressing this with an expression
TL (i) = (F (i) == 1)? S (i) .TM: S (i) .TL
It becomes.

As further shown in FIG. 26, the LSB propagation time SO ′ (i) .TL of the output signal is equal to the LSB propagation time TL (i) of the input signal in consideration of the signal synchronization. ) Is added. Expressing this with an expression
SO '(i) .TL = TL (i) + L (i)
It becomes.

The MSB propagation time SO '(i) .TM of the output signal is the sum of the LSB propagation time TL (i) of the input signal and the carry propagation delay C (i) of the computing unit, and the MSB propagation time of the input signal. TM (i) plus the simple propagation delay L (i) of the arithmetic unit, whichever is greater. Expressing this with an expression
SO '(i) .TM = max (S (i) .TM + L (i), TL (i) + C (i))
It becomes.

  From these equations, it can be seen that unless the LSB propagation time of the input signal at each port of each computing unit is slower than the MSB propagation time, the LSB propagation time of the output signal will not be slower than the MSB propagation time. Therefore, in the entire logic circuit, the LSB propagation time of one signal does not become slower than the MSB propagation time.

  As shown in FIG. 27, the MSB propagation time SO.TM of the final output signal SO of the computing unit is the MSB propagation time SO ′ of the output signal via the input port i for all the input ports i of the computing unit. (i) Required as the slowest of the TMs. Similarly, the LSB propagation time SO.TL is obtained as the slowest of the LSB propagation times SO ′ (i) .TL of the output signal passing through the input port i for all the input ports i of the computing unit. However, when the output signal width of the arithmetic unit is 1 bit, since the LSB and the MSB are the same bit, the value obtained as the MSB propagation time SO.TM is also adopted as the LSB propagation time SO.TL. To do.

Here, B (output delay synchronization flag) indicates whether or not the width of the output signal of the arithmetic unit is 1 bit, and B = 1 in the case of 1-bit output, and B = 0 in the other cases To do. Using this, the MSB propagation time SO.TM and the LSB propagation time SO.TL of the final output signal SO of the computing unit are expressed by equations.
SO.TM = max {SO '(i) .TM | i ∈ I}
SO.TL = (B == 1)? SO.TM: max {SO '(i) .TL | i ∈ I}
It becomes. In these equations, I represents the set of all input ports i of the computing unit.

  The circuit delay model and area model of the arithmetic unit described above will be described more specifically for each type of arithmetic unit. For this purpose, first, the circuit delay and circuit area of the basic logic gate are appropriately modeled corresponding to the assumed mounting technology (semiconductor process, FPGA: Field Programmable Gate Array). The basic gates to be modeled here are a logical product (AND), a logical sum (OR), a logical negation (NOT), an exclusive logical sum (XOR), and a two-input one-output multiplexer (MUX). FIG. 28 shows a circuit diagram and operation of the 2-input 1-output multiplexer. In addition to these, other basic gates such as NAND or NOR may be added. The circuit delay model of each of these basic logic gates G is denoted as G.delay, and the circuit area model is denoted as G.area (for example, the circuit delay of the AND gate is denoted as AND.delay) .

  Next, a composite gate model in which basic logic gates are combined will be described. As a typical composite gate, a 1-bit full adder (FA), a 1-bit half adder (HA), and a Booth recorder (BR) are considered. In the description, the circuit delay and the circuit area are calculated on the assumption of the circuit structure, but may be strictly calculated from the circuit library to be used.

The 1-bit full adder (FA) inputs 3 bits, a, b, and c, and outputs sum and carry bits. The relationship between input and output is
sum = a ^ b ^ c;
carry = (a & b) | (b & c) | (a &c);
It is expressed. Assuming a circuit structure that directly implements the operations of these equations, the sum output delay FA.s_delay, carry output delay FA.c_delay, and circuit area FA.area are expressed as follows.
FA.s_delay = 2 * XOR.delay;
FA.c_delay = AND.delay + OR.delay; (carry propagation delay)
FA.c_area = 3 * AND.area + 2 * OR.area; (Carry output circuit area)
FA.area = 2 * XOR.area + FA.c_area;

A 1-bit half adder (HA) inputs 2 bits a and b and outputs sum and carry bits. The relationship between input and output is
sum = a ^ b;
carry = a &b;
It is expressed. Assuming a circuit structure that directly implements the operations of these equations, sum output delay HA.s_delay, carry output delay HA.c_delay, and circuit area HA.area are expressed as follows.
HA.s_delay = XOR.delay;
HA.c_delay = AND.delay; (carry propagation delay)
HA.c_area = AND.area; (Carry output circuit area)
HA.area = XOR.area + HA.c_area;

The Booth recorder (BR) is used in the multiplier to decode the consecutive 3 bits of input port 1, and to double, 1 times, 0 times, -1 times, -2 times the data of input port 0 It is a circuit to output. As shown in Fig. 29, 2 bits of input port (x0, x1) consisting of 1x and 2x of input port 0 (x0, x1) are made -1 times and -2 times by two XOR gates, and these are input as 2 Assume a circuit structure that obtains each bit of the output by selecting it with a 1-output multiplexer and realizing it with an AND gate that produces 0 times. The sel, neg and nz signals in the figure are
sel = y _i ^ y _i-1 ;
neg = y _{i + 1} ;
nz = ~ (y _{i + 1} & y _i & y _i-1 ) & (y _{i + 1} | y _i | y _i-1 );
It is expressed. Directly following these equations, a circuit structure of a decoder circuit that outputs these signals is assumed. The output delay BR.delay and the circuit area BR.area are expressed as follows. Here, bw_0 represents the bit width of the input port 0.
BR.delay = XOR.delay + MUX.delay + AND.delay;
BR.dec_area = XOR.area + AND.area * 3 + OR.area * 2 + NOT.area; (decoder circuit area)
BR.area (bw_0) = (XOR.area * 2 + MUX.area + AND.area) * bw_0 + BR.dec_area;

  Processing for estimating the circuit delay model and circuit area model of each arithmetic unit using the basic logic gate and composite gate models described above will be described below. In the description, the circuit delay and the circuit area are estimated by assuming a circuit structure, but the results may be different when another circuit structure is assumed.

In the explanation, the circuit area of the calculator X is expressed as X.AREA.
In addition, parameters related to input / output signals are expressed as follows.
bw_in (i) represents the bit width of the input signal of the input port i.
bw represents the bit width of the output signal.
bw_max represents the maximum value of the bit width of the input signal for all input ports.
bw_min represents the minimum value of the bit width of the input signal for all input ports.
bw_dif represents the difference between the maximum value and the minimum value of the bit width of the input signal.
Expressing these relationships as an expression,
bw_max = max {bw_in (i) | i ∈ I}
bw_min = min {bw_in (i) | i ∈ I}
bw_dif = bw_max-bw_min
It becomes. In these equations, I represents the set of all input ports i of the computing unit.

The adder (ADD) assumes a circuit structure in which bw_min bits of the output are realized by a full adder (FA) and the remaining bw_dif bits are realized by a half adder (HA). The circuit delay and circuit area of the adder in this circuit structure are as follows. In the equation, i representing the input port is 0 or 1.
ADD.L (i) = FA.s_delay (for one FA sum output delay)
ADD.C (i) = FA.c_delay * bw_min + HA.c_delay * bw_dif (FA carry output delay bw_min and HA carry output delay bw_dif)
ADD.F (i) = 0
ADD.AREA = FA.area * bw_min + HA.area * bw_dif

The subtractor (SUB) assumes a circuit structure in which a NOT gate is added before input port 1 in the adder. The circuit delay and circuit area of the subtractor in this circuit structure are as follows. In the equation, i representing the input port is 0 or 1.
SUB.L (i) = FA.s_delay + NOT.delay
SUB.C (i) = FA.c_delay * bw_min + HA.c_delay * bw_dif + NOT.delay
SUB.F (i) = 0
SUB.AREA = FA.area * bw_min + HA.area * bw_dif + NOT.area * bw_in (1)

The multiplier (MUL) here assumes a circuit structure that adds the ceil (bw_1 / 2) outputs of the Booth recorder. The circuit delay and circuit area of the multiplier in this circuit structure are as follows. In the equation, i representing the input port is 0 or 1.
booth_count = ceil (bw_in (1) / 2) (number of Booth recoder units)
MUL.L (i) = BR.delay + booth_count * FA.s_delay (1 Booth recoder output delay plus FA sum output delay booth_count)
MUL.C (i) = MUL.L (i) + bw_in (0) * FA.c_delay (multiplier output delay and FA carry propagation delay for bw_in (0) bits)
MUL.F (i) = 0
MUL.AREA = booth_count * BR.area (bw_in (0)) + booth_count * (bw_in (0) + 1) * FA.area (Booth recoder with bit width bw_in (0) and full adder circuit for output addition Total area)

The selection calculator (SEL) outputs one of the two selected inputs based on a 1-bit selection input. Here, a circuit structure using a multiplexer having the number of bit widths of the output signal is assumed. The circuit delay and circuit area of the selected arithmetic unit in this circuit structure are as follows. In the equation, i representing the input port is 0 or 1.
SEL.L (i) = MUX.delay
SEL.C (i) = 0
SEL.F (i) = 0
SEL.AREA = MUX.area * bw
If the bit widths of the two input ports are different, it can be calculated more strictly using bw_min and bw_dif.

A large / small comparator (CMP) is assumed to be a circuit that subtracts two input ports and outputs a result calculated from a sign bit of an operation result. Since the output of the subtraction result is not necessary, it becomes smaller than the circuit area of the subtractor accordingly. Since the output bit width is 1, the output delay synchronization flag (B) is 1. The circuit delay and circuit area of the large / small comparator in this circuit structure are as follows. In the equation, i representing the input port is 0 or 1.
CMP.L (i) = FA.c_delay
CMP.C (i) = FA.c_delay * bw_min + HA.c_delay * bw_dif + NOT.delay
CMP.F (i) = 0
CMP.AREA = FA.c_area * bw_min + HA.c_area * bw_dif + NOT.area * bw_in (1)

The equivalence comparison negator (NEQ) outputs 0 when all the bits of the two input ports are equal, and outputs 1 otherwise. As a circuit structure, as shown in FIG. 30, it is assumed that two-input bitwise XOR operation outputs are connected by OR using a binary tree structure. Since the output bit width is 1, the output delay synchronization flag (B) is 1. However, since the delay is synchronized on the input port side, the LSB propagation time and the MSB propagation time of the output port signal are automatically set. Be the same. The circuit delay and circuit area of the equivalence comparison negator in this circuit configuration are as follows. In the equation, i representing the input port is 0 or 1.
NEQ.L (i) = XOR.delay + ceil (log ₂ (bw)) * OR.delay
NEQ.C (i) = 0
NEQ.F (i) = 1 (input delay synchronization)
NEQ.AREA = bw * XOR.area + (bw-1) * OR.area

The shift calculator (SHF) outputs the right shift or left shift of the data of port 0 using the value specified by port 1 as the shift amount. As the circuit structure, a barrel shifter is assumed. The barrel shifter is configured by connecting in series a circuit that shifts a power of 2 bits in the binary representation of the shift amount of port 1. For example, Z = X >> Y (X, Y, Z: unsigned 32 bits) has a circuit structure as shown in FIG. Here, only the lower 5 bits of Y indicate the shift amount. The circuit delay and circuit area of the shift calculator in this circuit configuration are as follows. In the equation, i representing the input port is 0 or 1.
bw_1 '= min (bw_in (1), ceil (log ₂ (bw_in (0))) (Calculate the port 1 bit width as the maximum log ₂ (bw_in (0)) bits)
SHF.L (i) = bw_1 '* MUX.delay
SHF.C (i) = 0
SHF.F (0) = 0, SHF.F (1) = 1 (delay synchronization of input port 1)
SHF.AREA = bw_in (0) * bw_1 '* MUX.area

  The logic circuit generation device 1 can output the circuit delay and circuit size estimate calculated by the circuit delay / circuit size evaluation unit 31 of the arithmetic unit to, for example, the output device 17. In another embodiment, the logic circuit generation device 1 may not include the circuit delay / circuit scale evaluation unit 31 of the arithmetic unit. In this case, the logic circuit generation device 1 does not calculate an estimate of the circuit delay and the circuit scale, but since the estimate is not information that directly configures the generated logic circuit, the object of the present invention is achieved. There is no change.

[Pipeline boundary arrangement part 32]
The data flow graph Fdfg in which the circuit delay and the circuit scale of the arithmetic unit are evaluated by the circuit delay / circuit scale evaluation unit 31 of the arithmetic unit is then input to the pipeline boundary arrangement unit 32. The pipeline boundary arrangement unit 32 synthesizes a pipeline circuit from the data flow graph Fdfg and outputs pipeline circuit data Fplc. The pipeline circuit has a structure in which arithmetic processing that is repeatedly executed is divided into processing units called pipeline stages, and circuit blocks that execute these processing units are connected in series. In this specification, the pipeline stage is also referred to as a “pipe stage”.

  The program converted into the data flow graph directly corresponds to the circuit structure of the logic circuit. That is, the operation instruction of the data flow graph corresponds to the arithmetic unit on the circuit, and the directed edge of the data flow graph corresponds to the wiring (or signal) on the circuit. Therefore, synthesizing the pipeline circuit is equivalent to dividing the data flow graph into pipe stages, that is, assigning the pipe stage to each instruction node of the data flow graph. By inserting a register in a data flow directed edge that crosses the pipeline boundary between two adjacent pipe stages, the value input to the register can be referenced at the register output after a delay time of one clock. .

  Therefore, the pipeline boundary arrangement unit 32 first performs a process of extracting constraints when the data flow graph Fdfg is divided into a pipeline structure, and then performs a process of assigning a pipe stage to each instruction node of the data flow graph Fdfg. Do. More specifically, the pipeline boundary arrangement unit 32 includes a pipeline constraint extraction unit 321, a pipeline stage number determination unit 322, and a pipeline circuit synthesis unit 323.

  The pipeline constraint extraction unit 321 performs processing for extracting constraints when the data flow graph Fdfg is divided into pipe stages as preparation for processing in a pipeline circuit synthesis unit 323 described later.

  The register attribute specifies that the value of the variable is stored in a register in which a delay time of one clock occurs between assignment (writing) to the variable and reference (reading) of the variable. Similarly, in the case of a synchronous memory that is normally used, a read time of an array variable having a memory attribute is also delayed by one clock. When synthesizing the pipeline circuit structure, it is necessary to accurately evaluate the referenceable timing of each variable. Since a variable that represents a state variable of a sequential circuit needs to hold a value before and after the clock, it needs to have a register attribute. In the present embodiment, in the program P input to the logic circuit generation device 1, it is essential that register attributes be specified for variables representing state variables of sequential circuits, and register attribute descriptions are omitted. No circuit synthesis is possible. In another embodiment, even if the register attribute description is omitted for a variable representing the state variable of the sequential circuit, the register attribute can be automatically added. In any of the embodiments, the register attribute is added to the state variable of the sequential circuit in the subsequent stage of this process.

  Reference instructions to register variables with one clock delay are classified into the following two types. One is a post-assignment reference instruction. This is a reference instruction to the same variable after the assignment instruction is executed. The other is a pre-assignment reference instruction. This is a reference instruction to the same variable before the assignment instruction is executed.

  The pipeline constraint extraction unit 321 first assigns these reference instructions to the pipe stage. At this time, the post-assignment reference instruction is assigned to a pipe stage that is one backward from the pipe stage including the assignment instruction. That is, a pipeline boundary is sandwiched between the assignment instruction and the post-assignment reference instruction. As a result, the reference timing of the register variable in the post-assignment reference instruction is delayed by one clock from the assignment timing, and the data assigned to the variable by the assignment instruction is read. On the other hand, the pre-assignment reference instruction is assigned to the same pipe stage as the assignment instruction. As a result, the pre-assignment reference instruction reads data before execution of the assignment instruction.

  With reference to FIGS. 32 and 33, processing for assigning a reference instruction to a pipe stage will be described using a specific example. FIG. 32 shows an example of a program including a pre-assignment reference instruction for register variables and a post-assignment reference instruction. FIG. 33 shows a pipeline arrangement in a pipeline circuit generated from the program of FIG. In this example, the pipeline constraint extraction unit 321 is on the path of the reference instruction before assignment (◯ 1), the assignment instruction (○ 3), and (◯ 1) → (○ 3) of the data flow graph Fdfg for the variable stt. An instruction (（2) is assigned to the same pipe stage.

  Next, the pipeline constraint extraction unit 321 performs a register variable update instruction node group grouping process. As described above, the pre-assignment reference instruction for the register variable is assigned to the same pipe stage as the assignment instruction, so that the data before execution of the assignment instruction, that is, the data before one clock is read out. Cannot be assigned to a stage. This is because, when assigned to a pipe stage ahead of the pipe stage of the assignment instruction, the read reference data becomes assignment data two clocks or more before, and the operation intended by the program (that is, assignment one clock before) This is because the circuit of the operation for referring to data) is not realized. Also, all instructions on the data flow graph path from each pre-assignment reference instruction to the assignment instruction (in FIG. 33, the path (◯ 1) → (○ 2) → (○ 3) corresponds to this). Need to be assigned to the same pipe stage. Therefore, the pipeline constraint extraction unit 321 converts the data flow graph Fdfg into a structure that guarantees that these instructions are assigned to the same pipe stage by the processing described below.

  All instruction node groups on the data flow graph path from the reference instruction node before assignment to the register variable to the assignment instruction node to the variable are called register variable update instruction node groups. However, for a pre-substitution reference instruction node that does not have a data flow graph path to the assignment instruction node, only this pre-substitution reference instruction node is included in the register variable update instruction node group. The pipeline constraint extraction unit 321 performs data flow graph conversion processing in which the register variable update instruction node group is replaced with a register variable update degenerate instruction node that has been degenerated into one instruction node. More specifically, all directional branches connecting instruction nodes included in the register variable update instruction node group are removed. Then, the directional branch connecting the instruction node included in the register variable update instruction node group and the external instruction node is reconnected to the register variable update degenerate instruction node. Note that, by this data flow graph conversion processing, all the directed data flow graph directed edges (that is, the directed edges forming a loop) connecting the assignment instruction and the pre-assignment reference instruction are removed.

  FIG. 34 shows a data flow graph Fdfg as a result of performing the register variable update instruction node group grouping process on the data flow graph Fdfg of FIG. In FIG. 33, all instruction node groups (○ 1) on the data flow graph path from the reference instruction node (○ 1) before assignment to the register variable stt to the assignment instruction node (○ 3) to the variable, (○ 2) and (○ 3) are one register variable update instruction node group. The pipeline constraint extraction unit 321 replaces the register variable update instruction node group with register variable update degenerate instruction nodes indicated as (◯ 1) (◯ 2) (◯ 3) in FIG.

  Next, the pipeline constraint extraction unit 321 performs a process of adding a pipeline boundary attribute to the data flow graph directed edge. A pipeline boundary must exist between the register variable assignment instruction and the reference instruction after assignment to the same variable in order to realize a register output delay time of one clock. Therefore, the pipeline constraint extraction unit 321 adds a pipeline boundary attribute to the directed edge of the data flow graph connecting these instructions, and performs pipe stage assignment such that the directed edge intersects the pipeline boundary.

  Further, the reference instruction for the memory array variable is subdivided into an assignment instruction for the read address variable and an array reference instruction using the read address variable as an array index in the register / memory array access instruction decomposition unit 25 described above. . Here, as described above, in order to realize a data read delay time of one clock in the synchronous memory, a pipeline boundary needs to exist between these two instructions. Therefore, the pipeline constraint extraction unit 321 adds a pipeline boundary attribute to the directed edge of the data flow graph corresponding to the read address variable that connects these instructions, and the directed edge intersects the pipeline boundary. Perform pipe stage assignment.

  As described above, synthesizing a pipeline circuit is equivalent to assigning a pipe stage to each instruction node on the data flow graph. The pipeline circuit synthesis unit 323 performs pipe stage initial assignment that satisfies the pipe stage assignment constraint described below, and then changes the pipe stage assignment of each instruction node of the data flow graph Fdfg while propagating the signal of each pipe stage. By performing pipeline delay equalization processing for equalizing time (hereinafter also referred to as “pipeline delay”) and pipeline register number minimization processing for minimizing the number of registers arranged at pipeline boundaries Then, the clock synchronous pipeline circuit Fplc is synthesized from the data flow graph Fdfg. The flow of these processes in the pipeline circuit synthesis unit 323 is shown in FIG. Hereinafter, these processes will be described more specifically. In the following description, the pipe stage of the start node of the directional branch of the data flow graph is called the “start pipe stage” of the directional branch, and the pipe stage of the end node is called the “end pipe stage” of the directional branch. I will decide.

  The pipe stage allocation constraint for each instruction node of the data flow graph Fdfg includes a data dependency constraint and a pipeline boundary constraint described below.

  The directional branch of the data flow graph represents data dependency between the start node (assignment instruction node to variable) and the end node (reference instruction node to variable). Here, it is necessary that the start pipe stage and the end pipe stage of the directional branch are the same or that the start pipe stage is a pipe stage ahead of the end pipe stage. This constraint is called a data dependency constraint.

  The data flow graph directed edge to which the pipeline boundary attribute is added is called a pipeline boundary edge. The pipeline boundary branch needs to be assigned so that the start pipe stage is a pipe stage ahead of the end pipe stage, and cannot be assigned to the same pipe stage. This is called pipeline boundary constraint.

  Also, when the start pipe stage and the end pipe stage are adjacent to each other in the pipeline boundary branch (that is, the pipe stage immediately after the start pipe stage is the end pipe stage), this directed branch is This is called a critical pipeline boundary branch. This is not the pipe stage allocation constraint itself, but an attribute for determining whether the pipeline boundary constraint is satisfied when the pipe stage allocation is changed.

  If a pipeline boundary branch exists, at least two pipe stages are required across the pipeline boundary. When there are a plurality of pipeline boundary branches on one data flow graph path, all of the pipeline boundary branches on the data flow graph path need to cross different pipeline boundaries. The minimum necessary number of pipe stages determined by the pipeline boundary constraint is called a pipeline stage number lower limit value. For example, as shown in FIG. 36, when three pipeline boundary branches exist on one data flow graph path, the pipeline stage number lower limit value is 4. The pipeline stage number determination unit 322 determines the maximum one of the calculated pipeline stage number lower limit value and the pipeline stage number based on the designation of the circuit designer described below as the final pipeline stage number.

  The circuit designer who uses the logic circuit generation device 1 of the present embodiment can specify the clock cycle of the generated logic circuit, or can specify the number of pipeline stages of the generated logic circuit. When the circuit designer designates the clock period, the number of pipeline stages calculated from the clock period is set as the number of pipeline stages based on the designation of the circuit designer. When the circuit designer designates the number of pipeline stages, the number of pipeline stages is set as the number of pipeline stages based on the designation of the circuit designer.

More specifically, when the circuit designer designates the clock period, the number of pipeline stages is calculated such that the maximum signal propagation time of each pipe stage is less than the designated clock period. If the maximum signal propagation time of the entire data flow graph Fdfg before pipeline division is Dtotal and the specified clock period is Dspec, the calculated value PSspec of the pipeline stage is
PSspec = ceil (Dtotal / Dspec)
Is calculated. If the circuit designer specifies the number of pipeline stages, the specified value is PSspec. In either case, if the lower limit value of the pipeline stage number is PSmin, the final pipeline stage PS is
PS = max (PSspec, PSmin)
Is calculated.

  The pipeline circuit synthesis unit 323 first performs a pipe stage initial allocation process in which a pipe stage is allocated to each instruction so as to satisfy the pipe stage allocation constraint. The assignment of pipe stages to instructions in this process is called pipe stage initial assignment. This process is realized by a simple process in which each instruction on the data flow graph path is sequentially assigned from the preceding pipe stage while following each instruction in the forward direction (ie, from the input side to the output side).

  Next, the pipeline circuit synthesis unit 323 performs pipeline delay equalization processing and pipeline register minimization processing. In these processes, the process of locally changing the pipeline boundary determined from the pipe stage assignment (that is, changing the pipe stage assignment of one instruction node) is repeated. The instruction nodes that can change the pipe stage assignment while satisfying the pipe stage assignment constraint are limited to the pipe stage output border node and the pipe stage input border node described below.

Pipe stage output border node is a certain instruction node.
(1) The end pipe stages of all directed branches of the data flow graph starting from the instruction node are located behind the pipe stage of the instruction node (that is, the starting pipe stage of the directed branch), and
(2) An instruction node having no critical pipeline boundary branch starting from the instruction node. The pipe stage output border node can move to the rear pipe stage.

The pipe stage input border node is an instruction node.
(1) The start pipe stage of all the directed branches of the data flow graph having the instruction node as an end point is located in front of the pipe stage of the instruction node (that is, the end pipe stage of the directed branch), and
(2) An instruction node in which there is no critical pipeline boundary branch whose end point is the instruction node. The pipe stage input border node can move to the preceding pipe stage.

  An objective function for determining whether or not each local change is “useful” in the pipeline boundary local change process will be described. This objective function is defined as follows depending on the purpose of the local change processing of the pipeline boundary.

The purpose of the pipeline delay equalization process is to maximize the operation clock frequency of the entire circuit by equalizing the signal propagation time of each pipe stage. Here, when the maximum signal propagation time of the nth pipe stage is D (n), the objective function E1 of the pipeline delay equalization process is defined by the following equation.
E1 = Σ _n D (n) ²
That is, the sum of squares of the maximum signal propagation times of individual pipe stages is used as the objective function here. The pipeline circuit synthesis unit 323 equalizes the maximum signal propagation time of each pipeline stage by adjusting the pipeline boundary so as to minimize the objective function. In the present embodiment, the maximum signal propagation time D (n) of the pipe stage is calculated based on the circuit delay of the arithmetic unit evaluated by the circuit delay / circuit scale evaluation unit 31 of the arithmetic unit.

In the pipeline register number minimization process, an object is to minimize the circuit area by minimizing the number of registers inserted on the directed edge of the data flow graph crossing each pipeline boundary. . Here, the bit width of the variable corresponding to the directed edge of the data flow graph is referred to as the weight of the directed edge. The objective function E2 is defined by the following equation, where R (n) is the total weight of the directed edge of the data flow graph that crosses the pipeline boundary on the output side of the nth pipe stage.
E2 = Σ _n R (n)
That is, the sum of the weights of the data flow graph directed edges that cross the pipeline boundary is used as the objective function here. The pipeline circuit synthesis unit 323 minimizes the number of pipeline registers by adjusting the pipeline boundary so as to minimize the objective function.

Furthermore, in addition to the objective functions E1 and E2 in the pipeline delay equalization process and pipeline register number minimization process, an evaluation function of the following expression that finally determines the operation clock frequency of the entire pipeline circuit is defined. .
Dmax = max {D (n) | n ∈ all pipe stages}
Local changes to the pipeline boundary that increase this Dmax are prohibited.

  In this embodiment, an annealing method (Simulated Annealing method, also referred to as “SA method” in this specification) is used as a method for controlling the local change processing of the pipeline boundary. With reference to FIG. 37, the SA method performed by the pipeline circuit synthesis unit 323 will be described more specifically.

  First, an appropriate initial value is set for the temperature T which is a parameter of the SA method. The meaning of temperature T will be described later.

  Next, one instruction node is randomly selected from the pipe stage output border node and the pipe stage input border node, and the pipe stage assignment is changed in a movable direction. Here, if the maximum pipeline delay Dmax before the pipe stage assignment change (described above) and the maximum pipeline delay D'max after the pipe stage assignment change, if Dmax <D'max, the pipe stage assignment change Reject and return to pipe stage assignment before change. If Dmax> = D'max, the process proceeds to the following process.

Next, using the objective function defined above (E1 or E2), the pipe stage allocation change cost ΔC, which is the difference between the objective function value E before the pipe stage allocation change and the objective function value E ′ after the change, is calculated. calculate. That is,
ΔC = E-E '
And

Next, an adoption threshold for probabilistically determining whether or not to adopt a pipe stage assignment change from the pipe stage assignment change cost ΔC is defined by the following equation.
P = exp (ΔC / T)
In this equation, T is a parameter that takes a positive real value called “temperature” in the SA method for controlling the adoption probability of allocation change.

Next, in order to finally determine whether to adopt the pipe stage allocation change, a random number R between 0 and 1 is generated, and one of the following is executed according to the relationship between P and R.
(1) If R <P, change pipe stage allocation. Also, compare the minimum evaluation values Emin and E 'of the pipe stage assignment objective function so far, and if Emin>E', set Emin = E 'and update the optimum pipe stage assignment solution.
(2) When R> = P, the pipe stage assignment change is rejected and the state before the pipe stage assignment change is restored.
Note that in the case of pipe stage allocation change in which the objective function value decreases, that is, when ΔC = E = E '<0, the adoption threshold P is greater than 1, so (1) above is always executed and the pipe stage Allocation changes are adopted.

  Next, the temperature T is updated. The temperature T is set to a relatively large value (that is, “hot”) in the initial stage, and the probability of adopting a pipe stage assignment change that increases the objective function value is increased, so that the local optimum solution of the pipe stage arrangement is increased. Make it easy to escape from. As the allocation change process proceeds, the temperature T is gradually decreased (that is, “cooled”), so that it is controlled to approach the global optimum solution of the pipe stage arrangement.

  The above processing from the selection of the node to the update of the temperature T is repeated until the temperature T falls below a predetermined value. The above-described optimal solution when the temperature T falls below a predetermined value is the result of pipeline delay equalization processing and pipeline register minimization processing by the SA method.

[RTL description output unit 33]
The pipeline circuit data Fplc output by the pipeline boundary arrangement unit 32 is then input to the RTL description output unit 33. The logic circuit generation device 1 in the present embodiment outputs the generated logic circuit in the RTL description format. Therefore, the RTL description output unit 33 converts the input pipeline circuit data Fplc into an RTL description. Since the expression of the logic circuit by the RTL description is a well-known technique, the specific description is omitted here. However, the pipeline circuit data Fplc is a data flow graph, and the data flow graph is a circuit of the logic circuit as described above. Since it corresponds to the structure, it can be expressed as it is by RTL description. In order to achieve the object of the present invention, the output format of the logic circuit generation device 1 is not limited to the RTL description format, and may be any appropriate format describing the logic circuit. That is, the logic circuit generation device 1 of the present invention generally includes a logic circuit description output unit, and the logic circuit description output unit in the present embodiment is an RTL description output unit 33 that outputs an RTL description.

  The RTL description converted by the RTL description output unit 33 is output from the logic circuit generation device 1 as the logic circuit description D. The above is the description of each unit of the logic circuit generation device 1 in the present embodiment.

  Next, some examples of the embodiment of the logic circuit generation device 1 of the present invention will be described with reference to FIGS. In each figure, the portion shown in light color is shown in order to contrast the constituent elements not included in the logic circuit generation device 1 in the embodiment shown in the figure with other embodiments.

  The logic circuit generation device 1 of the embodiment shown in FIG. 38 includes a control flow graph generation unit 23, a control flow degeneration conversion unit 28, a data flow graph generation unit 29, and an RTL description output unit (logic circuit description output unit). 33. The control flow degeneration conversion unit 28 includes a basic block unification unit 282. The logic circuit generation device 1 of this embodiment takes as input a program P described in a static single assignment format that does not include a function call instruction or a loop control unit, and does not include an array access instruction using a variable as an index. The logic circuit description D is output. The input signal and output signal of the logic circuit can be explicitly specified in the program P.

  The logic circuit generation device 1 of the embodiment shown in FIG. 39 further includes a static single assignment format conversion unit 27 in addition to the embodiment of FIG. The control flow degeneration conversion unit 28 further includes a φ function instruction materialization unit 281. Since the logic circuit generation device 1 of the present embodiment converts the input program P into the static single assignment format internally, the program P taken by the logic circuit generation device 1 as an input is not necessarily the static single assignment format. It does not have to be described in.

  The logic circuit generation device 1 of the embodiment shown in FIG. 40 further includes a register / memory array access instruction decomposition unit 25 and a memory port number determination unit 26 in addition to the embodiment of FIG. The control flow degeneration conversion unit 28 further includes a register / memory array instruction fusion unit 283. The logic circuit generation device 1 of the present embodiment can take a program P including an array access instruction with a variable as an index, and a logic circuit description D representing a logic circuit including a multiport register file and a multiport memory. Can be generated.

  In addition to the embodiment of FIG. 38, the logic circuit generation device 1 of the embodiment shown in FIG. 41 includes a data flow graph optimization unit 30, a circuit delay / circuit scale evaluation unit 31, and a pipeline boundary arrangement unit. 32 is further provided. The logic circuit generation device 1 according to the present embodiment can output an optimized pipeline circuit description. Further, the logic circuit generation device 1 according to the present embodiment can calculate the circuit delay and the circuit scale estimate of the logic circuit to be generated.

  The logic circuit generation device 1 of the embodiment shown in FIG. 42 further includes a logic circuit input / output signal extraction unit 22 in addition to the embodiment of FIG. Since the logic circuit generation device 1 of the present embodiment extracts the input signal and output signal of the logic circuit to be generated, these signals do not need to be explicitly specified from the outside of the logic circuit generation device 1. .

  The logic circuit generation device 1 of the embodiment shown in FIG. 43 further includes an acyclic / non-hierarchical conversion unit 21 in addition to the embodiment of FIG. The logic circuit generation device 1 of the present embodiment internally converts the highest function Ftop included in the input program P into an acyclic bottom layer function Fexp, so that the highest function Ftop included in the input program P is converted. Need not be an acyclic bottom layer function.

The logic circuit generation device 1 of the embodiment shown in FIG. 44 further includes a state variable instruction dependency determination unit 24 in addition to the embodiment of FIG. The logic circuit generation device 1 according to the present embodiment, when a program P is input in which an assignment instruction, a reference instruction, and an assignment instruction are successively executed in this order for the same state variable, Stop processing to be generated.

Claims (23)

A logic circuit generation device that takes a program including a top-level function to be generated as a logic circuit generation target describing an operation description, which is a flow of a series of hardware processes for circuit design, and generates a logic circuit description. ,
A control flow graph generation unit that generates a control flow graph from the top-level function that does not include a loop processing unit and a function call instruction;
Control flow degenerative transformation that generates a control flow degenerate program that is a program in which the control flow is degenerated by removing all conditional branch instructions from the control flow graph including only one assignment instruction for variables for each variable. And
From the control flow degeneracy program, each instruction of the control flow degeneration program is a node, and a data flow graph is generated by adding a directional branch from an assignment instruction to each variable to an instruction that refers to the variable. A data flow graph generator,
A logic circuit description output unit that generates a logic circuit description representing a sequential circuit in which the directed edge of the data flow graph corresponds to a wiring of a logic circuit and the node of the data flow graph corresponds to an arithmetic unit of the logic circuit. When,
With
The state variable representing the state of the sequential circuit is expressed in the program as a local variable or a static variable of an upper layer function that calls the top function,
The value of the state variable before execution of the assignment instruction to the state variable represents the current state of the sequential circuit, and the value of the state variable after execution of the assignment instruction to the state variable is the sequential circuit. A logic circuit generation device characterized by representing a next state of The logic circuit generation device according to claim 1,
If the top-level function is not in a static single assignment form that includes only one assignment instruction for a variable for each variable, the control flow graph is statically input before being input to the control flow degeneration conversion unit. A static single assignment format conversion unit for converting to a single assignment format is further provided.
The static single assignment format conversion unit includes:
In the control flow graph, a φ function instruction for selecting a variable definition on the actually executed path is inserted from all the variable definitions that merge at the location where a plurality of value definitions for the same variable merge. , Φ function instruction insertion part,
By converting the name of each variable included in the control flow graph so as to have a different name for each assignment instruction for the variable, the control flow graph includes only one assignment instruction for each variable after the name conversion. A variable name conversion unit that converts to a static single assignment form;
About the state variable after the name conversion, a state variable name reconverting unit that converts the variable name again so as to match the variable name in the start block of the control flow graph and the variable name reaching the end block;
Including
The control flow degeneration conversion unit includes a φ function instruction materializing unit that converts the φ function instruction into a specific operation instruction.
A logic circuit generation device characterized by that. The logic circuit generation device according to claim 1 or 2,
When the top-level function includes an array assignment instruction that is a write processing instruction for an array variable,
For each array variable, add a write data variable and a write address variable to the control flow graph,
An array determined by assigning each array assignment instruction to an assignment value to the write data variable, an instruction to assign an array index value to the write address variable, and an array index as the write address variable Disassembled into an instruction that assigns the value of the write data variable to the element;
An array assignment instruction decomposition unit;
When the top-level function includes an array reference instruction that is a read processing instruction for an array variable,
For each array variable, add a read address variable to the control flow graph,
Decomposing each array reference instruction into an instruction that assigns an array index value to the read address variable and an instruction that refers to an array element determined by using the read address variable as an array index.
An array reference instruction decomposition unit;
A register / memory array access instruction decomposition unit including
Memory for holding each array element data in the logic circuit is
The write data variable corresponds to a write data port of the memory;
The write address variable corresponds to a write address port of the memory;
The read address variable corresponds to a read address port of the memory;
The control flow graph generated by the control flow graph generation unit is processed by the register / memory array access instruction decomposition unit and then processed by the control flow degeneration conversion unit. . The logic circuit generation device according to claim 3,
The register / memory array access instruction decomposition unit includes:
For each array assignment instruction for each array variable in the control flow graph, the array array instruction is executed with the maximum value of the number of executions of the array assignment instruction to the array variable executed between the start point block and the array assignment instruction as the write port number. A write port number assigning section to be assigned to an assignment instruction;
For each array reference instruction for each array variable in the control flow graph, the maximum number of execution times of the array reference instruction to the array variable executed between the start point block and the array reference instruction is used as the read port number. A read port number assigning unit assigned to a reference instruction;
Further including
The array assignment instruction decomposition unit adds the write data variable and the write address variable to the control flow graph for each write port number for each array variable, and adds the read address for each read port number. Add variables to the control flow graph,
The memory for holding each array element data includes the same number of write ports as the number of write port numbers assigned to the array variable assignment instruction, and the read port number assigned to the reference instruction of the array variable. A logic circuit generation device having the same number of read ports. The logic circuit generation device according to claim 4,
It is determined whether or not the number of the write port numbers assigned by the write port number assigning unit is equal to or less than a predetermined write memory port number threshold, and the read port number assigned by the read port number assigning unit A memory port number determination unit for determining whether the number is equal to or less than a predetermined read memory port number threshold;
Further comprising
If the number of write port numbers is less than or equal to a predetermined write memory port number threshold, or if the number of read port numbers is less than or equal to a predetermined read memory port number threshold, a logic circuit description The logic circuit generation device is characterized in that the processing for generating the logic circuit is stopped. In the logic circuit generation device according to any one of claims 1 to 5,
The inputted program includes an attribute description for giving an attribute to each variable, and the attribute is
A bit width attribute that specifies the bit width of the variable's data,
A register attribute that specifies that the value of the variable is held in the register, and
A memory attribute that specifies that the value of the array element of the array variable is retained in memory, and
Including
An apparatus for generating a logic circuit, comprising: a logic circuit description including a sequential circuit in which a state is expressed by using a variable having the register attribute or the memory attribute as the state variable. The logic circuit generation device according to claim 6,
For a variable included in the data flow graph, the bit width of the variable is calculated from the bit width of the variable and / or constant referenced in the assignment instruction for the variable and the type of operation executed in the assignment instruction. A bit width determination unit;
An arithmetic circuit delay evaluation unit that calculates a signal propagation delay time of an arithmetic unit based on a bit width calculated for a variable included in the data flow graph;
A pipeline boundary arrangement unit including a pipeline constraint extraction unit and a pipeline stage number determination unit;
Further comprising
The pipeline constraint extraction unit adds a pipeline boundary attribute to a directional branch between an arithmetic unit that executes an assignment instruction for the state variable and an arithmetic unit that executes a reference instruction for the state variable in the data flow graph. And
The pipeline stage number determining unit is configured to determine a pipeline stage number used to generate a circuit description of a clock synchronous pipeline circuit as a pipeline number that is a minimum necessary pipeline stage number determined by a constraint based on the pipeline boundary attribute. A logic circuit generation apparatus, comprising: a stage number lower limit value, and a pipeline stage number calculated from a designated clock period or a pipeline stage number designated in advance. In the logic circuit generation device according to any one of claims 1 to 7,
A logic circuit input signal extraction unit that extracts an input signal of a circuit to be described by the circuit description from an argument of the top-level function and a global variable;
A logic circuit output signal extraction unit that extracts an output signal of a circuit to be described by the circuit description from an argument and a return value of the top-level function and a global variable;
The logic circuit generation device further comprising: The logic circuit generation device according to any one of claims 1 to 8,
A complete inline expansion unit that converts the top-level function into a lowest-level function that does not include a function call instruction by inlining each function call instruction when the top-level function includes a function call instruction;
When the lowermost layer function converted by the complete inline expansion unit includes a loop processing unit having a fixed number of repetitions, the lowermost function is loop-processed by expanding each loop processing unit having a fixed number of repetitions. A complete loop expansion part that converts to a non-circular bottom layer function that does not include a part,
A non-circular / non-hierarchical conversion unit including
The program input to the logic circuit generation device is converted into a non-circular bottom layer function by the non-circular / non-hierarchical conversion unit and then input to the control flow graph generation unit Generator. The logic circuit generation device according to claim 9, wherein
The complete inline expansion unit determines that the function cannot be converted into a lowermost layer function when the function call instruction is not fully expanded even if the inline expansion is repeated a predetermined number of times for the input function. Configured to stop processing,
When the input function includes a loop processing unit whose number of iterations is not a constant, the complete loop expansion unit determines that the function cannot be converted into an acyclic bottom layer function and stops the processing. Configured as
When the complete inline expansion possibility determination unit stops processing, or when the complete loop expansion possibility determination unit stops processing, a logic circuit that stops generating a logic circuit description Generator. In the logic circuit generation device according to any one of claims 1 to 10,
In the control flow graph, a state variable instruction dependency determination unit that determines whether or not an assignment instruction, a reference instruction, and an assignment instruction are continuously executed in this order for the same state variable is further provided Prepared,
When the state variable instruction dependency determining unit determines “No”, the process of generating the logic circuit description is stopped.
Performed by a logic circuit generation device that takes as input a program that includes a top-level function for generating a logic circuit that describes an operation description, which is a flow of a series of hardware processing for circuit design, and generates a logic circuit description. A logic circuit generation method comprising:
The logic circuit generation device includes:
A control flow graph generation step of generating a control flow graph from the top-level function not including a loop processing unit and a function call instruction;
Control flow degenerative transformation that generates a control flow degenerate program that is a program in which the control flow is degenerated by removing all conditional branch instructions from the control flow graph including only one assignment instruction for variables for each variable. Steps,
From the control flow degeneracy program, each instruction of the control flow degeneration program is a node, and a data flow graph is generated by adding a directional branch from an assignment instruction to each variable to an instruction that refers to the variable. A data flow graph generation step;
A logic circuit description generating step for generating a logic circuit description representing a sequential circuit in which the directed edge of the data flow graph corresponds to a wiring of a logic circuit and the node of the data flow graph corresponds to an arithmetic unit of the logic circuit. When,
And
The state variable representing the state of the sequential circuit is expressed in the program as a local variable or a static variable of an upper layer function that calls the top function,
The value of the state variable before execution of the assignment instruction to the state variable represents the current state of the sequential circuit, and the value of the state variable after execution of the assignment instruction to the state variable is the sequential circuit. A logic circuit generation method characterized by representing a next state of The logic circuit generation method according to claim 12, wherein
When the highest-order function is not a static single assignment form including only one assignment instruction for a variable for each variable, the logic circuit generation device displays the control flow graph before the control flow degeneration conversion step. Further performing a static single assignment form conversion step to convert to a static single assignment form,
The static single assignment format conversion step includes:
In the control flow graph, a φ function instruction for selecting a variable definition on the actually executed path is inserted from all the variable definitions that merge at the location where a plurality of value definitions for the same variable merge. , Φ function instruction insertion step,
By converting the name of each variable included in the control flow graph so as to have a different name for each assignment instruction for the variable, the control flow graph includes only one assignment instruction for each variable after the name conversion. A variable name conversion step for converting to a static single assignment form;
About the state variable after the name conversion, a state variable name re-conversion step that converts the variable name again so that the variable name in the start block of the control flow graph matches the variable name reaching the end block;
Including
The control flow degeneration conversion step further includes a φ function instruction instantiation step for converting the φ function instruction into a specific operation instruction.
A logic circuit generation method characterized by the above. The logic circuit generation method according to claim 12 or 13,
The logic circuit generation device performs the control when the top-level function includes an array assignment instruction that is a write processing instruction for an array variable and / or includes an array reference instruction that is a read processing instruction for an array variable. Before the flow degeneration conversion step, a register / memory array access instruction decomposition step for decomposing the array assignment instruction and / or the array reference instruction of the control flow graph is further performed.
The register / memory array access instruction decomposition step comprises:
For each array variable, add a write data variable and a write address variable to the control flow graph,
An array determined by assigning each array assignment instruction to an assignment value to the write data variable, an instruction to assign an array index value to the write address variable, and an array index as the write address variable Disassembled into an instruction that assigns the value of the write data variable to the element;
An array assignment instruction decomposition step;
For each array variable, add a read address variable to the control flow graph,
Decomposing each array reference instruction into an instruction that assigns an array index value to the read address variable and an instruction that refers to an array element determined by using the read address variable as an array index.
An array reference instruction decomposition step;
Including
Memory for holding each array element data in the logic circuit is
The write data variable corresponds to a write data port of the memory;
The write address variable corresponds to a write address port of the memory;
The read address variable corresponds to a read address port of the memory;
A logic circuit generation method characterized by the above. The logic circuit generation method according to claim 14,
The register / memory array access instruction decomposition step consists of:
For each array assignment instruction for each array variable in the control flow graph, the array array instruction is executed with the maximum value of the number of executions of the array assignment instruction to the array variable executed between the start point block and the array assignment instruction as the write port number. A write port number assignment step assigned to an assignment instruction;
For each array reference instruction for each array variable in the control flow graph, the maximum number of execution times of the array reference instruction to the array variable executed between the start point block and the array reference instruction is used as the read port number. A read port number assignment step assigned to a reference instruction;
Further including
The array assignment instruction decomposition step adds, for each write port number, the write data variable and the write address variable to the control flow graph for each array variable, and for each read port number, the read address Adding a variable to the control flow graph;
Each array having the same number of write ports as the number of write port numbers assigned to the array variable assignment instruction and the same number of read ports as the number of read port numbers assigned to the array variable reference instructions A description of the memory for holding element data is generated;
A logic circuit generation method characterized by the above. The logic circuit generation method according to claim 15, wherein
The logic circuit generation device further performs a memory port number determination step,
The memory port number determination step includes:
Determining whether the number of write port numbers assigned in the write port number assignment step is less than or equal to a predetermined threshold;
Determining whether the number of read port numbers assigned in the read port number assigning step is less than or equal to a predetermined threshold;
Further including
When the number of the write port numbers or the number of the read memory ports exceeds a threshold value, the logic circuit generation device stops a process of generating a logic circuit description. The logic circuit generation method according to any one of claims 12 to 16,
The inputted program includes an attribute description for giving an attribute to each variable, and the attribute is
A bit width attribute that specifies the bit width of the variable's data,
A register attribute that specifies that the value of the variable is held in the register, and
A memory attribute that specifies that the value of the array element of the array variable is retained in memory, and
Including
The logic circuit generation device generates a circuit description including a sequential circuit in which a state is expressed by using a variable having the register attribute or the memory attribute as the state variable.
A logic circuit generation method characterized by the above. The logic circuit generation method according to claim 17, wherein
The logic circuit generation device includes:
For a variable included in the data flow graph, the bit width of the variable is calculated from the bit width of the variable and / or constant referenced in the assignment instruction for the variable and the type of operation executed in the assignment instruction. A bit width determination step;
An arithmetic circuit delay evaluation step for calculating a signal propagation delay time of an arithmetic unit based on a bit width calculated for a variable included in the data flow graph;
A pipeline boundary placement step including a pipeline constraint extraction step and a pipeline stage number determination step;
And further
In the pipeline constraint extraction step, a pipeline boundary attribute is added to a directional branch between an arithmetic unit that executes an assignment instruction for the state variable and an arithmetic unit that executes a reference instruction for the state variable in the data flow graph. And
In the pipeline stage number determining step, the pipeline stage number used for generating the circuit description of the clock synchronous pipeline circuit is a pipeline stage number that is the minimum necessary pipeline stage number determined by the constraint based on the pipeline boundary attribute. A logic circuit generation method, comprising: determining according to a stage number lower limit value and a pipeline stage number calculated from a designated clock cycle or a pipeline stage number designated in advance. The logic circuit generation method according to any one of claims 12 to 18,
The logic circuit generation device, before the control flow graph generation step,
A logic circuit input signal extraction step for extracting an input signal of a circuit to be described by the circuit description from an argument of the top-level function and a global variable;
A logic circuit output signal extraction step of extracting an output signal of a circuit to be described by the circuit description from an argument and a return value of the top-level function and a global variable;
A logic circuit generation method, further comprising: The logic circuit generation method according to any one of claims 13 to 19,
The logic circuit generation device may perform a non-control flow graph generation step before the control flow graph generation step when the highest function includes a function call instruction and / or when the highest function includes a loop processing unit having a fixed number of repetitions. Perform further circular / non-hierarchical transformation steps,
The acyclic / non-hierarchical conversion step includes:
A fully inline expansion step of transforming the top-level function into a lowest-level function not including a function call instruction by inlining each function call instruction;
A complete loop unrolling step of transforming the lowest layer function into a non-circular bottom layer function not including a loop processing unit by loop unrolling each fixed iteration number of loop processing units;
A logic circuit generation method comprising: The logic circuit generation method according to claim 20,
In the complete inline expansion step, when the function call instruction is not completely expanded even if the inline expansion for the input function is repeated a predetermined number of times, it is determined that the function cannot be converted into the lowest layer function. Stop
If the input function includes a loop structure in which the number of iterations is not a constant, the complete loop expansion step determines that the function cannot be converted into an acyclic bottom layer function, and stops processing.
When the process is stopped in the complete inline expansion step, or when the process is stopped in the complete loop expansion step, the logic circuit generation device stops the process of generating the logic circuit description.
A logic circuit generation method characterized by the above. The logic circuit generation method according to any one of claims 13 to 21,
The logic circuit generation device includes:
In the control flow graph, a state variable instruction dependency determining step for determining whether or not an assignment instruction, a reference instruction, and an assignment instruction are continuously executed in this order for the same state variable is further included Done
A logic circuit generation method characterized by stopping the process of generating a logic circuit description when it is determined as “No” in the state variable instruction dependency determining step. A logic circuit generation computer program for causing a computer to execute each step of the logic circuit generation method according to any one of claims 12 to 22.

Images