JP5835821B1 - Statistical information memory system, network device, and statistical information storage method - Google Patents

Abstract

Statistical information that is sequentially input is accumulated at high speed and efficiently with a less expensive memory configuration. A coarse-grained memory for storing each coarse-grained statistical information, and a fine-grained memory for temporarily storing fine-grained statistical information from a host device by operating at high speed with a smaller storage capacity than the coarse-grained memory. 11 are arranged in series, and the update processing unit STA stores the fine-grained statistical information temporarily stored in the fine-grained memory 11 in accordance with the access period of the coarse-grained memory 12 and is stored in the coarse-grained memory 12. The coarse-grained statistical information is updated sequentially. [Selection] Figure 1

Description

  The present invention relates to a memory system technology, and more particularly to a statistical information storage technology for performing high-speed acquisition and storage of statistical information in a network device such as a router for the purpose of optimization and management of the entire network.

FIG. 7 is an explanatory diagram showing a general network configuration using an IP router. Here, four IP routers R1, R2, R3, and R4 are individually connected on a one-to-one basis via communication lines L1, L2, L3, L4, L5, and L6.
In such a network configuration, when a failure occurs in L1 connecting R1 and R2, R1 exchanges route information between adjacent R3 and R4, and selects another route, for example, R1 → R3 → R2. Maintain communication with R2. When the failure is recovered, R1 similarly exchanges route information between adjacent R3 and R4, and reselects the original route R1 → R2. In this way, a network is realized in which communication does not stop even if a line failure occurs.

  FIG. 8 is a block diagram showing an internal configuration of a conventional IP router. The packet input unit 51 uses the lookup table 51A to analyze the header information of the IP packet that has arrived on the input line 31, and uses the destination search unit 51B to search the destination of the incoming IP packet based on the obtained analysis result. And a function of discarding a packet by the destination search unit 51B based on a discard instruction from the packet output unit 53. As an advanced analysis process, for example, a source / destination IP address called 5-tuple, a protocol number, a source / destination port number (L3 Src., L3 Dst., #Protocol, L4 Src., L4 There is a processing method for analyzing flow information or the like by a combination of five attribute values consisting of Dst.).

The packet switching unit 52 rewrites or switches the header information for the arrival packet based on the destination searched by the packet input unit 51, and outputs it to the queue (queue) of the packet output unit 53 corresponding to the destination. have.
The packet output unit 53 has a queue for temporarily accumulating packets for each output line 32, and sequentially outputs the packets accumulated in each queue to the corresponding output line 32, and hardware-implemented resources. It has a function of dropping a packet when exceeding packets are accumulated, and instructing the packet input unit 51 to discard the packet.

Japanese Patent Laid-Open No. 2006-5402 JP 2008-250834 A

National Institute of Information and Communications Technology, NTT Future Network Research Laboratories, KDDI Research Laboratories, Hitachi, NEC, Osaka University, “Time-varying information distribution network architecture design version Version 1.1 (2013.9.1)”, “5. Elemental technologies”, 2013 September

However, the above-described conventional IP router controls and sets each device installed in the network independently. Therefore, when rebuilding the entire network, for example, bandwidth control for priority designation or power saving, or emergency measures in the event of a failure, grasp the status of all devices and set each device individually. There was a problem that had to be done.
In addition, since the amount of traffic on the network varies characteristically with time, it is possible to expect significant power savings by reconstructing an optimal network in each time zone using this feature (Non-patent Document 1). In conventional IP routers, it is difficult to dynamically collect information on the status of all devices as described above.

  Furthermore, in a network constructed with conventional IP routers, the administrator must reconfigure all IP routers in the network, for example, when setting priorities (QoS: Quality of Service) corresponding to applications. I must. In a limited network or LAN network, this arrangement may cause a wasteful route due to excessive service, power consumption by a router, and a load on an administrator related to a setting change.

  SDN (Software Defined Network) is a new network specification proposed under such a background. FIG. 9 is a configuration example of a network based on SDN. Here, all the routers R1, R2, R3, and R4 in the network each have an SDN-compatible function, are connected to the SDN controller (server) SV via the SDN, and are managed by the SV software. As a result, when the traffic volume decreases at night or on weekends, unnecessary communication lines and routers can be cut off to reduce power consumption, and optimal load distribution and priority control can be performed while monitoring the traffic volume between routers. Can manage.

  As described above, according to SDN, the status of each router can be intensively grasped by SV. Therefore, an administrator can obtain information on the entire network at any time and can be installed in the network only by software installed in SV. All routers can be set and changed dynamically and centrally.

  OpenFlow (registered trademark) is known as a representative of SDN. Routers installed in the OpenFlow environment have hardware specifications different from those of conventional IP routers, and are manufactured and sold by manufacturers separately from IP routers. Therefore, for example, when attempting to change an existing network to be compatible with SDN, all IP router devices must be changed to routers that support SDN, and functions for realizing operations and processing contents required in SDN must be added. I must.

As one of main functions for supporting SDN in an existing IP router, there is a function of acquiring and storing statistical information indicating its own operation status from a packet. This is because, in response to a request from the SV, it is necessary to notify its own operation status, specifically, statistical information regarding the flow of the packet transferred by itself.
Such statistical information is set in detail for each port and queue. FIG. 10 is an example of statistical information required for OpenFlow. Since the IP router is provided with a plurality of these ports and queues, the statistical information to be acquired / stored is extremely large.

  Therefore, in order to acquire such statistical information from a packet and store it for each item, it is necessary to operate at a high speed and have a large capacity memory. Common semiconductor memories used for storing statistical information include SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory). SRAM can operate at high speed but is expensive, and DRAM is inexpensive but operates at low speed. Therefore, it is difficult to accumulate statistical information on a large number of statistical items input sequentially from a host device at a high speed with a single hardware component.

  Conventionally, a technique combining SRAM and DRAM has been proposed as a memory configuration for storing various types of information extracted from packets (see Patent Document 1). FIG. 11 is a block diagram showing a conventional memory configuration. In this example, the SRAM 61 and the DRAM 62 are arranged in parallel, and the flow identification conditions for identifying the statistical information to be accumulated are accumulated in a flow table composed of the SRAM 61 in order to realize high-speed search. Statistical information extracted from a packet that satisfies any one of the identification conditions is stored in a statistical information table composed of the DRAM 62.

  Also, fixed-length header information with a relatively small amount of data acquired from a packet is stored at high speed in the packet header storage memory, and variable-length packet data with a relatively large amount of data is stored in the packet data storage memory. ing. Therefore, it can be considered that the header information is stored in the SRAM 61 and the packet data is stored in the DRAM 62 using the SRAM or DRAM.

  However, according to such a memory configuration, the information to be stored is stored in the SRAM or DRAM according to the purpose of use and the amount of data. In the SDN that needs to be stored at high speed, there is a problem in that the storage is concentrated only on one of them and statistical information cannot be stored efficiently.

  In order to achieve such an object, a statistical information memory system according to the present invention aims to provide a statistical information storage technique capable of storing statistical information that is sequentially input at high speed and efficiently with a cheaper memory configuration. It is said.

In order to achieve such an object, the statistical information memory system according to the present invention, for each statistical item, provides fine-grained statistical information, which is a statistical value with a fine temporal granularity regarding statistical items , that is sequentially input from a host device. in a statistics memory system computes the coarse grain statistics is rough statistics of time granularity by statistical processing, storing calculation results obtained as a new coarse grain statistics, relating to the statistic The coarse-grained memory for accumulating the coarse-grained statistical information, and the fine-grained granularity related to the statistical items sequentially input from the host device, operating at high speed and having a smaller storage capacity than the coarse-grained memory The fine-grained memory for temporarily storing statistical information and the fine-grained memory temporarily stored in the fine-grained memory in accordance with the access period of the coarse-grained memory. In degrees statistics and an update processing unit that the accumulated coarse granularity memory said sequential updating coarse grain statistics are.

Also, in one configuration example of the statistical information memory system according to the present invention, the update processing unit sequentially selects the target statistics selected as the update target from among all the statistical items in accordance with the access period of the coarse-grained memory. For each item, the coarse-grained statistical information related to the target statistical item stored in the coarse-grained memory is updated with all the fine-grained statistical information related to the target statistical item temporarily stored in the fine-grained memory. The obtained coarse granularity statistical information is written into the coarse granularity memory as new coarse granularity statistical information relating to the target statistical item.

In addition, one configuration example of the statistical information memory system according to the present invention sequentially selects the target statistical item to be updated from all the statistical items for each access period of the coarse-grained memory, and updates the update The image processing apparatus further includes an update control unit that instructs the processing unit to update the coarse-grained statistical information regarding the target statistical item.

In addition, one configuration example of the statistical information memory system according to the present invention includes a plurality of update processing units that execute update of the coarse-grained statistical information regarding different target statistical items in parallel, and the update control unit includes: In addition, for each access cycle to the coarse-grained memory, a plurality of the target statistical items to be updated are selected from all the statistical items , and the update processing unit updates the coarse-grained statistical information related to the target statistical items. Each is individually instructed.

  Also, in one configuration example of the statistical information memory system according to the present invention, after the fine-grained memory transfers the updated new coarse-grained statistical information to the coarse-grained memory, a new fine-grained granularity is given to itself. Statistic information is accumulated and it is detected whether or not it has been updated. If no update is detected during the next update process, communication between the fine-grained memory and the coarse-grained memory is performed. It is intended to block.

In addition, according to an exemplary configuration of the statistical information memory system according to the present invention, the number of statistical items is N [number], the communication required time between memories is Td [s], the packet throughput is T [bps], When the packet length is L [bit] and the bit length of the fine-grained memory is W [bit], the fine-grained memory is set to the minimum W satisfying the following expression 2 ^W ≧ N × Td × T / L It has a storage capacity C = W × N [bit] obtained by multiplying N.

  A network device according to the present invention includes the above-described statistical information memory system, and accumulates statistical information regarding packets arriving in the statistical information memory system.

The statistical information accumulating method according to the present invention is obtained by performing statistical processing for each statistical item, with fine granularity statistical information, which is a statistical value having a fine temporal granularity related to statistical items , sequentially input from a host device. A statistical information storage method for calculating coarse-grained statistical information, which is a coarse statistical value, and storing the obtained calculation result as new coarse-grained statistical information, the coarse-grained statistical information related to the statistical items being stored in a coarse-grained memory And the step of accumulating the fine-grained statistical information on the statistical items sequentially input from the host device, having a storage capacity smaller than that of the coarse-grained memory and operating at high speed. In the fine-grained statistical information temporarily accumulated in the fine-grained memory in accordance with the step of temporarily accumulating in each, and according to the access period of the coarse-grained memory, And an update processing step of sequentially updating the coarse grain statistical information accumulated in the particle size memory.

  According to the present invention, the fine granularity statistical information with fine temporal granularity, which is sequentially input from the host device every time a new packet arrives from the input line, is fine granularity composed of, for example, SRAM capable of high speed operation. It is sequentially stored in the memory. The coarse-grained statistical information with a coarse temporal granularity is updated with the fine-grained statistical information temporarily stored in the fine-grained memory in accordance with the access period of the coarse-grained memory made of DRAM, for example.

  Therefore, not only an SRAM that can operate at high speed but has a high price per unit capacity, but also a DRAM that has a relatively low operating speed but a low price per unit capacity compared to SRAM, can be used from the input line. Fine-grained statistical information that is sequentially input from the host device at high speed every time a packet arrives can be received without loss, and these fine-grained statistical information is statistically processed for each statistical item to obtain coarse-grained statistical information. Can be accumulated. Thereby, it is possible to realize a statistical information memory system that is excellent in cost performance and capable of high-speed operation.

  Further, when trying to change an existing network to be compatible with SDN, there has been a problem that all IP router devices must be changed to routers corresponding to SDN. According to the present invention, by adding a statistical information memory system as a circuit unit to an existing IP router, it is possible to support SDN while utilizing resources of the existing IP router. Therefore, the entire network can be reconstructed very easily to be compatible with SDN, and the capital investment accompanying the migration can be greatly reduced.

It is a block diagram which shows the structure of the statistical information memory system concerning 1st Embodiment. It is a block diagram which shows the structure of the IP router which mounted the statistical information memory system concerning 1st Embodiment. It is explanatory drawing which shows the statistics information acquisition operation | movement in an IP router. It is a flowchart which shows the statistical information update process of a statistical information memory system. It is a block diagram which shows the principal part structure of the statistical information memory system concerning 2nd Embodiment. It is a timing chart which shows an update process operation. It is explanatory drawing which shows the general network structure using an IP router. It is a block diagram which shows the internal structure of the conventional IP router. It is a structural example of the network based on SDN. It is an example of statistical information required by OpenFlow. It is a block diagram which shows the conventional memory structure.

Next, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
First, a statistical information memory system 10 according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing the configuration of the statistical information memory system according to the first embodiment.

  The statistical information memory system 10 includes a circuit unit such as an FPGA (Field Programmable Gate Array) on which a semiconductor memory is mounted as a whole. For example, the statistical information memory system 10 is mounted on a host device including a network device such as an IP router. Calculate the coarse-grained statistical information indicating the statistical value with coarse temporal granularity by statistically processing the fine-grained statistical information indicating the fine statistical value of temporal granularity related to each statistical item, for each statistical item, It has a function of accumulating the obtained calculation results as new coarse grain statistical information.

  As described above, typical semiconductor memories used for accumulation of statistical information include SRAM and DRAM. Among these, the SRAM can operate at high speed, but the price per unit capacity is high and is not suitable for a large storage capacity. On the other hand, DRAM has a lower price per unit capacity than SRAM and can easily realize a large storage capacity, but its operation speed is relatively slow.

  Further, when the statistical information to be accumulated is analyzed at the time granularity, that is, at the statistical information processing (occurrence) interval, the fine granularity statistical information with fine temporal granularity sequentially input from the host device, and these fine granularity statistics. The information is classified into two types of coarse-grained statistical information with coarse temporal granularity obtained by statistically processing information.

  The present invention pays attention to the fact that such SRAM and DRAM have contradictory performance, and the fact that there are two types of statistical information having different temporal granularities in the statistical information, and the fine-grained memory 11 composed of SRAM. And fine-grained memory 12 consisting of DRAM and serially arranged in parallel rather than in parallel, and for fine fine-grained statistical information that is sequentially input from a host device at high speed at packet arrival intervals, fine-grained memory 11 capable of high-speed operation The coarse-grained statistical information in the coarse-grained memory 12 is sequentially updated with the fine-grained statistical information in the fine-grained memory 11 in accordance with the access cycle of the coarse-grained memory 12. .

[Statistical information memory system]
Next, the detailed configuration of the statistical information memory system 10 according to the present embodiment will be described with reference to FIG.
The statistical information memory system 10 includes a fine grain memory 11, a coarse grain memory 12, an update processing unit STA, and an update control unit CNT.

[Fine grain memory]
The fine-grained memory 11 has an SRAM that has a smaller storage capacity than the coarse-grained memory 12 and operates at a high speed, and temporarily stores fine-grained statistical information on all statistical items that are sequentially input from the host device at a high speed. It has a function to accumulate.
The coarse-grained memory 12 is connected to the fine-grained memory 11 via the data line 13A and the control line 13B for performing data communication, has a DRAM having a larger storage capacity than the fine-grained memory 11, and includes all statistics It has a function of accumulating coarse grain statistical information on items.

  The update processing unit STA sequentially updates the coarse-grained statistical information stored in the coarse-grained memory 12 with the fine-grained statistical information temporarily stored in the fine-grained memory 11 in accordance with the access cycle of the coarse-grained memory 12. It has a function.

  More specifically, the update processing unit STA is accumulated in the coarse-grained memory 12 for each target statistical item that is sequentially selected as an update target from among all statistical items in accordance with the access period of the coarse-grained 12 memory. A function for updating the coarse-grained statistical information on the target statistical item with all the fine-grained statistical information on the target statistical item temporarily accumulated in the fine-grained memory 11, and the obtained coarse-grained statistical information on the target statistical item A function of writing to the coarse-grained memory 12 as new coarse-grained statistical information.

  The update control unit CNT has a function of sequentially selecting target statistical items to be updated from all the statistical items for each access cycle of the coarse-grained memory 12, and the update processing unit SAT with respect to the target statistical items. And a function for instructing update of the granularity statistical information.

  The fine grain memory 11 includes a fine grain storage unit 11A, a fine grain control unit 11B (update control unit CNT), a data transfer unit 11C, and an update processing unit STA as main circuit units. In the present embodiment, the case where the update processing unit STA is provided in the fine-grained storage unit 11A of the fine-grained memory 11 will be described as an example. However, the present invention is not limited to this, and the update processing unit STA is not limited to this. The update processing unit STA may be provided independently of the granularity memory 11 and the coarse granularity memory 12. Further, in the present embodiment, the case where the update control unit CNT is configured by a fine grain control unit 11B and a coarse grain control unit 12B of the coarse grain memory 12 described later will be described as an example, but the present invention is not limited thereto. Instead, the update processing unit STA may be provided in another circuit unit or independently of the fine-grained memory 11 and the coarse-grained memory 12.

  The fine-grain accumulation unit 11A has a function of temporarily accumulating fine-grain statistical information that is sequentially input from the host device to the data transfer unit 11C at a high speed, and the update processing unit STA described above. Specifically, in the fine-grain accumulation unit 11A, for example, a plurality of queues (queues) corresponding to each statistical item are provided, and the fine-grain statistical information from the data transfer unit 11C is sequentially stored in the corresponding queues. Accumulated.

  The fine granularity control unit 11B controls the input / output of fine granularity statistical information in the data transfer unit 11C in response to an instruction from the host device, and the fine granularity statistical information from the data transfer unit 11C to the fine granularity accumulation unit 11A. A function for controlling writing, and reading, updating from the coarse-grained memory 12 and writing to the coarse-grained memory 12 regarding coarse-grained statistical information in the update processing unit STA in response to an update request from the coarse-grained memory 12 are controlled. Function (update control unit CNT).

  The data transfer unit 11C receives fine granularity statistical information sequentially input from the host device at a high speed and writes it to the fine granularity storage unit 11A, and reads the fine granularity statistical information from the fine particle storage unit 11A and outputs it to the host device. It has a function.

[Coarse grain memory]
The coarse grain memory 12 is provided with a coarse grain accumulation unit 12A and a coarse grain control unit 12B (update control unit CNT) as main circuit units.
The coarse-grain accumulation unit 12A has a function of reading coarse-grain statistical information related to the target statistical item selected as the update target and outputting the coarse-grain statistical information to the fine-grain memory 11 at the start of the update processing of the coarse-grain statistical information in the update processing unit STA. The update processing unit STA has a function of receiving and storing fine-grained statistical information related to the target statistical item from the fine-grained memory 11 at the end of the update processing of the coarse-grained statistical information.

  The coarse granularity control unit 12B outputs an update request for requesting the update of the coarse granularity statistical information to the fine granularity memory 11 (update control unit CNT) in accordance with the access period of the coarse granularity memory 12, and the update. A function for controlling reading and writing of coarse-grained statistical information in the fine-grained storage unit 11A in synchronization with the update processing of the coarse-grained statistical information in the processing unit STA or in response to a request from the fine-grained memory 11 ing. In the present embodiment, an example in which an update request for the fine-grain memory 11 is output from the coarse-grain control unit 12B will be described as an example. However, the present invention is not limited to this, and an update request is output from another circuit unit. It may be.

[IP router]
FIG. 2 is a block diagram illustrating a configuration of an IP router in which the statistical information memory system according to the first embodiment is mounted.
The IP router 20 is a packet transfer device having an SDN-compatible function, and includes a packet transfer processing unit 20R, a statistical information memory system 10, a memory system control unit 25, and an SDN control unit 26 as main functional units. Yes.

  The packet transfer processing unit 20 </ b> R has a packet transfer function that a general IP router has, and corresponds to a host device of the statistical information memory system 10. The packet transfer processing unit 20R is provided with a packet input unit 21, a packet switching unit 22, and a packet output unit 23 as main circuit units.

  The packet input unit 21 uses the lookup table 21A to analyze the header information of the IP packet that has arrived on the input line 31, and uses the destination search unit 21B to search the destination of the incoming IP packet based on the obtained analysis result. And a function of discarding a packet by the destination search unit 21B based on a discard instruction from the packet output unit 23.

The packet switching unit 22 rewrites or switches the header information for the arrival packet based on the destination searched by the packet input unit 21 and outputs it to the queue (queue) of the packet output unit 23 corresponding to the destination. have.
The packet output unit 23 has a queue for temporarily accumulating packets for each output line 32, and sequentially outputs the packets accumulated in each queue to the corresponding output line 32, and hardware-implemented resources. It has a function of dropping a packet when exceeding the number of packets accumulated, and instructing the packet input unit 21 to discard the packet.

  In response to an instruction from the memory system control unit 25 via the control bus CB, the statistical information memory system 10 receives fine-grain statistical information acquired by the packet input unit 21 and the packet output unit 23 via the data bus DB. A function of receiving and accumulating, and a function of outputting the read fine-grained statistical information to the packet output unit 23 via the data bus DB

The memory system control unit 25 has a function of controlling writing / reading of statistical information to / from the statistical information memory system 10 in synchronization with the internal operation timing of the IP router 20. Regarding the reading of the statistical information, for example, the statistical information may be read directly from the coarse-grained memory 12 by the FPGA constituting the statistical information memory system 10 or another FPGA and output to the data bus DB.
Note that the clock CLK used in the statistical information memory system 10 may be generated inside the statistical information memory system 10, or the clock CLK generated by the memory system control unit 25 may be distributed to the statistical information memory system 10. Good.

  In response to an instruction from the SDN controller received from the packet input unit 21 via the control bus CB, the SDN control unit 26 instructs the memory system control unit 25 to read the specified statistical information via the control bus CB. And a function of receiving statistical information output from the statistical information memory system 10 via the control bus CB and transmitting the statistical information from the packet output unit 23 to the SDN controller via the control bus CB.

[Operation of First Embodiment]
Next, the operations of the statistical information memory system 10 according to the present embodiment and the IP router 20 in which the statistical information memory system 10 is mounted will be described with reference to the drawings.
First, the statistical information acquisition operation in the IP router 20 will be described with reference to FIG. FIG. 3 is an explanatory diagram showing a statistical information acquisition operation in the IP router. The statistical information is acquired using a general acquisition method.

  Statistical information relating to packets arriving from the input line 31 is obtained mainly by the packet input unit 21 and the packet output unit 23. For example, the packet input unit 21 acquires arrival packet information for identifying an arrival packet and header analysis information indicating an analysis result of header information. Further, the packet output unit 23 acquires departure packet information for identifying a departure packet transmitted from the output line 32 and discard packet information regarding a packet discarded in the queue of the packet output unit 23.

  Further, the packet input unit 21 acquires the number of arrival packets indicating the number of arrival packets and the packet length, and the source / destination IP address, protocol number, source / destination port number (L3 Src. , L3 Dst., #Protocol, L4 Src., L4 Dst.), The lookup table 21A is referred to based on a combination of five attribute values, destination routing information indicating the routing of the incoming packet, and the flow of the incoming packet Is obtained.

  Next, with reference to FIG. 4, the update operation | movement of the statistical information in the statistical information memory system 10 concerning this Embodiment is demonstrated. FIG. 4 is a flowchart showing statistical information update processing of the statistical information memory system.

First, the fine-grain memory 11 receives fine-grain statistical information sequentially input from the host device at a high speed by the data transfer unit 11C and temporarily accumulates it in the queue of the fine-grain accumulation unit 11A provided for each statistical item ( Step 100).
After this, since the resources of the fine-grain accumulation unit 11A are depleted with time, the fine-grain memory 11 performs steps 101 to 101 in accordance with the access cycle of the coarse-grain memory 12 based on the update request from the coarse-grain memory 12. The statistical information update process shown in 106 is executed.

  First, the update control unit CNT selects a part of all statistical items as target statistical items to be updated, and instructs the update processing unit STA to update coarse-grained statistical information regarding the target statistical items ( Step 101) At this time, since all statistical items cannot be updated by one update process, a part of all statistical items are sequentially selected as target statistical items, and all statistical items are updated by a plurality of update processes. ing. Regarding the target statistical item, the update control unit CNT may autonomously sequentially select, or may select based on an instruction from the update request from the coarse-grained memory 12.

  Subsequently, in response to an update instruction from the update control unit CNT, the update processing unit STA obtains coarse-grained statistical information related to the specified target statistical item from the coarse-grained memory 12 (step 102), and sets the target statistical item as the target statistical item. All the fine-grained statistical information temporarily stored in the corresponding queue is read from the coarse-grained memory 12 (step 103).

Next, the update processing unit STA collectively updates the coarse-grained statistical information by adding all the fine-grained statistical information regarding the read target statistical item to the coarse-grained statistical information of the target statistical item. (Step 104), the obtained coarse-grained statistical information is written into the coarse-grained memory 12 as new coarse-grained statistical information related to the target statistical item (Step 105).
Thereafter, the update processing unit STA clears (deletes) all the fine-grained statistical information temporarily stored in the queue corresponding to the target statistical item (step 106), returns to step 100, and is sequentially input. Repeat the update process for subsequent fine-grained statistical information.

[Effect of the first embodiment]
As described above, the present embodiment has a coarse-grained memory 12 that accumulates each coarse-grained statistical information, and has a smaller storage capacity than the coarse-grained memory 12 and operates at high speed, thereby obtaining fine-grained statistical information from a host device. The fine-grained memory 11 temporarily stored is arranged in series, and the update processing unit STA uses the fine-grained statistical information temporarily stored in the fine-grained memory 11 according to the access period of the coarse-grained memory 12, The coarse grain statistical information stored in the grain memory 12 is sequentially updated.

  As a result, each time a new packet arrives from the input line 31, the fine-grained statistical information with fine temporal granularity that is sequentially inputted from the host device is sequentially input to the fine-grained memory 11 that is an SRAM capable of high-speed operation. Accumulated. The coarse-grained statistical information having a coarse temporal granularity is updated with the fine-grained statistical information temporarily stored in the fine-grained memory 11 in accordance with the access period of the coarse-grained memory 12.

  Therefore, not only an SRAM that can operate at high speed but has a high price per unit capacity, and a DRAM that has a relatively low operating speed but a low price per unit capacity compared to SRAM, is also newly introduced from the input line 31. Can receive fine-grained statistical information that is input sequentially from the host device at high speed every time a new packet arrives without loss, and the fine-grained statistical information is statistically processed for each statistical item to obtain coarse-grained statistical information Can be accumulated. Thereby, it is possible to realize a statistical information memory system that is excellent in cost performance and capable of high-speed operation.

  As described above, the router installed in the environment of OpenFlow, which is representative of SDN, has a hardware specification different from that of the conventional IP router, and is manufactured and sold by the manufacturer separately from the IP router. Therefore, for example, when an existing network is to be changed to be compatible with SDN, there has been a problem that all IP router devices must be changed to routers corresponding to SDN.

  According to the present embodiment, it is possible to cope with SDN while utilizing resources of an existing IP router by simply adding the statistical information memory system 10 as a circuit unit to the existing IP router. Therefore, the entire network can be reconstructed very easily to be compatible with SDN, and the capital investment accompanying the migration can be greatly reduced.

  Further, in the present embodiment, the update processing unit STA accumulates in the coarse-grained memory 12 for each target statistical item that is sequentially selected as an update target from among all statistical items in accordance with the access period of the coarse-grained memory 12. The coarse-grained statistical information on the target statistical item is updated with all the fine-grained statistical information on the target statistical item temporarily accumulated in the fine-grained memory 11, and the obtained coarse-grained statistical information is updated to the target statistical item. The new coarse grain size statistical information may be written in the coarse grain memory 12.

  As a result, in the update process for one target statistical item, it is only necessary to read and write the coarse-grained statistical information between the item fine-grained memory 11 and the coarse-grained memory 12. For this reason, for example, all the fine-grained statistical information related to the target statistical item temporarily stored in the fine-grained memory 11 is updated to the coarse-grained memory 12 and updated very efficiently compared to the case where it is sequentially updated. It becomes possible to execute.

Further, in the present embodiment, the update control unit CNT sequentially selects the target statistical items to be updated from all the statistical items for each access period of the coarse-grained memory 12, and the update processing unit STA You may make it instruct | indicate the update of the coarse grain statistical information regarding the said target statistical item.
As a result, it is possible to update the coarse-grained statistical information regarding all statistical items with the minimum necessary access cycle.

[Second Embodiment]
Next, a statistical information accumulation operation in the statistical information memory system 10 according to the second exemplary embodiment of the present invention will be described with reference to FIGS. FIG. 5 is a block diagram showing a main configuration of the statistical information memory system according to the second embodiment. FIG. 6 is a timing chart showing the update processing operation.

  In the present embodiment, as an example of the configuration of the update processing unit STA, the fine-grain storage unit 11A of the fine-grain memory 11 divides the update processing unit STA into each of the bank storage units BM provided for each statistical item. A configuration example provided will be described in detail.

  In obtaining and accumulating statistical information in a network traffic of 100 Gbps class with a high bandwidth, in addition to the above-mentioned resource problem, a memory band (bandwidth) becomes a major technical problem. For example, when the traffic to the router is 100 Gbps and the average packet length is 200 bytes, the average packet rate arrival interval is 16 ns (62.5 M-pps: Packet Per Second). That is, it is necessary to add and update all the statistical information shown in Table 1 at an average interval of 16 ns. Among the commercially available memories, registers and SRAMs satisfy an access time of 16 ns or less. However, since the unit price per bit is very expensive, it is difficult to mount a large capacity. On the other hand, although DRAM is advantageous in terms of a unit price and a large capacity, random access performance requires 60 ns or more, so it is not possible to guarantee acquisition of statistical information at the wire rate.

  Another problem that occurs when the high-speed and small-capacity fine-grained statistical memory 11 is composed of SRAM and the low-speed and large-capacity coarse-grained memory 12 is composed of DRAM will be described. As described above, before SRAM resources are exhausted, data must be transferred to the DRAM. At this time, if the data transfer timing from the SRAM to the DRAM occurs simultaneously for each statistic, the DRAM side band (bandwidth) becomes insufficient. The time at which the statistics configured by SRAM are exhausted cannot be controlled because it depends on packet traffic. Since the band on the DRAM side cannot follow the band from the external traffic to the SRAM, it is necessary to take measures for communication between the SRAM and the DRAM.

  Another feature of the present invention relates to data transfer and communication control between SRAM and DRAM, and solves the problem not by packet traffic but by periodic data communication synchronized with a low-band DRAM. FIG. 6 shows a time chart regarding data communication with the SRAM when the coarse-grained memory 12 is configured using a commercial DDR-SDRAM. In this example, REN (Read command) and WEN (Write command) are received in an active period TP from ACT (page activation command) to PRE (page deactivation command), which arrives at every DDR-SDRAM access cycle. Are designated for the four banks A, B, C and D.

  In each bank A, B, C, and D, periods TA, TB, TC, and TD from REN to WEN are allocated as times for performing data communication with the SRAM and updating statistical information. Accordingly, in this example, four pieces of statistical information are updated in parallel in the TP from ACT to PRE. That is, with respect to data communication between the SRAM and the DRAM, the DRAM statistical information is updated and aligned (reset) based on the DRAM side. In this way, it is possible to update statistical information within the DRAM band tolerance without depending on external network traffic.

[Operation of Second Embodiment]
Next, the update processing operation according to the present embodiment will be described in detail with reference to FIGS.
The update control unit CNT of the fine grain control unit 11B monitors the page signal PAGE of the fine grain storage unit 11A in response to an update request from the coarse grain memory 12, and the active state ACT of the fine grain storage unit 11A ends. During the free period TP until the inactive state PRE is reached, the update processing unit STA of the bank storage unit BM corresponding to the target statistical item selected in advance is instructed to accumulate statistical information. Here, it is assumed that four statistical items are sequentially selected as target statistical items from all the statistical items, and in the following, a case where statistical items A, B, C, and D are selected as target statistical items will be described as an example.

  First, the update control unit CNT sends the read control signal REN and the bank selection signal BANK to the clock CLK for the four bank storage units BM corresponding to the target statistical items A, B, C, and D in the free period TP. Synchronously output in order. At this time, the update control unit CNT outputs REN and BANK to each bank storage unit BM by shifting by one clock so that the read timing of the coarse grain statistical information from the coarse grain memory 12 does not overlap. Thereby, the calculation process in each bank memory | storage part BM is performed in parallel.

  The bank storage unit BM is provided with a statistical processing unit STA for updating the coarse-grained statistical information with the fine-grained statistical information, and the coarse-grained statistical information read from the coarse-grained memory 12 in synchronization with the REN. DC0 is received by controlling the gate G by BEN, and all the fine-grained statistical information DS read from its own queue Q0 corresponding to the bank storage unit BM is added to DC0 by the adder ADD and updated. Then, new coarse grain statistical information DC1 is calculated.

  Thereafter, the update control unit CNT sequentially outputs the write signal WEN to the four bank storage units BM corresponding to the target statistical items A, B, C, and D in synchronization with the clock CLK in the remaining free period TP. To do. At this time, the update control unit CNT outputs WEN and BANK to each bank storage unit BM while shifting by one clock so that the timing of writing the coarse-grained statistical information to the coarse-grained memory 12 does not overlap.

The bank storage unit BM outputs the coarse grain statistical information DC1 obtained by the update to the coarse grain memory 12 in synchronization with WEN. As a result, DC1 obtained by updating DC0 with DS is written to the coarse-grained memory 12.
At this time, DC1 may be stored in its own queue Q1 corresponding to the bank storage unit BM. As a result, when the coarse-grained statistical information DC1 is output in response to a read request from the host device, reading from the coarse-grained memory 12 can be omitted, and a higher response can be obtained.

[Effect of the second embodiment]
As described above, the present embodiment includes a plurality of update processing units STA that execute update of coarse-grained statistical information regarding different target statistical items in parallel, and the update control unit CNT accesses the coarse-grained memory 12. For each period, select multiple target statistical items to be updated from all statistical items, and individually instruct the update processing unit STA to update coarse-grained statistical information related to these target statistical items It is.
As a result, the coarse-grained statistical information on a plurality of statistical items is updated in parallel, so that the update process can be executed very efficiently.

  In the present embodiment, after transferring the updated coarse-grained statistical information from the fine-grained memory 11 to the coarse-grained memory 12, new fine-grained statistical information is accumulated in the fine-grained memory 11, An update presence / absence detection unit that detects and outputs whether or not the fine-grain memory 11 has been updated is provided. When the update presence / absence detection unit indicates no update at the next update processing, Communication between the fine grain memory 11 and the coarse grain memory 12 may be blocked. Thereby, unnecessary power consumption due to communication maintenance can be reduced.

[Third Embodiment]
Next, a statistical information memory system 10 according to a third embodiment of the present invention will be described.
Although the fine-grain memory 11 can have a smaller storage capacity than the coarse-grain memory 12, the required storage capacity varies depending on the packet rate of packets arriving from the input line 31. In the present embodiment, the relationship between the packet rate of packets arriving from the input line 31 and the storage capacity required for the fine-grain memory 11 will be described in detail.

Let Td be the communication time required for exchanging coarse grain statistical information between the SRAM (fine grain memory 11) and the DRAM (coarse grain memory 12). Here, when the clock frequency of the DRAM is 400 MHz and Td corresponds to four cycles of the clock signal CLK, Td = 4 / (4 × 10 ⁸ ) = 10 [ns].
For this reason, when the total number of statistical items N is 100,000, the turnaround time required to update the coarse-grained statistical information of all statistical items is TAT = N × Td = 1 [ms].

On the other hand, when the packet throughput in the IP router 20 is T [bps] and the packet length is L [bit], the packet rate is PPS = T / L [pps (Packet Per Second)], and the permissible delay per packet. The time is D = 1 / PPS.
Therefore, when the wire rate condition is T = 100 G [bps] and L = 64 [Bytes], assuming that the overhead is 20 [Bytes], D is as follows.
L = 64 [Byte] +20 [Byte] = 672 [bit]
^{PPS = 100 × 10 9/672} ≒ 148M [pps]
D = 1 / 148M [pps] ≒ 6.72 [ns]

Further, when T = 100 G [bps] and L = 200 [Bytes],
L = 200 [Byte] = 1600 [bit] (considered as the average packet length)
^{PPS = 100 × 10 9/1600} ≒ 62.5M [pps]
D = 1 / 62.5M [pps] ≒ 16 [ns]
When T = 100G [bps] and L = 1518 [Byte],
L = 1518 [Byte] + 20 [Byte] = 12304 [bit]
^{PPS = 100 × 10 9/12304} ≒ 8.2M [pps]
D = 1 / 8.2M [pps] ≒ 122 [ns]
It becomes.

  Here, since the random access performance of a general DRAM is 60 ns or more, for example, it cannot be applied to the wire rate condition of T = 100 G [bps] and L = 200 [Byte], and it is understood that an SRAM is required. .

On the other hand, since the number of memory accesses is determined by M = TAT / D, the SRAM bit length W [bit] required for each wire rate condition is as follows.
M _64B = 1 × 10 ⁻³ /(6.72×10 ⁻⁹ ) ≒ 148809 [times] <2 ¹⁸ (= 262144)
W _64B = 18 [bit]
M _200B = 1 × 10 ⁻³ / (16 × 10 ⁻⁹ ) ≒ 62500 [times] <2 ¹⁶ (= 65536)
W _200B = 16 [bit]
M _1518B = 1 × 10 ⁻³ / (122 × 10 ⁻⁹ ) ≒ 8197 [times] <2 ¹⁴ (= 16384)
W _1518B = 14 [bit]

Therefore, it is understood that a maximum of W = 18 [bit] SRAM may be used in consideration of the correspondence to 64 [Byte] which is the strictest wire rate condition. At this time, the storage capacity required for the SRAM is obtained by C = W × N and is as follows.
C _64B = 18 × 10 ⁵ = 1.8M [bit]
C _200B = 16 × 10 ⁵ = 1.6M [bit]
C _1518B = 14 × 10 ⁵ = _1.4M [bit]

[Effect of the third embodiment]
To summarize the above calculation process, the total number of statistical items is N [pieces], the required communication time between memories is Td [s], the packet throughput is T [bps], the packet length is L [bit], and the SRAM When the bit length is W [bits], the SRAM has the following expressions (1) and (2).
2 ^W ≧ N × Td × T / L (1)
C = W × N (2)
It can be seen that the storage capacity C [bit] required by the above is sufficient. Therefore, if the minimum value satisfying the expression (1) is selected as W and the storage capacity C of the SRAM is determined, the minimum C required to satisfy the given wire rate condition can be very easily achieved. Can be calculated.

[Extended embodiment]
The present invention has been described above with reference to the embodiments, but the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention. In addition, each embodiment can be implemented in any combination within a consistent range.

  DESCRIPTION OF SYMBOLS 10 ... Statistical information memory system, 11 ... Fine grain memory, 11A ... Fine grain storage part, 11B ... Fine grain control part, 11C ... Data transfer part, 12 ... Coarse grain memory, 12A ... Coarse grain storage part, 12B ... Coarse grain size Control unit, 13A ... data line, 13B ... control line, STA ... update processing unit, CNT ... update control unit, BM ... bank storage unit, 20 ... IP router, 20R ... packet transfer processing unit, 21 ... packet input unit, 22 ... packet switching unit, 23 ... packet output unit, 25 ... memory system control unit, 26 ... SDN control unit.

Claims (8)

The coarse-grained statistical information, which is the statistical value with coarse temporal granularity, is statistically processed for each statistical item, and the fine-grained statistical information, which is the statistical value with fine temporal granularity related to the statistical items , input sequentially from the host device. A statistical information memory system that calculates and accumulates the obtained calculation results as new coarse-grained statistical information,
A coarse-grained memory for storing the coarse-grained statistical information related to the statistical items ;
A fine-grained memory that has a small storage capacity compared to the coarse-grained memory, operates at high speed, and temporarily accumulates the fine-grained statistical information on the statistical items sequentially input from the host device;
An update processing unit that sequentially updates the coarse-grained statistical information stored in the coarse-grained memory with the fine-grained statistical information temporarily accumulated in the fine-grained memory in accordance with the access period of the coarse-grained memory; A statistical information memory system comprising: The statistical information memory system according to claim 1,
The update processing unit, for each target statistical item sequentially selected as an update target from among all the statistical items in accordance with the access cycle of the coarse-grained memory, the target statistical item stored in the coarse-grained memory The coarse-grained statistical information is updated with all the fine-grained statistical information related to the target statistical item temporarily accumulated in the fine-grained memory, and the obtained coarse-grained statistical information is updated with a new coarse-grained statistical information. A statistical information memory system, characterized in that the granularity statistical information is written in the coarse grain memory. The statistical information memory system according to claim 2,
For each access period of the coarse-grained memory, sequentially select the target statistical item to be updated from all the statistical items , and update the coarse-grained statistical information related to the target statistical item to the update processing unit The statistical information memory system further comprising an update control unit for instructing. The statistical information memory system according to claim 3,
A plurality of the update processing units that execute the update of the coarse-grained statistical information regarding different target statistical items in parallel,
The update control unit selects a plurality of target statistical items to be updated from all the statistical items for each access cycle to the coarse-grained memory, and updates the coarse-grained statistical information related to these target statistical items. The statistical information memory system, wherein the update processing unit is individually instructed. In the statistical information memory system according to any one of claims 1 to 4,
The fine-grained memory detects whether the self-updated new fine-grained statistical information has been accumulated after transferring the new updated coarse-grained statistical information to the coarse-grained memory. In the next update process, if no update is detected, communication between the fine-grained memory and the coarse-grained memory is cut off. In the statistical information memory system according to any one of claims 1 to 5,
The number of statistical items is N [pieces], the required communication time between memories is Td [s], the packet throughput is T [bps], the packet length is L [bits], and the bit length of the fine-grained memory is When W [bit], the fine-grained memory has the following formula 2 ^W ≧ N × Td × T / L
A statistical information memory system having a storage capacity C = W × N [bit] obtained by multiplying N by the minimum W satisfying   A network device comprising the statistical information memory system according to any one of claims 1 to 6, and storing statistical information relating to packets arriving in the statistical information memory system. The coarse-grained statistical information, which is the statistical value with coarse temporal granularity, is statistically processed for each statistical item, and the fine-grained statistical information, which is the statistical value with fine temporal granularity related to the statistical items , input sequentially from the host device. A statistical information accumulation method for calculating and accumulating the obtained calculation results as new coarse-grain statistical information,
Storing the coarse-grained statistical information related to the statistical items in a coarse-grained memory, respectively;
A step of temporarily storing the fine-grained statistical information regarding the statistical items sequentially input from the host device in the fine-grained memory, each having a storage capacity smaller than that of the coarse-grained memory and operating at high speed. ,
An update process step of sequentially updating the coarse-grained statistical information stored in the coarse-grained memory with the fine-grained statistical information temporarily accumulated in the fine-grained memory in accordance with the access period of the coarse-grained memory; A statistical information accumulating method comprising:

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