JP5834907B2 - Semiconductor device, semiconductor device manufacturing method, and electronic device - Google Patents

Description

  The present invention relates to a semiconductor device, a method for manufacturing the semiconductor device, and an electronic device using the semiconductor device.

  With respect to semiconductor devices, various mounting techniques are known, such as a technique for mounting a semiconductor chip on a substrate, a technique for mounting a component including a semiconductor chip on a substrate, and a technique for stacking and mounting components including semiconductor chips. A technique is also known in which a through via is provided in a semiconductor chip, a component including the semiconductor chip, or a substrate, and electrical connection is made in the vertical direction using the through via.

  A semiconductor device having a form such as a multi-chip package (MCP) in which a plurality of semiconductor chips are accommodated in one package or a multi-chip module (MCM) is known. As one form of MCP, for example, there is known one in which a plurality of semiconductor chips are provided in an insulating layer such as resin or ceramics, and a wiring layer electrically connected to the plurality of semiconductor chips is provided on the insulating layer. It has been.

JP 2007-201254 A JP-A-7-307434 JP 2004-64043 A JP 2008-182225 A JP-A-8-186155 JP 2000-22311 A Japanese Patent Laid-Open No. 7-7134 JP 2010-141173 A

  When the MCP as described above is stacked on an electronic element such as a semiconductor chip, a component incorporating the semiconductor chip, or a substrate, for example, a through via that penetrates the MCP semiconductor chip portion is provided. Is formed. On the insulating layer, a wiring layer for electrically connecting the semiconductor chip in the insulating layer and the through via is provided, and the stacked MCP and the electronic element are electrically connected using the through via.

  However, the formation of through vias in the insulating layer portion of the MCP cannot accurately form through vias having a desired diameter and arrangement depending on the material used for the insulating layer, the thickness of the insulating layer, and the like. In some cases, it was not always easy.

According to one aspect of the present invention includes an insulating layer, wherein the first chip is disposed in the insulating layer, and the second chip and the third chip, and a wiring layer in which the disposed on an insulating layer, wherein the first chip includes at least one only of the first through via the first diameter as the through vias, the second chip, the second through-via the second diameter greater than said first diameter as the through vias only at least one has, the wiring layer includes a first through via and the second through-hole via, the third chip and the semiconductor device having a wiring portion for electrically connecting is provided. Furthermore, an electronic device in which such a semiconductor device is mounted on an electronic element is provided.

According to an aspect of the present invention, on a support, and a step of disposing a first chip having at least one only of the first through via the first diameter as the through vias, on the support, through Disposing a second chip having at least one second through via having a second diameter larger than the first diameter as a via ; disposing a third chip on the support; and Forming an insulating layer on the body, embedding the first chip , the second chip, and the third chip in the insulating layer; removing the support from the insulating layer; and removing the support to have been the insulating layer, a method of manufacturing a semiconductor device and forming a wiring layer having a first through via and the second through-hole via, the wiring portion for electrically connecting the third chip Is provided.

Furthermore, according to one aspect of the present invention, a step of disposing a first chip on a support, a step of disposing a second chip on the support, and a third chip on the support. A step of forming an insulating layer on the support, embedding the first chip , the second chip, and the third chip in the insulating layer, and a step of removing the support from the insulating layer. And forming a wiring layer having a wiring portion electrically connected to the third chip on the insulating layer from which the support has been removed, penetrating the wiring layer and the first chip, A step of forming at least one first through via having a first diameter electrically connected to the wiring portion; and passing through the wiring layer and the second chip and electrically connected to the wiring portion; Forming at least one second through via having a second diameter larger than the first diameter; Look containing a degree, the first chip has only the first through via of said first diameter as the through vias, the second chip, the second through-hole via said second diameter as the through vias only A method of manufacturing a semiconductor device having the above is provided.

  According to the disclosed technique, a through via is provided in one of the chips provided in the insulating layer. By using a chip provided with a through via, a high-performance semiconductor device including a through via formed with higher precision than the through via formed in the insulating layer can be realized.

1 is a diagram (part 1) illustrating an example of a semiconductor device according to a first embodiment; FIG. 3 is a second diagram illustrating an example of a semiconductor device according to the first embodiment; FIG. 3 is a diagram (part 3) illustrating an example of a semiconductor device according to the first embodiment; It is a figure which shows an example of the semiconductor device of another form. It is FIG. (1) explaining an example of the formation method of a penetration via. It is FIG. (2) explaining an example of the formation method of a penetration via. FIG. 10 is a first diagram illustrating an example of a semiconductor device according to a second embodiment; FIG. 10 is a second diagram illustrating an example of a semiconductor device according to the second embodiment; It is a figure explaining an example of the formation method of the via terminal chip concerning a 3rd embodiment. It is FIG. (1) explaining an example of the formation method of the semiconductor device using MCP and MCP which concerns on 3rd Embodiment. It is FIG. (2) explaining an example of the formation method of the semiconductor device using MCP and MCP which concerns on 3rd Embodiment. It is FIG. (3) explaining an example of the formation method of the semiconductor device using MCP and MCP which concerns on 3rd Embodiment. It is a figure explaining an example of the formation method of the via terminal chip concerning a 4th embodiment. It is FIG. (1) explaining an example of the formation method of the semiconductor device using MCP and MCP which concerns on 4th Embodiment. It is FIG. (2) explaining an example of the formation method of the semiconductor device using MCP and MCP which concerns on 4th Embodiment. It is FIG. (3) explaining an example of the formation method of the semiconductor device using MCP and MCP which concerns on 4th Embodiment. It is a figure explaining the planar layout of the semiconductor device which concerns on 5th Embodiment. It is a figure which shows an example of the semiconductor device which concerns on 6th Embodiment. It is a figure which shows an example of an electronic device.

First, the first embodiment will be described.
FIG. 1 is a diagram illustrating an example of a semiconductor device according to the first embodiment. FIG. 1 schematically shows a cross section of an essential part of an example of the semiconductor device according to the first embodiment.

  A semiconductor device (MCP) 10 shown in FIG. 1 includes a semiconductor chip 11, a semiconductor chip 12, and a via terminal chip 13. The via terminal chip 13 has a plurality of through vias 13a.

  The semiconductor chip 11, the semiconductor chip 12, and the via terminal chip 13 are provided in a resin layer (insulating layer) 14. For example, an epoxy resin is used for the resin layer 14. In addition to the epoxy resin, a material such as a phenol resin, a melamine resin, a urea resin, an unsaturated polyester resin, an alkyd resin, a polyurethane resin, or a polyimide resin may be used for the resin layer 14. Further, the resin layer 14 may include a nonconductive filler such as silica.

  The semiconductor chip 11 and the semiconductor chip 12 are provided in the resin layer 14 together with the via terminal chip 13 so that their circuit surfaces (electrode pad arrangement surfaces) 11a and circuit surfaces (electrode pad arrangement surfaces) 12a are aligned. It has been. The semiconductor chip 11, the semiconductor chip 12, and the via terminal chip 13 are arranged in the resin layer 14 such that one end of the circuit surface 11 a, the circuit surface 12 a, and the through via 13 a is exposed from one surface (surface) 14 a of the resin layer 14. Is provided.

  A wiring layer 15 is provided on the surface 14 a of the resin layer 14. The wiring layer 15 includes a wiring portion 15 a that electrically connects at least one of the semiconductor chip 11 (circuit surface 11 a) and the through via 13 a of the via terminal chip 13. Furthermore, the wiring layer 15 includes a wiring portion 15 b that electrically connects at least one of the semiconductor chip 12 (circuit surface 12 a) and the through via 13 a of the via terminal chip 13. The wiring part 15a and the wiring part 15b are covered with an insulating part 15c using silicon oxide, polyimide, or the like. A part of each of the wiring part 15a and the wiring part 15b is exposed from the insulating part 15c, and the exposed part is electrically connected to the wiring part 15a and the wiring part 15b as external connection terminals of the semiconductor device 10. Bumps 16 are provided. Various forms such as a ball, a post, or a combination thereof can be adopted as the bump 16.

  In the MCP 10, for example, the via terminal chip 13 may be formed by using silicon (Si) for the main body portion 13b and forming the through via 13a by a through silicon via (TSV) forming technique. A metal material such as copper (Cu) can be used for the through via 13a. The main body 13b is not limited to Si, and various materials such as other semiconductors, compound semiconductors, oxides, compounds, and resins can be used. Further, the through via 13a is not limited to the TSV forming technique, and various forming techniques used for forming an interposer (relay substrate) including the through via can be used.

The MCP 10 can be stacked and mounted on an electronic element using the through via 13a of the via terminal chip 13.
FIG. 2 is a diagram illustrating an example of the semiconductor device according to the first embodiment. 2A is a schematic cross-sectional view of an essential part of a first configuration example of the semiconductor device according to the first embodiment, and FIG. 2B is a second configuration example of the semiconductor device according to the first embodiment. It is a principal part cross-sectional schematic diagram.

  FIG. 2A illustrates a semiconductor device 20 a in which the MCP 10 is mounted on a semiconductor chip (electronic element) 21. On the circuit surface (electrode pad disposition surface) 21 a of the semiconductor chip 21, a wiring layer 22 including a wiring portion 22 d electrically connected to the semiconductor chip 21 is provided. The wiring part 22d is covered with an insulating part 22c using silicon oxide, polyimide, or the like. The through via 13 a of the MCP 10 is electrically connected to the wiring portion 22 d of the wiring layer 22 via the bump 23. An adhesive layer 24 such as an underfill resin is filled between the wiring layer 22 on the semiconductor chip 21 and the MCP 10. FIG. 2B illustrates the semiconductor device 20b in which the through via 13a is electrically connected to the wiring layer 22 without a bump.

  Thus, in the semiconductor device 20a and the semiconductor device 20b, the semiconductor chip 21 and the MCP 10 are stacked. Then, the semiconductor chip 21 is electrically connected to the semiconductor chip 11 and the semiconductor chip 12 of the MCP 10 using the through via 13 a of the via terminal chip 13.

  1 and 2 show an example in which two semiconductor chips 11 and 12 and one via terminal chip 13 are provided in the MCP 10, but the MCP 10 includes three or more semiconductor chips, Two or more via terminal chips may be included.

FIG. 3 is a diagram illustrating an example of the semiconductor device according to the first embodiment. FIG. 3 schematically shows a perspective view of main parts of another example of the semiconductor device according to the first embodiment.
FIG. 3 illustrates the MCP 10 including the semiconductor chip 11 and the semiconductor chip 12, the semiconductor chip 17 and the semiconductor chip 18, and a plurality of via terminal chips 13. Such an MCP 10 is mounted on the semiconductor chip 21 to constitute, for example, a semiconductor device 20a. In FIG. 3, the resin layer 14, the insulating portion 15 c of the wiring layer 15, parts of the wiring portions 15 a and 15 b, the bumps 16, and the adhesive layer 24 are omitted for convenience.

  As described above, in the semiconductor device 20a shown in FIG. 3, the four semiconductor chips of the semiconductor chip 11, the semiconductor chip 12, the semiconductor chip 17, and the semiconductor chip 18 are provided in the resin layer 14, and in the gaps or the periphery thereof, A plurality of via terminal chips 13 are provided. In addition to the signal via terminal chip 13A, the via terminal chip 13 can be provided with a power supply via terminal chip 13B having a through via 13Ba having a larger diameter than the through via 13Aa of the signal via terminal chip 13A.

  3 shows a configuration example of the semiconductor device 20a (FIG. 2A) in which the through via 13a of the MCP 10 is electrically connected to the wiring layer 22 on the semiconductor chip 21 via the bumps 23. . In addition, the semiconductor device 20b (FIG. 2B) in which the through via 13a is electrically connected to the wiring layer 22 without the bumps 23 can also have the same configuration.

  Here, the semiconductor device 20a and the semiconductor device 20b in which the MCP 10 is mounted on the semiconductor chip 21 have been described. In addition, the MCP 10 is not limited to the semiconductor chip 21 as described above, but can be similarly mounted on a package component or a substrate component incorporating the semiconductor chip, or other electronic elements such as an MCP. Further, the semiconductor device 20a and the semiconductor device 20b as described above can be stacked and mounted on another electronic element.

  As described above, in the MCP 10, the via terminal chip 13 having the through vias 13a (13Aa, 13Ba) is provided in the resin layer 14. In the MCP 10, it is not necessary to form a through via in the resin layer 14 itself or to form a through via (TSV) in the semiconductor chip 11 or the semiconductor chip 12 itself.

Here, for comparison, another type of semiconductor device that does not use the via terminal chip 13 as described above will be described.
FIG. 4 is a diagram illustrating an example of another type of semiconductor device. FIG. 4A is a schematic cross-sectional view of a main part of a semiconductor device according to another embodiment, and FIG. 4B is a schematic perspective view of the semiconductor device according to another embodiment.

  A semiconductor device 120 shown in FIGS. 4A and 4B is provided with a plurality of semiconductor chips, here two semiconductor chips 111 and 112 as an example, in a resin layer 114 using an epoxy resin or the like. It has MCP110. The MCP 110 is provided with a plurality of through vias (resin through vias) 113 a penetrating the resin layer 114 in the resin layer 114. The through resin via 113a is electrically connected to the semiconductor chip 111 and the semiconductor chip 112 by the wiring part 115d in the insulating part 115c of the wiring layer 115 provided on the resin layer 114. Bumps 116 are provided on the wiring part 115d. Such an MCP 110 is stacked on the electronic element 121 via an adhesive layer 124, and is electrically connected to the electronic element 121 by, for example, bumps 123 to constitute the semiconductor device 120. 4B, illustration of the resin layer 114, the insulating portion 115c of the wiring layer 115, a part of the wiring portion 115d, the bump 116, and the adhesive layer 124 is omitted for convenience. Yes.

  In the semiconductor device 120, the via terminal chip 13 is not used, and a resin through via 113 a is formed in the resin layer 114. As a method for forming the through resin via 113a, for example, there is the following method. Here, an example of a method of forming the resin through via 113a will be described with reference to FIG.

  First, the semiconductor chip 111 and the semiconductor chip 112 are arranged in a predetermined region on the support 200 (FIG. 5A), a resin layer 114 is formed on the support 200, and the semiconductor chip 111 and the semiconductor chip 112 are formed. It is embedded in the resin layer 114 (FIG. 5B). The resin layer 114 is cured by heating or light irradiation. In the state where the semiconductor chip 111 and the semiconductor chip 112 are embedded in the resin layer 114 as described above, a resin through via 113a is formed in the resin layer 114 (FIG. 5C). The resin through via 113a is formed by filling the hole with a conductive material after the resin layer 114 is drilled. The through resin via 113a can be formed before or after the support 200 is separated from the resin layer 114. Further, the support 200 is separated from the resin layer 114 and the wiring layer 115 is further formed. It can also be performed after formation.

A laser processing technique or an etching technique can be used for drilling the resin layer 114. However, with these techniques, it may be difficult to perforate the resin layer 114.
For example, in the method using a laser, when the material of the resin layer 114 is relatively weak to heat, the resin layer 114 may be deteriorated or deformed by heat generated during laser irradiation. Accordingly, a hole having a predetermined diameter cannot be formed at a predetermined position of the resin layer 114, and there is a possibility that the resin through via 113a cannot be formed with a desired arrangement density with high accuracy. In addition, it is difficult to perform reactive ion etching (RIE) on the resin layer 114. In particular, when the resin layer 114 contains a filler, RIE becomes difficult. Even with the etching technique, a hole having a predetermined diameter cannot be formed at a predetermined position in the resin layer 114, and the resin through-via 113a may not be formed with a desired arrangement density with high accuracy. .

  In addition, when the resin layer 114 is relatively thick, the aspect ratio of the resin through-via 113a to be formed is high, so that it is difficult to form the resin through-via 113a with high accuracy, or the resin through-via 113a with high reliability is formed. It may be difficult to form. Further, depending on the technique used for the drilling process and the material used for the resin layer 114, it is difficult to form a small diameter hole or resin through-hole via 113a, or a single resin layer 114 having a different diameter hole or resin through via 113a. May be difficult to form. Furthermore, even if holes having different diameters are formed in one resin layer 114, the conductive material may not be satisfactorily filled into holes having different diameters. Alternatively, in order to avoid such a point and perform highly accurate drilling and formation of the resin through via 113a, the number of processes and cost may increase.

  The reduction in accuracy of the plurality of through resin vias 113a formed may cause problems such as poor connection with the electronic element 121 when the semiconductor device 120 as shown in FIG. 4 is formed.

  On the other hand, in the MCP 10, the via terminal chip 13 provided in the resin layer 14 together with the semiconductor chips 11, 12, 17, 18 is provided with through vias 13a (13Aa, 13Ba). That is, although details will be described later, the via terminal chip 13 in which the through via 13a is formed or formed is arranged on the support body together with the semiconductor chips 11, 12, 17, and 18, and they are placed in the resin layer 14. The MCP 10 is obtained by embedding and then separating the support. As described above, in the MCP 10, the resin layer 14 is not formed, and the via terminal chip 13 provided with the through via 13a is provided in the resin layer 14 so that the resin layer 114 is perforated as described above. It is possible to avoid situations that may occur at times.

  For example, when Si is used for the main body portion 13b of the via terminal chip 13 and the through via 13a is formed by using the TSV forming technique, a hole having a good shape and the through via 13a are formed at predetermined positions at predetermined diameters. It can be formed with high accuracy. Furthermore, the through via 13a can be formed at a lower cost than the case where the resin through via 113a is formed as shown in FIG.

  In the MCP 10, the via terminal chip 13 provided with the through via 13 a is prepared by a process different from that of the semiconductor chips 11, 12, 17, and 18, and the semiconductor chip 11, 12, 17, and 18 are placed in the resin layer 14. Embedded. Therefore, the via terminal chip 13 can be disposed at an appropriate arbitrary position in the resin layer 14 such as between predetermined semiconductor chips or around a predetermined semiconductor chip. Electrical connection between the through via 13 a and the semiconductor chips 11, 12, 17, 18 is performed by the wiring layer 15.

  In order to perform the electrical connection in the vertical direction, a method of providing a TSV inside the semiconductor chip is also conceivable. However, the provision of the TSV may cause the electrical characteristics of the semiconductor chip to be impaired, or the semiconductor chip itself needs to be newly designed to provide the TSV. On the other hand, in the method of providing the via terminal chip 13, it is not necessary to separately design the semiconductor chip to be used for the MCP 10, and the influence on the electrical characteristics of the semiconductor chip to be used can be suppressed. By using the via terminal chip 13, a system (MCP10) that meets the needs of the market and customers can be quickly realized in a short period of time and at a low cost compared to a system such as SOC (System On Chip). It becomes possible.

  When a plurality of via terminal chips 13 are provided, the diameters of the through vias 13a provided in each via terminal chip 13 can be set. Therefore, as the via terminal chip 13, the via vias 13a (13Aa, 13Ba) having different diameters, such as the signal via terminal chip 13A and the power supply via terminal chip 13B, are formed in one resin layer 14. Can be provided. As described above, by using the via terminal chip 13, the through vias 13 a having different diameters, which has been difficult when forming the resin through via 113 a, can be easily provided in one resin layer 14. .

Further, when the via terminal chip 13 is provided in the resin layer 14 as in the MCP 10, the amount of resin contained in the MCP 10 can be reduced accordingly.
Here, for example, as shown in FIGS. 5A and 5B described above, the semiconductor chip 111 and the semiconductor chip 112 are arranged on the support 200, embedded in the resin layer 114, and the resin layer 114 is cured. Assume a case.

  In this case, the resin layer 114 is subjected to stress accompanying the curing and shrinkage of the resin. When the support 200 is separated from the resin layer 114, the resin in which the semiconductor chip 111 and the semiconductor chip 112 are embedded as shown in FIG. Deformation such as warpage may occur in the layer 114 (resin substrate). When the semiconductor chip 111 and the semiconductor chip 112 are embedded on one side of the resin substrate, since the arrangement is asymmetrical in the thickness direction, warping occurs when the support 200 is separated after returning to room temperature after curing. Such deformation is likely to occur. For example, a thermosetting resin is reduced to 0. Although thermal contraction of several% to several% occurs, the thermal contraction of the resin substrate may lead to such a situation that the substrate size is reduced, the substrate thickness is changed, and the distance between chips is reduced. When such a situation occurs in the resin substrate, when the wiring layer 115 is subsequently formed on the resin layer 114, the wiring portion 115d may not be formed or electrically connected with high accuracy. . The deformation of the resin substrate can also be caused by heat applied during the formation of the wiring layer 115 and further mounting (reflow) of the MCP 110 thereafter.

  In order to suppress such deformation of the resin substrate, methods such as increasing the glass transition point (Tg) of the resin layer 114 and increasing the high-temperature elastic modulus are conceivable, but these methods alone are highly accurate wiring layers. It is not always sufficient to form In addition, a method of suppressing deformation such as warping as described above by using resin materials having significantly different Young's moduli on the side surfaces of the semiconductor chip is also considered. However, resin materials having significantly different Young's moduli have greatly different coefficients of thermal expansion (CTE). For example, in a resin material having Young's modulus of 100 MPa and 14 GPa, which are 140 times different, the thermal expansion coefficient is 10 ppm / ° C. and 125 ppm / ° C., which is 12 times different. If the thickness of the resin substrate is 800 [mu] m and a temperature change of 200 [deg.] C. occurs, a difference of 18.4 [mu] m occurs between the thicknesses of both resin materials. Since a temperature change of about 200 ° C. may occur sufficiently in the manufacturing process, it is not a good idea to include a resin material having such a large Young's modulus in the resin substrate.

  On the other hand, in the MCP 10 described above, by providing the via terminal chip 13 in the resin layer 14, compared to the case where the via terminal chip 13 is not provided, and compared with the case where the through via is formed in the resin layer 14 itself, The amount of resin can be reduced. Therefore, it is possible to suppress the occurrence of deformation such as warpage due to curing shrinkage of the resin layer 14 during the manufacturing process of the MCP 10 or the semiconductor device using the MCP 10.

Next, a second embodiment will be described.
FIG. 7 is a diagram illustrating an example of a semiconductor device according to the second embodiment. FIG. 7 schematically shows a cross section of an essential part of an example of the semiconductor device according to the second embodiment.

  A semiconductor device (MCP) 30 shown in FIG. 7 has a semiconductor chip 11 and a semiconductor chip 31 provided in the resin layer 14. In the MCP 30 according to the second embodiment, one semiconductor chip 31 is provided with a plurality of through vias 31a (here, two through vias 31a are illustrated), and the via terminal chip 13 as described above is not provided. This is different from the MCP 10 according to the first embodiment.

  The through via 31a can be formed in the semiconductor chip 31 by the TSV forming technique. The semiconductor chip 31 has a region (via terminal region) 30a for forming the through via 31a at the end on the side of the semiconductor chip 11 provided side by side. The semiconductor chip 31 has a function corresponding to the semiconductor chip 12 described in the first embodiment. The semiconductor chip 31 has an area (chip function area) 30b having a function corresponding to the semiconductor chip 12 together with the via terminal area 30a.

  The semiconductor chip 11 and the semiconductor chip 31 are provided in the resin layer 14 with the directions of the circuit surface 11a and the circuit surface 31b aligned. The semiconductor chip 11 and the semiconductor chip 31 are provided in the resin layer 14 such that the circuit surface 11 a and the circuit surface 31 b are exposed from the surface 14 a of the resin layer 14.

  On the resin layer 14, a wiring layer 15 including a wiring part 15a, a wiring part 15b, and an insulating part 15c covering them is provided. The wiring portion 15 a electrically connects at least one of the semiconductor chip 11 and the through via 31 a provided in the via terminal region 30 a of the semiconductor chip 31. The wiring portion 15b electrically connects at least one of the chip functional region 30b of the semiconductor chip 31 and the through via 31a provided in the via terminal region 30a. Bumps 16 are provided on the wiring portion 15a and the wiring portion 15b.

  As described above, in the MCP 30, the via terminal region 30a is provided in the semiconductor chip 31 provided in the resin layer 14, and a plurality of through vias 31a are provided in the via terminal region 30a. The semiconductor chip 11 is electrically connected to the through via 31a of the via terminal region 30a via the wiring portion 15a. The semiconductor chip 31 has a chip function region 30b via the wiring portion 15b and a via terminal. It is electrically connected to the through via 31a in the region 30a.

  Such a MCP 30 also avoids a situation that may occur during the drilling process of the resin layer 114 as described above with reference to FIG. 5, and allows the through via 31a having a good shape to be high at a predetermined diameter and at a predetermined position. It can be formed with high accuracy.

  Here, two semiconductor chips 11 and a semiconductor chip 31 having a through via 31a are illustrated here, but a semiconductor in which a through via having a diameter different from that of the through via 31a of the semiconductor chip 31 is provided in the via terminal region. A chip can also be provided in the resin layer 14. For example, a semiconductor chip in which a through via having a larger diameter is provided in the via terminal region as in a power supply can be an MCP provided in the resin layer 14 together with the semiconductor chip 11 and the semiconductor chip 31.

  Further, in the MCP 30, by providing the via terminal region 30a in which the through via 31a is formed in the semiconductor chip 31, compared with the case where the via terminal region 30a is not provided, and compared with the case where the through via is formed in the resin layer 14 itself. Thus, the amount of resin in the MCP 30 can be reduced. Therefore, deformation such as warpage due to curing shrinkage of the resin layer 14 can be suppressed in the manufacturing process of the MCP 30 or the semiconductor device using the MCP 30.

The MCP 30 can be stacked and mounted on the electronic element by using the through via 31a in the via terminal region 30a.
FIG. 8 is a diagram illustrating an example of a semiconductor device according to the second embodiment. FIG. 8A is a schematic cross-sectional view of the main part of the first configuration example of the semiconductor device according to the second embodiment, and FIG. 8B is the second configuration example of the semiconductor device according to the second embodiment. It is a principal part cross-sectional schematic diagram.

  FIG. 8A illustrates a semiconductor device 20 c in which the MCP 30 is mounted on the semiconductor chip 21. On the circuit surface 21 a of the semiconductor chip 21, a wiring layer 22 including a wiring portion 22 d that is electrically connected to the semiconductor chip 21 is provided. A through via 31 a provided in the via terminal region 30 a of the semiconductor chip 31 of the MCP 30 is electrically connected to the wiring portion 22 d of the wiring layer 22 via the bump 23. An adhesive layer 24 is filled between the wiring layer 22 on the semiconductor chip 21 and the MCP 30. FIG. 8B illustrates the semiconductor device 20d in which the through via 31a is electrically connected to the wiring layer 22 without a bump.

  Thus, in the semiconductor device 20c and the semiconductor device 20d, the semiconductor chip 21 and the MCP 30 are stacked. Then, the semiconductor chip 21 is electrically connected to the semiconductor chip 11 of the MCP 30 and the chip functional area 30b of the semiconductor chip 31 using the through via 31a of the via terminal area 30a.

  Note that the MCP 30 may include three or more semiconductor chips. In addition to the semiconductor chip 21 as described above, the MCP 30 can be similarly mounted on a package component or a substrate component incorporating a semiconductor chip, or other electronic elements such as an MCP. In addition, the semiconductor device 20c and the semiconductor device 20d as described above can be stacked and mounted on another electronic element.

  The MCP 10, the semiconductor device 20a and the semiconductor device 20b using the MCP 10, and the semiconductor device 20c and the semiconductor device 20d using the MCP 30 and the semiconductor device 20d (second embodiment) have been described above. .

Next, an example of a method for forming an MCP as described above and a semiconductor device using the MCP will be described in detail as a third embodiment and a fourth embodiment.
First, a third embodiment will be described.

First, a method for forming a via terminal chip according to the third embodiment will be described.
FIG. 9 is a diagram for explaining an example of a method of forming a via terminal chip according to the third embodiment. FIGS. 9A to 9E are schematic cross-sectional views of the relevant part in each process of forming the via terminal chip according to the third embodiment.

  As shown in FIG. 9A, a resist pattern 41 having an opening 41 a in a region where a through via is formed is formed on the surface of a Si wafer 40. The film thickness of the resist pattern 41 is, for example, 10 μm. The diameter (opening diameter) of the opening 41a is, for example, 20 μm.

Next, as shown in FIG. 9B, the wafer 40 is etched using the resist pattern 41 as a mask to form via holes 42 for forming through vias. The via hole 42 can have a diameter of 20 μm and a depth of 200 μm. The via hole 42 can be formed by dry etching. For dry etching of the wafer 40, a mixed gas of sulfur hexafluoride (SF ₆ ) and octafluorobutene (C ₄ F ₈ ) can be used. In that case, dry etching can be performed under conditions of a gas pressure of 0.1 Torr and an input power of 500 W. The etching rate of the wafer 40 is set to 20 μm / min, for example. The end point of etching can be controlled by the etching time. After the formation of the via hole 42, the resist pattern 41 is removed.

  Next, a liner layer and a seed layer are formed on the surface of the wafer 40. Titanium (Ti) can be used for the liner layer, and Cu can be used for the seed layer. The liner layer and the seed layer can be formed by physical sputtering. For example, the liner layer is formed with a thickness of 20 nm, and the seed layer is formed with a thickness of 100 nm. Following the formation of the liner layer and seed layer, a plating layer is formed. The plating layer can be formed by depositing Cu by an electrolytic plating method. For electroplating, a semi-additive method in which a desired resist pattern is formed and plating is performed on the opening can be used. The electrolytic plating can be performed with a film thickness of 10 μm, for example. At this time, the via hole 42 having a diameter of 20 μm and a depth of 200 μm is sufficiently filled with the plating layer. Thereafter, the excess liner layer, seed layer, and plating layer on the upper surface of the wafer 40 are removed by CMP (Chemical Mechanical Polishing) or the like. Thereafter, an insulating film having a thickness of 2 μm may be formed using TEOS (Tetra Ethoxy Silane) or the like, and a bump hole may be patterned to form a bump. In this way, a wafer 40 having vias 43 as shown in FIG. 9C is obtained.

  Next, as shown in FIG. 9D, the wafer 40 is back-ground. By this back grinding, the wafer 40 is thinned to a thickness of about 200 μm, for example, and the vias 43 are exposed from the back surface of the wafer 40. Thereby, a via (through via) 43 penetrating the wafer 40 is formed. Formation of the through via 43 (TSV) in the Si wafer 40 can be performed with a predetermined diameter at a predetermined position with high accuracy.

Next, as shown in FIG. 9E, the wafer 40 is diced and separated into via terminal chips 44 including through vias 43 to obtain individual via terminal chips 44.
Note that the method of forming the via terminal chip 44 is not limited to the above example. The diameter and depth values of the via hole 42 (through via 43) are not limited to the above example. In the above example, the via terminal chip 44 is formed using the Si wafer 40, but other semiconductor wafers, compound semiconductor wafers, oxides, compounds, resins, and other substrates can also be used. In the above example, the through via 43 mainly composed of Cu is illustrated, but the material for filling the via hole 42 is not limited to Cu. The embedding method is not limited to the plating method.

Subsequently, a method for forming a semiconductor device using the MCP and the MCP according to the third embodiment will be described.
10 to 12 are views for explaining an example of the MCP and the method for forming a semiconductor device using the MCP according to the third embodiment. FIGS. 10A to 10C are schematic cross-sectional views of the main part of the pseudo wafer forming process according to the third embodiment, and FIGS. 11A to 11C are pseudo wafer laminations according to the third embodiment. FIGS. 12A and 12B are schematic cross-sectional views of the relevant part of the rewiring process according to the third embodiment. 10 to 12, the semiconductor device is focused on an area where one via terminal chip 44 and a pair of semiconductor chips 51 and 52 (both of which are shown) sandwiching the via terminal chip 44 are arranged. An example of the forming method will be described.

  The semiconductor chip 51 and the semiconductor chip 52 are prepared by a process different from the via terminal chip 44 as described above. The semiconductor chip 51 and the semiconductor chip 52 are thinned to the same thickness as the via terminal chip 44 by backgrinding, up to about 200 μm in the above example. As the semiconductor chip 51 and the semiconductor chip 52, for example, those having a planar size of 3 mm × 5 mm can be used.

  As shown in FIG. 10A, the semiconductor chip 51 and the semiconductor chip 52 prepared in advance are respectively disposed at predetermined positions on a support body 70 in which an adhesive layer 70b is provided on a support substrate 70a ( Temporary bonding). A glass substrate can be used as the support substrate 70a. A thermoplastic resin can be used for the adhesive layer 70b. Then, the via terminal chip 44 is disposed (temporarily bonded) with a gap of 1 mm between the disposed semiconductor chip 51 and the semiconductor chip 52. For the via terminal chip 44, for example, a planar size of 3 mm × 1 mm can be used. A die bonder can be used to arrange the semiconductor chip 51, the semiconductor chip 52, and the via terminal chip 44.

  After the semiconductor chip 51, the semiconductor chip 52, and the via terminal chip 44 are arranged on the support 70, they are embedded and sealed with a resin layer 53 as shown in FIG. The resin layer 53 is formed by, for example, providing a mold around the support 70 and pouring a resin such as an epoxy resin into the mold. The poured resin is flattened by removing excess resin with a squeegee, for example. Then, the poured resin is heated to the curing temperature and cured.

  The resin layer 53 may be formed using a spin coating method or a spray method. As a material for the resin layer 53, a resin mainly composed of a thermosetting resin such as a phenol resin, a melamine resin, a urea resin, an unsaturated polyester resin, an alkyd resin, a polyurethane resin, and a polyimide resin is used in addition to an epoxy resin. Can do. The resin layer 53 may contain a nonconductive filler such as silica. The space into which the resin is poured in the mold may be trapezoidal in cross section in order to suppress the formation of an unfilled region of resin in the mold.

  The resin layer 53 obtained after curing may have a recess of about 2 μm due to curing shrinkage. After the formation of the resin layer 53, back-grinding is performed to remove the recess, and the surface of the resin layer 53 is flattened as shown in FIG. Furthermore, through via grinding of the resin layer 53, the through via 43 of the via terminal chip 44 is exposed from the resin layer 53 as shown in FIG. The back grinding amount is, for example, 5 μm. Thereby, a pseudo wafer (resin mold substrate, chip built-in substrate) 54 including the semiconductor chip 51 and the semiconductor chip 52 and the via terminal chip 44 embedded in the resin layer 53 on the support 70 is obtained.

  Further, a wafer (device wafer) 60 on which a semiconductor chip 61 is mounted and a wiring layer (rewiring layer) 62 is formed as shown in FIG. Be prepared. The wiring layer 62 on the semiconductor chip 61 includes a wiring part 62d in the insulating part 62c, and the wiring part 62d is electrically connected to the semiconductor chip 61.

  On such a device wafer 60, the pseudo wafer 54 obtained as described above is laminated. In the pseudo wafer 54, after the resin layer 53 is planarized, bumps 63 are formed on the through vias 43 of the via terminal chips 44 exposed from the resin layer 53. The pseudo wafer 54 is stacked on the device wafer 60 and then reflowed, whereby the through via 43 of the pseudo wafer 54 and the wiring part 62 d of the device wafer 60 are electrically connected via the bumps 63. Connected. As shown in FIG. 11B, an adhesive layer 64 such as an underfill resin is filled between the laminated pseudo wafer 54 and the device wafer 60.

  The adhesive layer 64 can be filled in the gap between the two wafers after the pseudo wafer 54 and the device wafer 60 are electrically connected via the bumps 63. In addition, the pseudo wafer 54 on which the bumps 63 are previously formed may be laminated on the device wafer 60 on which the adhesive layer 64 is previously provided. In that case, the bump 63 on the pseudo wafer 54 side is made to contact the wiring part 62d through the adhesive layer 64 on the semiconductor chip 61 side, and the two are electrically connected.

  After the pseudo wafer 54 is stacked and mounted on the device wafer 60 as described above, the support 70 is separated from the stack of the pseudo wafer 54 and the device wafer 60 (see FIG. 11C). Debond). In the case of using a thermoplastic resin for the adhesive layer 70b, this debonding is performed by heating to a temperature equal to or higher than the softening temperature and sliding off, thereby stacking the pseudo wafer 54 and the device wafer 60, the support 70, Are separated (slide-off method).

  The warpage of the pseudo wafer 54 after the slide-off is, for example, about 10 μm in the case of the pseudo wafer 54 having a diameter of 200 mm, which is sufficient to perform the subsequent wafer process (for example, a rewiring layer forming process described later) with high accuracy. The value is suppressed. In the pseudo wafer 54, since the via terminal chip 44 is incorporated in the resin layer 53 in addition to the semiconductor chip 51 and the semiconductor chip 52, the amount of resin in the pseudo wafer 54 is suppressed, and such warpage is suppressed. An effect is obtained.

  After the support 70 is separated, as shown in FIG. 12A, the wiring portion 55a and the wiring portion 55b are provided in the insulating portion 55c by forming an insulating film and a conductive film and patterning using a photolithography technique. A wiring layer (rewiring layer) 55 is formed. The wiring layer 55 is formed by a wafer level process. The wiring part 55 a is formed as a pattern for electrically connecting the semiconductor chip 51 and a predetermined through via 43 of the via terminal chip 44. The wiring part 55 b is formed as a pattern for electrically connecting the semiconductor chip 52 and a predetermined through via 43 of the via terminal chip 44.

  Next, as shown in FIG. 12B, a bump hole is formed so that a part of the wiring part 55a and the wiring part 55b of the wiring layer 55 is exposed from the insulating part 55c, and the bump 56 is provided there. As a result, a structure in which the MCP 50 a having the resin layer 53 containing the semiconductor chip 51, the semiconductor chip 52, and the via terminal chip 44 and the wiring layer 55 and the bump 56 provided thereon is stacked on the device wafer 60 is obtained. can get.

  The wafer level structure that has been formed up to the formation of the wiring layer 55 and the bumps 56 in this way is diced at a predetermined position and separated into individual semiconductor devices. With respect to the semiconductor device formed as described above, it was confirmed that good electrical connection was realized without any deformation or disconnection of the wiring part 55a and the wiring part 55b in the wiring layer 55.

  In the third embodiment, the pseudo wafer 54 is attached to the support body 70 (support substrate 70a) in order to handle the pseudo wafer 54 while preventing damage during the formation process such as when it is transported or mounted on the device wafer 60. The use of a glass substrate was exemplified. In addition, the material used for the support 70 such as a resin substrate is not particularly limited as long as the pseudo wafer 54 can be maintained at a certain strength during the formation process.

  When the pseudo wafer 54 itself has a certain strength for handling in the forming process, the support 70 is formed by a slide-off method or the like after the pseudo wafer 54 is formed and before mounting on the device wafer 60. May be separated from the pseudo wafer 54.

  In addition, here, a mode in which the pseudo wafer 54 and the device wafer 60 are stacked and mounted (a so-called Wafer to Wafer mounting mode) is illustrated. In addition, before mounting the pseudo wafer 54 (FIG. 10C) on the device wafer 60, first, the wiring layer 55 and the bump 56 are formed on the pseudo wafer 54, and the chips are separated into chips by dicing. Then, the separated chips are stacked and mounted at predetermined positions on the device wafer 60. Such a form (a so-called Chip to Wafer mounting form) can also be adopted.

  Further, a semiconductor chip other than the semiconductor chip 51 and the semiconductor chip 52 or a via terminal chip other than the via terminal chip 44 may be disposed in the resin layer 53 of the MCP 50a. For example, a via terminal chip other than the via terminal chip 44 may have a through via having a diameter different from that of the through via 43 of the via terminal chip 44. Such through vias with different diameters can also be formed using the method shown in FIG.

Next, a fourth embodiment will be described.
First, a method for forming a via terminal chip according to the fourth embodiment will be described.
FIG. 13 is a diagram for explaining an example of a via terminal chip forming method according to the fourth embodiment. FIGS. 13A to 13E are schematic cross-sectional views of the relevant part in each step of forming the via terminal chip according to the fourth embodiment.

  As shown in FIG. 13A, a resist pattern 41 having openings 41 a is formed on the surface of a Si wafer 40. The film thickness of the resist pattern 41 is, for example, 10 μm, and the diameter of the opening 41a is, for example, 20 μm.

Next, as shown in FIG. 13B, the wafer 40 is etched using the resist pattern 41 as a mask to form, for example, a via hole 42 having a diameter of 20 μm and a depth of 200 μm. The via hole 42 can be formed by dry etching. The dry etching of the wafer 40 can be performed, for example, using a mixed gas of SF ₆ and C ₄ F ₈ under conditions of a gas pressure of 0.1 Torr and an input power of 500 W. The etching rate of the wafer 40 is set to 20 μm / min, for example, and the end point of the etching is controlled by the etching time, for example. After the formation of the via hole 42, the resist pattern 41 is removed.

Next, as shown in FIG. 13C, a resin 45 is filled into the via hole 42. As the resin 45, an epoxy resin, a phenol resin, or the like that can be removed in a later step is used.
Next, as shown in FIG. 13D, back grinding of the wafer 40 is performed, the wafer 40 is thinned to, for example, about 200 μm, and the resin 45 of the via hole 42 is exposed from the back surface of the wafer 40.

Next, as shown in FIG. 13E, the wafer 40 is diced into individual via terminal chips 46 including the resin 45, and individual via terminal chips 46 are obtained.
Subsequently, a method for forming a semiconductor device using the MCP and the MCP according to the fourth embodiment will be described.

  14 to 16 are diagrams for explaining an example of the MCP and the method for forming the semiconductor device using the MCP according to the fourth embodiment. 14A to 14C are schematic cross-sectional views of the main part of the pseudo wafer forming process according to the fourth embodiment, and FIGS. 15A and 15B are pseudo wafer stacks according to the fourth embodiment. FIGS. 16A and 16B are schematic cross-sectional views of the relevant part of the rewiring process according to the fourth embodiment. 14 to 16, the semiconductor device is focused on an area where one via terminal chip 46 and a pair of semiconductor chips 51 and 52 (both of which are shown) sandwiching the via terminal chip 46 are arranged. An example of the forming method will be described.

  The semiconductor chip 51 and the semiconductor chip 52 are prepared by a process different from the via terminal chip 46 as described above. The semiconductor chip 51 and the semiconductor chip 52 are thinned to the same thickness as the via terminal chip 46 by backgrinding. As the semiconductor chip 51 and the semiconductor chip 52, for example, those having a planar size of 3 mm × 5 mm can be used.

  As shown in FIG. 14A, the semiconductor chip 51 and the semiconductor chip 52 prepared in advance are mounted on a support 70 in which an adhesive layer 70b such as a thermoplastic resin is provided on a support substrate 70a such as a glass substrate. , Respectively (preliminary adhesion) at predetermined positions. Then, the via terminal chip 46 is disposed (temporarily bonded) with a gap of 1 mm between the disposed semiconductor chip 51 and the semiconductor chip 52. As the via terminal chip 46, for example, one having a planar size of 3 mm × 1 mm can be used. A die bonder can be used to arrange the semiconductor chip 51, the semiconductor chip 52, and the via terminal chip 46.

  After the semiconductor chip 51, the semiconductor chip 52, and the via terminal chip 46 are disposed on the support 70, as shown in FIG. 14B, these are embedded in a resin layer 53 such as an epoxy resin. The resin layer 53 can be formed, for example, by providing a mold around the support 70 and pouring resin into the mold. The poured resin is flattened with, for example, a squeegee. Then, the poured resin is cured by heating.

  After the resin layer 53 is formed, back grinding is performed to flatten the surface of the resin layer 53 and to expose the resin 45 of the via terminal chip 46 as shown in FIG. The back grinding amount is, for example, 5 μm. Thereby, a pseudo wafer (resin mold substrate, chip built-in substrate) 57 including the semiconductor chip 51 and the semiconductor chip 52 and the via terminal chip 46 embedded in the resin layer 53 on the support 70 is obtained.

  Further, a device wafer 60 on which a semiconductor chip 61 is mounted and a wiring layer (rewiring layer) 62 is formed as shown in FIG. 15A is prepared by a process different from the pseudo wafer 57 as described above. The The wiring layer 62 on the semiconductor chip 61 includes a wiring part 62d in the insulating part 62c, and the wiring part 62d is electrically connected to the semiconductor chip 61. An adhesive layer 64 is provided in advance on such a device wafer 60, and the pseudo wafer 57 obtained as described above is laminated (adhered) to the adhesive layer 64.

  After the pseudo wafer 57 is stacked on the device wafer 60, the support 70 is separated from the stack of the pseudo wafer 57 and the device wafer 60 by a slide-off method, as shown in FIG. The warpage of the pseudo wafer 57 after the slide-off is, for example, about 10 μm in the case of the pseudo wafer 57 having a diameter of 200 mm, and is sufficient to perform the subsequent wafer process (for example, a rewiring layer forming process described later) with high accuracy. The value is suppressed.

  After the support 70 is separated, as shown in FIG. 16A, the wiring portion 55a and the wiring portion 55b are provided in the insulating portion 55c by forming an insulating film and a conductive film and patterning using a photolithography technique. A wiring layer (rewiring layer) 55 is formed. The wiring part 55 a includes a pattern electrically connected to the semiconductor chip 51, and the wiring part 55 b includes a pattern electrically connected to the semiconductor chip 52. The wiring portion 55a and the wiring portion 55b may be formed so as to be completed at this time, but are formed halfway so that the wiring portion 55a and the wiring portion 55b are completed together with the through via 43 when a later-described through via 43 is formed. You can also keep it. FIG. 16A illustrates a case where the formation of the wiring portion 55a and the wiring portion 55b is stopped halfway.

After forming the wiring layer 55 (a part) as shown in FIG. 16A, a part of the insulating part 55c, the resin 45 in the via hole 42 of the via terminal chip 46, and the adhesive layer 64 below it, etc. The part is removed by dry etching. For example, the insulating portion 55c corresponding to the via hole 42 is removed by RIE, and the resin 45 in the via hole 42 is removed by oxygen (O ₂ ) plasma ashing. Following the removal of the resin 45, the adhesive layer 64 exposed at the bottom of the via hole 42 is etched to the surface of the wiring part 62d of the wiring layer 62 on the semiconductor chip 61 to open. The opening of the adhesive layer 64 can be performed by RIE using oxygen-based plasma.

  Next, for example, a Ti liner layer having a thickness of 20 nm and a Cu seed layer having a thickness of 100 nm are formed on the surface after opening. The liner layer and the seed layer can be formed by physical sputtering. Subsequent to the formation of the liner layer and the seed layer, for example, Cu is deposited with a film thickness of 10 μm by electrolytic plating using a semi-additive method to form a plating layer. Thereby, the via terminal chip 46 provided with the through via 43 reaching the wiring part 62d of the semiconductor chip 61 as shown in FIG. 16B is formed. At the time of this electrolytic plating of Cu, a resist mask is used to simultaneously deposit Cu on the remaining portions of the wiring portion 55a and the wiring portion 55b of the wiring layer 55. Thereby, the wiring part 55a and the wiring part 55b of the wiring layer 55 are completed together with the through via 43. Unnecessary liner layers and seed layers are removed.

  Next, as shown in FIG. 16B, a bump hole is formed so that a part of the wiring portion 55a and the wiring portion 55b of the wiring layer 55 is exposed from the insulating portion 55c, and the bump 56 is provided there. As a result, the structure in which the MCP 50b having the resin layer 53 containing the semiconductor chip 51, the semiconductor chip 52, and the via terminal chip 46, and the wiring layer 55 and the bump 56 provided thereon is laminated on the device wafer 60 is obtained. can get.

  The wafer-level structure that has been formed up to the formation of the through via 43, the wiring layer 55, and the bump 56 in this way is diced at a predetermined position and separated into individual semiconductor devices. With respect to the semiconductor device formed as described above, it was confirmed that good electrical connection was realized without any deformation or disconnection of the wiring part 55a and the wiring part 55b in the wiring layer 55.

  Before forming the wiring layer 55 (a part) as shown in FIG. 16A, the resin 45 of the via terminal chip 46 is removed and the adhesive layer 64 is opened below to form the through via 43. May be. Then, after forming the via terminal chip 46 provided with the through via 43 in this way, the wiring layer 55 is formed, and the bump 56 is formed. When such a procedure is adopted, when removing the resin 45, if the oxygen plasma ashing is performed in a state where the resin layer 53 is also exposed together with the resin 45, the resin layer 53 can also be etched. Therefore, the resin layer 53 is masked. It is desirable to keep it.

  As in the third embodiment, in the fourth embodiment, the support 70 (support substrate 70a) is not limited to the glass substrate, and the pseudo wafer 57 has a certain strength during the formation process. Various materials can be used as long as they can be maintained at the same level. Further, when the pseudo wafer 57 itself has a certain strength, the support 70 may be separated from the pseudo wafer 57 after the pseudo wafer 57 is formed and before lamination on the device wafer 60. .

  Further, here, a form (Wafer to Wafer) in which the pseudo wafer 57 and the device wafer 60 are stacked is illustrated. In addition, before the pseudo wafer 57 (FIG. 14C) is stacked on the device wafer 60, first, the through via 43, the wiring layer 55, and the bump 56 are formed on the pseudo wafer 57, and this is performed by dicing. Divide into chips. Then, the separated chips are mounted at predetermined positions on the device wafer 60. Such a form (Chip to Wafer) can also be adopted.

  Further, a semiconductor chip other than the semiconductor chip 51 and the semiconductor chip 52 or a via terminal chip other than the via terminal chip 46 may be disposed in the resin layer 53 of the MCP 50b. As the via terminal chip other than the via terminal chip 46, for example, one having a through via having a diameter different from that of the through via 43 of the via terminal chip 46 may be used. Such through vias (via holes) having different diameters can also be formed using the method shown in FIG.

Hereinafter, still another embodiment of the MCP will be described as a fifth embodiment and a sixth embodiment.
First, a fifth embodiment will be described.

FIG. 17 is a diagram for explaining a planar layout of a semiconductor device according to the fifth embodiment.
FIG. 17A shows an example of a pseudo wafer 80 on which a plurality of semiconductor devices (MCPs) are formed. In the pseudo wafer 80, a via terminal chip 83 having through vias, a pair of semiconductor chips 81 and a pair of semiconductor chips 82 electrically connected to the via terminal chip 83, and a layout region 88 (dotted line frame in the drawing) are arranged in a plurality of rows and columns. Has a planar layout. Each via terminal chip 83 in the layout region 88 is disposed between a pair of semiconductor chips 81 and 82. The semiconductor chip 81, the semiconductor chip 82, and the via terminal chip 83 are provided in the resin layer 84. On the resin layer 84, a wiring layer (rewiring layer) including a wiring part 85a and a wiring part 85b is provided. The semiconductor chip 81 is a wiring part 85a, the semiconductor chip 82 is a wiring part 85b, and a via terminal chip 83 is provided. Is electrically connected to the through via.

  In the planar layout as shown in FIG. 17A, there is a via terminal between the semiconductor chip 81 in a certain layout area 88 and the semiconductor chip 81 or the semiconductor chip 82 in another layout area 88 adjacent to the layout area 88. An area where the chip 83 is not arranged is formed. Similarly, an area where the via terminal chip 83 is not disposed is formed between the semiconductor chip 82 in a certain layout area 88 and the semiconductor chip 82 or the semiconductor chip 81 in another layout area 88 adjacent to the layout area 88. Therefore, the amount of resin in the resin layer 84 differs between a region where the via terminal chip 83 is disposed between predetermined semiconductor chips and a region where the via terminal chip 83 is not disposed. In this case, when the pseudo wafer 80 is formed, a resin stress difference and a curing shrinkage difference occur between predetermined semiconductor chips, so that the pseudo wafer 80 may be distorted and deformation such as warpage may occur.

  On the other hand, in the planar layout of FIG. 17B, the dummy chips 86 are respectively disposed in regions where the via terminal chips 83 are not disposed between predetermined semiconductor chips. For example, a dummy chip 86 having the same size as the via terminal chip 83 is used. By arranging the dummy chip 86 together with the via terminal chip 83 as shown in FIG. 17B, the amount of resin existing between predetermined semiconductor chips can be made uniform. Accordingly, it is possible to suppress the difference in curing and shrinkage of the resin between predetermined semiconductor chips, and to suppress deformation such as distortion and warpage when the pseudo wafer 80 is formed.

  For example, in the pseudo wafer 80, the adjacent semiconductor chips 81 and 82, the adjacent semiconductor chips 81, and the adjacent semiconductor chips 82 are arranged at intervals of 5 mm. A via terminal chip 83 having a width of 3 mm is arranged between the pair of semiconductor chips 81 and the semiconductor chip 82 in each layout region 88. At this time, when the dummy chip 86 is not arranged as shown in FIG. 17A, if the curing shrinkage rate of the resin is 5%, the region of 5 mm between the semiconductor chips in the adjacent layout region 88 is in the plane direction. A cure shrinkage of 250 μm will occur. On the other hand, when the dummy chip 86 is arranged as shown in FIG. 17B, the curing shrinkage in the planar direction between the semiconductor chips in the adjacent layout region 88 is 100 μm. There is a 2.5-fold difference in the amount of cure shrinkage between the case where the dummy chip 86 is not disposed and the case where the dummy chip 86 is disposed. When the dummy chip 86 is not disposed, the pseudo-wafer 80 may be deformed and cracks may be generated due to distortion caused by a curing shrinkage of 150 μm between predetermined semiconductor chips. By arranging the dummy chip 86 as shown in FIG. 17B, the curing shrinkage in the surface of the pseudo wafer 80 can be made uniform, and the distortion and deformation can be effectively suppressed.

  For example, the dummy chip 86 can be disposed on a dicing area when a plurality of MCPs are cut out from the pseudo wafer 80 by dicing. It is also possible to arrange a dummy chip 86 between the semiconductor chips in each cut MCP. The dummy chip 86 can be applied to the pseudo wafer forming the MCP 10 and the MCP 30 according to the first and second embodiments, and the pseudo wafer 54 and the pseudo wafer 57 according to the third and fourth embodiments. is there.

Next, a sixth embodiment will be described.
FIG. 18 is a diagram illustrating an example of a semiconductor device according to the sixth embodiment. FIG. 18 schematically illustrates a cross-section of an essential part of an example of the semiconductor device according to the sixth embodiment.

  In a semiconductor device (MCP) 90 shown in FIG. 18, a semiconductor chip stacked body 91 and a semiconductor chip stacked body 92 are arranged with a via terminal chip 13 provided with a through via 13a interposed therebetween, and these are embedded with a resin layer 14. It has a structure. The MCP 90 is different from the MCP 10 according to the first embodiment in this respect. Other configurations are the same as those of the MCP 10 described above.

  The semiconductor chip stacked body 91 has a structure in which a plurality of semiconductor chips, here two semiconductor chips 91a and 91b are stacked as an example. The semiconductor chip 91a and the semiconductor chip 91b are electrically connected by a bump 93 and a TSV 91ba provided on the upper semiconductor chip 91b. The TSV 91ba is electrically connected to the through via 13a of the via terminal chip 13 through the wiring portion 15a of the wiring layer 15.

  Similarly, the semiconductor chip stacked body 92 has a structure in which a plurality of semiconductor chips, for example, two semiconductor chips 92a and 92b are stacked. The semiconductor chip 92a and the semiconductor chip 92b are electrically connected by a bump 93 and a TSV 92ba provided on the upper semiconductor chip 92b. The TSV 92ba is electrically connected to the through via 13a of the via terminal chip 13 through the wiring portion 15b of the wiring layer 15.

  The MCP 90 can be stacked and mounted on an electronic element such as a semiconductor chip in accordance with the example of FIGS. In addition, a semiconductor device using the MCP 90 can be formed according to the example of the method as described in the third embodiment and the fourth embodiment. The dummy chip 86 as described in the fourth embodiment can also be applied to the pseudo wafer on which the MCP 90 is formed.

By using the semiconductor chip stacked body 91 and the semiconductor chip stacked body 92 as described above, it is possible to realize the MCP 90 with higher integration.
In the above description, the via terminal chip provided in the resin layer and the semiconductor chip or the semiconductor chip stacked body are not necessarily required to have the same or similar thickness. The via terminal chip may be exposed from the resin layer, and the semiconductor chip or the semiconductor chip laminated body may be embedded without being exposed to the resin layer.

In addition, a semiconductor device including an MCP as described above can be mounted on an electronic element such as a circuit board to form an electronic device.
FIG. 19 illustrates an example of an electronic device. FIG. 19 schematically illustrates a cross section of an essential part of an example of the electronic device.

  An electronic device 300 illustrated in FIG. 19 includes an electronic element 310 and a semiconductor device mounted on the electronic element 310, here, as an example, the semiconductor device 20a described in the first embodiment. As the electronic element 310, in addition to a circuit board, a package component or a substrate component incorporating a semiconductor chip, another MCP, or the like is applicable. The semiconductor device 20a is electrically connected to a predetermined connection pad 320 provided on the electronic element 310 via the bumps 16 provided as external connection terminals.

  A semiconductor device 20a including a high-performance, high-quality MCP 10 that includes a via terminal chip 13 provided with a through-via 13a formed with high precision and is prevented from being deformed such as warping is mounted on an electronic element 310. A high-performance and high-quality electronic device 300 is realized.

  Although the electronic device 300 using the semiconductor device 20a is illustrated here, the electronic element 310 is similarly applied to the MCPs described in the first to sixth embodiments and the semiconductor devices using those MCPs. It is possible to implement an electronic device by mounting on top.

Regarding the embodiment described above, the following additional notes are further disclosed.
(Appendix 1) an insulating layer;
A first chip and a second chip arranged in parallel in the insulating layer;
A first wiring layer disposed on the insulating layer,
The first chip has a first through via,
The first wiring layer includes a first wiring portion that electrically connects the first through via and the second chip.

(Additional remark 2) In the said insulating layer, The 3rd chip | tip arranged in parallel with the said 1st chip | tip and the said 2nd chip | tip is included,
The first chip has a second through via,
The semiconductor device according to appendix 1, wherein the first wiring layer has a second wiring portion that electrically connects the second through via and the third chip.

(Additional remark 3) In the said insulating layer, The 4th chip | tip arranged in parallel with the said 1st chip | tip and the said 2nd chip | tip is included,
The semiconductor device according to appendix 1 or 2, wherein the fourth chip has a fourth through via having a diameter different from that of the first through via.

(Appendix 4) Including electronic elements,
The semiconductor device according to any one of appendices 1 to 3, wherein the insulating layer is disposed above the electronic element.

(Additional remark 5) The 2nd wiring layer arrange | positioned between the said electronic element and the said insulating layer is included,
The semiconductor device according to appendix 4, wherein the second wiring layer includes a third wiring portion that electrically connects the first through via and the electronic element.

(Additional remark 6) The semiconductor device in any one of Additional remark 1 thru | or 5 characterized by including the dummy chip arrange | positioned in the said insulating layer.
(Additional remark 7) In the said insulating layer, The 5th chip | tip arranged in parallel with the said 1st chip | tip is included,
The semiconductor device according to any one of appendices 1 to 6, wherein the fifth chip is disposed above the second chip.

(Supplementary Note 8) The fifth chip has a fifth through via,
The semiconductor device according to appendix 7, wherein the second chip and the fifth chip are electrically connected using the fifth through via.

  (Supplementary Note 9) The first chip has only the first through via or the through via group including the first through via as a conductive portion electrically connected to the first wiring layer. The semiconductor device according to any one of appendices 1 to 8.

(Additional remark 10) The process of arrange | positioning the 1st chip | tip which has a penetration via on a support body,
A step of arranging a second chip on the support side by side with the first chip;
Forming an insulating layer on the support, and embedding the first chip and the second chip in the insulating layer;
Removing the support from the insulating layer;
Forming a wiring layer having a wiring portion for electrically connecting the through via and the second chip on the insulating layer from which the support has been removed. Method.

(Appendix 11) Before the step of removing the support,
Disposing the insulating layer including the first chip and the second chip above an electronic element;
The method of manufacturing a semiconductor device according to appendix 10, further comprising a step of electrically connecting the through via and the electronic element.

(Supplementary Note 12) A step of arranging the first chip and the second chip on the support,
Forming an insulating layer on the support, and embedding the first chip and the second chip in the insulating layer;
Removing the support from the insulating layer;
Forming a wiring layer having a wiring portion electrically connected to the second chip on the insulating layer from which the support has been removed;
Forming a through via that penetrates through the wiring layer and the first chip and is electrically connected to the wiring portion.

(Additional remark 13) Before the process of removing the said support body, The process which arrange | positions the said insulating layer containing the said 1st chip | tip and the said 2nd chip | tip above an electronic element,
13. The method of manufacturing a semiconductor device according to appendix 12, wherein in the step of forming the through via, a through via that is electrically connected to the electronic element is formed as the through via.

(Supplementary Note 14) An insulating layer, a first chip and a second chip arranged in parallel in the insulating layer, and a wiring layer disposed on the insulating layer, wherein the first chip has a through via. A semiconductor device, wherein the wiring layer has a wiring portion that electrically connects the through via and the second chip;
An electronic device comprising: an electronic element disposed on the wiring layer side of the semiconductor device and electrically connected using the second chip and the wiring layer.

10, 30, 50a, 50b, 90, 110 MCP
11, 12, 17, 18, 21, 31, 51, 52, 61, 81, 82, 91a, 91b, 92a, 92b, 111, 112 Semiconductor chip 11a, 12a, 21a, 31b Circuit surface 13, 44, 46, 83 Via terminal chip 13A Via terminal chip for signal 13B Via terminal chip for power supply 13a, 13Aa, 13Ba, 31a Through-via 13b Body portion 14, 53, 84, 114 Resin layer 14a Surface 15, 22, 55, 62, 115 Wiring layer 15a, 15b, 22d, 55a, 55b, 62d, 85a, 85b, 115d Wiring portion 15c, 22c, 55c, 62c, 115c Insulating portion 16, 23, 56, 63, 93, 116, 123 Bump 20a, 20b, 20c, 20d, 120 semiconductor device 24, 64, 70b, 124 contact Layer 30a via the terminal region 30b chip functional region 40 wafer 41 resist pattern 41a opening 42 via hole 43 via (through via)
45 Resin 54, 57, 80 Pseudo wafer 60 Device wafer 70, 200 Support body 70a Support substrate 86 Dummy chip 88 Layout area 91, 92 Semiconductor chip stack 91ba, 92ba TSV
113a Through resin via 121,310 Electronic element 300 Electronic device 320 Connection pad

Claims (8)

An insulating layer;
A first chip , a second chip and a third chip disposed in the insulating layer;
A first wiring layer disposed on the insulating layer,
It said first chip, only the first through via the first diameter as the through via at least one has,
The second chip has at least one second through via having a second diameter larger than the first diameter as a through via,
The first wiring layer to a semiconductor device and having a first through via and the second through-hole via, the first wiring portion for electrically connecting the third chip. A fourth chip disposed in the insulating layer;
The first chip has a plurality of the first through via,
The first wiring layer includes a first electrically connected to the respective other of said first through-hole via, and said fourth tip and the first wiring portion and electrically connected to the one of the first through via The semiconductor device according to claim 1, comprising two wiring portions. Including electronic elements,
The insulating layer, the semiconductor device according to claim 1 or 2, characterized in that it is disposed above the electronic element. The semiconductor device according to any one of claims 1 to 3, characterized in that it comprises a dummy chip disposed on the insulating layer. Wherein the insulating layer, a semiconductor device according to any one of claims 1 to 4, characterized in including that the third fifth chips are stacked into chips arranged. On a support, and a step of disposing a first chip having only at least one of the first through via the first diameter as the through vias,
Disposing a second chip having at least one second through via having a second diameter larger than the first diameter as a through via on the support;
Disposing a third chip on the support;
Forming an insulating layer on the support, and embedding the first chip , the second chip, and the third chip in the insulating layer;
Removing the support from the insulating layer;
On said support said insulating layer which is removed, and forming a wiring layer having a first through via and the second through-hole via, the wiring portion for electrically connecting the third chip A method for manufacturing a semiconductor device. Disposing a first chip on a support;
Disposing a second chip on the support;
Disposing a third chip on the support;
Forming an insulating layer on the support, and embedding the first chip , the second chip, and the third chip in the insulating layer;
Removing the support from the insulating layer;
Forming a wiring layer having a wiring portion electrically connected to the third chip on the insulating layer from which the support has been removed;
Forming at least one first through via having a first diameter that penetrates the wiring layer and the first chip and is electrically connected to the wiring portion ;
The wiring layer and through said second chip is electrically connected to the wiring part, viewed including the step of forming at least one second through-hole via the second diameter greater than said first diameter,
The first chip has only the first through via having the first diameter as a through via, and the second chip has only the second through via having the second diameter as a through via. A method for manufacturing a semiconductor device. An insulating layer, wherein the first chip is disposed in the insulating layer, and the second chip and the third chip, and a said insulating layer disposed on the wiring layer, wherein the first chip, a through via having at least one of only the first through via the first diameter, said second chip, at least one has only the second through-hole via the second diameter greater than said first diameter as the through vias, the wiring layer, and a semiconductor device having a first through via and the second through-hole via, the third wiring portion for electrically connecting the chip,
Wherein disposed on the wiring layer side of the semiconductor device, an electronic device which comprises a third chip and electrically connected to the electronic device using a pre-Symbol wiring layer.

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