JP5832311B2 - Reconfiguration device, process allocation method, and program - Google Patents

Description

  The present invention relates to a technique for generating circuit configuration information of a reconfigurable device whose circuit configuration can be changed.

  Conventionally, there has been proposed a reconfigurable device capable of changing the processing content performed by the above circuit by changing the internal circuit configuration even in an LSI circuit device after manufacture. Since the processing can be changed even in the manufactured LSI circuit device, it is not necessary to recreate the LSI in accordance with the specification change or the like. Currently, reconfigurable devices are used in various fields in that the manufacturing cost can be reduced and the development period can be shortened.

  As a configuration of the reconfigurable device, a type in which a large number of LUTs (Look-Up-Tables) are mounted and a type in which a large number of processing elements are mounted are typical. Each element is connected to a switching element such as a multiplexer. Here, settings for operating each component such as the LUT, processing element, and switching element are collectively referred to as circuit configuration information. There are various methods for generating circuit configuration information. Generally, (1) logical processing called technology mapping, (2) physical allocation to each component, (3) route determination of each component, These processes are often performed in order. The circuit configuration information is finally generated through the above three steps.

  (1) In the logical process assignment step, the process is assigned to a component. Specifically, each process is assigned to a logical component without specifying a physical component. As an index for order change, the viewpoint of circuit area, operation speed, and power consumption is generally used. (2) In the placement step, physical assignment of which process is performed with which component in the reconfigurable device is determined. Since the number of switching elements related to data communication differs depending on the distance between processing elements in which processing related to data input / output is arranged, the delay time (maximum operating frequency) varies greatly. For this reason, it is usually important to arrange the processing having an input / output relationship on the processing elements as close as possible to shorten the delay time. (3) In the route determination step, a route by the switching element is determined for data communication between processing elements in an input / output relationship of data communication. In order to determine a specific path as compared with the arrangement process, it is important to determine a path with a reduced delay time between processing elements.

  In recent years, the scale of processing that can be executed in the reconfigurable device is increasing with the improvement in the degree of integration. However, recently, the demand for processing itself has become more complicated and sophisticated than that, and it may be difficult to perform all processing at once with one reconfigurable device. In contrast, there is a method in which processing is sequentially performed in a time-division manner in one reconfigurable device. More specifically, a desired process is first divided, and circuit configuration information corresponding to the divided process is generated. Thereafter, the circuit configuration of the reconfigurable device is changed and processed based on the circuit configuration information. This makes it possible to perform large-scale processing with the reconfigurable device. However, if all the circuit configurations are changed every time, the entire processing time becomes long, and the speed performance deteriorates. Similarly, when the number of processing divisions is large, the processing speed is deteriorated.

  As a method for solving this problem, there is a multi-context reconfiguration device. The context is circuit configuration information, and the multi-context reconfiguration device is a device in which a memory for storing a plurality of circuit configuration information is mounted in the reconfiguration device. When the circuit configuration is changed, the device can be reconfigured by switching the memory, and the circuit reconfiguration time can be greatly reduced by switching at high speed. However, since it is necessary to additionally install a memory for circuit configuration information, there is a problem that the circuit scale increases.

  On the other hand, Patent Document 1 proposes a method based on a skeleton circuit technique as a method for shortening the reconstruction time. In this method, circuit configuration information called a preceding base circuit is configured in advance in a reconfigurable device. Here, the preceding base circuit is a common circuit portion that is common to all of the plurality of circuit configuration information, and a non-exclusive independent circuit that is not common to the plurality of circuits and that does not share the circuit configuration information on the reconfigurable device. This is circuit configuration information consisting of parts. By partially reconfiguring only the circuit differences on the reconfigurable device, a circuit necessary for processing is configured. Compared with the multi-context type, this method does not require an additional configuration memory, so that the circuit scale does not increase.

Japanese Patent No. 3558119

  However, in general, the reconstruction device may execute various applications, and the number of common parts is reduced depending on the application. Further, the number of circuit configuration information to be reconfigured varies depending on the application. In the generation of the preceding base circuit unit described in Patent Document 1, when there are few common parts or the number of circuit configuration information is large and greatly exceeds the circuit scale of the reconfigurable device, the circuit configuration is changed. It is difficult to reduce the period efficiently.

  The present invention has been made in view of the above-described problems, and an object thereof is to efficiently reduce the circuit change period without increasing the circuit scale by considering the order of circuit configuration change.

  The process allocation method of the present invention is a process allocation method for allocating processes to each component for a reconfigurable device composed of a plurality of components, and inputting at least two different data flows and the execution order of the data flows. A data flow input step, a constraint step for inputting the constraint of the component, and a process allocation so that the number of setting changes necessary for reconfiguration of the component based on the constraint and execution order of the component is reduced. And a process allocation determining step for determining.

  According to the present invention, by creating circuit configuration information so as to reduce the number of settings required for reconfiguration, it is possible to shorten the reconfiguration period of the reconfiguration device without increasing the circuit scale.

It is a figure which shows the structural example of the processing apparatus containing a reconstruction device. It is a figure which shows the structural example of a reconstruction device. It is a figure which shows the example of a procedure of the data communication between the elements of a reconstruction device. It is a figure which shows the structural example of a processing element. It is a figure which shows the example of a format of a configuration command. It is a figure which shows the example of an outline | summary of the setting stored in the configuration memory of a processing element. It is a flowchart which shows the procedure which reads / writes a setting. It is a figure which shows the structural example of a switching element. It is a figure which shows the example of an outline | summary of the setting stored in the configuration memory of a switching element. 6 is a time chart for sequentially executing a plurality of data flows. It is a figure which shows the example of an outline of process allocation. It is a figure which shows the example of an outline for performing the process allocation of the data flow in 1st Embodiment. 6 is a flowchart illustrating a process for performing process assignment in the first embodiment. It is a figure which shows the example of an outline for performing the process allocation of the data flow in 2nd Embodiment. It is a figure which shows the example of an outline for performing the process allocation of the data flow in 3rd Embodiment. It is a figure which shows the example of an outline for performing process allocation of the data flow in 4th Embodiment. It is a block diagram which shows an example of a structure of the apparatus which produces circuit structure information.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments to which the invention is applied will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a diagram showing an example of the overall configuration of a system having a reconfigurable device according to an embodiment of the present invention. The external memory 101 holds circuit configuration information 106 therein. The circuit configuration information 106 is a setting group for operating the elements constituting the reconfiguration device 105. The configuration controller 102 acquires circuit configuration information 106 from the memory 101 through the connection 104. The acquired circuit configuration information 106 is sent to the reconfiguration device 105 through the connection 103. Here, a processing element array is used as an example of the reconstruction device 105.

  Although the processing element array will be specifically described below, the present invention is not limited to the configuration and path configuration of each processing element described below.

  FIG. 2 is a diagram showing an outline of a processing element array which is a reconfigurable device in the present embodiment. In the reconfigurable device, switching elements 201 as input / output processing means with 8 inputs and 8 outputs are arranged in a two-dimensional lattice, and processing elements 202 with 4 inputs and 4 outputs as processing means are arranged in the lattice of the switching elements 201. Is arranged. The eight inputs and eight outputs of the switching elements 201a to i are connected to the other four switching elements 201 in the direction of east, west, south, and north (upper right and lower left), respectively, as a set, with one input and one output as a set. . Furthermore, it has a configuration in which it is bidirectionally connected to four different processing elements 202 in the northeast, southeast, southwest and northwest directions via connection lines 204a and 204b. The switching elements 201a to 201i and the processing elements 202a to 202d are connected in a daisy chain in one direction by a connection 205.

  Connections 203 a and 203 b and connection lines 204 a and 204 b are connections that are connected to communicate processing target data between the switching element 201 and the processing element 202. A connection 205 is a connection for supplying settings to the switching element 201 and the processing element 202. With the above settings, the switching element 201 determines the input / output destination of the processing target data, and the processing element 202 determines the input / output destination and processing content of the processing target data. In addition, the direction of the arrow of each connection 203a, 203b, 204a, 204b, 205 of FIG. 2 has shown the direction of data. The switching elements 201a to 201i have the same configuration, and the processing elements 202a to 202d have the same configuration.

  Here, as an example of a communication protocol for each of the connections 203a, 203b, 204a, 204b, and 205, a two-wire handshake using a Valid signal and a Ready signal is shown in FIG. In FIG. 3, a data signal line 303, a valid signal line 304, and a ready signal line 305 are connected between the module A301 on the transmission side and the module B302 on the reception side. The Valid signal is a signal indicating that the transmitting side can transmit to the receiving side through the Valid signal line 304. The Ready signal is a signal indicating that the receiving side can receive data to the transmitting side through the Ready signal line 305. In this protocol, the data on the data signal line 303 is transmitted from the module A301 to the module B302 at the clock rising timing when both the valid signal line 304 from the module A301 and the ready signal line 305 of the module B302 are valid. In the waveform of FIG. 3, data A is transferred from module A301 to module B302 at timing 306a, data B at timing 306b, data C at timing 306c, and data D at timing 306d. The configuration of the processing element 202 is shown in FIG. The processing element 202 includes a configuration unit 401, an input unit 402, a computational unit 403, an output unit 404, and a temporary buffer 405.

  The configuration unit 401 manages settings for determining the operation content of the processing element 202. The input unit 402 performs input processing based on the setting of the configuration unit 401. The computational unit 403 performs arithmetic processing based on the setting of the configuration unit 401. In addition, the computational unit 403 can hold the processed result in the temporary buffer 405 for input to the computational unit 403 again. The output unit 404 performs output processing based on the setting of the configuration unit 401.

  The operation of the processing element 202 will be described more specifically. The input unit 402 acquires the setting for determining the input destination from the configuration unit 401 through the connection 406. The acquired setting specifies which input port is used to communicate with the externally connected module. Based on the information, data to be processed is acquired through the connections 204a-ne, 204a-se, 204a-sw, and 204a-nw. Here, reference numerals ne, se, sw, and nw indicate directions, respectively, and the connection line 204a-ne is connected to a switching element arranged in the northeast. 204a-se is connected to a switching element arranged in the southeast. 204a-sw is connected to a switching element arranged in the southwest. 204a-nw is connected to a switching element arranged in the northwest. The acquired data is sent to the computer unit 403 through the connection 409.

  The computational unit 403 acquires settings for determining the processing contents from the configuration unit 401 through the connection 407. Data sent from the input unit 402 is acquired based on the acquired setting, and the set processing is performed. The processed data is sent to the output unit 404 through the connection 410.

  The computational unit 403 holds at least one computing unit. The arithmetic unit is, for example, an arithmetic unit such as an adder / subtractor, a comparator, a multiplier, a divider, a logical arithmetic unit, or a combination of these, or a combination of these and other arithmetic units. Such as a vessel. In the following, as a specific example, the above-described computational unit 403 will be described assuming that product-sum operation and comparison operation processing can be performed, and one of them can be selectively performed in one operation. In the product-sum operation, the process of a · b + c · d is performed, and in the comparison operation, c is output if a> b, and d is output otherwise. In addition, the computational unit 403 is configured to be able to repeatedly use the arithmetic unit for one input. In the case of repeated use, the processing results once used by the computing unit are stored in a temporary buffer through the connection 412 and then input to the computer unit 403 again through the connection 411. A new process is performed on the data inputted again by the above computing unit. As will be described in detail later, the setting refers to the type of operation and the iterative process, and the values of the variables a, b, c, and d required for each process are referred to. Means to specify.

  The output unit 404 acquires the setting indicating the output destination of the processed data through the connection 408. The acquired setting specifies which output port is used to communicate with the switching element. Based on the information, the data is output to the switching element through connection lines 204b-ne, 204b-se, 204b-sw, and 204b-nw. Here, the connection line 204b-ne is connected to a switching element arranged in the northeast. 204b-se is connected to a switching element arranged in the southeast. 204b-sw is connected to a switching element arranged in the southwest. 204b-nw is connected to a switching element arranged in the northwest.

  Next, the operation of the configuration unit 401 will be described. The configuration unit 401 holds a unique ID for each processing element 202. The configuration unit acquires the setting sent from the input side connection 205, processes it in the configuration unit, and outputs the setting through the output side connection 205. The configuration unit 401 has a configuration memory 413 for storing settings corresponding to its own ID.

  FIG. 5 shows a configuration command 501 for setting that is transmitted to and received from the configuration unit. The configuration command 501 includes a read / write mode 502, an ID 503, a configuration address 504, and a setting value 505. The read / write mode 502 is a signal that determines the read / write processing of the configuration command. The ID 503 is a signal that determines the processing element 202 to be processed. The configuration address 504 is a signal for designating an address in the memory where the setting in the configuration unit 401 is held. A set value 505 is a signal representing an actual set value. In FIG. 5, M, N, O, and P indicating the bit width are values determined by the actually configured architecture.

  Hereinafter, the setting based on the above-described configuration will be described more specifically. Reference numeral 601 in FIG. 6 denotes an address of the configuration memory 413, which corresponds to an address designated by the configuration address 504 in FIG. Reference numeral 602 denotes an actual set value, which corresponds to the set value 505 in FIG. In the present embodiment, each of these is read as a setting, but the present invention is not limited to the units described above. In the figure, an example in which settings relating to the input unit 402, the computational unit 403, and the output unit 404 are held in the configuration memory 413 is shown.

  A setting value indicated by an address 0x0000 — 0000 (“0x” indicates a hexadecimal number) is a setting value for determining an input destination in the input unit 402, and a predetermined input destination is determined according to the value. The iteration number indicated by the address 0x0000 — 0004 is a setting for determining the number of repetitions of the operation in the computational unit 403, and the number of repetitions of the operation is determined according to the value. In the present embodiment, up to four calculations are assumed.

  The operation setting indicated by the address 0x0000 — 0008 is a setting for determining the type of calculation performed in the first calculation, and the product-sum calculation or the comparison calculation is determined according to the value. The variable setting indicated by the address 0x0000 — 000c is a setting for determining the reference destination of the value of the variable a in the first calculation. The reference destination includes an input value from the input port, a fixed value held in the configuration memory 413, and a temporary buffer value holding a previous calculation result. Depending on this value, one of the above values is input to this variable a. Similarly to 0x0000_000c, variable settings indicated by 0x0000_0010, 0x0000_0014, and 0x0000_0018 are settings for determining reference destinations of the values of the variables b, c, and d in the first calculation. Next, the parameter indicated by 0x0000 — 001c is a fixed value for the variable a when the reference destination specified by 0x0000 — 000c in the first calculation is a fixed value. Similar to 0x0000 — 001c, the fixed values indicated by 0x0000 — 0020, 0x0000 — 0024, and 0x0000 — 0028 are values used in the variables b, c, and d in the first calculation.

  Subsequent 0x0000 — 002c to 0x0000 — 0094 indicate setting values for the second, third, and fourth times, respectively, similarly to the setting related to the first calculation indicated by the above 0x0000 — 0008 to 0x0000 — 0028. Finally, an output select value indicated by 0x0000 — 0098 is a setting value for determining an output destination in the output unit 404, and a predetermined output destination is determined according to the value.

  Next, FIG. 7 shows a processing flow performed in the configuration unit. In step S701, a configuration command 501 is input. In step S <b> 702, it is determined whether the ID 503 specified by the input configuration command 501 matches the own ID of the configuration unit 401. If it is determined in step S702 that the ID is different from its own ID, in step S711 and 712, the input configuration command 501 is output without being processed. If it coincides with its own ID, it is next determined in step S703 whether the value of the read / write mode 502 is the read mode. If it is not the read mode, it is determined in step S707 whether or not it is the write mode. If it is not in any mode, the data is output as it is without being processed in steps S711 and 712. If the read mode is determined, the data designated by the configuration address 504 is read from the configuration memory 413 in step S704. Thereafter, the read data is written in the set value 505 of the input configuration command 501 in step S705, and the configuration command 501 is output in step S706. If the write mode is determined, the setting value 505 of the configuration command 501 input in step S708 is written into the configuration memory 413 designated by the configuration address 504. Next, in step S709, the value of the input configuration command 501 is not changed and is output as it is in step S710. One setting value 505 can be changed by a single configuration command, and a desired process is realized by sequentially transmitting configuration commands and changing all necessary setting values. In other words, this set number determines the processing content switching time.

  The configuration of the switching element 201 is shown in FIG. The switching element 201 includes a configuration unit 801 and a crossbar switch 802. The configuration unit 801 manages setting values for determining a connection destination to which data is transferred. The crossbar switch 802 connects the input and output one to one based on the setting of the configuration unit 801. Similar to the configuration unit 401 of the processing element 202, the configuration unit 801 holds a unique ID for each switching element 201. The configuration unit acquires the set value sent from the input side connection 205, performs processing in the configuration unit, and outputs the set value through the output side connection 205. The configuration unit holds the acquired setting in the configuration memory 804. The configuration command of the configuration unit and its processing flow are the same as the format shown in FIG. 5 and the processing flow shown in FIG. The crossbar switch 802 acquires the setting for determining the data input / output destination from the configuration unit 801 through the connection 803. The switching element 201 acquires data through the connections 203a-w, -s, 203b-e, -n, and the connections 204b-ne, -se, -sw, -nw based on the acquired set values. The acquired data is passed through the connected connections 203a-e, -n, 203b-w, -s, and the connections 204a-ne, -se, -sw, -nw.

  Here, the connections 203a-w and -s mean that they are connected to the switching elements arranged in the west and south, respectively. 203b-e and -n mean that the switching elements are connected to the east and north, respectively.

  Connections 203a-e and -n mean that they are connected to switching elements arranged east and north, respectively. 203b-w and -s mean that they are connected to switching elements arranged in the west and south, respectively.

  Connections 204a-ne, -se, -sw, and -nw mean that they are connected to switching elements arranged in the northeast, southeast, southwest, and northwest, respectively. Connections 204b-ne, -se, -sw, and -nw mean that they are connected to switching elements arranged in the northeast, southeast, southwest, and northwest, respectively.

  FIG. 9 shows a setting example related to the input / output connection of the crossbar switch 802 in the switching element 201, which is held in the configuration memory 804. Reference numeral 901 denotes a memory address, which corresponds to the address specified by the configuration address 504 in FIG. Reference numeral 902 denotes a set value, which is the set value 505 in FIG. The connection setting indicated by the address 0x0000_0000 determines whether the input from the connection line 203a-w is output to 203a-e, n, 203b-w, -s, 204a-ne, -se, -sw, or -nw. Is a set value for Subsequently, 0x0000_0004 is a setting value that determines which connection the input from the connection 203a-s is to be output in the same way as 0x0000_0000. 0x0000_0008 is a setting value that determines which connection the input from the connection 203b-e is to be output in the same way as 0x0000_0000. 0x0000 — 000c is a setting value that determines which connection the input from the connection 203b-n is to be output in the same way as 0x0000 — 0000. 0x0000 — 0010 is a setting value that determines to which connection the input from the connection 204b-ne is output as in the case of 0x0000 — 0000. 0x0000 — 0014 is a setting value that determines to which connection the input from the connection 204b-se is output as in the case of 0x0000 — 0000. 0x0000 — 0018 is a setting value that determines which connection the input from the connection 204b-sw is output in the same way as 0x0000 — 0000. 0x0000 — 001c is a setting value that determines to which connection the input from the connection 204b-nw is output as in the case of 0x0000 — 0000.

FIG. 10 shows an example of a time chart for realizing a desired process by changing a plurality of types of the configuration of the reconfigurable device described above. FIG. 10 shows a time chart in which a plurality of different data flows A to Z are sequentially executed by the same reconstruction device. In this embodiment, the data flow and the data flow execution order are input by data flow input.
The data flow handled in the present embodiment is a data flow configured in units that can assign processing to the reconfigurable device at one time. Settings for processing each data flow are generated in advance. A series of processes of reconfiguring the reconfigurable device based on settings generated in advance for the reconfigurable device and performing processing based on the configuration is sequentially performed in a desired execution order.

  In the following description, it is assumed that the data flow A is already assigned processing and the data flow B is subject to processing assignment. Specifically, the process allocation of data flow B is determined with reference to a setting value for executing data flow A to which process allocation has been performed. After determining the process assignment of the data flow B with reference to the process assignment of the data flow A, the data flow B is assumed to be already assigned and the data flow C is set as the process assignment target. Specifically, the processing assignment of data flow C is determined with reference to the setting value for executing the data flow B to which processing has been assigned in the same manner as when the processing assignment of data flow B has been determined. By repeating the above procedure in order, it is possible to assign processing of data flows from A to Z.

  Next, allocation of processing to the processing element of the reconfigurable device in the data flow will be described. Here, the process assignment of the data flow to the processing element is a method of logically assigning each process of the data flow to the processing element. More specifically, as shown in FIG. 11, in which processing element and in which order processing contents corresponding to each node of the data flow are performed are determined. The left diagram in FIG. 11 represents a certain data flow A, the central diagram represents an example of process allocation, and the right diagram represents the settings shown in FIG. 6 based on the process allocation. As described above, the processing element shown in the present embodiment assumes the number of repeated processing, the processing content at each processing number, and a fixed value required at that time. To decide. In the present embodiment, it is assumed that the maximum number of iterations is four. For the data flow, as shown in the central diagram, processing is assigned in order to different processing elements 202 for each group grouped by 1101a to 1104a. Based on the above 1101a to 1104a, settings 1101b to 1104b for the processing elements 202-1 to 202-4 are determined.

  This embodiment is a process allocation method for the purpose of reducing the number of settings shown in FIG. 11, which is required when the processing content (data flow) is switched in the same reconfigurable device as shown in FIG. . FIG. 12 shows an outline of setting change of each processing element 202-1 to 202-4 when the processing in the reconfigurable device is changed from the data flow A to the data flow B. The process of the data flow 1204 corresponds to the process 1201 of the time chart, and it is assumed that the process has already been assigned. The processing of the data flow 1205 corresponds to the processing 1203 of the time chart, and is a data flow to be processed. The processing elements 202-1 to 202-4 to which the respective processes of the data flow 1204 and the data flow 1205 are assigned mean logically identical processing elements. 1101b to 1104b are settings related to the processing elements 202-1 to 202-4 when processing the data flow A, and 1206 to 1209 are settings related to the processing elements 202-1 to 202-4 when processing the data flow B, respectively. is there. In the processing element 202-1, the setting change 1210 is performed from the setting 1101b to the setting 1206 in the setting change period 1202 from the data flow A to B in the time chart. In the processing element 202-2, the setting change 1211 is performed from the setting 1102b to the setting 1207 in the setting change period 1202 from the data flow A to B of the time chart. In the processing element 202-3, the setting change 1212 is performed from the setting 1103b to the setting 1208 in the setting change period 1202 from the data flow A to B in the time chart. In the processing element 202-4, the setting change 1213 is performed from the setting 1104b to the setting 1209 in the setting change period 1202 from the data flow A to B in the time chart. In the present embodiment, when assigning the process of data flow B, first, the data flow A to which processing has been assigned in each processing element 202-1 to 202-4 is referred. Then, data flow B processing is assigned for the purpose of reducing the number of setting changes required when the setting changes 1210, 1211, 1212, and 1213 are performed.

  FIG. 17 shows a block configuration diagram of an apparatus for generating circuit configuration information 106 at the time of transition from the data flow A to the data flow B. In FIG. 17, reference numeral 2501 denotes a CPU that controls the entire apparatus. A ROM 2502 stores a boot program and BIOS. A RAM 2503 is used as a work area of the CPU 2501 and stores an OS (operating system) and applications. Reference numeral 2504 denotes an OS, an application for creating the circuit configuration information 106, and a hard disk drive (HDD) for storing various data. A keyboard 2505 and a mouse 2506 function as a user interface. Reference numeral 2507 denotes a display control unit incorporating a video memory and a display controller therein. Reference numeral 2508 denotes a display device for receiving and displaying a video signal from the display control unit 2507. An interface 2509 communicates with various external devices. For example, when the external memory 101 shown in FIG. 1 is connected, the circuit configuration information 106 created by this apparatus is written into the external memory 101.

  In the above configuration, when the apparatus is turned on, the CPU 2501 executes the boot program stored in the ROM 2502, loads the OS stored in the HDD 2504 into the RAM, and then creates an application for creating the circuit configuration information 106. By starting, this apparatus functions as a circuit configuration information creation apparatus.

  Hereinafter, the processing procedure of this apparatus functioning as the circuit configuration information creating apparatus will be described with reference to the flowchart of FIG. This procedure shows an example of a process assignment method based on simulated annealing, but the present invention is not limited to the above method, and various approximate solutions such as genetic algorithms and numerical optimization methods may be used.

First, elements necessary for explaining the flowchart will be described with reference to FIG. Assume that the index indicating each data flow is i, the index of the processing element is j, and the configuration address of the memory held in the processing element corresponding to the address 601 in FIG. 6 is k. From the above, the set value in each memory can be expressed as u _{i, j, k} . Here, a data flow that has been assigned a process is i0, and a data flow that is a process assignment target is i1. First, in step S1301, a plurality of data flows and their execution order relationship (i order) are input. For data flows that have already been assigned processing, the set values u _{i0, j, k} are also input. In this embodiment, the data flow 1204 has already been assigned processing, and the setting value in each memory of each processing element related to the data flow 1204 is given as a fixed value. The data flow 1205 is a process allocation target.

  In step S1302, the required specifications and hardware constraint conditions are input. Here, the hardware constraint condition may be a constraint on the hardware configuration such as the number of processing elements in the reconfigurable device, the number of repetition processes that can be processed by the processing element, and the type of arithmetic unit. The required specifications are items that should be restricted in terms of hardware usage, such as the number of processing elements used, the number of repetitions, and the types of computing units that can be used. Furthermore, whether there is any contradiction in the input / output order relationship of processing, deadlocks, etc. are also related to this constraint. Further, there is a restriction that the processing assignment is not changed for a data flow that has already been assigned a processing. However, the present invention is not limited only to the above-described restrictions.

  Subsequently, in step S1303, process allocation of the data flow to be processed is performed. In the initial process assignment, there is a method of assigning processes randomly or assigning processes in the order of the depth direction of the data flow, but it is not limited to these methods. If it is not the initial allocation, for example, the processing allocation is changed based on simulated annealing so that two arrangements are randomly selected and exchanged. In this embodiment, an initial process allocation or a process allocation change is performed for the data flow 1205 to be allocated to a process. For data flows that have already been assigned a process, the process assignment is not changed based on the constraints. In step S1304, it is determined whether the process assignment result satisfies the requirement specification input in step S1303.

As shown in the following equation, if the constraint is satisfied, the penalty variable p _{0 is set} to 0, and if it is violated, the penalty variable p ₀ is set to the penalty value C _p0 .

Here, in this embodiment, when there is a violation, the uniform C _p0 is treated as a constant value, but it may be a variable value according to the violation item. In step S1305, it is determined whether the process assignment result satisfies the hardware constraint condition input in step S1302. As shown in the following equation, if the constraint is satisfied, the penalty variable P _{1 is set} to 0, and if it is violated, the penalty variable P ₁ is set to the penalty value C _p1 .

Here, in this embodiment, when there is a violation, the uniform C _p1 is treated as a constant value, but it may be a variable value according to the violation item. In step S1306, the number of setting changes between target data flow changes is calculated, and an evaluation value is calculated. If it demonstrates in the example of FIG. 12, it is the setting number which needs to be changed in the case of the setting changes 1210, 1211, 1212, 1213. More specifically, the setting value u _{i0, j, k} in the data flow i0 to which processing has been assigned matches the setting value u _{i1, j, k at} the same address in the data flow i1 to be processed. If not, add α ₁ to the number of setting changes. If the above values match, nothing is added. The above calculation is performed for all memories k of all processing elements j. The number of setting changes described above can be expressed by the following formula.

Here, α ₁ is normally 1, but it is also possible to change the weight for each address where each setting is stored according to the structure of the configuration memory of the processing element. In addition, in order to give priority to the switching time for each data flow, it is possible to weight each data flow.

  As shown in FIG. 7, since one setting value can be changed with a single configuration command, the processing content switching time can be reduced if this number is reduced. The formula for calculating the evaluation value in this step is defined as follows from the above formula.

  That is, the evaluation value decreases as the number of setting changes necessary for reconfiguration decreases while satisfying the required specifications and hardware constraint conditions. Finally, in step S1307, it is determined whether the target has been achieved based on simulated annealing. If the target has been achieved, the process ends. If the target has not been reached, the process returns to step S1303, and steps S1303 to S1307 are repeated. Here, the target value is repeated until a sufficiently good result is obtained or a predetermined calculation time is reached.

  As a result, the circuit configuration information 106 is generated in the HDD 2504. After that, it can be written to the external memory 101 to be used via the interface 2509 and mounted in the actual product.

  In the embodiment described above, the example in which the circuit configuration information 106 is created by an external device (FIG. 17) has been shown. This is the same in all embodiments described below. Further, the configuration controller 102 may create the circuit configuration information 106 by executing the processing of FIG. 13 instead of the external device. For example, the external memory 101 stores settings for each of a plurality of data flows (required number of processors and processing parameters for each processor), and the configuration controller 102 creates circuit configuration information 106 based on the settings of the plurality of data flows. That's fine. This point is also applicable to all embodiments described below.

  In the method of assigning a process to a processing element of a data flow in a general reconfigurable device, since the number of setting changes is not conscious, it is necessary to change all settings between data flow process changes. In the present invention, it is possible to effectively reduce the number of setting changes by paying attention to the processing order of the data flow and reducing the total number of changes at the setting level which is the minimum unit.

  Next, a second embodiment of the present invention will be described. FIG. 14 shows an overview of the process time chart and process allocation according to the second embodiment. In this embodiment, when processing a plurality of data flows by changing the setting of the reconfigurable device, the processing content itself of each data flow is determined, but the execution order of the data flow is indeterminate, This is an embodiment relating to process assignment when changing according to input data or the like. Specifically, in FIG. 14, it is assumed that the processing performed by the reconfigurable device is not constant, for example, the execution order changes according to the result or state as shown in the time chart 1401.

  In the period 1402 in the time chart 1401, processing related to the data flow A is performed, processing related to the data flow C is performed in the periods 1404 and 1408, and processing related to the data flow B is performed in the period 1406. In the period 1403, the setting change of the data flow A to the data flow C is performed. In the period 1405, the setting change from the data flow C to the data flow B is performed. In the period 1407, the setting change of the data flow C from the data flow B is performed. In this embodiment, since the execution order of the data flows A, B, and C is not constant, it is necessary to perform processing assignment in consideration of all setting changes between the respective data flows. Data flows A, B, and C are all processing allocation targets.

  14, 1409, 1410, and 1411 respectively show setting examples of the PEs 202-1 to PE 202-4 in the data flows A, B, and C, and all the data flows A, B, and C are assigned processing at once. And do it. Similarly to the first embodiment, 1409, 1410, and 1411 are the settings shown in FIG. In the present embodiment, attention is paid to the total number of setting changes necessary for data flow change in the PEs 202-1 to 202-4 between the data flows A and B, between B and C, and between C and A. By calculating the total number as an evaluation value, the number of setting changes at the time of reconfiguration of the reconfigurable device is reduced.

  Note that changes in the settings of the PEs 202-1 to 202-4 between the data flows A and B are represented by 1412, 1415, 1418, and 1421, respectively. In addition, setting changes of the PEs 202-1 to 202-4 between the data flows B and C are represented by 1413, 1416, 1419, and 1422, respectively. Changes in the settings of the PEs 202-1 to 202-4 between the data flows C and A are represented by 1414, 1417, 1420, and 1423, respectively.

  The difference between the present embodiment and the first embodiment is that processing allocation of a plurality of data flows is performed at the same time. In step S1301 in FIG. 13, a plurality of data flows are input, and at the same time, an arbitrary execution order is input.

  In the process assignment performed in step S1303 of FIG. 13, process assignment is performed for all the data flows 1409, 1410, and 1411 that are the process assignment targets. The number of setting changes used in step S1306 in FIG. 13 has the following difference from the first embodiment.

If the set value u _{i0, j, k} in the data flow i0 to be processed and the set value u _{i1, j, k at} the same address in the data flow i1 to be processed do not match, α ₂ is set. Add to the number of setting changes. If the set value u _{i1, j, k} in the data flow i1 to be processed and the set value u _{i2, j, k at} the same address in the data flow i2 to be processed do not match, β Add ₂ to the number of setting changes. Furthermore, if the set value u _{i2, j, k} in the data flow i2 to be processed and the set value u _{i0, j, k at} the same address in the data flow i0 to be processed do not match, γ Add ₂ to the number of setting changes. Other than the above, nothing is added if the set values match. The above calculation is performed for all memories k of all processing elements j as in the following equation.

Here, i0 indicates a data flow A 1409, i1 indicates a data flow B1410, and i2 indicates a data flow C1411, and these set values u _{i0, j, k} , u _{i1, j} are reduced so that the value shown in the above equation is reduced. _{, k} and u _{i2, j, k} are determined. Α ₂ , β ₂ , and γ ₂ are normally 1 respectively, but the weight can be changed for each address in which each setting is stored according to the configuration of the configuration memory of the processing element. In addition, in order to give priority to the switching time for each data flow, it is possible to weight each data flow. According to the present embodiment, by considering all the data flows, an effect of reducing the number of setting changes can be obtained on average even when the execution order of processing is indefinite.

  Next, a third embodiment of the present invention will be described. FIG. 15 shows a time chart of processing according to the present embodiment and an outline of processing allocation. In the present embodiment, it is assumed that the execution order of a plurality of data flows and the respective process assignments are already determined. This is an embodiment relating to process assignment for inserting a process corresponding to a new data flow without changing the process assignment before and after the insertion between processes of an arbitrary data flow in the execution order described above.

  A time chart 1501 in FIG. 15 is a time chart in which the execution order to be performed by the reconfigurable device is already determined, and the process allocation is also determined. In the time chart 1501, after the processing 1503 of the data flow A, the processing 1505 of the data flow C is performed after a period 1504 of changing from the setting of the data flow A to the setting of the data flow C. The time chart 1502 is a time chart in which the data flow B is newly inserted between the data flow A and the data flow C in the time chart 1501. After the processing 1503 of the data flow A, the processing 1507 of the newly inserted data flow B is performed after a period 1506 of changing from the setting of the data flow A to the setting of the data flow B. Thereafter, processing 1505 of data flow B is performed after a period 1508 of changing from setting of data flow B to setting of data flow C. At this time, in order to determine the process assignment of the data flow B without changing the process assignments of the data flows A and C, the setting change amount between the data flows that have already been assigned before and after the insertion is considered.

  15, 1509, 1510, and 1511 indicate the settings of the PEs 202-1 to 202-4 in the data flows A, B, and C, respectively. In this embodiment, data flows A and C have already been assigned processing, and data flow B is assigned processing. Similarly to the first embodiment, 1509, 1510, and 1511 are the settings shown in FIG. Specifically, in the present embodiment, the process assignment for the data flows A and C has been determined, and the process assignment for the data flow B is performed.

  At that time, attention is paid to the total number of setting changes necessary for changing the settings of the PEs 202-1 to 202-4 from data flow A to B and from B to C. The total number is calculated as the evaluation value indicated by 1308 in FIG. 13 in the first embodiment, thereby reducing the number of setting changes when reconfiguring the reconfigurable device.

  Note that the setting changes of the PEs 202-1 to 202-4 between the data flows A and B are represented by 1512, 1514, 1516, and 1518, respectively. In addition, changes in the settings of the PEs 202-1 to 202-4 between the data flows B and C are represented by 1513, 1515, 1517, and 1519. The difference between the present embodiment and the first embodiment is that, when allocating a process of one data flow, a plurality of other process-allocated data flows are referred to at the same time.

  The process assignment performed in step S1303 of FIG. 13 is the data flow 1510 that is a process assignment target. Data flows 1509 and 1511 have already been assigned processing, and the processing assignment is not changed. The number of setting changes used in step S1306 in FIG. 13 has the following difference from the first embodiment.

If the setting value u _{i0, j, k} in the data flow i0 to which processing has been assigned and the setting value u _{i1, j, k at} the same address in the data flow i1 to be processed do not match, α ₃ is set. Add to the number of setting changes. If the setting value u _{i1, j, k} in the data flow i1 to be allocated for processing does not match the value of the setting value u _{i2, j, k at} the same address in the data flow i2 to which processing has been allocated, β Add ₃ to the number of setting changes. If the above values match, nothing is added. The above calculation is performed for all memories k of all processing elements j. The number of setting changes described above can be expressed by the following formula.

Here, i0 indicates data flow A1509, i1 indicates data flow B1510, and i2 indicates data flow C1511. Among these set values, u _{i0, j, k} and u _{i2, j, k} have already been assigned to processing, and u _{i1, j, k} is determined so that the value shown in the above equation is reduced. Α ₃ and β ₃ are normally 1 respectively, but the weight can be changed for each address where each setting is stored according to the configuration of the configuration memory of the processing element. In addition, in order to give priority to the switching time for each data flow, it is possible to weight each data flow. When a new data flow is inserted, the effect of reducing the number of setting changes with the data flow before and after the insertion can be obtained.

  Next, a fourth embodiment of the present invention will be described. FIG. 16 shows a time chart of processing according to the present embodiment and an outline of processing assignment. In this embodiment, after processing a data flow as a reference, the embodiment relates to processing allocation when the data flow to be performed next differs depending on the result.

  The time chart 1601 in FIG. 16 performs processing of the reference data flow X in the period 1602, and then changes the setting from the data flow X to the data flow A, B, or C in the period 1603 according to the result. After the setting is completed, the data flow A, B, or C is processed in the period 1604, and the setting is changed from the data flow A, B, or C to the data flow X in the period 1605 in order to perform the reference data flow X again. I do. The above execution order is repeated, but whether data flow A, B, or C is performed varies depending on the result of data flow X.

  In FIG. 16, 1606, 1607, 1608, and 1609 indicate the settings of the PEs 202-1 to PE202-4 in the data flows X, A, B, and C, respectively. In the present embodiment, processing allocation of all data flows X, A, B, and C is performed. Similar to the first embodiment, 1606, 1607, 1608, and 1609 are the settings shown in FIG. In the present embodiment, specifically, processing allocation of the data flows X, A, B, and C is performed.

  At the time of process allocation, attention is paid to the total number of setting changes necessary for data flow changes in the PEs 202-1 to 202-4 between the data flows X and A, between X and B, and between X and C. The total number is calculated as an evaluation value indicated by 1304 in FIG. 13 in the first embodiment, thereby reducing the number of setting changes when reconfiguring the reconfigurable device. Note that the setting changes of the PEs 202-1 to 202-4 between the data flows X and A are represented by 1610, 1613, 1616, and 1619, respectively. In addition, changes in the settings of the PEs 202-1 to 202-4 between the data flows X and B are represented by 1611, 1614, 1617, and 1620, respectively. Changes in the settings of the PEs 202-1 to 202-4 between the data flows X and C are represented by 1612, 1615, 1618, and 1621, respectively. The difference between this embodiment and the first embodiment is that there is a branch in the execution order, and processing is assigned to the data flow between the branch destination and the branch source.

  In step S1301 of FIG. 13, a plurality of data flows are input, and an arbitrary execution order is partially input. The process assignment performed in step S1303 in FIG. 13 assigns the process to all the data flows 1606, 1607, 1608, and 1609 that are the process assignment targets. In the present embodiment, an example is shown in which all data flows are handled as processing allocation targets, but the present invention is not limited to this. In this embodiment, attention is paid to the execution order of data flows. When at least one data flow has already been assigned processing, processing assignment for other data flows is performed.

The number of setting changes used in step S1306 in FIG. 13 has the following difference from the first embodiment. If the set value u _{i0, j, k} in the data flow i0 to be processed and the set value u _{i1, j, k at} the same address in the data flow i1 to be processed do not match, α ₄ is set. Add to the number of setting changes. If the set value u _{i0, j, k} in the data flow i0 to be processed and the set value u _{i2, j, k at} the same address in the data flow i2 to be processed do not match, β Add ₄ to the number of setting changes. Further, if the set value u _{i0, j, k} in the data flow i0 to be processed and the set value u _{i3, j, k at} the same address in the data flow i3 to be processed do not match, γ Add ₄ to the number of setting changes. Other than the above, nothing is added when the set values match. The above calculation is performed for all memories k of all processing elements j.

Here, i0 indicates data flow X1606, i1 indicates data flow A1607, i2 indicates dataflow B1608, and i3 indicates dataflow A1609. U _{i0, j, k} , u _{i1, j, k} , u _{i2, j, k} , u _{i3, j, k} are determined so that the value shown in the above equation is reduced. Α ₄ , β ₄ , and γ ₄ are normally 1 respectively, but the weight can be changed for each address where each setting is stored according to the configuration of the configuration memory of the processing element. In addition, in order to give priority to the switching time for each data flow, it is possible to weight each data flow.

  According to this embodiment, when performing a plurality of data flows in order, even if there is a branch in the execution order, by considering a data flow that is a branch source and a plurality of other data flows that are a branch destination, The effect of reducing the number of setting changes can be obtained.

  In the above-described embodiment, each route setting method has been described for each use case, but the present invention may be a combination of these methods. Further, although the processing element has been described as a component of the reconfigurable device, the present invention is not limited to this, and an LUT or a combination thereof may be used. Further, the setting is not limited to the setting shown in the embodiment, and may be a setting used in an LUT-based reconfiguration device. In the embodiment, the processing allocation target is set for all the input data flows. However, the processing allocation may be performed for only a part of the data flow by specifying the processing allocation range. In the embodiment, the number of processing elements is the same between data flows, but the number of processing elements to which processing is assigned may be different.

  The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and a computer (or CPU, MPU, or the like) of the system or apparatus reads the program. It is a process to be executed.

Claims (6)

A process assignment method for assigning a process to each component with respect to a reconfigurable device composed of a plurality of components,
A data flow input step for entering at least two different data flows and the execution order of the data flows;
A constraint step for inputting constraints of the component;
And a process allocation determining step of determining a process allocation so that the number of setting changes necessary for reconfiguration of the component elements based on the constraints and execution order of the component elements is reduced.   Of the input data flows, at least one data flow has been assigned a process, and the process flow is assigned to a data flow that has not been assigned a process by referring to the data flow to which the process has been assigned. The process allocation method according to claim 1.   2. The process allocation method according to claim 1, wherein a process allocation is performed for a plurality of data flows that are not allocated to a process among the data flows.   2. The process allocation method according to claim 1, wherein the setting change number is weighted by a setting for determining a processing content of each component or each component.   The program for making a computer perform each step of the process allocation method of any one of Claims 1 thru | or 4. A reconfiguration device that assigns processing to each component for a reconfiguration device composed of a plurality of components,
Data flow input means for inputting at least two different data flows and the execution order of the data flows;
Constraint means for inputting the constraint of the component;
A reconfiguration device, comprising: process allocation determination means for determining a process allocation so that the number of setting changes required for reconfiguration of the component based on the constraint of the component and the execution order is reduced.

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