JP5773306B2 - Method and apparatus for forming a semiconductor device structure - Google Patents

Description

  The present invention relates to a method of forming a material layer on a partially fabricated integrated circuit. More particularly, the present invention relates to a method for forming a protective cap in a copper wire to improve the electromigration characteristics of a damascene interconnect.

  The damascene process is a method of forming a metal line on an integrated circuit, in which a metal line is provided in a trench and a via is formed in a dielectric layer (inter layer dielectric). Damascene processes are often preferred because they require fewer processing steps than other methods but have a high yield. The damascene process is particularly suitable for applications to metals such as copper that are difficult to pattern by plasma etching.

  In a typical damascene process flow, metal is deposited on the patterned dielectric to fill the vias and trenches formed in the dielectric layer. The resulting metallized layer is usually laminated directly on the layer having the laminated active element or on the underlying metallized layer. A thin film layer made of a dielectric diffusion barrier material such as silicon carbide or silicon nitride is deposited between adjacent metallization layers to prevent the metal from diffusing into the dielectric bulk layer. In some cases, a dielectric diffusion barrier layer made of silicon carbide or silicon nitride may be used as an etching stop layer used for patterning an interlayer dielectric (ILD).

  In a typical integrated circuit (IC), a plurality of metallized layers are deposited to form a stacked body, and vias and trenches filled with metal are used as IC conductive paths. A plurality of conductive paths in one metallization layer are connected to a plurality of conductive paths in the lower layer or upper layer by a series of damascene interconnects.

  The manufacture of these interconnects presents challenges that have become increasingly prominent in recent years as the dimensions of IC element features continue to shrink. In the current 90 nm technology node or a more advanced node, there is a strong demand for a method of manufacturing an interconnect that can provide an interconnect with increased lifetime and reliability.

  A problem in the IC manufacturing stage is electromigration failure. Electromigration is caused by the formation of voids in the interconnect as a result of the movement of metal atoms carrying the current due to the high current density experienced by the interconnect. The device may eventually fail due to the formation of voids, which is known as electromigration failure. As the scale of IC elements progresses, the dimensions of the interconnect also decrease, and the current density experienced by the interconnect increases. Therefore, the possibility of electromigration failure increases as the scale of the device progresses. Copper has a higher electromigration resistance than aluminum, but even in copper interconnects, reliability is significantly threatened by electromigration failures at 45nm technology nodes or even more advanced nodes.

  In accordance with the present invention, a protective cap is provided at the interface between the metal line and the dielectric diffusion barrier (or etch stop) layer to enhance the electromigration performance of the interconnect. A method of forming this cap is also provided. When this protective cap is formed as a very thin layer located at the interface with the dielectric diffusion barrier layer in the upper part of the metal line, it is preferable that the interconnect resistance is not increased so much. For example, the protective cap layer may include a solid solution, an alloy, a compound, or the like of an interconnect metal (such as copper) with a doping element (such as boron, aluminum, or titanium). In many embodiments, it is preferred to select a doping element that can form an alloy with the interconnect metal and / or can accumulate at grain boundaries to reduce the migration of interconnect metal atoms.

  According to the provided method, a source layer of a dopant generating material (eg, a material comprising B, Al, Ti, etc.) is deposited over the exposed metal lines, and the top of the source layer is exposed to a passivation layer (eg, Nitrides or oxides) and allowing the unmodified portion of the dopant-generating source layer to remain in contact with the interconnect metal to diffuse dopant from the unmodified portion of the source layer into the interconnect metal. And / or by acting on the interconnect metal, the thickness of the protective cap can be controlled. In one embodiment, the amount of dopant introduced into the interconnect is limited by the thickness of the unmodified portion of the source layer that is in contact with the interconnect. In other embodiments, the amount of dopant introduced into the interconnect is controlled by controlling the temperature during diffusion and / or reaction.

  The thin protective cap formed in this manner provides a resistance to interconnect that tends to be inadvertent when depositing large amounts of highly reactive or diffusible dopants (eg, Si or Ge) on the interconnect metal. This is preferable because it does not cause a significant increase. In addition, as described below, the provided method is suitable for forming a protective cap layer from a dopant-generating source layer that is scarcely or selectively deposited on both exposed metal and dielectric. Yes. It should be understood that these methods can also be used when the source layer containing the dopant is selectively deposited only on the metal layer with little deposition on the dielectric.

  In one aspect, a method for forming a semiconductor device structure is provided. In one embodiment, the method includes: (a) applying a substrate having a first metal (eg, copper or copper alloy) exposure layer and a dielectric exposure layer to boron or a second metal (eg, Al, Hf, Ti). Depositing a source layer comprising boron or a second metal on both the dielectric and the first metal in contact with a compound comprising, Co, Ta, Mo, Ru, Sn, Sb); (B) modifying at least the top of the source layer above the first metal region to form a passivation layer, and keeping the unmodified source layer portion in contact with the first metal layer; (c) Diffusing the active component of the unmodified source layer into the first metal and / or reacting with the first metal to form a protective cap in the first metal layer.

In one embodiment, the substrate is a damascene structure that includes exposed copper wires embedded in an intermetallic dielectric layer. Optionally, prior to the deposition of the source layer, the substrate can be pre-cleaned to remove contaminants (eg, copper oxide) from the copper surface. For example, this pre-cleaning can be performed, for example, by exposing the substrate to a reducing gas (eg, H ₂ or NH ₃ ) in plasma. Thereafter, a source layer containing a dopant source (active component) may be deposited by contacting the substrate with a volatile dopant precursor at a constant temperature. Usually (although not essential), the deposition of the source layer is performed thermally without using a plasma discharge. Pre-cleaning and source layer deposition can be performed in a CVD apparatus without releasing the vacuum (eg, can be performed in the same process chamber).

In one embodiment, exposing the substrate to a gas mixture comprising B ₂ H ₆ (or a precursor containing other volatile boron) and an inert carrier gas at a chamber temperature between about 200 and 400 degrees Celsius. A source layer containing boron is deposited. The pressure in the deposition chamber is maintained in the range of about 0.5 to 10 Torr, and the concentration of B ₂ H ₆ in the mixed gas is maintained in the range between about 0.5 and 20% volume ratio. Under this condition, a source layer containing boron is deposited over the exposed dielectric and over the metal portion of the substrate. The source layer is known to contain B—H bonds and may be referred to as a BH _x layer.

  In many embodiments, because of the high precursor decomposition rate at the metal surface, a greater amount of dopant source material is deposited on the metal portion than on the dielectric portion in the substrate. As a result, in these embodiments, the thickness of the source layer deposited on the metal portion is greater than the thickness of the source layer deposited on the dielectric. However, in a precursor containing many boron and a precursor containing metal, it is usually difficult to perform deposition on the metal and the dielectric in this manner. The described deposition method is preferred because the source layer deposition need not be absolutely selective with respect to the metal / dielectric.

In some embodiments, precursors containing volatile metals (eg, metal halides, metal hydrides, metal carbonyls, etc.) at temperatures and pressures that can decompose the precursors and deposit a metal-containing layer on the substrate. Alternatively, the source layer containing the metal is deposited by exposing the substrate to a volatile organometallic compound). In many cases, temperatures and pressures in the same range as described above can be applied during the deposition of the BH _x layer. One skilled in the art understands that deposition conditions can be optimized depending on the type of metal precursor.

  There are a number of metals that are suitable as dopants to form protective caps, including those that form solid solutions, alloys, or intermetallic layers with interconnect metals and can diffuse and accumulate at grain boundaries within the interconnect. Metal is included. Examples of components of the protective cap include Al, Hf, Ti, Co, Ta, Mo, Ru, Sn, and Sb. It is also possible to use alloys and solid solutions between these metals, and alloys and solid solutions of these metals with other metals. Some suitable volatile precursors for source layers containing aluminum include trimethylaluminum, dimethylaluminum hydride, triethylaluminum, triisobutylaluminum, and tris (diethylamino) aluminum. Is included, but is not limited thereto. Suitable precursors for the deposition of other metals include bis (cyclopentadienyl) cobalt, cobalt (II) acetylacetonate, tetrakis (diethylamide) hafnium ( tetrakis (diethylamido) hafnium), tetrakis (dimethylamido) hafnium, tetrakis (dimethylamido) molybdenum, tetrakis (dimethylamino) titanium (TDMAT) TDMAT)), tetrakis (diethylamino) titanium (TDEAT), tetrakis (ethylmethylamido) titanium, bis (diethylamino) bis (diisopropylamino) titanium (bis (diethylamino) bis (diisopropylamino) titanium), penta Pentakis (dimethylamino) tantalum, tertiary (butylimidotris) (diethylamido) tantalum (TBTDET) tert (butylimidotris) (diethylamido) tantalum (TBTDET), pentakis (diethylamido) tantalum (pentakis (diethylamido) tantalum), bis (ethylcyclopentadienyl) ruthenium, tris (dimethylamido) antimony, and tetramethyltin, including but not limited to Not done.

As described above, after deposition of a source layer containing boron or metal, the upper portion is modified to form a passivation layer (eg, a layer containing nitride or oxide), and the lower portion is not modified, without modification. Keep in contact with. In many embodiments where deposition is performed such that the thickness of the source layer on the metal is greater than on the dielectric, this modification process causes the portion of the source layer on the dielectric to have a low conductivity material (eg, Completely converted into a passivation layer including BN _x , AL _x O _{y and the} like. This correction is made to prevent a short circuit between adjacent interconnects. Furthermore, a partial modification of the source layer above the metal line has the effect of controlling the amount of dopant above this layer so that the thickness of the protective cap and thus the interconnect resistance can be controlled. become.

Many processes can be used to form the passivation layer. In one embodiment, the source layer is modified by exposing the substrate to a reactant comprising nitrogen during the plasma discharge. For example, NH ₃ , N ₂ H ₄ , amine, N ₂ , and mixtures thereof can be utilized. In a particular example, exposing the substrate to a mixture of N ₂ and NH _{3 in} a plasma modifies the BH _x source layer to form a passivation layer containing BN _x . In other embodiments, the source layer (eg, a metal containing source layer) is modified by exposing the substrate to a compound containing oxygen (eg, O ₂ , N ₂ O, or CO ₂ ) during plasma discharge to modify the oxide A passivation layer containing (eg, aluminum oxide, titanium oxide) is formed. In yet another embodiment, the source layer is modified with carbon that contains reactants in the plasma to form a passivation layer that includes carbides or hydrocarbons (eg, BC _x , C _x H _y ).

  The thickness of the correction layer can be formed to a desired thickness. By controlling the thickness of the correction layer, the thickness of the remaining unmodified layer containing the dopant source can be controlled, so that the thickness of the protective cap in the interconnect can also be controlled. For example, between about 20 to 60% of the thickness of the source layer above the metal line is modified to form a passivation layer, and the portion containing the remaining unmodified dopant remains in contact with the metal line. In one example, the source layer on the metal line has a thickness of about 50 to 500 Angstroms. After converting between about 20 to 60% of the thickness of the source layer to a passivation layer, an unmodified source layer of between about 20 to 400 angstroms remains in contact with the metal lines.

  Next, after forming the modification layer, the active component of the unmodified source layer is diffused into and / or reacted with the interconnect metal to form a protective cap in the interconnect metal layer. In some embodiments, the active ingredient is first formed in the source layer prior to forming the protective cap. Depending on the nature of the active component, various conditions can be used to generate the active component and promote its diffusion into the interconnect metal. In some embodiments, exposing the substrate to a high temperature for a predetermined time facilitates the formation of a protective cap in the metal interconnect. In other embodiments, the protective cap is formed by placing at room temperature after sufficient dopant diffusion time.

  In some embodiments, after forming the passivation layer, an etch stop layer or a dielectric diffusion barrier layer (eg, a layer comprising doped or undoped silicon carbide or silicon nitride) is deposited over the passivation layer. Let In other embodiments, the passivation layer itself may function as an etch stop layer or a dielectric diffusion barrier layer, and there is no need to provide a separate etch stop layer. In the latter case, the intermetallic dielectric is deposited directly on the passivation layer.

  In some embodiments, doping of the interconnect metal by diffusing the dopant into and / or reacting with the interconnect metal occurs after deposition of the dielectric diffusion barrier or etch stop layer. For example, the formation of the protective cap may be facilitated by heating the substrate to at least about 100 degrees Celsius after deposition of the etch stop layer (eg, a nitrogen carbide layer).

  Some embodiments have the advantage that the entire capping process and diffusion barrier (or etch stop) deposition process can be performed sequentially in one module without releasing the vacuum. A PECVD module apparatus in which a plurality of stations are included in one chamber or has a plurality of chambers is suitable as an apparatus for performing this deposition. An advantage is that both the metal-containing layer and the dielectric layer are sequentially deposited without releasing the vacuum in one PECVD apparatus. For example, in one embodiment, the process includes depositing a source layer comprising a metal, converting the top of the source layer to a passivation layer, and forming a protective cap with an active component within the metal interconnect to form a dielectric diffusion barrier. Alternatively, a process of forming an etching stop layer is included, and all these processes are performed in one apparatus without releasing the vacuum state.

  An element formed using these methods has excellent electromigration characteristics and excellent adhesion characteristics at the metal / dielectric diffusion interface.

In another aspect, a semiconductor device is provided. The semiconductor device includes a dielectric material region and a region of copper or copper alloy embedded in the dielectric material. The device further includes a layer comprising BN _x provided on the dielectric layer and on the copper or copper alloy region. The device further includes a cap containing boron in the region of copper or copper alloy.

  In another aspect, an apparatus is provided for forming a protective cap on or in a metal portion of a partially fabricated semiconductor device. The apparatus includes: (a) a process chamber having an inlet for introducing a reactant; (b) a wafer support that supports the wafer during formation of the protective cap; and (c) a controller that includes program instructions for depositing the protective cap. Including. The instructions include: (i) depositing a source layer containing boron or a second metal over the exposed portion of metal or dielectric on the wafer substrate, and (ii) modifying the top of the active component layer. Including instructions for forming a passivation layer and (iii) diffusing the active component of the source layer into the metal on the substrate and / or reacting with the metal to form a protective cap. In some embodiments, the apparatus is a PECVD apparatus. The described process can also be executed sequentially at one station in a multi-station device. In other embodiments, some processing may be performed at the first station of the apparatus and other processing may be performed at other stations. One station may perform processing at a first temperature and the other station may perform processing at another temperature. For example, the deposition of the source layer can be performed at a first temperature in one station of the multi-station apparatus, and subsequent source layer modification processes can be performed at different temperatures at different stations. The movement of the substrate between the stations can be performed without releasing the vacuum state. In other embodiments, the process can be performed in a multi-chamber apparatus as well, in which case movement of the substrate between the chambers can be performed without exposing the substrate to ambient conditions.

  In another aspect, a method is provided for forming a protective cap comprising aluminum on an oxide free copper surface. The method comprises: (a) exposing a substrate having an oxide-free copper or copper alloy exposed layer and a dielectric exposed layer to a compound comprising aluminum to form the dielectric and the copper or copper alloy; A process for forming a first layer comprising aluminum on both; (b) a process for chemically modifying at least a portion of the first layer to form a passivation layer comprising aluminum; and (c) And) a process of depositing a dielectric layer over the passivation layer. In some embodiments, each of processes (a), (b), and (c) is performed in a chemical vapor deposition (CVD) apparatus. In a further embodiment, the dielectric layer deposited in step (c) is an etch stop dielectric layer. The etch stop dielectric layer may be a doped or undoped material such as, for example, silicon nitride or silicon carbide. In another embodiment, the dielectric layer deposited in step (c) is an interlayer dielectric (ILD) layer deposited directly on the passivation layer.

In certain embodiments, the method further includes additional processing prior to processing (a). Specifically, the surface of the substrate is cleaned to completely remove copper oxide from the surface of copper or copper alloy. Examples of cleaning techniques include (1) direct plasma treatment, (2) remote plasma treatment, (3) UV treatment, and (4) heat treatment in a gas containing at least one of N ₂ , NH ₃ , and H _2. Is mentioned.

  In the embodiments described above, process (a) includes a process wherein the substrate temperature is at least about 350 degrees Celsius (eg, at least about 400 degrees Celsius) and the substrate is exposed to the organoaluminum compound without using plasma. For example, the organoaluminum compound may be trimethylaluminum.

  In certain embodiments, treatment (b) substantially completely passivates the first layer on the copper or copper alloy without substantially diffusing aluminum into the copper layer. Alternatively, process (b) may partially diffuse aluminum into the copper layer and partially passivate the first layer on the copper or copper alloy.

  In certain embodiments, the passivation of the layer in step (b) includes a step of forming a substantially immobile compound having an Al-N bond. In certain embodiments, passivation includes treating the substrate with a nitrogen containing agent, which may include, for example, direct plasma treatment, remote plasma treatment, UV treatment, or heat treatment. . More specifically, the substrate can be exposed to a substance containing nitrogen without using plasma in the processing. This latter process is suitable, for example, when the dielectric is a ULK dielectric.

In yet another embodiment, the passivation of the layer in step (b) includes a step of forming a substantially immobile compound containing an AL-O bond. The treatment includes treating the substrate with a substance that includes oxygen, and the treatment may be, for example, any one of direct plasma treatment, remote plasma treatment, UV treatment, or heat treatment. In certain embodiments, the treatment may include exposing the substrate to a material containing oxygen without utilizing a plasma. This process is suitable when the dielectric is, for example, a ULK dielectric. Examples of substances containing oxygen include O ₂ , N ₂ O, CO ₂ , and O ₃ .

  Another aspect of the present invention relates to an apparatus for forming a semiconductor device structure, the apparatus comprising: (a) a process chamber having an inlet for introducing a reactant containing a gas or a volatile metal; A) a wafer support for supporting the wafer while depositing a layer containing metal on the wafer substrate of the process chamber; and (c) a controller including program instructions. The program instructions include: (i) exposing a substrate having an oxide-free copper or copper alloy exposed layer and a dielectric exposed layer to a reactant comprising aluminum, both a dielectric and a first metal; And (ii) instructions to perform a process of chemically modifying at least a portion of the first layer to form a passivation layer including aluminum. May be included.

  The foregoing and other features and advantages of the present invention are described in detail below with reference to the associated drawings.

It is a cross-sectional view of an element structure created during a copper dual damascene manufacturing process. It is a cross-sectional view of an element structure created during a copper dual damascene manufacturing process. It is a cross-sectional view of an element structure created during a copper dual damascene manufacturing process. It is a cross-sectional view of an element structure created during a copper dual damascene manufacturing process. It is a cross-sectional view of an element structure created during a copper dual damascene manufacturing process. FIG. 2 is a cross-sectional view of a partially fabricated device structure, showing a protective cap. FIG. 2 is a cross-sectional view of a partially fabricated device structure, showing a protective cap. FIG. 2 is a cross-sectional view of a partially fabricated device structure, showing a protective cap. FIG. 3 illustrates an example process flow diagram of a cap formation process in some embodiments. FIG. 4 illustrates another example process flow diagram of a cap formation process in some embodiments. 2 is a cross-sectional view of a device structure created during formation of a cap layer in some embodiments. FIG. 2 is a cross-sectional view of a device structure created during formation of a cap layer in some embodiments. FIG. 2 is a cross-sectional view of a device structure created during formation of a cap layer in some embodiments. FIG. 2 is a cross-sectional view of a device structure created during formation of a cap layer in some embodiments. FIG. 2 is a cross-sectional view of a device structure created during formation of a cap layer in some embodiments. FIG. 1 is a schematic diagram of a PECVD apparatus that can utilize low frequency (LF) and high frequency (HF) radio frequency plasma sources that can be used to form a cap layer in some embodiments of the present invention. FIG. It is the schematic which shows an example of the multi-station apparatus suitable for formation of the cap layer in some embodiment of this invention. FIG. 6 is a schematic diagram illustrating another example of a multi-station apparatus suitable for forming a cap layer in some embodiments of the present invention.

<Introduction and outline>
As device dimensions continue to shrink and the current density experienced by interconnects increases, electromigration has become a significant challenge that threatens reliability in IC manufacturing. Electromigration causes current-carrying metal atoms to migrate and form voids in the interconnect. Formation of voids leads to device failure. Metal atom migration occurs significantly at the metal / diffusion barrier interface and grain boundaries. At the current 90 nm and 45 nm technology node levels, there is a need for methods to improve electromigration performance. Electromigration performance can be improved by introducing dopant elements into the interconnect, but most of these dopants are usually higher in resistance than the interconnect metal (eg, Cu), greatly increasing the interconnect resistance. Therefore, uncontrolled doping of the interconnect may result in an unacceptably high resistance.

  The present application provides a method for controlling dopant implantation. The method includes a process of forming a protective cap in the metal interconnect by implanting the interconnect with a controlled amount of dopant. As a result of this treatment, a very thin protective cap can be formed in the upper part of the metal line, especially at the interface between the metal and the dielectric diffusion barrier (or etch stop) layer. Suitably, the protective cap comprises (but is not essential) a solid solution, alloy or compound with the interconnect metal dopant. For example, copper may be doped with B, Al, Hf, Ti, Co, Ta, Mo, Ru, Sn, or Sb. These dopants can be combined with each other or with other elements. In general, various dopants are available. Particularly suitable are dopants that can form solid solutions, alloys, and compounds with interconnect metals, and dopants that can accumulate at the metal / diffusion barrier interface and at grain boundaries within the interconnect.

  Although the protective caps and cap formation methods described herein have the advantage of improving the electromigration performance of the interconnect, the described devices and processes are not limited to this particular application. For example, the protective cap has a function of improving the adhesion performance between the metal line and the dielectric diffusion barrier or the etching stop layer, and also has a function of preventing the interconnect metal from being oxidized during the manufacture of the IC element. .

  The formation of a protective cap on the interconnect is shown in the context of a copper dual damascene process. The method disclosed herein can be used in other processing methods including a single damascene process, and can be applied to various interconnect metals other than copper. For example, these methods can be applied to interconnects including aluminum, gold, silver, and the like.

  1A to 1D are cross-sectional views of an element structure formed on a semiconductor substrate at each stage of a dual damascene manufacturing process. A cross-sectional view of the complete structure created by the dual damascene process is shown in FIG. 1E. The term “semiconductor substrate” used in the present application is not limited to a semiconductor portion of an IC element, but is broadly defined as a substrate including a semiconductor. FIG. 1A shows an example of a partially fabricated IC structure 100 utilized in dual damascene fabrication. The structure 100 shown in FIGS. 1A-1D is part of a semiconductor substrate, and in some embodiments may be provided directly on a layer that includes active devices (eg, transistors). In other embodiments, a metallized layer containing a conductive material or other layer (eg, a layer containing a memory capacitor) may be provided.

Layer 103 shown in FIG. 1A is an intermetallic dielectric layer, which may be silicon dioxide, but is typically a dielectric material with low k. In order to minimize the dielectric constant of the intermetal dielectric stack, a material having a k value of less than about 3.5 (preferably less than 3.0 and often less than about 2.8) is used between the layers. Used as a dielectric. These materials include, but are not limited to, fluorine or carbon doped silicon dioxide, low k materials including organics, and porous doped silicon dioxide materials known to those skilled in the art. These materials can be deposited, for example, by PECVD or spin-on methods. Layer 103 is etched with a line path (trench or via) in which a partially conductive metal diffusion barrier 105 is deposited to fit a conductive path 107 of copper. Copper or other mobile conductive material provides a conductive path for the semiconductor substrate, so that the silicon elements and dielectric layers adjacent to the metal lines below it are protected from metal ions (eg, Cu ²⁺ ) to form silicon or interlayer dielectrics. It is necessary to prevent the characteristics from deteriorating due to diffusion or floating. Various types of metal diffusion barriers are utilized to protect the dielectric layer of the IC element. These various types can be classified into a layer containing a partially conductive metal such as 105 and a dielectric barrier layer described in detail with reference to FIG. 1B. Suitable materials for the partially conductive diffusion barrier 105 include materials such as tantalum, tantalum nitride, titanium, and titanium nitride. They are typically deposited on the dielectric layer with vias and trenches by PVD or ALD methods.

  The copper conductive route 107 can be formed by a plurality of techniques including PVD, electroplating, electrodeless deposition, CVD, and the like. In some implementations, a suitable method for forming the copper fill is to deposit a thin seed layer of copper by PVD and then deposit the bulk copper fill by electroplating. Usually, copper is excessively deposited in the electric field region, so that it is necessary to perform a chemical mechanical polishing (CMP) process to remove excess and obtain a flat structure 100.

Next, as shown in FIG. 1B, after the structure 100 is completed, the surface of the substrate 100 is previously cleaned to remove contaminants and metal oxides. After this precleaning process, a dopant source layer containing an active component (a component that produces boron or a metal containing dopant) is deposited on both the copper wire 107 and the dielectric 103. Next, the source layer is converted to the passivation layer 109 by, for example, nitriding or oxidizing the source layer. For example, the passivation layer may include BN _x , BO _x , ALO _x , TiO _{x and the} like. The source layer is fully converted to a non-conductive passivation layer over the dielectric region to prevent shorting between adjacent metal lines 107. The portion of the source layer directly provided on the copper wire 107 is only partially converted into a passivation layer so that the portion of the unmodified source layer remains in contact with copper. A protective cap 108 is formed in the upper portion of the metal line 107 after the dopant from the non-passivated portion of the source layer is diffused into and / or contacted with copper. The thickness of the protective cap can be controlled in the source layer by controlling the degree of modification in partially passivating the source layer, and by controlling the conditions utilized during dopant diffusion and / or reaction with copper. It can be controlled by controlling the amount of material deposited. The protective cap may include, for example, a solid solution or alloy of copper and B, Al, Ti, or the like. In some embodiments, the amount of dopant in the alloy or solid solution is controlled by controlling the temperature and time in promoting the diffusion of the dopant from the source layer. The composition of the protective cap and the passivation layer will be described in detail later.

  In some embodiments, the passivation layer also functions as a diffusion barrier layer. In other embodiments, another diffusion barrier (or etch stop) layer is deposited over the passivation layer. Typically, these diffusion barrier layers comprise doped or undoped silicon carbide or silicon nitride.

As shown in FIG. 1B, the film 109 may be a single passivation layer (eg, a BN _x or AlO _x layer) or a passivation layer adjacent to the copper wire 107 and an upper dielectric diffusion barrier provided over the passivation layer. A double layer composed of a layer (doped silicon carbide layer) may be included. These embodiments will be described in detail later with reference to FIGS. 2A-2C. The film 109 is referred to as a Cu / dielectric interface film or simply “interface film”.

  In embodiments where the interfacial film includes a separate dielectric diffusion barrier layer, the dielectric diffusion barrier layer is deposited over the passivation layer, typically by PECVD. In one embodiment, passivation layer deposition, protective cap 108 formation, and dielectric diffusion barrier layer deposition are performed by a single PECVD apparatus without releasing the vacuum. The interface film 109 can be used as an etching stop in a subsequent damascene process.

  Returning to the reference of FIG. 1B, a first dielectric layer 111 of a dual damascene dielectric structure is deposited on the film 109. As an option, an etching stop film 113 may be deposited on the first dielectric layer 111 by PECVD after this. The dielectric layer 111 is usually formed of a dielectric material having a low k as described above as the material of the dielectric layer 103. Layers 111 and 103 do not necessarily have the same composition.

  Next, as shown in FIG. 1C, a process of depositing a second dielectric layer 115 having a dual damascene dielectric structure on the etching stop film 113 by the same method as that for the first dielectric layer 111 is performed. Next, a process of depositing a reflection protective layer (not shown) and a CMP stop film 117 is performed. Second dielectric layer 115 typically includes a low-k dielectric material as described above for layers 103 and 111. The CMP stop film 117 serves to protect the delicate dielectric material of the intermetal dielectric (IMD) layer 115 in the subsequent CMP process. Typically, the CMP stop layer is integrated with similar integration requirements as the diffusion barrier and etch stop films 109 and 113 and can include materials based on silicon carbide or silicon nitride.

  Next, in the dual damascene process, a process of etching the via 119 and the trench 121 in the first and second dielectric layers as shown in FIGS. 1D to 1E is performed. A pattern as shown in FIG. 1D is formed by etching using a standard lithography technique. The method of first forming a trench or the method of first forming a via, known to those skilled in the art, may be utilized.

  These newly formed vias and trenches are then coated with a metal diffusion barrier 123 as described above, as shown in FIG. 1E. The metal diffusion barrier 123 can include tantalum, tantalum nitride, titanium nitride, and other barrier materials that effectively shield the diffusion of copper atoms into the dielectric layer.

  After the diffusion barrier 123 is deposited, a copper seed layer is provided (usually by a PVD process) and the feature is subsequently copper filled with electrofill. The copper layer is deposited by, for example, electrofilling, and excess metal deposited in the electric field is removed by a CMP process in which CMP is stopped at the CMP stop film 117. FIG. 1E illustrates the completion of the dual damascene process with copper conductive routes 124 and 125 embedded in the via and trench surfaces on the barrier 123 (seed layer not shown). FIG. 1E shows three interconnects made with controlled copper wire doping.

  If further processing is required, an interfacial film similar to film 109 and a protective cap similar to cap 108 are formed on the structure shown in FIG. 1E to deposit a new metallization layer.

  The structure and composition of the protective cap 108 and the interface layer 109 will be described in detail below with reference to FIGS. 2A-2C.

<Element structure>
FIG. 2A shows an example of a cross-sectional view of a partial IC structure. In this device, the vias and trenches formed in the interlayer dielectric 201 are aligned with the diffusion barrier material 203 and filled with copper or copper alloy 205. A thin protective cap 207 provided at the interface between the copper wire 205 and the passivation layer 209 is included above the copper wire 205. The passivation layer 209 is provided on both the ILD layer 201 and the protective cap 207, and is in contact with both layers. A dielectric diffusion barrier or etching stop layer 211 is provided on the passivation layer 211. Although not shown in the drawing for the sake of clarity, a further ILD layer is also provided over the dielectric diffusion barrier or etch stop layer 211. The passivation layer 209 and the diffusion barrier (or etch stop) layer 211 cooperate to form an interface film located at the metal / ILD interface (similar to the layer 109 described with reference to FIG. 1B).

  In one embodiment, interlayer dielectric layer 201 has a thickness between about 1,000 and 10,000 angstroms. Layer 201 can comprise various ILD materials, such as dielectrics with low k and very low k, known to those skilled in the art. For example, carbon-doped silicon oxide or an organic dielectric material with k less than about 2.8 can be utilized. The copper wire 205 may have a thickness between about 500 and 10,000 angstroms, of which preferably no more than about 10% (more preferably no more than about 2%) of the layer thickness has a protective cap. Occupy. In many embodiments, the protective cap has a graded composition and has a maximum dopant concentration at the passivation layer interface. The allowable thickness of the protective cap is determined according to the resistance of the dopant. In general, the protective cap will have a via resistance shift of less than about 10% (preferably less than about 5%, more preferably less than about 3%) according to the described method. It is formed. Resistance shift is measured as the difference between the resistance of an interconnect without a cap and the resistance of an interconnect with a cap. In some embodiments, an acceptable resistance shift is achieved by forming a protective cap having a thickness not exceeding 500 angstroms (preferably not exceeding 100 angstroms).

  When different dopants are used, the diffusion state in the copper interconnect is also different and the degree of influence on the interconnect resistance is also changed. Accordingly, it should be understood that the above-described numerical values are only examples and are not intended to limit the structure to the above-described thickness parameters. For example, some dopants do not diffuse into the copper interconnect and deposit across the copper wire to form a distinguishable cap, accumulate at grain boundaries, and / or other interfaces (eg, diffusion barriers). Or accumulated on the interface of the copper layer 205 having 203. In the provided method, it is preferable that the interconnect resistance can be controlled by controlling the implantation amount of these dopants, even if the layer thickness is not precisely defined.

  A plurality of doping elements can be used for the protective cap. Among them, a dopant that forms a solid solution, an alloy, or a compound with copper, and a dopant that can accumulate at the grain boundary of copper and the interface between copper and another layer are preferable. In many cases, low resistivity materials such as metals are preferred. Furthermore, materials that do not readily diffuse into copper at low temperatures (eg, preferably at temperatures below about 100 degrees Celsius) are preferred. Examples of suitable dopants include, but are not limited to, B, Al, Hf, Ti, Co, Ta, Mo, Ru, Sn, and Sb. In general, it is preferred that the selected dopant has a volatile precursor for performing CVD deposition. Accordingly, metal dopants having volatile hydrides, carbonyls, halides, and organometallic precursors are usually preferred. Compounds that can be injected in the gas phase at temperatures up to 450 degrees Celsius and pressures greater than about 1 Torr may be suitable precursors.

In certain embodiments, the protective cap 207 includes copper and boron, or copper and aluminum, or copper and titanium. Some embodiments utilize a combination of dopants. For example, the protective cap 207 may include copper, aluminum, and titanium, or other combinations of copper and dopants. In some embodiments, the dopants described above are utilized in combination with materials utilized to form protective self-aligned buffer (PSAB) layers (eg, materials such as CuSi _x , CuGe _x , SiN _x , and SiC _x ). To do. These layers are described in commonly assigned US patent application Ser. No. 11 / 726,363 entitled “Protective Self-aligned Buffer Layers for Damascene Interconnects” (filing date: 2007). March 20, inventor Yu et al.), US patent application Ser. No. 11 / 709,293 entitled “Protective Self-aligned Buffer Layers for Damascene Interconnects” : February 20, 2007, inventor Chattopadhyay et al.), US patent application entitled “Protection of Cu Damascene Interconnects by Formation of a Self-aligned Buffer Layer” No. 10 / 980,076 (Filing date: November 3, 2004, Inventor Schrave It is described in detail in such) Dijk, incorporated in their entirety from all purposes herein.

The passivation layer 209 provided both on the ILD layer 201 and on the protective cap 207, in one embodiment, has a thickness of about 50 to 500 angstroms. The passivation layer typically includes a non-conductive material that prevents a short circuit between adjacent interconnects. The passivation layer typically includes a modified dopant (eg, may include nitrides, oxides, carbides, sulfides, selenides, phosphides, and arsenides of dopants that are boron or metal). Further, the passivation layer may include hydrocarbon C _x H _y . In one embodiment, the passivation layer includes BN _x . The BN _x layer may further include hydrogen, and in some embodiments may include other elements. In another example, the passivation layer comprises a metal oxide such as AlO _x , HfO _x , TiO _x , CoO _x , TaO _x , MoO _x , RuO _x , SnO _x , and SbO _x .

  As shown in FIG. 2A, a dielectric diffusion barrier or etch stop layer 211 is provided on the passivation layer. Layer 211, in one embodiment, has a thickness between about 50 and 500 angstroms. Conventionally, silicon nitride and nitrogen doped silicon carbide (NDC) have been utilized for this application. Currently, a material having a dielectric constant lower than that of silicon nitride is often used as a dielectric diffusion barrier. These materials include carbon-rich silicon carbide materials described in US patent application Ser. No. 10 / 869,474 (filed on Jun. 15, 2004, inventor Yu et al.) And the like by the same applicant, Patent Application No. 10 / 915,117 (Application Date: August 9, 2004, Inventor Yu et al.) And US Patent Application No. 11 / 373,847 (Application Date: March 8, 2006) Boron-doped silicon carbide materials described in Inventor Yu et al.), And US Pat. No. 6,855,645 (issue date: February 15, 2005, inventor Tang et al.), Etc. The oxygen-doped silicon carbide material described in 1). All patent applications referred to in this paragraph are incorporated herein for all purposes. In some embodiments, layer 211 includes several sublayers (eg, sublayers comprising doped and / or undoped silicon carbide of different compositions adjusted to improve diffusion barrier and etch stop properties). ). For example, the barrier may include an undoped carbide sublayer, a nitrogen doped carbide sublayer, and an oxygen doped carbide sublayer. The barrier may include two sublayers, three sublayers, and a greater number of sublayers. Regarding the combination of the barrier layers, US Patent Application No. 10 / 869,474 filed on June 15, 2004 (currently, Patent No. 7,282,438 (issue date: October 16, 2007)) (Patented), an example of which is provided herein in its entirety. In general, the dielectric diffusion barrier layer may include doped or undoped silicon carbide, silicon nitride, or silicon carbonitride.

  In the embodiment shown in FIG. 2A, layers 209 and 211 cooperate to form an interface layer provided between two ILD layers (the upper ILD layer is not shown).

  In some embodiments, the passivation layer 209 can function as a diffusion barrier or etch stop layer without the need for a separate silicon carbide or silicon nitride layer 211. In this embodiment, as shown in FIG. 2B, the interface layer provided between the two ILD layers is composed only of the passivation layer 209. For example, certain metal oxides and metal nitrides can function as etch stops or diffusion barrier layers.

FIG. 2C shows an embodiment in which a dopant layer or dopant-generating compound 208 is provided between the protective cap 207 and the passivation layer 209 and is in contact with these two layers. Layer 208 is aligned on copper wire 205 and is not provided on dielectric layer 201. Layer 208 may include pure dopants or dopant generating compounds. For example, the layer 208 can include BH _x , Al, Ti, Ta, Hf, Ru, and the like. The metal in this layer may be free or may be combined with other elements (H, C, N, etc.). In some embodiments, copper may be diffused over layer 208 to form an alloy, mixture, or solid solution with the dopant in layer 208. In these embodiments, a 207/208 bilayer can also be utilized as a protective cap. In general, the protective cap described herein may be completely contained in the copper wire at the same level as the surrounding dielectric 201, or may include a portion above the level of the surrounding dielectric 201.

The device in one particular example has a structure as shown in FIG. 2A that includes a boron-doped protective cap 207 and a passivation layer 209 that includes BN _x . Copper wire 205 is provided in a layer of ULK dielectric (about 2.5 k) having a thickness of about 3,500 angstroms. The protective cap 207 includes copper and boron and has a thickness of about 100 angstroms. The protective cap may be provided on the upper part of the copper wire and the interface with the passivation layer. The passivation layer has a thickness of about 150 Å and includes BN _x . The passivation layer may further contain hydrogen, in which case it is referred to as a (BNH) _x layer in the experimental section. Diffusion barrier layer 211 can include nitrogen-doped silicon carbide, oxygen-doped silicon carbide, or undoped silicon carbide. Layer 211 has a thickness of 100 angstroms to 500 angstroms.

The device in another specific example has a structure as shown in FIG. 2A including a protective cap 207 made of titanium and a passivation layer 209 containing TiN _x . Copper wire 205 is provided in a layer of ULK dielectric (about 2.5 k) having a thickness of about 3,500 angstroms. The protective cap 207 includes copper and titanium and has a thickness of about 100 angstroms. The protective cap is provided at the upper part of the copper wire and the interface with the passivation. The passivation layer has a thickness of about 150 Å and includes TiN _x . The passivation layer may further contain hydrogen. Diffusion barrier layer 211 can include nitrogen-doped silicon carbide, oxygen-doped silicon carbide, or undoped silicon carbide. Layer 211 has a thickness of 100 angstroms to 500 angstroms.

The device in another specific example has a structure as shown in FIG. 2A including a protective cap 207 doped with aluminum. Copper wire 205 is provided in a layer of ULK dielectric (about 2.5 k) having a thickness of about 3,500 angstroms. The protective cap 207 includes copper and aluminum and has a thickness of about 100 angstroms. The protective cap is provided at the upper part of the copper wire and the interface with the passivation. The thickness of the passivation layer is less than about 100 angstroms and consists essentially of AlO _x . A diffusion barrier layer 211 having a thickness of about 100 angstroms to 500 angstroms is provided in contact with the AlO _x and can include silicon carbide doped with nitrogen, silicon carbide doped with oxygen, or undoped silicon carbide.

<Method for forming protective cap layer>
An example of a method for forming the protective cap layer is shown in the process flow diagram of FIG. 3A. 4A to 4E show cross-sectional views of the device structure resulting from this process. The method shown here can be implemented in many types of apparatus, and in some embodiments, a PECVD (plasma chemical vapor deposition) apparatus is preferred. In some embodiments, the PECVD apparatus can provide high frequency (HF) and low frequency (LF) plasma generation sources.

Referring to FIG. 3A, the process begins by providing a partially fabricated semiconductor device having a copper wire pattern in a dielectric (see operation 301). An element as shown in FIG. 4A can be used. In this element, a copper or copper alloy layer 405 is embedded in a dielectric layer 401. A thin layer of diffusion barrier material (including, for example, Ta, TaN _x , TiN _x , Ru, W) is provided at the interface between copper and the dielectric. The copper layer and the dielectric layer are exposed on the substrate surface.

The substrate may optionally be pre-cleaned in process 303 to remove contaminants from its surface. For example, the substrate is exposed to a reducing gas in the plasma (eg, a gas selected from the group consisting of H ₂ , N ₂ , NH ₃ , and mixtures thereof in the plasma discharge) to perform this pre-cleaning process. And the copper oxide is removed from the copper surface. In some embodiments, pre-cleaning with H ₂ plasma resulted in devices with particularly improved characteristics. The process gas in the pre-cleaning process may further include a carrier gas (N ₂ , He, Ar, etc.). In one example, the pre-clean is performed in a PECVD chamber of H ₂ at a temperature of about 200 degrees Celsius to 400 degrees Celsius, a pressure of about 1.5 to 4 Torr, and a flow rate of about 4,000 to 10,000 sccm. A plasma that may contain HF and LF components is ignited to maintain a total power of 200 to 1000 W per 300 mm wafer. In some embodiments, it is desirable before HF power 1.5 W / cm ² and LF power from 0.1 during the cleaning process is 0.8 W / cm ² from 0. In another example, NH ₃ as a reducing gas is flowed into the process chamber at a flow rate in the range of about 6,000 to 8,000 sccm instead of H ₂ . N ₂ carrier gas is flowed into the chamber at a flow rate of about 2,000 to 4,000 sccm. The pre-cleaning process is performed for several seconds (for example, about 6 to 20 seconds).

  In some embodiments, it may be preferable to perform the precleaning process in a milder manner rather than direct exposure to plasma. This milder method is particularly suitable when the copper wire is embedded in a delicate ULK dielectric that is easily damaged by direct exposure to plasma.

In some _{embodiments, H 2, N 2, NH} 3, and completely or partially removing copper oxide by utilizing a remote plasma comprises a gas selected from the group consisting of mixtures. In this implementation, one or more of these gases (eg, a mixture of H ₂ and N ₂ or a mixture of NH ₃ and N ₂ ) is used to physically separate from the chamber holding the wafer substrate. A plasma is formed in the chamber. The plasma thus formed is sent to the ion filter via the delivery line, where the ion plasma is depleted and radicals remain. The resulting radical rich process gas is sent from the inlet (eg, showerhead) to the chamber housing of the substrate. A radical rich process gas (in some embodiments, containing little or substantially no ionic species) contacts the surface of the substrate to remove copper oxide partially or completely as desired. To do. It is suggested that high-energy ions directly contained in the plasma damage the dielectric, so pre-cleaning is mild and effective by using a remote plasma with few ions. A suitable example for a remote plasma system is the product of the Gamma® line from Novellus Systems, Inc. of San Jose, California.

In another embodiment, copper oxidation is performed by performing ultraviolet (UV) irradiation treatment using a reducing gas (for example, a gas selected from the group consisting of H ₂ , N ₂ , NH ₃ , and a mixture thereof). Remove the object completely or partially. In this mounting example, the substrate is exposed to one or more of these gases (for example, a mixture of H ₂ and N ₂ or a mixture of NH ₃ and N ₂ ), and the substrate is irradiated with UV light. For example, US Provisional Patent Application No. 61 / 260,789 entitled “UV and Reducing Treatment for K Recovery and Surface Clean in Semiconductor Processing” by the same applicant. The apparatus and process conditions exemplified by those described in the specification (application date: November 12, 2009, inventor B. Varadarajan et al.) Can be used, the entire implementation of which is described herein Incorporated herein for purposes of detailing UV processing apparatus and methods suitable for use in the form. By utilizing the described UV treatment, it becomes possible to remove copper oxide in a controlled manner, and the thickness of the removed oxide depends on the duration of UV exposure, process gas composition, substrate temperature, and other conditions. Will be able to control.

In some embodiments, the pre-cleaning process is performed by heat treatment in an environment that does not use plasma. For example, the wafer may be heated in an environment containing at least about at a temperature of 200 degrees Celsius for about 15 to 60 _{seconds, H 2, N 2, NH} 3, and mixtures thereof. By utilizing this heat treatment, the copper oxide can be partially removed, and this method is particularly suitable for processing a substrate containing a delicate ULK dielectric.

  After the pre-clean process is completed, a source layer of a material containing dopant is deposited on the surface of the substrate (process 305). The material containing the dopant may not be selectively deposited on the surface of the metal, or may be deposited both on the surface of the dielectric and on the metal. The source layer is a reactant containing a dopant (eg, a reaction containing boron) under conditions such that a partially fabricated device deposits a source layer containing the dopant (eg, containing boron, or containing a metal). Or a reactant containing a metal).

  In one embodiment, the source layer containing the dopant is thermally deposited without using a plasma discharge. For example, volatile precursors such as volatile hydrides, halides, carbonyls, or organometallic compounds can be reacted (eg, decomposed) at high temperatures to deposit a material layer containing a dopant on the surface of the substrate. One skilled in the art will appreciate that temperature ranges, substrate exposure times, and other deposition conditions can be adjusted depending on the particular precursor.

In one embodiment, B ₂ H ₆ is used as a precursor to form a B-doped protective cap. In one example process, B ₂ H ₆ is introduced into the process chamber along with one or more carrier gas additives (N ₂ , O ₂ , CO ₂ , He, NH ₃ , Ar, etc.). In this example, the concentration of B ₂ H ₆ is between about 0.5 and about 20% and the pressure is between about 0.5 Torr and about 10 Torr. Without utilizing a plasma discharge, B ₂ H ₆ is exposed to the substrate at a chamber temperature between about 200 degrees Celsius and 400 degrees Celsius to deposit a layer containing boron on the substrate. Since this layer is known to contain B—H bonds, it is referred to as a BH _x layer. The BH _x layer functions as a source of B dopant and diffuses into the copper wire to form a protective cap.

  In another example, a precursor containing a volatile metal is introduced into the chamber. Examples of suitable precursors include organometallic compounds, metal hydrides, metal halides, and metal carbonyls. For example, alkyl-substituted metal derivatives and cyclopentadienyl-substituted metal derivatives can be used. The precursor is reacted at a high temperature to form a source layer containing a metal on the substrate. In some embodiments, pressure and temperature ranges similar to those utilized for depositing caps containing B can be utilized. In general, the deposition conditions can be optimized depending on the nature of the precursor to deposit the best quality metal-containing source layer. For example, the temperature range can be optimized to suit the specific decomposition mechanism of the precursor, and the composition of the source layer containing the metal can be adjusted accordingly. A person skilled in the art has conceived a method for optimizing the decomposition conditions and a method for obtaining a source layer containing a metal under the optimized decomposition conditions.

  As already suggested, various metals can be used as the dopant. For example, the copper wire can be doped with Al, Hf, Ti, Co, Ta, Mo, Ru, Sn, Sb. Other metals known for volatile precursors can also be utilized. Examples of suitable precursors for deposition of source layers containing aluminum include trimethylaluminum, dimethylaluminum hydride, triethylaluminum, triisobutylaluminum, and tris (diethylamino) aluminum. Including, but not limited to. Examples of precursors available for source layer deposition include bis (cyclopentadienyl) cobalt, cobalt (II) acetylacetonate, tetrakis (diethylamide) Hafnium (tetrakis (dimethylethyl) hafnium), tetrakis (dimethylamido) hafnium, tetrakis (dimethylamido) molybdenum, tetrakis (dimethylamino) titanium (TDMAT (tetrakis (dimethylamino)) titanium (TDMAT)), tetrakis (diethylamino) titanium (TDEAT), tetrakis (ethylmethylamido) titanium, bis (diethylamino) bis (diisopropylamino) titanium (Bis (diethylamino) bis (diisopropylamino) titani um), pentakis (dimethylamino) tantalum, tertiary (butylimidotris) (diethylamido) tantalum (TBTDET) tert (butylimidotris) (diethylamido) tantalum (TBTDET)), pentakis (diethylamido) tantalum (pentakis) (diethylamido) tantalum), bis (ethylcyclopentadienyl) ruthenium, tris (dimethylamido) antimony, and tetramethyltin, These are not limited.

  The source layer does not necessarily need to contain a pure element dopant, and may contain a compound of another element (for example, H, C, N, etc.) and a dopant. However, dopants are easily generated from these layers and, once generated, are likely to diffuse into and / or react with copper. In other embodiments, the source layer can include substantially pure metal or boron.

The source layer need not be selectively deposited only on the copper wire, but may be deposited both on the dielectric layer and on the copper. However, in many embodiments, some choice is made between copper and dielectric, and a thicker source layer is provided on the copper wire and provided on the copper wire 408 as shown in FIG. 4B. The thickness of the source layer 408 (which may be a BH _x layer or a metal-containing layer) is larger than that of the layer provided on the dielectric layer 401. Depending on the specific precursor and deposition conditions, for example, the source layer is deposited on both copper and dielectric in an even thickness, from the example of full selectivity where the source layer is deposited only on the copper wire Various processes can be selected up to a process example that does not exhibit selectivity. Although the methods described herein can be used to introduce dopants in a controlled manner both in the case of selectivity and in the case of non-selectivity, the illustrated method is partially as an example. Illustrated with layers deposited using the example of selection. This partial selection results in a source layer deposited on the copper wire that is thicker than the source layer deposited on the dielectric, which includes a source layer containing boron and a source containing many metals. The same is observed for both layers. In some embodiments, the thickness of the source layer on the copper is about 10 to 500% greater than the thickness of the source layer on the dielectric.

  Referring again to the process flow diagram shown in FIG. 3A, in process 307 after the source layer is formed in process 305, the upper portion of the source layer provided on the copper is modified to form a passivation layer and unmodified. A portion of the source layer remains in contact with the copper layer. This is shown in the structure of FIG. 4C, where a small portion of the source layer 408 remains unmodified and continues to contact the copper wire 405, and the top of the source layer above the copper is transformed to passivate. It can be seen that the layer 409 is formed. The portion of the source layer on the dielectric has been completely converted into a passivation material. The passivation process 309 has two purposes. First, partial passivation of the source layer limits the amount of dopant available, thus helping to control interconnect resistance. The passivation layer preferably includes a material that does not readily diffuse from the passivation material into the copper wire. For example, boron is converted to boron nitride and aluminum is converted to aluminum oxide. Free boron and aluminum can diffuse into the copper wire, but these materials are trapped in the passivation layer when converted to nitrides and oxides, so they do not enter the copper wire and increase its resistance . Since the top of the source layer is modified into a passivation layer, the amount of dopant introduced into the copper line is determined by the thickness of the unmodified part of the source layer that remains in contact with the copper line. Depending on the amount of dopant that needs to be introduced into the copper wire, the amount of source layer converted to a passivation layer can be determined. For example, the thickness of the source layer deposited first may be about 50 to 500 Angstroms, of which about 20 to 60% may be converted to a passivation layer.

Passivation is also necessary in embodiments where the source layer includes a conductive material deposited on both copper and dielectric. In these embodiments, passivation converts a conductive material (eg, metal) to a material that is less conductive or not conductive at all to prevent shorting between adjacent copper wires. For example, a partially conductive BH _x source layer overlying a dielectric can be completely converted to a passivation layer comprising BN _x that is substantially non-conductive. Similarly, a source layer containing aluminum can be converted into an aluminum oxide having no conductivity.

  A plurality of compounds (eg, nitrides, oxides, sulfides, selenides, tellurides, phosphides, and carbides) are suitable as materials for the passivation layer. Of course, nitrides and oxides are suitable in many embodiments.

The passivation layer can be formed by exposing the source layer containing the dopant to a reagent suitable for modifying the source layer material into a passivation material. In some embodiments, this modification can be done thermally without the use of plasma, but in many cases, modification of the source layer by plasma discharge is preferred. For example, nitriding can be performed by exposing the substrate to a reactant containing nitrogen (eg, N ₂ , NH ₃ , N ₂ H ₄ , amine, etc.) in the plasma. Oxides can also be formed in the same manner by exposure to reactants containing oxygen (O ₂ , CO ₂ , N ₂ O, etc.) in plasma. Sulfides, selenides, tellurides, phosphides, and carbides similarly expose the substrate to the required elements (eg, each H ₂ S, H ₂ Se, H ₂ Te, PH ₃ , C _x H _y ). Can be formed similarly.

In some embodiments, the post treatment includes direct plasma treatment. For example, a substrate having an exposed source layer can be treated with a plasma formed in a process gas selected from the group consisting of H ₂ , N ₂ , NH ₃ , and mixtures thereof. In some embodiments, a substrate having a source layer is treated with H ₂ in a plasma. By the hydrogen plasma treatment, an organic group remaining in the precursor layer can be removed, and a terminal metal-H bond can be formed. In other examples, the substrate is post-treated with a mixture of H ₂ and N ₂ in plasma, or post-treated with NH ₃ in plasma to remove organic groups and form metal-N bonds. To do. In some embodiments, other nitridizing agents such as N ₂ H ₄ and amines may be utilized.

As with pretreatment, it may be desirable to use a milder treatment method than direct plasma treatment. For example, in some embodiments, the substrate can be processed utilizing a remote plasma formed in a gas selected from the group consisting of H ₂ , N ₂ , NH ₃ , and mixtures thereof. As described above, a remote plasma is generated in a chamber that is physically different from the chamber containing the substrate to deplete the ionic species before being sent to the substrate, thereby reducing the possibility of damage to the dielectric. be able to. This is because radicals contained in remote plasma are usually less likely to cause damage than high energy ions. Even with remote plasma, the formation of metal-H and metal-N bonds occurs with the removal of organic groups from the layer.

Further, the mild post-treatment consists of H ₂ , N ₂ , NH ₃ , and mixtures thereof by the method described in US Provisional Patent Application No. 61 / 260,789, previously incorporated by reference. It can also be performed by performing UV irradiation in a process gas selected from the group. This UV treatment can also be used for applications such as forming metal-H bonds and metal-N bonds, and removing organic substituents from the precursor layer.

In some embodiments, the post-treatment is performed by heat treatment in an environment that does not use plasma. For example, the wafer to a temperature between 350 degrees from at least about 3000C _°, can be heated in an environment containing _{H 2, N 2, NH 3} , and mixtures thereof. This heat treatment method is particularly suitable for processing a substrate containing a delicate ULK dielectric.

In some embodiments, the post-treatment can be performed by treating the source layer with the reactants at room temperature, or by treating at a high temperature in an environment that does not use plasma. For example, in some embodiments, treating a substrate with a reactant comprising oxygen (eg, O ₂ , H ₂ O, N ₂ O) in a plasma-free environment (eg, containing Al or containing Ti). A passivation layer containing metal-oxygen bonds can be formed (in the layer etc.).

  Remote plasma aftertreatment, thermal aftertreatment, and UV aftertreatment are particularly suitable when ULK dielectrics (especially porous and organic dielectrics that are easily damaged) are utilized in the ILD layer.

  Although nitridation post-treatment methods are preferred in many embodiments, other types of post-treatment methods may be utilized in some embodiments.

For example, a substrate having a precursor layer exposed to a gas containing oxygen (for example, O ₂ , H ₂ O, N ₂ O, or the like) using a post-oxidation treatment method with or without using plasma. By exposing, a metal-O bond can also be formed. In other embodiments, metal-C bonds can be formed in a post-processing step, for example, by treating the source layer with a hydrocarbon in a plasma. Also, by exposing the substrate to reactants each containing necessary elements such as H ₂ S, H ₂ Se, H ₂ Te, and PH _{3 with} or without plasma in post-processing steps, -S, metal-Se, metal-Te, and metal-P bonds can also be formed. Both the direct plasma method and the remote plasma method can be used as these post-treatment methods.

Referring to FIG. 4C, it can be seen that a passivation layer 409 (including BN _x , AlO _x , TiO _x, etc.) is provided on the dielectric layer 401 and on the copper layer 405. A thin layer 408 containing an unmodified dopant source is provided between the copper wire and the layer of passivation material.

  After formation of the passivation layer, the active component (dopant) from the unmodified source layer is diffused into and / or reacted with copper to form a protective cap within the copper layer (treatment 309). ). This is indicated by the arrows in the structure shown in FIG. 4C. The resulting structure is shown in FIG. 4D and it can be seen that a protective cap 407 is formed in the upper portion of the copper wire. In this example, the entire dopant has moved from the source layer 408 to the copper wire. In other embodiments, some of the dopant may remain in the source layer. In other embodiments, the dopant may diffuse into the copper layer at the same time as the copper diffuses into the unmodified source layer. In the latter two cases, a protective cap may be present in or on the initially presented copper wire (see FIG. 2C).

  The formation of the protective cap can be performed under a variety of conditions depending on the particular dopant source in the unmodified source layer. In some embodiments, the material comprising the dopant in the source layer can easily diffuse into the copper or not react with the copper. In these embodiments, the dopant is first generated, for example, by exposing the substrate to a high temperature. In other embodiments, dopant diffusion and / or reaction is further facilitated by heating the substrate. In some embodiments, the thickness of the protective cap may be controllable by controlling the time and temperature at which the substrate is exposed to high temperatures. In some embodiments, the formation of the protective cap is facilitated by heating the substrate at a temperature of at least about 100 degrees Celsius for a predetermined time (eg, about 0.25 to 60 minutes).

In forming the protective cap, doped or undoped silicon carbide is deposited (process 311). The resulting structure is shown in FIG. 4E. It can be seen that a layer of silicon carbide 411 is deposited over the copper wire layer and over the passivation layer 409 over the dielectric region. The layer of silicon carbide functions as an etch stop or dielectric diffusion barrier layer and is typically deposited with a thickness of about 100 to 500 Angstroms. The layer of silicon carbide can be deposited by CVD (preferably PECVD), for example by exposing the substrate to a precursor comprising silicon and a precursor comprising carbon during plasma discharge. For example, silanes, alkyl silanes, and hydrocarbons can be utilized as precursors. When depositing doped silicon carbide, a precursor containing a dopant is added into the process chamber. For example, CO ₂ , O ₂ , or N ₂ O can be added in the deposition of silicon carbide containing oxygen, and B ₂ H ₆ can be added to deposit boron-doped silicon carbide. NH ₃ and N ₂ can be added to deposit nitrogen-doped silicon carbide. In other embodiments, doped or undoped silicon nitride is deposited over the passivation layer to function as an etch stop or diffusion barrier layer. In some embodiments, the deposition of the dielectric diffusion barrier layer is performed at a temperature higher than that utilized for the formation of the cap layer (including the formation of the source layer and passivation). For example, in some embodiments, the formation of the protective cap occurs at a temperature below 350 degrees Celsius (eg, about 200 to 350 degrees Celsius) and the deposition of the diffusion barrier is at least about 350 degrees Celsius (eg, 375 to 450 degrees Celsius). Temperature).

  In some cases, the deposition of the dielectric diffusion barrier or etch stop layer may be optional since the passivation layer itself may have properties suitable to function as a diffusion barrier or etch stop. For example, a passivation layer containing a certain type of metal oxide can function as a diffusion barrier layer, so that it is not necessary to deposit a separate silicon carbide layer.

  In the process shown in FIGS. 3A-3B, operation 313 is next performed, where an interlayer dielectric (eg, silicon dioxide, organosilicon glass, porous organic dielectric, etc.) is deposited. The dielectric is deposited on either the diffusion barrier or the etch stop layer (eg, on the silicon carbide layer) or the passivation layer if the passivation layer has suitable properties to function as a diffusion barrier. Directly deposited on top. The dielectric can be deposited by PECVD or spin-on methods and is typically deposited to a thickness of about 3,000 to 10,000 angstroms. Then, a damascene process is further performed as shown in FIGS. 1C to 1E.

  It should be understood that the process of the flow diagram shown in FIGS. 3A-3B is for illustration purposes and that various variations of this process are possible. For example, the various processes of the processes shown in FIGS. 3A-3B can be performed in different orders. In particular, the introduction of the active component (dopant) into the copper layer can take place at different points in the process. In some embodiments, dopant generation and diffusion can also begin after an etch stop or diffusion barrier layer deposition. In some embodiments, post-treatment after formation of the ILD layer facilitates dopant diffusion. In many cases, this process is performed by heating the substrate to a temperature of at least about 100 degrees Celsius. In yet another embodiment, the active component (dopant) can be diffused into and / or reacted with copper prior to passivation of the source layer. In this embodiment, the amount of dopant introduced can be controlled by controlling the time that the unmodified source layer is contacted with copper and / or by controlling the temperature of the process.

  In some embodiments, the process shown in FIG. 3A can be fully passivated, rather than partially, over the source layer on the copper wire to substantially prevent the dopant element from diffusing into the copper wire. To correct. This modification may be preferred in some cases because an increase in interconnect resistance due to dopant diffusion is minimized while an improvement in electromigration performance is still achieved.

  Another embodiment of the process is shown in the process flow diagram of FIG. 3B. In this process, a source layer containing aluminum is deposited at a high temperature on a copper surface that does not contain oxygen. The process begins at operation 301 by providing a partially fabricated semiconductor device that includes a copper wire pattern in a dielectric. For example, a substrate such as the substrate shown in FIG. 4A can be used. In some embodiments, a copper wire is embedded in a ULK dielectric layer (eg, a porous and organic dielectric having a dielectric constant of 2.8 or less). In the embodiment shown in FIG. 3B, it is very important to provide a copper surface that does not contain oxygen so that no reaction occurs between the copper oxide and the organoaluminum precursor. A thin layer of copper oxide alters the mechanism of aluminum deposition to form aluminum oxide. In the embodiment shown in FIG. 3B, it is not preferable that the aluminum oxide is formed at a position closest to the copper surface.

  The substrate is pre-cleaned at step 303 to remove the copper oxide. This pre-cleaning is controlled to completely remove the copper oxide from the copper surface. This can be done by selecting an appropriate pre-cleaning period and process conditions. As described above with reference to FIG. 3A, the pre-cleaning treatment can be performed by direct plasma treatment, remote plasma treatment, UV treatment, or heat treatment. In the case of using a delicate ULK dielectric, in some embodiments, a pre-treatment that does not directly use plasma is performed.

  After obtaining the oxide-free copper layer, the partially fabricated device is exposed to an organoaluminum reactant at a substrate temperature of at least about 350 degrees Celsius (eg, at least about 400 degrees Celsius) to form aluminum. Is formed (see process 305). It is noteworthy that at lower temperatures, a layer containing the proper proportion of aluminum does not deposit on the copper surface without the oxide. A variety of organoaluminum reactants can be utilized, including trialkylaluminum, particularly preferred in some embodiments is trimethylaluminum. Examples of suitable reactants include, but are not limited to, trimethylaluminum, dimethylaluminum hydride, triethylaluminum, triisobutylaluminum, and tris (diethylamino) aluminum. Not. The reactants are exposed to the substrate in a CVD chamber without using a plasma, and typically a layer comprising aluminum is formed on both the exposed dielectric and copper surfaces. The thickness of the layer can be controlled, for example, by controlling the reactant flow rate and the substrate temperature. The layer deposited on the dielectric usually oxidizes spontaneously during deposition to form a non-conductive layer containing Al-O bonds (since the dielectric contains oxidizing species). . If the layer containing aluminum on the dielectric is not fully oxidized, the layer is modified in a post-processing step to convert all conductive material on the dielectric to a non-conductive form Thus, a short circuit between interconnects is prevented. Regardless of whether the aluminum-containing layer deposited on the dielectric oxidizes spontaneously immediately after deposition or not, at least part of the aluminum-containing layer on the copper is immobilized by performing a post-processing step. It can also be converted to an immobile compound, which in some embodiments may not be conductive.

  In process 307, two post-processing steps are optionally provided. In the first embodiment, only the top of the layer containing aluminum over copper is modified to form a passivation layer, with a portion of the unmodified layer remaining in contact with the copper layer, Aluminum from the part is diffused into the copper (process 309). In another embodiment, the entire layer comprising aluminum over copper is modified to form an immobile compound that substantially prevents diffusion of aluminum into the copper wire. If aluminum diffuses excessively into the copper leads, the interconnect resistance is undesirably increased, and a thin immobile cap (eg, a cap containing Al-O or Al-N bonds) is formed on the copper to form a dielectric. Because of improved adhesion properties, in some embodiments it is preferable to minimize or completely prevent aluminum diffusion.

  As described with reference to FIG. 3A, various post-treatment methods are available including direct plasma treatment, remote plasma treatment, UV treatment, and thermal (no plasma) treatment at high or room temperature.

In one embodiment, a layer containing Al—O bonds is formed on the surface of copper using an oxidation process (room temperature or high temperature) that does not use plasma. For example, a substrate having an aluminum-containing layer (after treatment with an organoaluminum reactant) can be applied to a reactant containing oxygen (O ₂ , O ₃ , N ₂ O, H ₂ O, or CO without using plasma). ₂ ) to form an immobile Al-O containing material.

  In another embodiment, a layer containing Al—N bonds is formed on the surface of copper using a nitridation process (room temperature or high temperature) without using plasma. For example, a substrate having a layer containing aluminum (after treatment with an organoaluminum reactant) can be exposed to a reactant containing oxygen (ammonia or hydrazine) without using a plasma.

  Post-treatment without plasma (including UV and heat treatment) is particularly suitable when the substrate contains a mechanically fragile ULK dielectric because minimal dielectric damage is required.

  After the post-processing, the process ends at operations 311 and 313, a dielectric diffusion barrier layer is deposited, and an interfacial dielectric is deposited (see description regarding FIG. 3A).

  The method described above can provide an interconnect with controllable resistance and improved electromigration characteristics. The thickness of the protective cap layer formed by these methods may range from about 10 to 10,000 angstroms. These methods are particularly preferred when the thickness of the cap layer can be controlled in the range of about 10 to 100 angstroms, particularly preferably in the range of 10 to 60 angstroms. When the thickness of the cap film is in the range of about 10 to 60 angstroms, the resistance shift of the interconnect can be particularly reduced (a level of less than 1% to less than 3%, which is currently required in the IC industry).

<Device>
In general, the formation of the protective cap can be performed in any type of apparatus that can introduce volatile precursors and control reaction conditions (chamber temperature, precursor flow rate, exposure time, etc.). . It is generally preferred that treatments 301 through 311 can be performed without exposing the substrate to the surrounding environment, as this will not inadvertently oxidize and contaminate the substrate. In one embodiment, operations 301 through 311 are performed in substantially one module without releasing the vacuum. In some embodiments, the processes 301-311 are performed in a single CVD (preferably PECVD) apparatus having multiple stations in a single chamber or having multiple chambers. An example of a suitable apparatus is the VECTOR® PECVD apparatus available from Novellus Systems, Inc. of San Jose, California.

  An example of an apparatus includes one or more chambers or “reactors” (often including multiple stations) that contain one or more wares and are suitable for wafer processing. Each chamber may contain one or more wafers to be processed. These one or more chambers are capable of holding the wafer in place (s) (even if movement such as rotation, vibration or other movement is possible at that position, May be good). In one embodiment, the wafer with the deposited source and etch layers is moved between stations in the reactor during the process. During the process, each wafer is supported by a pedestal, wafer chuck, and / or other wafer support device. For the specific process of heating the wafer, the apparatus may include a heater such as a heating plate. A preferred embodiment of the present invention can utilize a PECVD system. In a further preferred embodiment, the PECVD system includes an LF RF power source.

  FIG. 5 is a simplified block diagram illustrating the various reaction components arranged to implement the present invention. As shown, the reactor 500 includes a process chamber 524 that includes other components of the reactor and includes a showerhead 514 that cooperates with a grounded heater block 520. It has the function including the plasma produced | generated by. A high frequency RF generator 502 and a low frequency RF generator 504 are connected to a matching network 506, which is connected to a showerhead 514.

  Within the reactor, wafer pedestal 518 supports substrate 516. The pedestal typically includes a chuck, fork, or lift pin that can hold and move the substrate during or between deposition reactions. The chuck may be an electrostatic chuck, a mechanical chuck, or various other types of chucks available in industry and / or research.

  Process gas is introduced from inlet 512. A plurality of source gas lines 510 are connected to the manifold 508. The gas may or may not be premixed. Appropriate valves and mass flow control mechanisms can be utilized to ensure that the proper gas is provided during precleaning, during the formation of the source layer, during the formation of the passivation layer, and during the doping period in the process. When the chemical precursor (s) are provided in liquid form, a liquid flow rate control mechanism is utilized. The liquid is then vaporized and mixed with other process gases during transport in a manifold heated to a temperature above the vaporization point before reaching the deposition chamber.

  Process gas exits chamber 500 through outlet 522. Typically, the process gas is removed by a vacuum pump 526 (eg, a one or two stage mechanical dry pump and / or a turbomolecular pump) and a closed loop controlled flow restricting element such as a throttle valve or a pendulum valve. To maintain an appropriate low pressure in the reactor.

  In one embodiment, a multi-station device may be utilized to form the cap layer and diffusion barrier. Multi-station reactors allow different processes to be performed simultaneously in one chamber environment, which increases the efficiency of the wafer process. An example of this device is shown in FIG. Here, a schematic top view is shown. The apparatus chamber 601 includes four stations 603 to 609 and two load locks (inlet load lock 619 and outlet load lock 617). In other embodiments, a single load lock is combined at the wafer entrance and exit. Any number of stations may be included within a single chamber of a multi-station device. The station 603 is used when a substrate wafer is loaded or unloaded. Stations 603 to 609 may have the same or different functions. For example, some of the stations may be provided specifically for the formation of the cap layer, and other stations may be provided for the deposition of the dielectric diffusion barrier film. In addition, a plurality of stations may be provided specifically for copper oxide reduction.

  In one embodiment, individual stations may operate with individual process conditions or may be substantially isolated from one another. For example, one station may operate in one temperature range and another station may operate in a different temperature range.

  In one embodiment, the precleaning process, source layer deposition, and passivation layer formation are performed at one suitable temperature range and at one station of the multi-station apparatus. Dielectric diffusion barrier deposition may require different temperature ranges in some embodiments and may need to be performed at different station (s). In some embodiments, the entire cap process, including pretreatment, source layer formation, passivation, and formation of caps containing dopants, is performed at one of the single station or multi-station devices. In some embodiments, the dielectric diffusion barrier layer may be deposited at the same station as the capping process. In some cases, the entire load lock 619 can be used for wafer pre-cleaning or pre-processing. This may include, for example, oxide removal by chemical reduction.

  In one example, the station 603 can be utilized specifically for pre-cleaning and cap layer formation (from precursor layer to passivation layer). Station 603 is operable in a temperature range of about 200 to 400 degrees Celsius, which is preferred in both embodiments for both the cap and preclean process. Deposition of a dielectric diffusion barrier material (eg, silicon carbide) can be performed at a temperature range of about 350 to 400 degrees Celsius at stations 605, 607, and 609, which is suitable as a process temperature for a silicon carbide deposition process. is there.

  Preferably, precleaning, source layer deposition, passivation, and dopant introduction may require similar conditions in some embodiments and may be performed at one station 603.

  In one embodiment described above, the station 603 is a pre-cleaning station and a protective cap forming station. Stations 605, 607, and 609 are all utilized for deposition of the dielectric diffusion barrier layer. Using the index plate 611, the substrate is removed from the pedestal and the substrate is accurately aligned to the next process station. After the wafer substrate is loaded into station 603 and subjected to a process (eg, capping including preclean and precursor layer deposition and passivation), it is indexed to station 605, where capping (including source layer deposition and passivation) is performed. ) And / or dielectric deposition. The wafer is then moved to station 607 where the deposition of the diffusion barrier dielectric is begun or continued. The substrate is further indexed to station 609, where further deposition of the barrier dielectric is performed, and further indexed to station 603, where it is unloaded to load the module with a new wafer. In normal processing, a separate substrate occupies each station and moves the substrate to a new station each time the process is repeated. An apparatus having four stations 603, 605, 607, and 609 processes four wafers simultaneously, so that at least one station performs a different process from that performed at the other station. Alternatively, instead of a specific station depositing a specific layer, all four stations can perform the same operation on four wafers.

  Some specific examples of station-to-station processing sequences are shown below. In the first example, the inlet load lock performs pretreatment (eg, reduction of copper oxide). The first station of the device (eg, station 603 or a plurality of consecutively arranged first stations) then forms a cap layer (eg, by exposure to a precursor such as TMA). The second station (eg, station 605 in FIG. 6) then performs post-treatment such as passivation (eg, by exposure to nitrogen, ammonia, and / or hydrogen as described herein). Next, the remaining stations of the apparatus (eg, stations 607 and 609) perform diffusion barrier formation.

  In another example, a first station (e.g., station 603) performs pre-processing, and a second station (e.g., station 605 or a series of consecutive stations) performs both cap layer formation and post-processing (e.g., passivation). And the remaining stations perform dielectric diffusion barrier layer deposition. In yet another example, the first station performs pre-processing, cap layer deposition, and post-processing. The remaining stations perform diffusion barrier formation.

  Process conditions and the process flow itself can be controlled by a controller unit 613 having program instructions to monitor, maintain and / or adjust certain process variables such as HF and LF power, gas flow and time, temperature, pressure, etc. It is. For example, instructions can be included that specify the flow rates of borane and ammonia for source layer deposition and passivation. The command can specify all parameters for processing according to the method described above. For example, the instructions can include parameters for precleaning, source layer deposition, passivation layer formation, dopant introduction into the copper line, and dielectric diffusion barrier deposition. The controller may include different or the same instructions for different device stations and can operate the device stations independently or synchronously.

  Another example of the multi-station device is shown in FIG. In multi-station apparatus 701, six stations 703, 705, 707, 709, 711, and 713 are located in three separate process chambers 717, 719, and 721 so that there are two stations in each chamber. ing. A chamber 715 containing a robot adjacent to chambers 717, 719, and 721 provides a mechanism for loading / unloading wafers to / from the station. The controller 723 provides instructions regarding the operation of the multi-station device 701. Individual stations within a chamber are isolated from each other and may perform the same or different processes. In one embodiment, two wafers are moved simultaneously to stations 703 and 705 in one chamber 721 and simultaneously undergo the same processing (precleaning, source layer deposition, passivation layer formation and copper doping). After this process is complete, the two wafers are removed from chamber 721 and simultaneously transferred to stations 707 and 709 in chamber 709. Within this chamber, a diffusion barrier material layer is deposited simultaneously. These wafers are then removed from chamber 719 and transferred to stations 711 and 713 in chamber 717 for further processing. In some embodiments, the formation of the protective cap layer can be performed in a multi-chamber apparatus where different sub-processes (eg, source layer deposition, passivation, dopant diffusion) are performed in different chambers.

  There are various ways to implement the capping process with a multi-station tool, several examples of which are shown in FIGS. In general, the process described can be easily incorporated into a damascene flow, does not require substantially resource consuming substrate processing, and can be performed in an apparatus similar to dielectric diffusion barrier deposition. Furthermore, resistance control by providing while controlling the dopant is particularly suitable. The described method is also useful for forming interconnects with good adhesion between copper and a dielectric diffusion barrier.

  Embodiments of the described method are detailed below by specific examples.

<Experimental example>
An experimental example illustrates the fabrication of a copper interconnect that includes a boron-doped protective cap and a passivation layer containing boron and nitrogen.

In the example described, the process begins with a plasma preclean process. A partially fabricated semiconductor device having a very low dielectric constant k (k = 2.5; 5,000 angstroms thick) copper wire exposed pattern was obtained after CMP processing to obtain PECVD VECTOR®. ) Placed in the process chamber of the apparatus. The full cap process was performed at one of the four station devices. First, the substrate was preheated to 350 degrees Celsius and H ₂ was introduced into the process chamber at a flow rate of 4,000 sccm. H ₂ was flowed in at a pressure of 4 Torr for 0 to 30 seconds at the process time. At the 30 second process time, the HF RF plasma was ignited and maintained at a power of 1.23 W / cm ² until the process time 45 seconds. The substrate was pre-cleaned with H ₂ plasma to stop H ₂ inflow and plasma power application, and B ₂ H ₆ was mixed with argon and introduced into the process chamber. The concentration of B ₂ H _{6 in} the mixture was about 5% by volume, and the mixture was introduced at a flow rate of about 3600 sccm with N ₂ introduced at a flow rate of 2400 sccm. Gas was flowed in for 45 to 85 seconds during the process, during which time a source layer containing BH _x was deposited on the substrate. Deposition was performed at a temperature of about 350 degrees Celsius and a pressure of about 2.3 Torr. The thickness of the source layer deposited on top of the copper was measured to be about 215 angstroms, and the thickness of the source layer deposited on top of the dielectric layer was measured to be about 159 angstroms. After the source BH _x layer was deposited, the introduction of borane was stopped and the layer was passivated to form (BNH) _x . Passivation was performed for 85 to 90 seconds at the time of the process, and NH ₃ was introduced at a flow rate of about 7000 sccm in addition to N 2 introduced at a flow rate of 2800 scc. Between the process time 90 sec 96 sec, 0.80 W / cm HF component of the ^two power levels and were maintained by igniting a plasma with a power level of the LF component of 0.37W / cm ^2. Passivation was performed at a temperature of about 350 degrees Celsius and a pressure of about 2.3 Torr. The total thickness of the BH _x layer on the dielectric was converted to (BNH) _x and about 25% of the thickness of the source layer on the copper was converted to (BNH) _x . The (BNH) _x layer was later analyzed by FT IR spectroscopy. In the IR spectrometer, peaks were observed at 3430 cm ⁻¹ (ν _N—H ), 2560 cm ⁻¹ (ν _B—H ), and 1375 cm ⁻¹ (ν _B—N ).

  Boron was diffused into the copper wire to form a cap layer doped with boron. It should be understood that boron diffusion can be performed before and after nitriding (passivation) the top of the source layer. The thickness of the boron doped cap in the copper wire was measured to be about 25 to 75 angstroms.

The entire cap process was performed in a single station at a temperature of 350 degrees Celsius. A Si _x C _y N _z diffusion barrier layer (approximately 500 Å) is then applied to the substrate at three different stations of the PECVD apparatus at 350 degrees Celsius using tetramethylsilane, ammonia, and nitrogen as process gases in the plasma. Deposited.

Cu (5,000 angstrom) -Si _x C _y N _z (500 angstrom) sandwiches with or without a boron-containing cap were measured by an adhesion test with 4 points curved. Compared to the adhesion energy of 15.3 J / m ² obtained with the conventional clamping structure not including the B-doped cap, the clamping body obtained by the above-described method has an adhesion energy of 28.4 J / m ^2. Was observed. It is known that the improvement in adhesion has a correlation with the improvement in electromigration performance.

Leakage current and saturation capacitance were also measured for structures containing a B-doped protective cap and a (BNH) _x passivation layer. It has been observed that these parameters are substantially unaffected by the capping process described above.

  While various details have been omitted for clarity, alternative implementations for various designs are possible. Accordingly, this example is intended to be illustrative rather than limiting, and the present invention is not limited to the details shown and modifications within the scope of the appended claims are possible.

Claims (23)

A method of forming a semiconductor device structure comprising:
(A) exposing a substrate including an oxide-free copper or copper alloy exposed region and a dielectric exposed region to a compound containing aluminum at a substrate temperature of at least 350 degrees Celsius, so that the dielectric and the copper Or forming a first layer comprising aluminum on both of the copper alloy layers;
(B) chemically modifying at least a portion of the first layer to form a passivation layer comprising aluminum;
(C) depositing a dielectric layer on the passivation layer.   The method according to claim 1, further comprising the step of cleaning the surface of the substrate to completely remove copper oxide from the surface of the copper or copper alloy before the step (a). The cleaning, direct plasma treatment, remote plasma treatment, UV treatment, and N _2, NH _3, and according to claim 2 of the H ₂ is selected from the group consisting of heat treatment in a gas containing at least any one Method.   The method according to any one of claims 1 to 3, wherein the step (a) includes a step of exposing the substrate to an organoaluminum compound without using plasma.   5. The method of claim 4, wherein step (a) comprises exposing the substrate to an organoaluminum compound at a substrate temperature of at least 400 degrees Celsius. The method according to claim 4 or 5 , wherein the organoaluminum compound is trimethylaluminum.   7. The method according to claim 1, wherein the step (b) includes a step of not allowing aluminum to diffuse into the copper by completely passivating the first layer on the copper or copper alloy. 8. The method described.   The step (b) includes the step of partially diffusing aluminum into the copper by partially passivating the first layer on the copper or copper alloy. The method according to claim 1.   The method according to claim 1, wherein the formation of the passivation layer in the step (b) includes forming an immobile compound containing an Al—N bond.   The step (b) includes the step of treating the substrate with a material containing nitrogen, wherein the treatment is selected from the group consisting of direct plasma treatment, remote plasma treatment, UV treatment, and heat treatment. The method described.   The method according to claim 10, wherein the step (b) includes a step of treating the substrate with a substance containing nitrogen without using plasma.   The method of claim 11, wherein the dielectric is a ULK dielectric.   The method according to any one of claims 1 to 8, wherein the formation of the passivation layer in the step (b) includes forming an immobile compound containing an Al-O bond.   The step (b) includes the step of treating the substrate with a substance containing oxygen, wherein the treatment is selected from the group consisting of direct plasma treatment, remote plasma treatment, UV treatment, and heat treatment. The method described.   The method according to claim 13, wherein the step (b) includes exposing the substrate to a substance containing oxygen without using plasma.   The method of claim 15, wherein the dielectric is a ULK dielectric. The method of claim 13, wherein step (b) comprises treating the substrate with a material comprising oxygen selected from the group consisting of O ₂ , N ₂ O, CO ₂ , and O ₃ .   The method according to any one of claims 1 to 17, wherein the steps (a), (b), and (c) are performed in the same chemical vapor deposition (CVD) apparatus.   The method according to claim 1, wherein the dielectric layer deposited in step (c) is an etch stop dielectric layer.   20. The method of claim 19, wherein the etch stop dielectric layer comprises a doped or undoped material selected from the group consisting of silicon nitride and silicon carbide.   19. A method according to any one of the preceding claims, wherein the dielectric layer deposited in step (c) is an interlevel dielectric (ILD) layer deposited directly on the passivation layer. An apparatus for forming a semiconductor element structure,
(A) a process chamber having an inlet for introducing a gaseous or volatile metal containing reactant;
(B) a wafer support for supporting the wafer while depositing a metal-containing layer on the wafer substrate in the process chamber;
(C) a controller having program instructions,
The program instructions are:
(I) a program instruction for processing a substrate comprising exposed copper or copper alloy and exposed dielectric to remove oxide from the exposed copper or copper alloy;
(Ii) exposing the substrate comprising an oxide-free copper or copper alloy exposed region and a dielectric exposed region to a reactant comprising aluminum at a substrate temperature of at least 350 degrees Celsius to provide the dielectric and Program instructions for forming a first layer comprising aluminum on both of the first metals;
(Iii) a program instruction for chemically modifying at least a portion of the first layer to form a passivation layer comprising aluminum.   23. The apparatus of claim 22, wherein the controller program instructions (ii) include instructions for exposing the substrate to a reactant comprising the aluminum without using plasma.

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