JP5731622B2 - Flash memory, bad block management method and management program - Google Patents

Description

  The present invention relates to a NAND flash memory, and more particularly to a bad block management method.

  A defective element generated in the manufacturing stage of the flash memory is relieved by replacing it with a memory element in a redundant area according to a redundancy scheme. On the other hand, even memory elements that are determined to be normal at the shipping stage may become defective due to repeated programming and erasing. In other words, even if a certain number of program pulses are applied, the threshold does not fall within the desired distribution width, and even if a certain number of erase pulses are applied, the threshold falls within the desired distribution width. A memory element that does not fit is generated. The flash memory employs so-called bad block management in which a block including such a defective memory element is recognized as a bad block, and the bad block is replaced with another normal block in block units (Patent Document 1). ).

JP2013-145545A

  FIG. 1 shows an operation flow of conventional bad block management. In flash memory, when a page program is performed, a program pulse is applied to the word line of the selected page, and then verification is performed to determine the threshold value of the memory cell. A program pulse higher by ΔVpgm is applied. Further, when the selected block is erased, an erase pulse is applied to the well or the substrate, and then verification is performed. If the erase is insufficient, an erase pulse higher by ΔVers than before is applied (S10). . Such a program is known as an ISPP (Incremental Step Pulse Erase) method, and erasure is known as an ISPE (Incremental Step Pulse Erase) method.

  In the flash memory, the status when the program or erasure is performed is held in the management memory (S12). The status includes, for example, that the verification of the selected page has failed due to application of a predetermined number of program pulses, that the verification of the selected block has failed due to application of a predetermined number of erase pulses, or It is stored that the final result was a failure.

  The status stored in the management memory is used to determine whether there is a bad block (S14). The presence / absence of a bad block is determined by, for example, an external controller sending a command to the flash memory, or by a program installed in the flash memory itself. If it is determined that there is a bad block, the bad block management unit performs address conversion so that access to the bad block is access to a normal spare block (S16).

  FIG. 2 is a diagram for explaining the details of the conventional bad block management. The flash memory has a bad block management unit 10 that manages bad blocks, a lookup table 20 that stores address conversion information for converting a bad block into a normal spare block, and a block selection based on row address information. And a word line selection circuit 30 for selecting a page and a memory array 40 including a plurality of blocks. M1 of the memory array 40 is a memory area allocated for user use, and SB is a spare area prepared for replacing bad blocks.

  The bad block management unit 10 determines the presence or absence of a bad block as described in step S14 in FIG. 1 according to an external command or a program installed in the bad block management unit 10. For example, as shown in FIG. 2B, it is assumed that the program (write) of the page Pi of the block 5 has been performed, but the verification has finally failed. The program failure status of this page Pi is stored in a management memory (not shown).

  If the bad block management unit 10 refers to the management memory and determines that the block 5 is a bad block because the block 5 includes the defective page Pi, the bad block management unit 10 allocates the block 5 to an empty block in the spare area SB, for example, the block 1004. At this time, the bad block management unit 10 writes the address conversion information for converting the access to the bad block 5 to the spare block 1004 in the lookup table 20. FIG. 3 is a diagram illustrating an example of a lookup table. In the lookup table, the address of the bad block 5 and the address of the spare block 1004 that replaces the address are stored in association with each other. Usually, since the logical address is provided from the external controller to the flash memory, the logical addresses of the bad block 5 and the spare block 1004 are stored in the lookup table.

  When reading, programming (writing) or erasing, the word line selection circuit 30 refers to the lookup table to determine whether or not the input row address matches the address of the bad block. The input row address is converted into a spare block address, which is converted into a physical address, and a block selection signal BSEL for selecting the block 1004 is output. Further, if it is a read or program (write) operation, a page in the selected block 1004 is selected.

  However, the conventional bad block management method has the following problems. As shown in FIG. 2B, the block 5 is determined to be a bad block due to a failure of the page Pi (for example, failure in verifying the program operation), and access to the block 5 is converted to the block 1004. Then, the data already written in the pages P0 to Pi-1 and Pi + 1 to Pn of the block 5 cannot be used. To use such data, a file management system different from the bat block management method must be executed, and pages P0 to Pi-1 and Pi + 1 to Pn of block 5 must be copied to block 1004. Therefore, complicated processing was required.

  An object of the present invention is to provide a flash memory, a bad block management method, and a management program that solve the problems of the conventional bad block management method.

  According to the NAND flash memory bad block management method of the present invention, a step of determining whether or not a bad block exists in a memory array, and when it is determined that a bad block exists, a part of the bad block is determined. A step of determining whether or not there is a bad page, and a step of setting address conversion information for converting a bad block and a page in the bad block when it is determined that there is a bad page in a part of the bad block And have.

  Preferably, the setting step sets address conversion information for converting a first page including a bad page into a corresponding page in a spare block, and a second page not including a bad page sets a bad block. Set address translation information to be accessed. Preferably, the setting step sets address conversion information for dividing a bad block into two page groups with a bad page as a boundary, and converting a page group including the bad page into a corresponding page of a spare block. Preferably, the setting step stores the address conversion information in a rewritable nonvolatile storage unit. Preferably, the bad block management method further includes a step of integrating the bad block and the spare block into one block. Preferably, the step of integrating is executed in response to the erasing of the bad block. Preferably, the step of integrating is performed by executing a command.

  The bad block management program according to the present invention is executed by the NAND flash memory. When it is determined that there is a bad block in the memory array, and when it is determined that there is a bad block, A step for determining whether or not there is a bad page in a part of the bad block, and for determining whether there is a bad page in a part of the bad block and for converting the bad block and the page in the bad block. Setting address translation information

  A NAND flash memory according to the present invention includes a memory array including a plurality of blocks, storage means for storing a status when programming and erasing are performed on the memory array, and a pad in the memory array based on the status. A first determination unit that determines whether or not a block exists; and a second determination unit that determines whether or not there is a bad page based on the status when it is determined that a bad block exists. And a setting unit that sets address conversion information for converting a bad block and a page in the bad block when it is determined that there is a bad page in a part of the bad block.

  Preferably, the flash memory is further determined to match the bad block, input means for inputting address information, third determination means for determining whether the address information from the input means matches the bad block, and And converting means for converting the address information in accordance with the address conversion information. Preferably, the flash memory further includes fourth determination means for determining whether the address information from the input means corresponds to a bad page, and when the conversion means is determined to match the bad page The address information is converted according to the address conversion information. Preferably, the conversion means does not convert the address information according to the address conversion information when the fourth determination means determines that the address information does not correspond to a bad page.

  According to the present invention, when it is determined that a part of the bad block is a bad page, the address conversion information for converting the page in the bad block is set. Data of pages that are not pages can be used continuously.

It is a figure which shows the operation | movement flow of the bad block management of the conventional flash memory. It is a figure explaining the conventional bad block management. It is a figure which shows an example of the look-up table used for the conventional bad block management. It is a block diagram which shows one structural example of the flash memory based on the Example of this invention. 3 is a circuit diagram showing a configuration of a NAND string of a memory cell array according to an embodiment of the present invention. FIG. It is a figure which shows an example of the voltage applied to each part at the time of programming of the flash memory which concerns on a present Example. 12 is a flowchart for explaining an LUT creation operation in bad block management of the flash memory according to the embodiment. It is a figure which shows an example of LUT of a present Example. 4 is a flowchart for explaining the operation of the flash memory according to the embodiment. It is a flowchart explaining the operation | movement of the defragmentation which concerns on a present Example. It is a figure explaining the example of the defragmentation and update of LUT which concern on a present Example.

  Next, embodiments of the present invention will be described in detail with reference to the drawings. In a preferred embodiment of the present invention, a NAND flash memory is exemplified. It should be noted that in the drawings, each part is highlighted for easy understanding, and is different from an actual device scale.

  FIG. 4 is a block diagram showing the configuration of the flash memory according to the embodiment of the present invention. However, the configuration of the flash memory shown here is an example, and the present invention is not necessarily limited to such a configuration.

  The flash memory 100 of this embodiment includes a memory array 110 in which a plurality of memory cells arranged in a matrix are formed, an input / output buffer 120 connected to an external input / output terminal I / O and holding input / output data, Address register 130 for receiving address data from input / output buffer 120, data register 140 for holding input / output data, command data from external input / output buffer 120 and external control signals (chip enable, address latch enable, etc. not shown) Controller 150 for supplying control signals C1, C2, C3, etc. for controlling each part based on the above, a look-up table (LUT) 152 storing address information necessary to replace bad blocks with normal spare blocks, and a program (Write) and erase The management memory 154 for storing the recell status and the like, and the row address information Ax from the address register 130 or the address-converted address information in the lookup table are decoded, and block selection and word line selection are performed based on the decoding result. A word line selection circuit 160, a page buffer / sense circuit 170 that holds data read from the page selected by the word line selection circuit 160, and holds write data to the selected page, and an address register 130 The column selection circuit 180 that decodes the column address information Ay from the column and selects the column data in the page buffer 170 based on the decoding result, and the voltage (program voltage Vpgm, pass Voltage Vpass, read voltage Vread, off And an internal voltage generation circuit 190 that generates a residual voltage Vers).

  The controller 150 has a function for managing bad blocks, as will be described later, and manages bad blocks in response to commands from an external controller or in response to a control sequence or control program installed in the controller 150. Run. When a program (write) or erase operation is performed, the controller 150 writes the status in the management memory 154 and writes address conversion information for converting the bad block and / or the page in the bad block into the LUT 152. . In a preferred embodiment, the LUT 152 and the management memory 154 are composed of a rewritable nonvolatile memory or a nonvolatile register.

  The memory array 110 has a plurality of blocks BLK (0), BLK (1),..., BLK (m) arranged in the column direction. A page buffer / sense circuit 170 is disposed at one end of the block. However, the page buffer / sense circuit 170 may be disposed at the other end of the block or at both ends. Further, the memory array 110 may be arranged on both sides of the word line selection circuit 160.

  As shown in FIG. 5, a plurality of NAND string units NU in which a plurality of memory cells are connected in series are formed in one memory block, and n + 1 string units NU are arranged in the row direction in one memory block. ing. The cell unit NU includes a plurality of memory cells MCi (i = 0, 1,..., 31) connected in series, and a selection transistor TD connected to the drain side of the memory cell MC31 which is one end. , The selection transistor TS connected to the source side of the memory cell MC0 which is the other end, the drain of the selection transistor TD is connected to the corresponding one bit line GBL, and the source of the selection transistor TS is common Connected to the source line SL.

  The control gate of the memory cell MCi is connected to the word line WLi, and the gates of the selection transistors TD and TS are connected to selection gate lines SGD and SGS parallel to the word line WL. When the word line selection circuit 160 selects a block based on the row address Ax or the converted address, the word line selection circuit 160 selectively drives the selection transistors TD and TS via the block selection gate signals SGS and SGD. Although FIG. 5 shows a typical cell unit configuration, the cell unit may include one or a plurality of dummy cells in the NAND string.

  A memory cell is typically formed on a source / drain which is an N type diffusion region formed in a P-well, a tunnel oxide film formed on a channel between the source / drain, and a tunnel oxide film. The MOS structure includes a floating gate (charge storage layer) and a control gate formed on the floating gate via a dielectric film. When charge is not accumulated in the floating gate, that is, when data “1” is written, the threshold value is in a negative state, and the memory cell is normally on. When electrons are accumulated in the floating gate, that is, when data “0” is written, the threshold value is shifted to positive, and the memory cell is normally off.

  FIG. 6 is a table showing an example of the bias voltage applied during each operation of the flash memory. In the read operation, a certain positive voltage is applied to the bit line, a certain voltage (for example, 0V) is applied to the selected word line, and a pass voltage Vpass (for example, 4.5V) is applied to the unselected word line. A positive voltage (for example, 4.5 V) is applied to the selection gate lines SGD and SGS, the bit line selection transistor TD and the source line selection transistor TS are turned on, and 0 V is applied to the common source line. In the program (write) operation, a high voltage program voltage Vprog (15 to 20 V) is applied to the selected word line, an intermediate potential (for example, 10 V) is applied to the non-selected word line, and the bit line selection transistor TD is turned on. The source line selection transistor TS is turned off, and a potential corresponding to data “0” or “1” is supplied to the bit line GBL. In the erasing operation, 0 V is applied to the selected word line in the block, a high voltage (for example, 20 V) is applied to the P well, and electrons in the floating gate are extracted to the substrate, thereby erasing data in units of blocks.

  Next, the LUT creation operation in the bad block management method of this embodiment will be described with reference to the flowchart of FIG. The controller 150 starts managing bad blocks in response to a command from the external controller or in response to a control sequence or control program installed in the controller 150 (S100).

  When bad block management is executed, the controller 150 reads the status from the management memory 154 and checks the verification result of the program or erase. As described above, when a program (write) or erase by the ISPP method or ISPE method is executed, verification is performed, and the verification result or the like is stored in the management memory 154. For example, the verification of the selected page failed or passed by applying a predetermined number of program pulses, the verification of the selected block failed or passed by applying a predetermined number of erase pulses, or the final verification The fact that the target result has been rejected is stored as a status.

  The presence or absence of a bad block is determined based on the status check result (S104). The determination as to whether or not the block is a bad block may be performed by the controller 150, or a status check result is provided to the external controller in response to a command from the external controller, and the determination result there is received. May be. Therefore, an algorithm for determining whether or not the block is a bad block is prepared in advance in the controller 150 or the external controller. The criteria for determining what block is a bad block can be arbitrarily determined. For example, if the final verification result is rejected, or if it is necessary to apply more than a certain number of program pulses or erase pulses even if the final verification result is acceptable, a bad block is selected. Can do.

  If it is determined that there is a bad block (S104), it is further determined whether or not a part of the bad block is a bad page (S106). The fact that part of the bad block is a bad page means that a bad page and a normal page exist in the bad block. The determination of whether or not the page is a bad page may be performed by the controller 150 or may be performed by an external controller, similarly to the determination of whether or not the page is a bad block. A criterion for determining which page is a bad page can be arbitrarily determined. For example, when the final verify result of the program fails or when the expected number of program pulses is exceeded, the page can be made a bad page, that is, a bad page. For example, as shown in FIG. 2B, the page Pi of the block 5 is determined as a bad page.

  When it is determined that there is a bad block and a bad page is included, the controller 150 writes the address conversion information for converting the bad block and the page in the bad block into the LUT 152 (S108). On the other hand, if it is determined that there is a bad block but there is no bad page, the controller 150 writes address conversion information for converting the bad block into the LUT 152 (S110).

  FIG. 8 is a diagram for explaining address conversion information of the LUT 152. In FIG. 8A, it is assumed that page Pi is a bad page (bad page) and block 5 is determined to be a bad block. In this case, pages other than page Pi in block 5 are normal, and continuous use of data written in pages other than page Pi is desired. In one aspect, access to pages P0 to Pi-1 is valid as it is, that is, access to block 5 is continued, and access to pages Pi to Pn is directed to corresponding pages Pi to Pn of spare block 1004. To be converted.

  FIG. 8B shows an example of address conversion information in the lookup table. The lookup table has a block conversion table, and address information for converting the bad block 5 into the spare block 1004 is defined in the block conversion table. Further, flag information is defined as additional information in the block conversion table. The flag information identifies whether a bad block includes a bad page and a normal page. If the bad block includes a bad page and a normal page, the flag is set to “1” and a page conversion table is created. When all the pages of the bad block are bad pages, or when it is not determined that the bad block contains the bad page, the flag is set to “0”. In the example of FIG. 8A, since the bad block 5 includes the bad page Pi and other normal pages, the flag is set to “1”, and a page conversion table is further added to the bad block 5.

  The page conversion table defines address conversion information for converting a page including a bad page in a bad block and address conversion information for converting a page not including a bad page. In the example of FIG. 8A, the block 5 is divided into a page group A of normal pages P0 to Pi-1 and a page group B of pages Pi to Pn including bad pages with a bad page Pi as a boundary. Then, the access to the page group A accesses the block 5 as it is, that is, the address to the page group A is not converted. On the other hand, for the access to the page group B, the address conversion information is defined so that the corresponding page of the block 1004 is accessed.

  It is arbitrary how to divide the block 5 that includes the defective page and the block 5 that does not include the defective page. For example, only the defective page Pi may be converted into the page Pi of the block 1004, and other normal pages P0 to Pi-1 and Pi + 1 to Pn may be continuously accessed in the block 5. However, as in the example of FIG. 8B, it is possible to increase the frequency of access to the same block by converting a continuous page including the defective page Pi into a spare block, which is advantageous in reducing the access time. It is.

  Next, read, program, and erase operations after bad block management is executed will be described with reference to the flowchart of FIG. When a command such as read, program (write), or erase is transmitted from the external controller to the flash memory 100, the controller 150 decodes the received command and determines its operation (S200). In the read and program operations, the controller 150 determines whether or not the block address of the input row address matches the bad block address (S202). For this determination, the LUT 152 is referred to.

  When matching the bad block, the controller 150 determines whether or not the bad block includes a bad page as a part thereof (S204). For this determination, the LUT flag is referred to “1”. When it is determined that a part includes a bad page, the controller 150 refers to the page conversion table of the bad block and converts the input page address (S206). For example, in the example of FIG. 8, if the input page address corresponds to P0 to Pi-1 of block 5, the address is converted to access page group A of block 5 according to the page conversion table, and the page If it corresponds to Pi to Pn, the address is converted to access page group B of block 1004.

  If it is determined that the bad block does not include a bad page, that is, if the flag is “0”, the input block address is converted into the address of the spare block according to the block conversion table (S208). When the input block address does not match the bad block address (S202), the input block address is used as it is without being converted (S210). The input address or the converted address is provided to the word line selection circuit 160, and the word line selection circuit 160 selects a block and a page (S220). As a result, the data stored in the normal page in the bad block can be continuously used.

  On the other hand, when the erase operation is performed (S200), the controller 150 determines whether or not the input block address matches the bad block address (S212). Accordingly, the block address is converted into the address of the spare block (S214). In the example of FIG. 8, if the input block address is block 5, it is converted to the address of block 1004.

  If the input block address does not correspond to the bad block address (S212), the input block address is used as it is. Then, the word line selection circuit 160 selects a block according to the input block address or the converted block address (S220). When the input block address corresponds to a bad block, at least the spare block is erased. At the same time, the bad block may be erased.

  Next, defragmentation and LUT update of the present embodiment will be described with reference to the flowchart of FIG. When a defragmentation command is determined in response to a command transmitted from the external controller or a control sequence or control program mounted on the controller (S300), the controller 150 executes defragmentation (S302). As shown in FIG. 8, when a bad page includes a bad page and a normal page, there are two blocks, block 5 including page group A and block 1004 including page group B. In the defragmentation, page data fragmented into two blocks is integrated or aggregated into one block.

  As shown in FIG. 11A, the controller 150 integrates the page group A of the block 5 and the page group B of the block 1004 into a free spare block, for example, the block 1006. The data of page group A in block 5 is programmed into each corresponding page in block 1006, and the data in page group B in block 1004 is programmed into each corresponding page in block 1006. As a result, the two blocks 5 and 1004 are integrated into one block 1006. Preferably, after defragmentation has been performed, block 1004 is erased, leaving block 1004 free.

  Next, the controller 150 updates the contents of the LUT 152 (S308). That is, the controller 150 updates the LUT address conversion information so that the defragmentation result is reflected. Specifically, as shown in FIG. 11B, the address conversion information is rewritten so that the address of the bad block 5 is converted to the address of the spare block 1006, and the flag is set to “0” at the same time. . Along with this, the page conversion table of the bad block 5 is deleted.

  Further, when the erase operation is executed (S304), the controller 150 determines whether or not the selected block is a bad block (S306). Erasing a bad block means that data stored in a normal page of the bad block is unnecessary. For example, the data of the page group A of the block 5 and the page group B of the block 1004 shown in FIG. 8A are not necessary, and it is not necessary to access the page groups A and B during page reading or page program. . Therefore, when the flag “1” is set in the bad block 5, the controller 150 rewrites the flag to “0” and updates the LUT 152 so as to delete the page conversion table of the block 5 (S308). .

  By executing defragmentation in this way, access across blocks can be reduced and access speed can be improved. Furthermore, the efficiency of bad block management can be improved by increasing the number of empty blocks in the spare memory area.

  In the above embodiment, the flash memory in which the memory cell stores binary data is exemplified. However, the present invention can also be applied to a flash memory in which the memory cell stores multilevel data. Further, in the above-described embodiment, an example is shown in which the controller 150 manages bad blocks, but this may be performed by the word line selection circuit 160, or a bad block management unit may be provided separately from the controller 150. It may be. Further, the LUT 152 and the management memory 154 can use a part of the memory area of the memory array 110, or the controller 150 may include the LUT and the management memory therein.

  Although the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

100: flash memory 110: memory array 120: input / output buffer 130: address register 140: data register 150: controller 152: lookup table 154: management memory 160: word line selection circuit 170: page buffer / sense circuit 180: column selection circuit

Claims (14)

A bad block management method for NAND flash memory,
Determining whether there is a bad block in the memory array;
When it is determined that a bad block exists, a step of determining whether or not there is a bad page in a part of the bad block;
When it is determined that there is a bad page in a part of the bad block, a step of setting address conversion information for converting the bad block and the page in the bad block,
The setting step is configured to divide a bad block into two page groups with a bad page as a boundary, and to set address conversion information for converting a page group including a bad page into a corresponding page of a spare block. Management method. The bad block management method according to claim 1, wherein the setting step sets address translation information such that a page group not including a bad page is accessed by a bad block. The bad block management method according to claim 1, wherein the setting step stores address conversion information in a rewritable nonvolatile storage unit. The bad block management method according to any one of claims 1 to 3, further comprising a step of integrating the bad block and the spare block into one block. The bad block management method according to claim 4, wherein the integrating step is executed in response to erasing of a bad block. The bad block management method according to claim 4, wherein the integrating step is executed by executing a command. A bad block management program executed by the NAND flash memory,
Determining whether there is a bad block in the memory array;
When it is determined that a bad block exists, a step of determining whether or not there is a bad page in a part of the bad block;
When it is determined that there is a bad page in a part of the bad block, a step of setting address conversion information for converting the bad block and the page in the bad block,
The setting step divides a bad block into two page groups with a bad page as a boundary, and sets address conversion information for converting a page group including a bad page into a corresponding page of a spare block. program. A memory array including a plurality of blocks;
Storage means for storing a status when the memory array is programmed and erased;
First determination means for determining whether or not a bad block exists in the memory array based on the status;
Second determination means for determining whether or not there is a bad page based on the status when it is determined that a bad block exists;
A setting means for setting address conversion information for converting a bad block and a page in the bad block when it is determined that there is a bad page in a part of the bad block;
The setting unit divides a bad block into two page groups with a bad page as a boundary, and sets address conversion information for converting a page group including a bad page into a corresponding page of a spare block. memory. 9. The flash memory according to claim 8, wherein the setting means sets address conversion information so that a page group not including a bad page can access a bad block. The flash memory further includes an input unit that inputs address information, a third determination unit that determines whether the address information from the input unit matches a bad block, and when it is determined that the address matches the bad block, 10. The flash memory according to claim 8, further comprising conversion means for converting the address information according to the address conversion information. The flash memory further includes fourth determination means for determining whether the address information from the input means corresponds to a bad page, and when the conversion means is determined to match the bad page, 11. The flash memory according to claim 10, wherein address information is converted according to the address conversion information. 12. The conversion unit according to claim 10 or 11, wherein the conversion unit does not convert the address information according to the address conversion information when the fourth determination unit determines that the address information does not correspond to a bad page. Flash memory. The flash memory according to any one of claims 8 to 12, further comprising integration means for integrating the bad block and the spare block into one block. 14. The flash memory according to claim 13, wherein the integration by the integration unit is executed in response to erasing of a bad block.

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