JP5727978B2 - FMCW signal generator - Google Patents

Description

  The present invention relates to an FMCW signal generator, and more particularly to an FMCW signal generator that is a frequency modulation signal generation circuit.

  Conventionally, there is an FMCW radar apparatus that uses an FMCW (Frequency Modulated Continuous Wave) signal as one of radar apparatuses that use radio signals. In the FMCW radar apparatus, the FMCW signal transmitted from the transmitter of the radar apparatus is reflected by the object, and the reflected wave is received by the receiver of the radar apparatus. The receiver multiplies the reception signal of the reflected wave by the transmission signal (FMCW signal) transmitted from the transmitter at the time of reception, so that the frequency of the output signal from the multiplier depends on the time difference between the reception signal and the transmission signal. Using the determined value, the distance to the object and the relative speed are measured. Such an FMCW signal for radar use is required to have a frequency swept almost linearly with respect to time.

  In general, an FMCW signal generator that enables such frequency sweeping includes a digital signal processor (DSP) that generates a digital value representing a discrete frequency of the FMCM signal, and the digital value as an analog signal. It is realized by a digital-to-analog converter (DAC) and a direct digital frequency synthesizer (DDFS) including an anti-aliasing filter. To generate an FMCW signal in the frequency band actually used by the radar, a method of mixing the DDFS output signal and the carrier frequency signal, or a frequency divider using the DDFS output signal as a phase reference signal is looped. A method using a PLL included in the above is known.

  For example, the one described in Patent Document 1 relates to a radar system that corrects frequency nonlinearity and frequency deviation of a voltage controlled oscillator (VCO) used for generation of a chirp signal in an FMCW radar. The chirp signal generated by the voltage controlled oscillator is mixed with a signal having a predetermined single frequency to cancel the center frequency of the voltage controlled oscillator, and the A / D conversion means performs the processing on the signal obtained by the mixing means. Analog-to-digital conversion is performed to generate a digital sample value. The error detection unit detects an error from the ideal chirp signal with respect to the digital sample value generated by the A / D conversion unit. The error detected by the detection means approaches 0 The frequency control signal for the voltage controlled oscillator is controlled. With such a configuration, in the FMCW radar, it is possible to correct the frequency nonlinearity and frequency deviation of the voltage controlled oscillator (VCO) used for generating the chirp signal.

In Non-Patent Document 1, the RAM data is changed by measuring the frequency of a certain frequency period existing between the ramp waves. Moreover, it converts into a low frequency using a DRO (dielectric resonator) and a down converter, and a reference frequency will carry out temperature fluctuation.
FIG. 1 is a block diagram of a conventional FMCW system, showing an FMCW modulation scheme. In order to realize the FMCW system, the sawtooth wave generation circuit 1, the voltage controlled oscillator (VCO) 2 that operates using the sawtooth wave generated by the sawtooth wave generation circuit 1 as a modulation wave, and the output of the VCO2 can be radiated from the antenna 7. A power amplifier (PA) 3 that amplifies the signal and a duplexer that transmits traffic to the antenna 7 while the signal from the antenna 3 is transmitted to an LNA (low noise preamplifier) 5. (Duplexer) 4, an antenna 7 that radiates and receives radio waves, an LNA 5 that amplifies a received signal from the duplexer 4, a signal from the VCO 2 and the output of the LNA 5 are multiplied and the frequency difference (Δf) is obtained. It comprises a mixer 6 to be generated.

However, the accuracy of the VCO output frequency fout is required to be very accurate in order to accurately detect the frequency difference (Δf), and calibration is indispensable in order to mitigate the effects of temperature fluctuations and secular changes. is there.
FIG. 2 is a diagram showing ideal FMCW (VF) characteristics and non-ideal effects, and is a diagram for explaining problems of the FMCW system shown in FIG. In the FMCW system, it is required that 1) the frequency changes linearly with respect to time, and 2) the slope of the frequency change does not change with time and temperature. For example, it is required to always maintain the time-frequency characteristic of the solid line as shown in org in FIG. However, in reality, the slope of time vs. frequency changes due to secular change like the “a” dashed line, or the frequency offset is added like the “b” dashed line. For this reason, calibration is required to return the lines “a” and “b” to the org line.

  FIG. 3 is a circuit configuration diagram for solving the problems of the FMCW system described in FIG. A system that distributes the output of the VCO with a coupler (coupler), converts the frequency to a low frequency using a DRO (Dielectric Resonator Oscillator) and a mixer (Mixer) with high frequency accuracy, and measures with a counter Was taken. However, in this case, 1) The signal-to-noise ratio (SNR) of the signal path is degraded by extracting the signal with the coupler. 2) DRO temperature characteristics fluctuate and accurate frequency measurement is not possible. 3) Since circuits such as a coupler, a DRO, and a mixer are blown, there are disadvantages such as an increase in cost and power consumption.

  FIG. 4 is a diagram showing necessary signals in the circuit configuration diagram for solving the problem of the FMCW system described in FIG. The conventional method shown in FIG. 2 has not only the above-mentioned electrical and physical defects, but also a systematic problem that the time available for radar measurement is limited for calibration.

The purpose of this calibration is to make the transmission signal frequency the same as the intended frequency of the system. Therefore, the transmission signal needs to be known, and the transmission signal frequency is preferably constant in order to perform highly accurate measurement. On the other hand, in the FMCW system, there is no fixed frequency period.
Therefore, the calibration signal needs to be embedded between the FMCW signals as shown in FIG. As is apparent from FIG. 4, the radar system has a drawback that it cannot operate as a radar during the period of the transmission signal frequency f1 and f2.

JP 2011-127923 A

“Novel FM Nonlinear Collection Method Basd on Periodic Monitoring and Adaptive Adjusting of FMCW Source” LI YANG and 4 others pp.465-466 IEE

As described above, the above-described prior art has a frequency error due to temperature fluctuation, a frequency error due to secular change, a performance deterioration due to addition of a special signal for frequency measurement, and a signal frequency of 10 G or more. There is a problem that it is difficult to directly count.
In addition, the accuracy of the VCO output frequency fout is required to be very accurate in order to accurately detect the frequency difference (Δf), and calibration is indispensable in order to mitigate the effects of temperature fluctuations and secular changes. is there.

  The present invention has been made in view of such a situation, and an object of the present invention is to perform frequency calibration of the FMCW system while adding a minimum circuit and avoiding a pause of the radar system. An FMCW signal generator is provided.

The present invention has been made to achieve such an object. The invention according to claim 1 is directed to a first PLL circuit that generates an FMCW signal from a reference signal having a predetermined reference frequency, and the FMCW. A frequency detector that generates frequency measurement data from a first signal obtained by down-converting the signal and feeds it back to the first PLL circuit; and a reference signal having a predetermined reference frequency and a frequency higher than the reference frequency. And a second PLL circuit for generating a second signal, wherein the first PLL circuit calibrates the FMCW signal based on the fed back signal and converts the FMCW signal by the second signal. A mixer unit for down-converting to generate the first signal, and the reference signal based on the feedback signal Characterized in that it comprises a correction unit for correcting the reference frequency.

Further, an invention according to claim 2, in the invention described in claim 1, wherein the first PLL circuit converts the FMCW signal to a third signal having a frequency lower than the frequency of the FMCW signal A frequency divider is provided.
According to a third aspect of the present invention, in the first or second aspect of the present invention, the frequency detector includes a first signal obtained by down-converting the output signal of the loop filter included in the first PLL circuit and the FMCW signal. The frequency measurement data is generated from one signal.

According to the present invention, it is possible to realize an FMCW signal generator configured to perform frequency calibration of an FMCW system while adding a minimum circuit and avoiding a pause of a radar system.
In addition, frequency errors due to temperature fluctuations, frequency errors due to secular changes, performance degradation due to addition of special signals for frequency measurement, and it is difficult to directly count signal frequencies above 10 GHz. The problem can be solved.

It is a block diagram of the conventional FMCW system, and is a figure which shows a FMCW modulation system. It is a figure which shows an ideal FMCW (VF) characteristic and a non-ideal effect. It is a circuit block diagram for solving the problem of the FMCW system demonstrated in FIG. It is a figure which shows the signal required in the circuit block diagram for solving the problem of the FMCW system demonstrated in FIG. It is a circuit block diagram for demonstrating embodiment of the FMCW signal generator based on this invention. FIG. 6 is a circuit configuration diagram for explaining a specific example of the FMCW signal generator according to the present invention shown in FIG. 5. It is a circuit block diagram of the frequency detector shown in FIG. It is a figure which shows the frequency (F) vs. voltage (V) characteristic example of a voltage controlled oscillator (VCO). (A) thru | or (g) is a figure for demonstrating operation | movement of a frequency detector with reference to the voltage waveform on the time-axis of each part of the circuit of the frequency detector shown in FIG.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 5 is a circuit configuration diagram for explaining an embodiment of the FMCW signal generator according to the present invention, and is a circuit configuration diagram of a double loop PLL (Phase Locked Loop). In the figure, reference numeral 11 denotes a first PLL circuit (main loop), 12 denotes a frequency detector, 13 denotes a second PLL circuit (2nd loop), and 14 denotes a reference frequency generator. Here, f0 is the output signal frequency, f2 is the output frequency of the second PLL circuit, f3 is the input frequency of the frequency detector << f0, f2, and fref is the reference signal frequency << f2.

  A radar system generally uses a frequency higher than the vicinity of 10 GHz. When such a high frequency is generated using the PLL system, since the reference clock (usually crystal oscillator <50 MHz) is low, the requirement for the phase noise of the reference clock becomes severe. Therefore, the present invention is based on the premise that a double-loop PLL having a rope for jumping up the reference clock is used in addition to the PLL main loop in order to ease the phase noise requirement for the reference clock.

  The FMCW signal generator of the present embodiment generates frequency measurement data from a first PLL circuit 11 that generates an FMCW signal from a reference signal having a predetermined reference frequency, and a first signal obtained by down-converting the FMCW signal, A frequency detector 12 that feeds back to the first PLL circuit 11, a second PLL circuit 13 that generates a second signal having a frequency higher than the reference frequency from a reference signal having a predetermined reference frequency, and a reference frequency The first PLL circuit 11 is configured to calibrate the FMCW signal based on the fed back signal. The second PLL circuit 13 is for jumping the frequency from the stable frequency fref to f2.

  FIG. 6 is a circuit configuration diagram for explaining a specific embodiment of the FMCW signal generator according to the present invention shown in FIG. In the figure, reference numeral 111 is a look-up table (Look Up Table; LUT / corrector), 112 is a digital-analog converter (DAC), 113 is a first phase frequency detector (Phase Frequency Detector; PFD1), 114 Is a first charge pump (CP1), 115 is a first loop filter (LF1), 116 is a first voltage controlled oscillator (VCO1), and 117 is a first frequency divider. Divider (Div1), 118 is a mixer (frequency converter) (Mixer / Frequency Converter), 119 is a low-pass filter (Low Pass Filter; LPF), 131 is a second frequency divider (Div2), 132 is a second phase frequency detector (PFD2), 132 is a second loop filter (LP2), 133 is a second charge pump (CP2), 134 is a second loop filter (LF2) , 135 are second voltage controlled oscillators (VCO2). In addition, the same code | symbol is attached | subjected to the component which has the same function as FIG.

  In order to correct the V / F characteristics without stopping the ramp wave, we have developed a double-loop PLL with a frequency detector. Since the frequency of the PLL having f0 exceeding 10 GHz cannot be directly counted, an offset loop (double loop) PLL is used. By inserting the first frequency divider 117, f2 = N × f1 + f3 => f2 << f0. The oscillation frequencies of the two voltage controlled oscillators (VCO) 116 and 135 are separated. Since it is a non-integer multiple, the problem of frequency jumping is alleviated. The second voltage controlled oscillator (VCO) 135 is easily reduced in power, and the entire power is reduced.

The first PLL circuit 11 includes a mixer unit 118 that down-converts the FMCW signal with the second signal to generate the first signal. The mixer unit 118 is used as a circuit for extracting f1 × f2 = (f1 + f2) + (f1−f2), f1−f2 = f3.
The first PLL circuit 11 includes a correction unit (LUT) 111 that corrects the reference frequency of the reference signal based on the fed back signal. The first PLL circuit 11 includes a frequency divider 117 that converts the FMCW signal into a third signal having a frequency lower than the frequency of the FMCW signal.

The frequency detector 12 generates frequency measurement data from the output signal of the loop filter 115 included in the first PLL circuit 11 and the first signal obtained by down-converting the FMCW signal.
By the 2nd loop, it was possible to increase the frequency of fref to f2 = Div2 × fref times. On the other hand, if the DAC operating at the reference frequency fref generates a signal of frequency f4, the input / output frequency of f4 = (f0 / Div1) −f2 from the relationship of f1 = f0 / Div1 f3 = f1−f2 = f4. Get a relationship. However, since f4 is a frequency-swept signal, f0 which is the output of the FMCW also obtains the same frequency modulation. The frequency f3 input to the frequency detector at this time is expressed by f3 = f0 / Div1-Div2 × fref, and a frequency (for example, about fref) that can be sufficiently measured by a digital circuit by appropriately selecting Div1 and Div2. Can be lowered to Since the frequency division value of the main loop at this time remains Div1, the required value for the phase noise of the reference signal generated by the DAC is greatly relaxed.

  FIG. 7 is a circuit configuration diagram of the frequency detector shown in FIG. In the figure, reference numeral 121 is an upper peak hold circuit (Upper Peak Hold), 122 is an average value circuit (Averaging), 123 is a lower peak hold circuit (Bottom Peak Hold), 124 is a maximum frequency (Max frequency) circuit, and 125 is an average. A frequency (Mean frequency) circuit, 126 is a minimum frequency (Min frequency) circuit, 127 is a frequency counter, and 128 is a DSP (Digital Signal Processor).

The frequency detector 12 includes a frequency counter 127 that counts the frequency of f3 in the main loop 11, an upper peak hold circuit 121 that captures the upper peak voltage of the loop filter voltage VLF1, and a lower peak hold that captures the lower peak voltage. A circuit 123 and an average value circuit 122 for capturing an average value are provided.
A maximum frequency circuit 124 for calculating the maximum frequency error D _U from the maximum frequency data Max calculated by the frequency counter 127 and the upper peak hold voltage V _U ; a minimum frequency data Min calculated by the frequency counter 127; minimum frequency circuit 126 for calculating an error D _B of the lowest frequency from the side peak hold voltage V _B, the average frequency value data mean frequency counter 127 has calculated, the error D _a mean frequency from the average voltage V _a Reference is made from the data of the average frequency circuit 125 to be calculated, the maximum, minimum and average frequency information given as specifications, the maximum frequency error D _U , the minimum frequency error D _B and the average frequency error D _A And a DSP 128 for creating an LUT to be performed.

FIG. 8 is a diagram illustrating a frequency (F) vs. voltage (V) characteristic example of the voltage controlled oscillator (VCO). In the DSP 128, typical characteristics of the voltage controlled oscillator (VCO) V-F characteristics are acquired in advance, and the latest measured values, the highest frequency error D _U , the lowest frequency error D _B , and the average frequency error D _A , Is used to determine data to be referred to by the LUT.
The maximum value and the minimum value of the oscillation frequency given as specifications are assumed to be f1 (max) and f1 (min), respectively. At this time, the average value f1 (mid) of the oscillation frequency is obtained by the following equation.

f1 (mid) = (f1 (max) −f1 (min)) / 2
= (F3 (max) -f3 (min)) / 2
However, f3 = f1-f2 and f2 are fixed frequencies.

On the other hand, the upper peak hold voltage V _U , the lower peak hold voltage V _B , and the average value voltage V _A are non-linear in the VF characteristics of the voltage controlled oscillator (VCO), and therefore V _A ≠ V _B + V _U / 2 and the average value voltage V _A is used as a parameter for minimizing the nonlinearity of the voltage controlled oscillator (VCO).

Further, when the VF characteristic of the voltage controlled oscillator (VCO) has a very large non-linearity, f1 (max) and f1 (min) times are calculated using the time during which radar measurement is not performed. The accuracy of correction can be improved by dividing the calibration into small sub-sectors.
FIGS. 9A to 9G are diagrams for explaining the operation of the frequency detector with reference to the voltage waveform on the time axis of each part of the circuit of the frequency detector shown in FIG. A voltage example is shown.

  FIG. 9A shows how the frequency f1 and f2 vary with time in the main loop. In the figure, f1 is the oscillation frequency of the first voltage-controlled oscillator (VCO1) 116, and it is expected that the frequency fluctuates linearly with respect to time. f2 is a fixed frequency. f3 is f1-f2, and assumes a frequency that can be measured by a frequency counter. FIG. 9B shows the down-converted f3. This is the input of the frequency detector.

FIG. 9 (c) shows the output of the upper peak hold circuit in the frequency detector. In dashed line VLF1 waveform in the drawing, the output of the upper peak hold circuit is attenuated, and more at the leak, this attenuation follows the input VLF1 signal from a point becomes V _U. FIG. 9D shows the output of the lower peak hold circuit. FIG. 9E shows the output of the average value circuit.
FIG. 9F shows an expected value of VLF1, and f4 is generated as a LUT + DAC pair so that the charge pump outputs this VLF1. The tent-shaped waveform of VLF1 is a loop filter output generated by a signal generated in the LUT in order to correct the V-F characteristic of VCO1.

FIG. 9G is a diagram for explaining the reason why the VLF 1 in FIG. 9F has a tent-shaped waveform. In the VF characteristics of VLF1 + VCO1, f1 (time vs. frequency) linearly increases or decreases.
In the figure, V _U (max) is a voltage indicating the highest oscillation frequency, and the timing of V _U (max) is the timing at which f1 is the highest. V _B (min) is a voltage indicating the lowest oscillation frequency, and the timing of V _B (min) is the timing at which f1 is lowest. V _A (mean) indicates the center of the oscillation frequency.

9C and 9D show the input VLF1 waveform when the blocks of the maximum frequency circuit 124 and the minimum frequency circuit 126 in FIG. 7 do not perform the peak hold operation. Therefore, the waveform of this dotted line is similar to that in FIG. Also, the dotted line in FIG. 9 (e) indicates the average value of the _VA waveform, unlike in FIGS. 9 (c) and 9 (d). The average value of the _VA waveform is a value indicating the center frequency of the oscillation frequency f0 of the VCO 1 in FIG.

  Further, the solid line and the dotted line in FIG. 9C intersect at the point where the VLF1 waveform becomes equal to the upper peak hold output, and the upper peak hold output is the output of the maximum frequency circuit 124 until the maximum value is shown after that moment. Follow. Similarly, the solid line and the dotted line in FIG. 9D intersect at a point where the VLF1 waveform becomes equal to the lower peak hold output, and the lower peak hold output is the minimum frequency until the minimum value is shown after that moment. Follow the output of circuit 126. On the other hand, the dotted line in FIG. 9E is the average value of the solid line, and its flatness mainly depends on the integration time of the average frequency circuit 125.

1 sawtooth wave generation circuit 2 voltage controlled oscillator (VCO)
3 Power Amplifier (PA)
4 Duplexer (Duplexer)
5 LNA (low noise preamplifier)
6 Mixer
7 Antenna 11 First PLL circuit (main loop)
12 Frequency detector 13 Second PLL circuit (2nd loop)
14 Reference Frequency Generator 111 Look Up Table (LUT)
112 Digital-to-analog converter (DAC)
113 1st phase frequency detector (Phase Frequency Detector; PFD1)
114 1st charge pump (Charge Pump; CP1)
115 First loop filter (LF1)
116 First Voltage Controlled Oscillator (VCO1)
117 1st frequency divider (Divider; Div1)
118 Mixer (Frequency Converter) (Mixer / Frequency Converter)
119 Low pass filter (LPF)
121 Upper Peak Hold Circuit (Upper Peak Hold)
122 Average value circuit (Averaging)
123 Bottom Peak Hold Circuit (Bottom Peak Hold)
124 Maximum frequency circuit 125 Mean frequency circuit 126 Minimum frequency circuit 127 Frequency counter 128 DSP (Digital Signal Processor)
131 Second frequency divider (Div2)
132 Second phase frequency detector (PFD2)
132 Second loop filter (LP2)
133 Second charge pump (CP2)
134 Second loop filter (LF2)
135 Second voltage controlled oscillator (VCO2)

Claims (3)

A first PLL circuit for generating an FMCW signal from a reference signal having a predetermined reference frequency;
A frequency detector that generates frequency measurement data from a first signal obtained by down-converting the FMCW signal and feeds it back to the first PLL circuit;
A second PLL circuit that generates a second signal having a frequency higher than the reference frequency from a reference signal having a predetermined reference frequency,
The first PLL circuit calibrates the FMCW signal based on the fed back signal, and down-converts the FMCW signal with the second signal to generate the first signal. And a correction unit that corrects the reference frequency of the reference signal based on the fed back signal . 2. The FMCW signal generator according to claim 1, wherein the first PLL circuit includes a frequency divider that converts the FMCW signal into a third signal having a frequency lower than the frequency of the FMCW signal. . It said frequency detector to claim 1 or 2, characterized in that generating said frequency measurement data from the first signal down-converted output signal and the FMCW signal of the loop filter included in the first PLL circuit The FMCW signal generator as described.

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