JP5693763B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP5693763B2
JP5693763B2 JP2014030594A JP2014030594A JP5693763B2 JP 5693763 B2 JP5693763 B2 JP 5693763B2 JP 2014030594 A JP2014030594 A JP 2014030594A JP 2014030594 A JP2014030594 A JP 2014030594A JP 5693763 B2 JP5693763 B2 JP 5693763B2
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electrode
insulating member
forming
electrode pad
semiconductor chip
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JP2014116640A (en
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健太 内山
健太 内山
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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    • H—ELECTRICITY
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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

本発明は、半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof.

図１は、従来の電子装置の断面図である。   FIG. 1 is a cross-sectional view of a conventional electronic device.

図１を参照するに、従来の電子装置２００は、半導体装置２０１，２０２と、内部接続端子２０３とを有する。半導体装置２０１は、配線基板２１１と、電子部品２１２と、アンダーフィル樹脂２１３と、外部接続端子２１４とを有する。   Referring to FIG. 1, a conventional electronic device 200 includes semiconductor devices 201 and 202 and an internal connection terminal 203. The semiconductor device 201 includes a wiring board 211, an electronic component 212, an underfill resin 213, and an external connection terminal 214.

配線基板２１１は、板状とされた多層配線構造体である。配線基板２１１は、積層された絶縁層２１６，２１７と、配線パターン２１９，２２８，２２９と、パッド２２１と、ソルダーレジスト層２２２，２２６と、外部接続用パッド２２３，２２４とを有する。絶縁層２１６は、絶縁層２１７の上面２１７Ａに設けられている。   The wiring board 211 is a multilayer wiring structure having a plate shape. The wiring board 211 includes laminated insulating layers 216, 217, wiring patterns 219, 228, 229, pads 221, solder resist layers 222, 226, and external connection pads 223, 224. The insulating layer 216 is provided on the upper surface 217A of the insulating layer 217.

配線パターン２１９及びパッド２２１は、絶縁層２１６の上面２１６Ａに設けられている。配線パターン２１９は、ソルダーレジスト層２２２から露出されたパッド部２３２，２３３を有する。パッド２２１は、ソルダーレジスト層２２２から露出されている。   The wiring pattern 219 and the pad 221 are provided on the upper surface 216A of the insulating layer 216. The wiring pattern 219 has pad portions 232 and 233 exposed from the solder resist layer 222. The pad 221 is exposed from the solder resist layer 222.

ソルダーレジスト層２２２は、絶縁層２１６の上面２１６Ａに設けられている。外部接続用パッド２２３，２２４は、絶縁層２１７の下面２１７Ｂに設けられている。外部接続用パッド２２３，２２４の下面は、ソルダーレジスト層２２６から露出されている。   The solder resist layer 222 is provided on the upper surface 216A of the insulating layer 216. The external connection pads 223 and 224 are provided on the lower surface 217B of the insulating layer 217. The lower surfaces of the external connection pads 223 and 224 are exposed from the solder resist layer 226.

ソルダーレジスト層２２６は、絶縁層２１７の下面２１７Ｂに設けられている。配線パターン２２８，２２９は、積層された絶縁層２１６，２１７に内設されている。配線パターン２２８は、パッド部２３３及び外部接続用パッド２２３と接続されている。配線パターン２２９は、パッド２２１及び外部接続用パッド２２４と接続されている。   The solder resist layer 226 is provided on the lower surface 217B of the insulating layer 217. The wiring patterns 228 and 229 are provided in the laminated insulating layers 216 and 217. The wiring pattern 228 is connected to the pad portion 233 and the external connection pad 223. The wiring pattern 229 is connected to the pad 221 and the external connection pad 224.

電子部品２１２は、半導体装置２０１と半導体装置２０２との間に配置されている。電子部品２１２は、電極パッド２３６を有する。電極パッド２３６は、バンプ２３７（例えば、はんだバンプ）を介して、パッド部２３２と電気的に接続されている。   The electronic component 212 is disposed between the semiconductor device 201 and the semiconductor device 202. The electronic component 212 has an electrode pad 236. The electrode pad 236 is electrically connected to the pad portion 232 through bumps 237 (for example, solder bumps).

アンダーフィル樹脂２１３は、電子部品２１２と配線基板２１１との隙間を充填するように設けられている。外部接続端子２１４は、外部接続用パッド２２３，２２４の下面に設けられている。   The underfill resin 213 is provided so as to fill a gap between the electronic component 212 and the wiring board 211. The external connection terminal 214 is provided on the lower surface of the external connection pads 223 and 224.

半導体装置２０２は、半導体装置２０１の上方に配置されている。半導体装置２０２は、配線基板２４１と、電子部品２４３と、モールド樹脂２４６とを有する。配線基板２４１は、板状とされており、パッド２５１，２５２，２５４を有する。パッド２５１は、パッド部２３３と対向すると共に、内部接続端子２０３を介して、パッド部２３３と電気的に接続されている。パッド２５２は、パッド２２１と対向すると共に、内部接続端子２０３を介して、パッド２２１と電気的に接続されている。パッド２５４は、パッド２５１又はパッド２５２と電気的に接続されている。   The semiconductor device 202 is disposed above the semiconductor device 201. The semiconductor device 202 includes a wiring board 241, an electronic component 243, and a mold resin 246. The wiring board 241 has a plate shape and includes pads 251, 252 and 254. The pad 251 faces the pad portion 233 and is electrically connected to the pad portion 233 via the internal connection terminal 203. The pad 252 faces the pad 221 and is electrically connected to the pad 221 via the internal connection terminal 203. The pad 254 is electrically connected to the pad 251 or the pad 252.

電子部品２４３は、配線基板２４１上に接着されると共に、金属ワイヤ２４４を介して、パッド２５４と電気的に接続されている。モールド樹脂２４６は、配線基板２４１上に設けられている。モールド樹脂２４６は、金属ワイヤ２４４及び電子部品２４３を封止している。   The electronic component 243 is bonded onto the wiring board 241 and is electrically connected to the pad 254 via the metal wire 244. The mold resin 246 is provided on the wiring board 241. The mold resin 246 seals the metal wire 244 and the electronic component 243.

内部接続端子２０３は、電子部品２１２と半導体装置２０２とが接触しないような大きさ（高さ）とされている。内部接続端子２０３の高さは、例えば、２００μｍとすることができる（例えば、特許文献１参照。）。   The internal connection terminal 203 is sized (height) so that the electronic component 212 and the semiconductor device 202 do not contact each other. The height of the internal connection terminal 203 can be set to 200 μm, for example (see, for example, Patent Document 1).

特開平６−１３５４１号公報JP-A-6-13541

しかしながら、従来の半導体装置２０１では、バンプ２３７を介して、配線基板２１１の上面側に配置された電子部品２１２と配線基板２１１（多層配線構造体）とを電気的に接続させていたため、半導体装置２０１の高さ方向のサイズが大型化してしまうという問題があった。   However, in the conventional semiconductor device 201, the electronic component 212 and the wiring substrate 211 (multilayer wiring structure) arranged on the upper surface side of the wiring substrate 211 are electrically connected via the bumps 237. There existed a problem that the size of the height direction of 201 will become large.

また、バンプ２３７を介して、電子部品２１２と配線基板２１１とを電気的に接続させる場合、隣り合うバンプ２３７が接触しないようにバンプ２３７を配置する必要があるため、バンプ２３７の配設ピッチを小さくすることが困難であり、バンプ２３７と接続される配線パターン２１９を微細かつ高密度に配置することができないという問題があった。   In addition, when the electronic component 212 and the wiring board 211 are electrically connected via the bump 237, it is necessary to arrange the bump 237 so that adjacent bumps 237 do not come into contact with each other. There is a problem that it is difficult to reduce the size, and the wiring pattern 219 connected to the bump 237 cannot be finely and densely arranged.

さらに、従来の電子装置２００では、半導体装置２０１と半導体装置２０２とを電気的に接続する内部接続端子２０３の高さを、電子部品２１２の高さとバンプ２３７の高さとを加算した値よりも大きくする必要があるため、電子装置２００の厚さ方向のサイズが大型化してしまうという問題があった。   Further, in the conventional electronic device 200, the height of the internal connection terminal 203 that electrically connects the semiconductor device 201 and the semiconductor device 202 is greater than the value obtained by adding the height of the electronic component 212 and the height of the bump 237. Therefore, there is a problem that the size of the electronic device 200 in the thickness direction is increased.

なお、半導体装置２０１及び電子装置２００の厚さ方向のサイズが大型化してしまうという問題は、電子部品２１２と配線基板２１１とをワイヤボンディング接続した場合にも発生する。   The problem that the size in the thickness direction of the semiconductor device 201 and the electronic device 200 increases also occurs when the electronic component 212 and the wiring substrate 211 are connected by wire bonding.

そこで本発明は、上述した問題点に鑑みなされたものであり、電子部品の電極パッドと接続される配線パターンを微細かつ高密度に配置することができると共に、厚さ方向のサイズの小型化を図ることのできる半導体装置及びその製造方法を提供することを目的とする。   Therefore, the present invention has been made in view of the above-described problems, and wiring patterns connected to electrode pads of electronic components can be finely and densely arranged, and the size in the thickness direction can be reduced. It is an object of the present invention to provide a semiconductor device that can be achieved and a manufacturing method thereof.

本発明の一観点によれば、電極パッドが設けられた電極パッド形成面、及び該電極パッド形成面の反対側に位置する背面を有する半導体チップと、前記電極パッド形成面を露出する第１の面、及び前記背面を露出する第２の面を有すると共に、前記第１の面から前記第２の面にかけて貫通し、前記半導体チップが収納された貫通部を有する絶縁部材と、前記半導体チップの側面を封止するよう前記貫通部内に設けられた封止樹脂と、前記絶縁部材の第１の面上及び前記電極パッド形成面上に積層された複数の絶縁層と配線パターンを有する多層配線構造体と、前記絶縁部材を前記第１の面から前記第２の面にかけて貫通する貫通電極と、を有し、複数の前記絶縁層は、前記第１の面及び前記電極パッド形成面を直接被覆する第１絶縁層を含み、複数の前記配線パターンは、前記第１絶縁層の前記半導体チップと反対側の面上に設けられた配線と、前記第１絶縁層内に設けられたビアとが一体に形成された第１配線パターンを含み、前記第１配線パターンの前記ビアが、前記電極パッド及び前記貫通電極と直接接続され、前記絶縁部材の前記第１の面と、前記貫通電極の前記第１の面側の端面と、前記電極パッドの接続面とが面一であり、前記半導体チップの前記電極パッド形成面と前記封止樹脂の前記第１の面側の端面とが面一である半導体装置が提供される。 According to one aspect of the present invention, a semiconductor chip having an electrode pad forming surface provided with an electrode pad and a back surface located on the opposite side of the electrode pad forming surface, and a first that exposes the electrode pad forming surface. An insulating member having a surface and a second surface exposing the back surface, penetrating from the first surface to the second surface, and having a penetrating portion storing the semiconductor chip; and A multilayer wiring structure having a sealing resin provided in the penetrating portion so as to seal a side surface, a plurality of insulating layers and a wiring pattern laminated on the first surface of the insulating member and the electrode pad forming surface And a through electrode penetrating the insulating member from the first surface to the second surface, and the plurality of insulating layers directly cover the first surface and the electrode pad forming surface Including a first insulating layer The plurality of wiring patterns include a first wiring in which a wiring provided on a surface of the first insulating layer opposite to the semiconductor chip and a via provided in the first insulating layer are integrally formed. The via of the first wiring pattern is directly connected to the electrode pad and the through electrode, the first surface of the insulating member, and the end surface of the through electrode on the first surface side a connection surface of the electrode pad is flush, the semiconductor chip of the electrode pad forming surface and the end surface of the first surface of the sealing resin and is flush der Ru semiconductor device is provided .

本発明によれば、電子部品の電極パッドと接続される配線パターンを微細かつ高密度に配置できると共に、半導体装置の厚さ方向のサイズの小型化を図ることができる。   According to the present invention, the wiring pattern connected to the electrode pad of the electronic component can be finely and densely arranged, and the size of the semiconductor device in the thickness direction can be reduced.

従来の電子装置の断面図である。It is sectional drawing of the conventional electronic device. 本発明の第１の実施の形態に係る電子装置の断面図である。1 is a cross-sectional view of an electronic device according to a first embodiment of the present invention. 本発明の第１の実施の形態に係る半導体装置の製造工程（その１）を示す図である。It is a figure which shows the manufacturing process (the 1) of the semiconductor device which concerns on the 1st Embodiment of this invention. 本発明の第１の実施の形態に係る半導体装置の製造工程（その２）を示す図である。It is a figure which shows the manufacturing process (the 2) of the semiconductor device which concerns on the 1st Embodiment of this invention. 本発明の第１の実施の形態に係る半導体装置の製造工程（その３）を示す図である。It is a figure which shows the manufacturing process (the 3) of the semiconductor device which concerns on the 1st Embodiment of this invention. 本発明の第１の実施の形態に係る半導体装置の製造工程（その４）を示す図である。It is a figure which shows the manufacturing process (the 4) of the semiconductor device which concerns on the 1st Embodiment of this invention. 本発明の第１の実施の形態に係る半導体装置の製造工程（その５）を示す図である。It is a figure which shows the manufacturing process (the 5) of the semiconductor device which concerns on the 1st Embodiment of this invention. 本発明の第１の実施の形態に係る半導体装置の製造工程（その６）を示す図である。It is a figure which shows the manufacturing process (the 6) of the semiconductor device which concerns on the 1st Embodiment of this invention. 本発明の第１の実施の形態に係る半導体装置の製造工程（その７）を示す図である。It is a figure which shows the manufacturing process (the 7) of the semiconductor device which concerns on the 1st Embodiment of this invention. 本発明の第１の実施の形態に係る半導体装置の製造工程（その８）を示す図である。It is a figure which shows the manufacturing process (the 8) of the semiconductor device which concerns on the 1st Embodiment of this invention. 本発明の第１の実施の形態に係る半導体装置の製造工程（その９）を示す図である。It is a figure which shows the manufacturing process (the 9) of the semiconductor device which concerns on the 1st Embodiment of this invention. 本発明の第１の実施の形態に係る半導体装置の製造工程（その１０）を示す図である。It is a figure which shows the manufacturing process (the 10) of the semiconductor device which concerns on the 1st Embodiment of this invention. 本発明の第１の実施の形態に係る半導体装置の製造工程（その１１）を示す図である。It is a figure which shows the manufacturing process (the 11) of the semiconductor device which concerns on the 1st Embodiment of this invention. 本発明の第１の実施の形態に係る半導体装置の製造工程（その１２）を示す図である。It is a figure which shows the manufacturing process (the 12) of the semiconductor device which concerns on the 1st Embodiment of this invention. 本発明の第２の実施の形態に係る電子装置の断面図である。It is sectional drawing of the electronic device which concerns on the 2nd Embodiment of this invention. 本発明の第２の実施の形態に係る半導体装置の製造工程を示す図（その１）である。It is FIG. (1) which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. 本発明の第２の実施の形態に係る半導体装置の製造工程を示す図（その２）である。It is FIG. (2) which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. 本発明の第２の実施の形態に係る半導体装置の製造工程を示す図（その３）である。It is FIG. (3) which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. 本発明の第２の実施の形態に係る半導体装置の製造工程を示す図（その４）である。It is FIG. (4) which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. 本発明の第２の実施の形態に係る半導体装置の製造工程を示す図（その５）である。It is FIG. (5) which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. 本発明の第２の実施の形態に係る半導体装置の製造工程を示す図（その６）である。It is FIG. (6) which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. 本発明の第２の実施の形態に係る半導体装置の製造工程を示す図（その７）である。It is FIG. (The 7) which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. 本発明の第２の実施の形態に係る半導体装置の製造工程を示す図（その８）である。It is FIG. (8) which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention.

以下、図面に基づいて本発明の実施の形態について説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

（第１の実施の形態）
図２は、本発明の第１の実施の形態に係る電子装置の断面図である。 (First embodiment)
FIG. 2 is a cross-sectional view of the electronic device according to the first embodiment of the present invention.

図２を参照するに、第１の実施の形態の電子装置１０は、半導体装置１１と、他の半導体装置である半導体装置１２と、内部接続端子１３とを有する。   Referring to FIG. 2, the electronic device 10 according to the first embodiment includes a semiconductor device 11, a semiconductor device 12 that is another semiconductor device, and an internal connection terminal 13.

半導体装置１１は、多層配線構造体１５と、電子部品１７，１８と、絶縁部材１９と、貫通電極２１〜２３と、外部接続端子２４を有する。   The semiconductor device 11 includes a multilayer wiring structure 15, electronic components 17 and 18, an insulating member 19, through electrodes 21 to 23, and external connection terminals 24.

多層配線構造体１５は、絶縁部材１９の下面１９Ｂ（第１の面）、電子部品１７，１８の後述する電極パッド形成面１７Ｂ，１８Ｂ、薄板化された電子部品１７，１８に設けられた後述する電極パッド６２，６３，６５，６６を覆うように設けられている。   The multilayer wiring structure 15 includes a lower surface 19B (first surface) of the insulating member 19, electrode pad forming surfaces 17B and 18B described later of the electronic components 17 and 18, and a later-described electronic component 17 and 18 provided on the thinned electronic components 17 and 18. The electrode pads 62, 63, 65 and 66 are provided so as to cover them.

多層配線構造体１５は、積層体２７と、外部接続用パッド３１−１，３１−２，３１−３，３１−４と、配線パターン３３〜３６と、ソルダーレジスト層３８とを有する。   The multilayer wiring structure 15 includes a laminated body 27, external connection pads 31-1, 31-2, 31-3 and 31-4, wiring patterns 33 to 36, and a solder resist layer 38.

積層体２７は、複数の絶縁層４１，４２が積層された構成とされている。絶縁層４１は、電子部品１７，１８に設けられた電極パッド６２，６３，６５，６６と、電子部品１７の電極パッド形成面１７Ｂ（電極パッド６２，６３が設けられた側の面）、電子部品１８の電極パッド形成面１８Ｂ（電極パッド６５，６６が設けられた側の面）、及び絶縁部材１９の下面１９Ｂに設けられている。絶縁層４１としては、例えば、絶縁樹脂層（例えば、エポキシ樹脂層）を用いることができる。絶縁層４１の厚さは、例えば、５〜３０μｍとすることができる。   The stacked body 27 has a configuration in which a plurality of insulating layers 41 and 42 are stacked. The insulating layer 41 includes electrode pads 62, 63, 65, and 66 provided on the electronic components 17 and 18, an electrode pad forming surface 17B of the electronic component 17 (a surface on the side where the electrode pads 62 and 63 are provided), electronic The component 18 is provided on the electrode pad forming surface 18 </ b> B (the surface on which the electrode pads 65 and 66 are provided) and the lower surface 19 </ b> B of the insulating member 19. As the insulating layer 41, for example, an insulating resin layer (for example, an epoxy resin layer) can be used. The thickness of the insulating layer 41 can be 5-30 micrometers, for example.

絶縁層４２は、絶縁層４１の下面４１Ｂに設けられている。絶縁層４２としては、例えば、絶縁樹脂層（例えば、エポキシ樹脂層）を用いることができる。絶縁層４２の厚さは、例えば、５〜３０μｍとすることができる。   The insulating layer 42 is provided on the lower surface 41 </ b> B of the insulating layer 41. As the insulating layer 42, for example, an insulating resin layer (for example, an epoxy resin layer) can be used. The thickness of the insulating layer 42 can be 5-30 micrometers, for example.

外部接続用パッド３１−１，３１−２，３１−３，３１−４は、絶縁層４２の下面４２Ｂに設けられている。外部接続用パッド３１−１は、外部接続端子２４が配設される接続面３１−１Ａを有する。外部接続用パッド３１−１は、配線パターン３３と接続されている。外部接続用パッド３１−１は、配線パターン３３を介して、電子部品１７，１８と電気的に接続されている。   The external connection pads 31-1, 31-2, 31-3, 31-4 are provided on the lower surface 42B of the insulating layer 42. The external connection pad 31-1 has a connection surface 31-1A on which the external connection terminal 24 is disposed. The external connection pad 31-1 is connected to the wiring pattern 33. The external connection pad 31-1 is electrically connected to the electronic components 17 and 18 via the wiring pattern 33.

外部接続用パッド３１−２は、外部接続端子２４が配設される接続面３１−２Ａを有する。外部接続用パッド３１−２は、配線パターン３４と接続されている。外部接続用パッド３１−２は、配線パターン３４を介して、半導体装置１２及び電子部品１７と電気的に接続されている。   The external connection pad 31-2 has a connection surface 31-2A on which the external connection terminals 24 are disposed. The external connection pad 31-2 is connected to the wiring pattern. The external connection pad 31-2 is electrically connected to the semiconductor device 12 and the electronic component 17 through the wiring pattern.

外部接続用パッド３１−３は、外部接続端子２４が配設される接続面３１−３Ａを有する。外部接続用パッド３１−３は、配線パターン３５と接続されている。外部接続用パッド３１−３は、配線パターン３５を介して、半導体装置１２及び電子部品１８と電気的に接続されている。   The external connection pad 31-3 has a connection surface 31-3A on which the external connection terminals 24 are disposed. The external connection pad 31-3 is connected to the wiring pattern 35. The external connection pad 31-3 is electrically connected to the semiconductor device 12 and the electronic component 18 through the wiring pattern 35.

外部接続用パッド３１−４は、外部接続端子２４が配設される接続面３１−４Ａを有する。外部接続用パッド３１−４は、配線パターン３６と接続されている。外部接続用パッド３１−４は、配線パターン３６を介して、半導体装置１２と電気的に接続されている。   The external connection pad 31-4 has a connection surface 31-4A on which the external connection terminals 24 are disposed. The external connection pad 31-4 is connected to the wiring pattern 36. The external connection pad 31-4 is electrically connected to the semiconductor device 12 through the wiring pattern 36.

上記構成とされた外部接続用パッド３１−１，３１−２，３１−３，３１−４の材料としては、例えば、Ｃｕを用いることができる。   As the material of the external connection pads 31-1, 31-2, 31-3, 31-4 having the above-described configuration, for example, Cu can be used.

配線パターン３３〜３６は、積層体２７を貫通するように、積層体２７に内設されている。配線パターン３３は、第１の接続部であるビア４５，４６と、ビア４８と、配線４７とを有する。ビア４５は、電子部品１７に設けられた電極パッド６２と対向する部分の絶縁層４１を貫通するように設けられている。つまり、ビア４５は、電子部品１７の配設領域に対応する部分の絶縁層４１から露出されている。ビア４５の上端は、電極パッド６２と直接接続されている。これにより、ビア４５は、電子部品１７と電気的に接続されている。   The wiring patterns 33 to 36 are provided in the stacked body 27 so as to penetrate the stacked body 27. The wiring pattern 33 includes vias 45 and 46 that are first connection portions, a via 48, and a wiring 47. The via 45 is provided so as to penetrate the insulating layer 41 at a portion facing the electrode pad 62 provided in the electronic component 17. That is, the via 45 is exposed from a portion of the insulating layer 41 corresponding to the arrangement region of the electronic component 17. The upper end of the via 45 is directly connected to the electrode pad 62. As a result, the via 45 is electrically connected to the electronic component 17.

ビア４６は、電子部品１８の電極パッド６５と対向する部分の絶縁層４１を貫通するように設けられている。つまり、ビア４６は、電子部品１８の配設領域に対応する部分の絶縁層４１から露出されている。ビア４６の上端は、電極パッド６５と直接接続されている。これにより、ビア４６は、電子部品１８と電気的に接続されている。   The via 46 is provided so as to penetrate the insulating layer 41 at a portion facing the electrode pad 65 of the electronic component 18. That is, the via 46 is exposed from a portion of the insulating layer 41 corresponding to the arrangement region of the electronic component 18. The upper end of the via 46 is directly connected to the electrode pad 65. As a result, the via 46 is electrically connected to the electronic component 18.

配線４７は、絶縁層４１の下面４１Ｂ及びビア４５，４６の下端面に設けられている。配線４７は、ビア４５，４６の下端と接続されている。配線４７は、ビア４５，４６を介して、電子部品１７，１８と電気的に接続されている。   The wiring 47 is provided on the lower surface 41 B of the insulating layer 41 and the lower end surfaces of the vias 45 and 46. The wiring 47 is connected to the lower ends of the vias 45 and 46. The wiring 47 is electrically connected to the electronic components 17 and 18 via the vias 45 and 46.

ビア４８は、配線４７と外部接続用パッド３１−１との間に位置する部分の絶縁層４２を貫通するように設けられている。ビア４８の上端は、配線４７と接続されている。ビア４８の下端は、外部接続用パッド３１−１と接続されている。これにより、ビア４８は、配線４７と外部接続用パッド３１−１とを電気的に接続している。上記構成とされた配線パターン３３の材料としては、例えば、Ｃｕを用いることができる。   The via 48 is provided so as to penetrate a portion of the insulating layer 42 located between the wiring 47 and the external connection pad 31-1. The upper end of the via 48 is connected to the wiring 47. The lower end of the via 48 is connected to the external connection pad 31-1. Thus, the via 48 electrically connects the wiring 47 and the external connection pad 31-1. For example, Cu can be used as the material of the wiring pattern 33 configured as described above.

配線パターン３４は、第１の接続部であるビア５１と、第２の接続部であるビア５２と、ビア５４と、配線５３とを有する。ビア５１は、電子部品１７の電極パッド６３と対向する部分の絶縁層４１を貫通するように設けられている。つまり、ビア５１は、電子部品１７の配設領域に対応する部分の絶縁層４１から露出されている。ビア５１の上端は、電極パッド６３と直接接続されている。これにより、ビア５１は、電子部品１７と電気的に接続されている。   The wiring pattern 34 includes a via 51 that is a first connection portion, a via 52 that is a second connection portion, a via 54, and a wiring 53. The via 51 is provided so as to penetrate the insulating layer 41 at a portion facing the electrode pad 63 of the electronic component 17. That is, the via 51 is exposed from a portion of the insulating layer 41 corresponding to the arrangement region of the electronic component 17. The upper end of the via 51 is directly connected to the electrode pad 63. Thereby, the via 51 is electrically connected to the electronic component 17.

ビア５２は、貫通電極２１の下方に位置する部分の絶縁層４１を貫通するように設けられている。つまり、ビア５２は、電子部品１７の配設領域の外側に位置する部分の絶縁層４１から露出されている。ビア５２の上端は、貫通電極２１の下端と直接接続されている。これにより、ビア５２は、貫通電極２１と電気的に接続されている。   The via 52 is provided so as to penetrate a portion of the insulating layer 41 located below the through electrode 21. That is, the via 52 is exposed from a portion of the insulating layer 41 located outside the region where the electronic component 17 is disposed. The upper end of the via 52 is directly connected to the lower end of the through electrode 21. Thereby, the via 52 is electrically connected to the through electrode 21.

配線５３は、絶縁層４１の下面４１Ｂ及びビア５１，５２の下端面に設けられている。配線５３は、ビア５１，５２の下端と接続されている。これにより、配線５３は、ビア５１，５２を介して、電子部品１７及び半導体装置１２と電気的に接続されている。   The wiring 53 is provided on the lower surface 41 B of the insulating layer 41 and the lower end surfaces of the vias 51 and 52. The wiring 53 is connected to the lower ends of the vias 51 and 52. Accordingly, the wiring 53 is electrically connected to the electronic component 17 and the semiconductor device 12 through the vias 51 and 52.

ビア５４は、配線５３と外部接続用パッド３１−２との間に位置する部分の絶縁層４２を貫通するように設けられている。ビア５４の上端は、配線５３と接続されており、ビア５４の下端は、外部接続用パッド３１−２と接続されている。これにより、ビア５４は、配線５３と外部接続用パッド３１−２とを電気的に接続している。上記構成とされた配線パターン３４の材料としては、例えば、Ｃｕを用いることができる。   The via 54 is provided so as to penetrate the portion of the insulating layer 42 located between the wiring 53 and the external connection pad 31-2. The upper end of the via 54 is connected to the wiring 53, and the lower end of the via 54 is connected to the external connection pad 31-2. Thereby, the via 54 electrically connects the wiring 53 and the external connection pad 31-2. For example, Cu can be used as the material of the wiring pattern 34 configured as described above.

配線パターン３５は、第１の接続部であるビア５６と、第２の接続部であるビア５７と、配線５８と、ビア５９とを有する。ビア５６は、電子部品１８の電極パッド６６と対向する部分の絶縁層４１を貫通するように設けられている。つまり、ビア５６は、電子部品１８の配設領域に対応する部分の絶縁層４１から露出されている。ビア５６の上端は、電極パッド６６と直接接続されている。これにより、ビア５６は、電子部品１８と電気的に接続されている。   The wiring pattern 35 includes a via 56 that is a first connection portion, a via 57 that is a second connection portion, a wiring 58, and a via 59. The via 56 is provided so as to penetrate the insulating layer 41 at a portion facing the electrode pad 66 of the electronic component 18. That is, the via 56 is exposed from a portion of the insulating layer 41 corresponding to the arrangement region of the electronic component 18. The upper end of the via 56 is directly connected to the electrode pad 66. Thereby, the via 56 is electrically connected to the electronic component 18.

ビア５７は、貫通電極２２の下方に位置する部分の絶縁層４１を貫通するように設けられている。ビア５７の上端は、貫通電極２２の下端と直接接続されている。これにより、ビア５７は、貫通電極２２と電気的に接続されている。   The via 57 is provided so as to penetrate the portion of the insulating layer 41 located below the through electrode 22. The upper end of the via 57 is directly connected to the lower end of the through electrode 22. Thereby, the via 57 is electrically connected to the through electrode 22.

配線５８は、絶縁層４１の下面４１Ｂ及びビア５６，５７の下端面に設けられている。配線５８は、ビア５６，５７の下端と接続されている。これにより、配線５８は、ビア５６，５７を介して、電子部品１８及び半導体装置１２と電気的に接続されている。   The wiring 58 is provided on the lower surface 41 B of the insulating layer 41 and the lower end surfaces of the vias 56 and 57. The wiring 58 is connected to the lower ends of the vias 56 and 57. As a result, the wiring 58 is electrically connected to the electronic component 18 and the semiconductor device 12 via the vias 56 and 57.

ビア５９は、配線５８と外部接続用パッド３１−３との間に位置する部分の絶縁層４２を貫通するように設けられている。ビア５９の上端は、配線５８と接続されており、ビア５９の下端は、外部接続用パッド３１−３と接続されている。これにより、ビア５９は、配線５８と外部接続用パッド３１−３とを電気的に接続している。上記構成とされた配線パターン３５の材料としては、例えば、Ｃｕを用いることができる。   The via 59 is provided so as to penetrate a portion of the insulating layer 42 located between the wiring 58 and the external connection pad 31-3. The upper end of the via 59 is connected to the wiring 58, and the lower end of the via 59 is connected to the external connection pad 31-3. Thereby, the via 59 electrically connects the wiring 58 and the external connection pad 31-3. As a material of the wiring pattern 35 having the above-described configuration, for example, Cu can be used.

配線パターン３６は、第２の接続部であるビア６１と、ビア６３と、配線６２とを有する。ビア６１は、貫通電極２３と対向する部分の絶縁層４１を貫通するように設けられている。つまり、ビア６１は、電子部品１８の配設領域の外側に位置する部分の絶縁層４１から露出されている。ビア６１の上端は、貫通電極２３の下端と直接接続されている。これにより、ビア６１は、貫通電極２３と電気的に接続されている。   The wiring pattern 36 includes a via 61, a via 63, and a wiring 62 that are second connection portions. The via 61 is provided so as to penetrate the insulating layer 41 at a portion facing the through electrode 23. That is, the via 61 is exposed from a portion of the insulating layer 41 located outside the area where the electronic component 18 is disposed. The upper end of the via 61 is directly connected to the lower end of the through electrode 23. As a result, the via 61 is electrically connected to the through electrode 23.

配線６２は、絶縁層４１の下面４１Ｂ及びビア６１の下端面に設けられている。配線６２は、ビア６１の下端と接続されている。これにより、配線６２は、ビア６１を介して、貫通電極２３と電気的に接続されている。   The wiring 62 is provided on the lower surface 41 </ b> B of the insulating layer 41 and the lower end surface of the via 61. The wiring 62 is connected to the lower end of the via 61. As a result, the wiring 62 is electrically connected to the through electrode 23 via the via 61.

ビア６３は、配線６２と外部接続用パッド３１−４との間に位置する部分の絶縁層４２を貫通するように設けられている。ビア６３の上端は、配線６２と接続されており、ビア６３の下端は、外部接続用パッド３１−４と接続されている。これにより、ビア６３は、配線６２と外部接続用パッド３１−４とを電気的に接続している。上記構成とされた配線パターン３６の材料としては、例えば、Ｃｕを用いることができる。   The via 63 is provided so as to penetrate the insulating layer 42 in a portion located between the wiring 62 and the external connection pad 31-4. The upper end of the via 63 is connected to the wiring 62, and the lower end of the via 63 is connected to the external connection pad 31-4. Thereby, the via 63 electrically connects the wiring 62 and the external connection pad 31-4. As a material of the wiring pattern 36 having the above-described configuration, for example, Cu can be used.

ソルダーレジスト層３８は、絶縁層４２の下面４２Ｂに設けられている。ソルダーレジスト層３８は、接続面３１−１Ａを露出する開口部３８Ａと、接続面３１−２Ａを露出する開口部３８Ｂと、接続面３１−３Ａを露出する開口部３８Ｃと、接続面３１−４Ａを露出する開口部３８Ｄとを有する。   The solder resist layer 38 is provided on the lower surface 42B of the insulating layer 42. The solder resist layer 38 includes an opening 38A that exposes the connection surface 31-1A, an opening 38B that exposes the connection surface 31-2A, an opening 38C that exposes the connection surface 31-3A, and a connection surface 31-4A. And an opening 38D for exposing the.

上記構成とされた多層配線構造体１５は、図２や後述する図１３及び図１４において、薄板化された電子部品１７，１８の厚さや絶縁部材１９の厚さよりも薄くなるように図示されている。しかし、実際には、多層配線構造体１５の厚さは、薄板化された電子部品１７，１８の厚さ（例えば、２００〜３００μｍ）や絶縁部材１９の厚さ（例えば、２００〜３００μｍ）よりも薄い。多層配線構造体１５の厚さは、例えば、２０〜８０μｍとすることができる。多層配線構造体１５は、電子部品１７，１８の電極パッド形成面１７Ｂ，１８Ｂや絶縁部材１９の下面１９Ｂに、膜状又は層状に形成されている。   The multilayer wiring structure 15 having the above-described configuration is illustrated in FIG. 2 and FIGS. 13 and 14 described later so as to be thinner than the thickness of the thinned electronic components 17 and 18 and the thickness of the insulating member 19. Yes. However, actually, the thickness of the multilayer wiring structure 15 is based on the thickness of the thinned electronic components 17 and 18 (for example, 200 to 300 μm) and the thickness of the insulating member 19 (for example, 200 to 300 μm). Is also thin. The thickness of the multilayer wiring structure 15 can be set to 20 to 80 μm, for example. The multilayer wiring structure 15 is formed in a film shape or a layer shape on the electrode pad forming surfaces 17B, 18B of the electronic components 17, 18 and the lower surface 19B of the insulating member 19.

電子部品１７は、薄板化された電子部品であり、背面１７Ａと、背面１７Ａの反対側に位置する電極パッド形成面１７Ｂと、複数の電極パッド６２，６３を有する。電子部品１７は、電子部品１７の電極パッド形成面１７Ｂと絶縁層４１の上面４１Ａ（積層体２７の上面）とが接触するように、絶縁層４１の上面４１Ａに配設されている。電極パッド６２，６３は、電子部品１７の電極パッド形成面１７Ｂに設けられている。電極パッド６２，６３は、電子部品１７の電極パッド形成面１７Ｂから突出している。電極パッド６２，６３は、絶縁層４１により覆われている。   The electronic component 17 is a thinned electronic component, and includes a back surface 17A, an electrode pad forming surface 17B located on the opposite side of the back surface 17A, and a plurality of electrode pads 62 and 63. The electronic component 17 is disposed on the upper surface 41A of the insulating layer 41 so that the electrode pad forming surface 17B of the electronic component 17 and the upper surface 41A of the insulating layer 41 (the upper surface of the multilayer body 27) are in contact with each other. The electrode pads 62 and 63 are provided on the electrode pad forming surface 17 </ b> B of the electronic component 17. The electrode pads 62 and 63 protrude from the electrode pad forming surface 17B of the electronic component 17. The electrode pads 62 and 63 are covered with the insulating layer 41.

電極パッド６２は、接続面６２Ａを有する。接続面６２Ａは、配線パターン３３の構成要素のうちの１つであるビア４５の上端と直接接続されている。電極パッド６３は、接続面６３Ａを有する。接続面６３Ａは、配線パターン３４の構成要素のうちの１つであるビア５１の上端と直接接続されている。つまり、電極パッド６２，６３と配線パターン３３，３４とが直接接続されることで、電子部品１７と多層配線構造体１５とが電気的に接続されている。絶縁層４１上に配置された部分の電子部品１７の厚さは、例えば、２００〜３００μｍとすることができる。   The electrode pad 62 has a connection surface 62A. The connection surface 62A is directly connected to the upper end of the via 45, which is one of the components of the wiring pattern 33. The electrode pad 63 has a connection surface 63A. The connection surface 63A is directly connected to the upper end of the via 51, which is one of the components of the wiring pattern 34. That is, the electronic component 17 and the multilayer wiring structure 15 are electrically connected by directly connecting the electrode pads 62 and 63 and the wiring patterns 33 and 34. The thickness of the electronic component 17 in the portion disposed on the insulating layer 41 can be set to 200 to 300 μm, for example.

電子部品１８は、薄板化された電子部品であり、背面１８Ａと、背面１８Ａの反対側に位置する電極パッド形成面１８Ｂと、複数の電極パッド６５，６６を有する。電子部品１８は、電子部品１８の電極パッド形成面１８Ｂと絶縁層４１の上面４１Ａとが接触するように、絶縁層４１上に配設されている。電極パッド６５，６６は、電子部品１８の電極パッド形成面１８Ｂに設けられている。電極パッド６５，６６は、電子部品１８の電極パッド形成面１８Ｂから突出している。電極パッド６５，６６は、絶縁層４１により覆われている。   The electronic component 18 is a thinned electronic component, and includes a back surface 18A, an electrode pad forming surface 18B located on the opposite side of the back surface 18A, and a plurality of electrode pads 65 and 66. The electronic component 18 is disposed on the insulating layer 41 so that the electrode pad forming surface 18B of the electronic component 18 and the upper surface 41A of the insulating layer 41 are in contact with each other. The electrode pads 65 and 66 are provided on the electrode pad forming surface 18 </ b> B of the electronic component 18. The electrode pads 65 and 66 protrude from the electrode pad forming surface 18B of the electronic component 18. The electrode pads 65 and 66 are covered with the insulating layer 41.

電極パッド６５は、接続面６５Ａを有する。接続面６５Ａは、配線パターン３３の構成要素のうちの１つであるビア４６の上端と直接接続されている。電極パッド６６は、接続面６６Ａを有する。接続面６６Ａは、配線パターン３５の構成要素のうちの１つであるビア５６の上端と直接接続されている。つまり、電極パッド６５，６６と配線パターン３３，３５とが直接接続されることで、電子部品１８と多層配線構造体１５とが電気的に接続される。   The electrode pad 65 has a connection surface 65A. The connection surface 65A is directly connected to the upper end of the via 46, which is one of the components of the wiring pattern 33. The electrode pad 66 has a connection surface 66A. The connection surface 66A is directly connected to the upper end of the via 56, which is one of the components of the wiring pattern 35. That is, the electrode parts 65 and 66 and the wiring patterns 33 and 35 are directly connected, so that the electronic component 18 and the multilayer wiring structure 15 are electrically connected.

絶縁層４１の上面４１Ａに配置された部分の電子部品１８の厚さは、絶縁層４１の上面４１Ａに配置された部分の電子部品１７の厚さと略等しい。絶縁層４１の上面４１Ａに配置された部分の電子部品１８の厚さは、例えば、２００〜３００μｍとすることができる。   The thickness of the portion of the electronic component 18 disposed on the upper surface 41A of the insulating layer 41 is substantially equal to the thickness of the portion of the electronic component 17 disposed on the upper surface 41A of the insulating layer 41. The thickness of the part of the electronic component 18 disposed on the upper surface 41A of the insulating layer 41 can be set to 200 to 300 μm, for example.

このように、絶縁層４１の上面４１Ａと電子部品１７，１８の電極パッド形成面１７Ｂ，１８Ｂとが接触するように、絶縁層４１の上面４１Ａに電子部品１７，１８を配置し、電子部品１７に設けられた電極パッド６２，６３と配線パターン３３，３４を構成するビア４５，５１とを直接接続させると共に、電子部品１８に設けられた電極パッド６５，６６と配線パターン３３，３５を構成するビア４６，５６とを直接接続させることにより、バンプ或いは金属ワイヤを介して、電子部品と配線パターンとを電気的に接続させた従来の半導体装置と比較して、半導体装置１１の厚さ方向のサイズの小型化を図ることができる。   Thus, the electronic components 17 and 18 are arranged on the upper surface 41A of the insulating layer 41 so that the upper surface 41A of the insulating layer 41 and the electrode pad forming surfaces 17B and 18B of the electronic components 17 and 18 are in contact with each other. The electrode pads 62, 63 provided on the wiring board 33 and the vias 45, 51 constituting the wiring patterns 33, 34 are directly connected, and the electrode pads 65, 66 provided on the electronic component 18 and the wiring patterns 33, 35 are formed. By directly connecting the vias 46 and 56, the thickness of the semiconductor device 11 can be increased as compared with a conventional semiconductor device in which an electronic component and a wiring pattern are electrically connected via bumps or metal wires. The size can be reduced.

また、電子部品１７，１８に設けられた電極パッド６２，６３，６５，６６と配線パターン３３〜３５とを直接接続することにより、電子部品１７，１８と配線パターン３３〜３５とを接続するバンプ（例えば、はんだバンプ）が不要となるため、配線パターン３３〜３５（具体的には、ビア４５，４６，５１，５６及び配線４７，５３，５８）を微細かつ高密度に配置することができる。   Further, the bumps for connecting the electronic components 17 and 18 and the wiring patterns 33 to 35 by directly connecting the electrode pads 62, 63, 65 and 66 provided on the electronic components 17 and 18 and the wiring patterns 33 to 35. Since (for example, solder bumps) are not required, the wiring patterns 33 to 35 (specifically, the vias 45, 46, 51, and 56 and the wirings 47, 53, and 58) can be finely and densely arranged. .

上記説明した電子部品１７，１８としては、例えば、半導体チップを用いることができる。具体的には、電子部品１７，１８としてＣＰＵ（Central Processing Unit）用の半導体チップを用いる場合や、電子部品１７，１８のどちらか一方にＣＰＵ（Central Processing Unit）用の半導体チップを用い、他方にメモリ用の半導体チップを用いる場合や、電子部品１７，１８のどちらか一方にＣＰＵ（Central Processing Unit）用の半導体チップを用い、他方にＧＰＵ（Graphics Processing Unit）用の半導体チップを用いる場合がある。   As the electronic components 17 and 18 described above, for example, a semiconductor chip can be used. Specifically, when a semiconductor chip for CPU (Central Processing Unit) is used as the electronic components 17 and 18, a semiconductor chip for CPU (Central Processing Unit) is used for one of the electronic components 17 and 18, and the other In some cases, a semiconductor chip for memory is used, or a semiconductor chip for CPU (Central Processing Unit) is used for one of the electronic components 17 and 18, and a semiconductor chip for GPU (Graphics Processing Unit) is used for the other. is there.

絶縁部材１９は、電子部品１７，１８の側面を覆うように、絶縁層４１の上面４１Ａに設けられている。これにより、絶縁部材１９は、電子部品１７，１８の周囲（側面部分）を封止している。絶縁部材１９は、絶縁層４１の上面４１Ａに配置された部分の電子部品１７，１８と略等しい厚さとされている。絶縁部材１９の厚さは、例えば、２００〜３００μｍとすることができる。   The insulating member 19 is provided on the upper surface 41A of the insulating layer 41 so as to cover the side surfaces of the electronic components 17 and 18. Thereby, the insulating member 19 seals the periphery (side surface portion) of the electronic components 17 and 18. The insulating member 19 has a thickness substantially equal to that of the electronic components 17 and 18 in the portion disposed on the upper surface 41A of the insulating layer 41. The thickness of the insulating member 19 can be 200-300 micrometers, for example.

絶縁部材１９の上面１９Ａは、電子部品１７，１８の背面１７Ａ，１８Ａと略面一となるように構成されている。これにより、絶縁部材１９の上面１９Ａと電子部品１７，１８の背面１７Ａ，１８Ａとは、同一平面上に配置されている。   The upper surface 19A of the insulating member 19 is configured to be substantially flush with the rear surfaces 17A and 18A of the electronic components 17 and 18. Thereby, the upper surface 19A of the insulating member 19 and the back surfaces 17A and 18A of the electronic components 17 and 18 are arranged on the same plane.

このように、絶縁層４１の上面４１Ａに、電子部品１７，１８の側面を封止すると共に、電子部品１７，１８の背面１７Ａ，１８Ａと略面一とされた上面１９Ａを有する絶縁部材１９を設けることにより、半導体装置１１の厚さ方向のサイズを大型化させることなく、電子部品１７，１８を封止することができる。   Thus, the insulating member 19 having the upper surface 19A that seals the side surfaces of the electronic components 17 and 18 to the upper surface 41A of the insulating layer 41 and is substantially flush with the rear surfaces 17A and 18A of the electronic components 17 and 18 is provided. By providing, the electronic components 17 and 18 can be sealed without increasing the size of the semiconductor device 11 in the thickness direction.

絶縁部材１９は、貫通孔７１〜７３を有する。貫通孔７１は、ビア５２の上端面を露出するように形成されている。貫通孔７２は、ビア５７の上端面を露出するように形成されている。貫通孔７３は、ビア６１の上端面を露出するように形成されている。   The insulating member 19 has through holes 71 to 73. The through hole 71 is formed so as to expose the upper end surface of the via 52. The through hole 72 is formed so as to expose the upper end surface of the via 57. The through hole 73 is formed so as to expose the upper end surface of the via 61.

上記構成とされた絶縁部材１９としては、例えば、モールド樹脂を用いることができる。モールド樹脂の材料としては、例えば、エポキシ樹脂を用いることができる。   As the insulating member 19 having the above configuration, for example, a mold resin can be used. As a material of the mold resin, for example, an epoxy resin can be used.

貫通電極２１は、貫通孔７１に設けられている。貫通電極２１の上端面は、平坦な面とされており、絶縁部材１９の上面１９Ａと同一平面上に配置されている。貫通電極２１の上端は、内部接続端子１３と接続されている。貫通電極２１は、内部接続端子１３を介して、半導体装置１２と電気的に接続されている。貫通電極２１の下端面は、平坦な面とされており、絶縁部材１９の下面１９Ｂと略同一平面上に配置されている。なお、貫通電極２１は、製造時の接着剤１０２の厚さ分だけ、絶縁部材１９の下面１９Ｂから突出する。このため、実際には、貫通電極２１の下端面と絶縁部材１９の下面１９Ｂとは、完全な同一平面上に配置されない。   The through electrode 21 is provided in the through hole 71. The upper end surface of the through electrode 21 is a flat surface and is disposed on the same plane as the upper surface 19 </ b> A of the insulating member 19. The upper end of the through electrode 21 is connected to the internal connection terminal 13. The through electrode 21 is electrically connected to the semiconductor device 12 through the internal connection terminal 13. The lower end surface of the through electrode 21 is a flat surface and is disposed on substantially the same plane as the lower surface 19B of the insulating member 19. The through electrode 21 protrudes from the lower surface 19B of the insulating member 19 by the thickness of the adhesive 102 at the time of manufacture. For this reason, actually, the lower end surface of the through electrode 21 and the lower surface 19B of the insulating member 19 are not arranged on the same same plane.

貫通電極２１の下端は、ビア５２と直接接続されている。これにより、貫通電極２１は、配線パターン３４を介して、外部接続用パッド３１−２と電気的に接続されている。貫通電極２１の材料としては、例えば、Ｃｕを用いることができる。   The lower end of the through electrode 21 is directly connected to the via 52. Thereby, the through electrode 21 is electrically connected to the external connection pad 31-2 through the wiring pattern 34. As a material of the through electrode 21, for example, Cu can be used.

貫通電極２２は、貫通孔７２に設けられている。貫通電極２２の上端面は、平坦な面とされており、絶縁部材１９の上面１９Ａと同一平面上に配置されている。貫通電極２２の上端は、内部接続端子１３と接続されている。貫通電極２２は、内部接続端子１３を介して、半導体装置１２と電気的に接続されている。貫通電極２２の下端面は、平坦な面とされており、絶縁部材１９の下面１９Ｂと略同一平面上に配置されている。なお、貫通電極２２は、製造時の接着剤１０２の厚さ分だけ、絶縁部材１９の下面１９Ｂから突出する。このため、実際には、貫通電極２２の下端面と絶縁部材１９の下面１９Ｂとは、完全な同一平面上に配置されない。   The through electrode 22 is provided in the through hole 72. The upper end surface of the through electrode 22 is a flat surface and is disposed on the same plane as the upper surface 19 </ b> A of the insulating member 19. The upper end of the through electrode 22 is connected to the internal connection terminal 13. The through electrode 22 is electrically connected to the semiconductor device 12 via the internal connection terminal 13. The lower end surface of the through electrode 22 is a flat surface and is disposed on substantially the same plane as the lower surface 19B of the insulating member 19. The through electrode 22 protrudes from the lower surface 19B of the insulating member 19 by the thickness of the adhesive 102 at the time of manufacture. For this reason, the lower end surface of the through electrode 22 and the lower surface 19B of the insulating member 19 are not actually arranged on the same plane.

貫通電極２２の下端は、ビア５７と直接接続されている。これにより、貫通電極２２は、配線パターン３５を介して、外部接続用パッド３１−３と電気的に接続されている。貫通電極２２の材料としては、例えば、Ｃｕを用いることができる。   The lower end of the through electrode 22 is directly connected to the via 57. Thereby, the through electrode 22 is electrically connected to the external connection pad 31-3 through the wiring pattern 35. As a material of the through electrode 22, for example, Cu can be used.

貫通電極２３は、貫通孔７３に設けられている。貫通電極２３の上端面は、平坦な面とされており、絶縁部材１９の上面１９Ａと同一平面上に配置されている。貫通電極２３の上端は、内部接続端子１３と接続されている。貫通電極２３は、内部接続端子１３を介して、半導体装置１２と電気的に接続されている。貫通電極２３の下端面は、平坦な面とされており、絶縁部材１９の下面１９Ｂと略同一平面上に配置されている。なお、貫通電極２３は、製造時の接着剤１０２の厚さ分だけ、絶縁部材１９の下面１９Ｂから突出する。このため、実際には、貫通電極２３の下端面と絶縁部材１９の下面１９Ｂとは、完全な同一平面上に配置されない。   The through electrode 23 is provided in the through hole 73. The upper end surface of the through electrode 23 is a flat surface and is disposed on the same plane as the upper surface 19 </ b> A of the insulating member 19. The upper end of the through electrode 23 is connected to the internal connection terminal 13. The through electrode 23 is electrically connected to the semiconductor device 12 via the internal connection terminal 13. The lower end surface of the through electrode 23 is a flat surface and is disposed on substantially the same plane as the lower surface 19B of the insulating member 19. The through electrode 23 protrudes from the lower surface 19B of the insulating member 19 by the thickness of the adhesive 102 at the time of manufacture. For this reason, the lower end surface of the through electrode 23 and the lower surface 19B of the insulating member 19 are not actually arranged on the same plane.

貫通電極２３の下端は、ビア６１と接続されている。これにより、貫通電極２３は、配線パターン３６を介して、外部接続用パッド３１−４と電気的に接続されている。貫通電極２３の材料としては、例えば、Ｃｕを用いることができる。   The lower end of the through electrode 23 is connected to the via 61. As a result, the through electrode 23 is electrically connected to the external connection pad 31-4 through the wiring pattern 36. As a material of the through electrode 23, for example, Cu can be used.

上記説明したように、貫通電極２１〜２３の上端面は、電子部品１７，１８の背面１７Ａ，１８Ａ及び絶縁部材１９の上面１９Ａと同一平面上に配置されている。   As described above, the upper end surfaces of the through electrodes 21 to 23 are disposed on the same plane as the back surfaces 17A and 18A of the electronic components 17 and 18 and the upper surface 19A of the insulating member 19.

このように、絶縁部材１９を貫通するように内部接続端子１３と接続される貫通電極２１〜２３を設けると共に、貫通電極２１〜２３の上端面、電子部品１７，１８の背面１７Ａ，１８Ａ、及び絶縁部材１９の上面１９Ａを同一平面上に配置することにより、半導体装置１２と対向する半導体装置１１の上面が平坦な面となるため、半導体装置１１と半導体装置１２とを電気的に接続する内部接続端子１３の高さ方向のサイズを小さくすることが可能となるので、電子装置１０の厚さ方向のサイズの小型化を図ることができる。   As described above, the through electrodes 21 to 23 connected to the internal connection terminals 13 so as to penetrate the insulating member 19 are provided, the upper end surfaces of the through electrodes 21 to 23, the back surfaces 17A and 18A of the electronic components 17 and 18, and By disposing the upper surface 19A of the insulating member 19 on the same plane, the upper surface of the semiconductor device 11 facing the semiconductor device 12 becomes a flat surface, so that the internal connection between the semiconductor device 11 and the semiconductor device 12 is electrically connected. Since the size of the connection terminal 13 in the height direction can be reduced, the size of the electronic device 10 in the thickness direction can be reduced.

また、内部接続端子１３の高さ方向のサイズを小さくすることにより、貫通電極２１〜２３を狭ピッチで配置することが可能となるので、半導体装置１１と半導体装置１２との間における電気的接続箇所を増加させることができる（言い換えれば、半導体装置１１，１２間に配置される内部接続端子１３の数を増加させることができる。）。   Moreover, since the through electrodes 21 to 23 can be arranged at a narrow pitch by reducing the size of the internal connection terminal 13 in the height direction, electrical connection between the semiconductor device 11 and the semiconductor device 12 is achieved. The number of locations can be increased (in other words, the number of internal connection terminals 13 arranged between the semiconductor devices 11 and 12 can be increased).

さらに、はんだボール等の内部接続端子１３を小径化が可能となることにより、貫通電極２１〜２３を狭ピッチ化できる。   Furthermore, since the internal connection terminals 13 such as solder balls can be reduced in diameter, the through electrodes 21 to 23 can be narrowed.

なお、内部接続端子１３が接続される側の貫通電極２１〜２３の端面に、保護層（例えば、貫通電極２１〜２３の端面に、Ｎｉめっき層と、Ａｕめっき層とを順次積層させたＮｉ／Ａｕ積層膜）を設けてもよい。   In addition, a protective layer (for example, an Ni plating layer and an Au plating layer are sequentially stacked on the end surfaces of the through electrodes 21 to 23 on the end surfaces of the through electrodes 21 to 23 on the side to which the internal connection terminal 13 is connected. / Au laminated film) may be provided.

外部接続端子２４は、接続面３１−１Ａ，３１−２Ａ，３１−３Ａ，３１−４Ａにそれぞれ設けられている。外部接続端子２４は、電子装置１０をマザーボード等の実装基板（図示せず）に接続する際、実装基板に設けられたパッドと接続される端子である。外部接続端子２４としては、例えば、はんだボールを用いることができる。図２では、外部接続端子２４としてはんだボールを用いた場合を例に挙げて図示したが、はんだボールの代わりにピン端子を外部接続端子２４として用いてもよい。   The external connection terminals 24 are provided on the connection surfaces 31-1A, 31-2A, 31-3A, and 31-4A, respectively. The external connection terminal 24 is a terminal that is connected to a pad provided on the mounting board when the electronic device 10 is connected to a mounting board (not shown) such as a mother board. For example, a solder ball can be used as the external connection terminal 24. In FIG. 2, a case where a solder ball is used as the external connection terminal 24 is illustrated as an example, but a pin terminal may be used as the external connection terminal 24 instead of the solder ball.

本実施の形態の半導体装置によれば、絶縁層４１の上面４１Ａと電子部品１７，１８の電極パッド形成面１７Ｂ，１８Ｂとが接触するように、絶縁層４１の上面４１Ａに電子部品１７，１８を配置し、電子部品１７に設けられた電極パッド６２，６３と配線パターン３３，３４を構成するビア４５，５１とを直接接続させると共に、電子部品１８に設けられた電極パッド６５，６６と配線パターン３３，３５を構成するビア４６，５６とを直接接続させることにより、バンプ或いは金属ワイヤを介して、電子部品と配線パターンとを電気的に接続させた従来の半導体装置と比較して、半導体装置１１の厚さ方向のサイズの小型化を図ることができる。   According to the semiconductor device of the present embodiment, the electronic components 17 and 18 are in contact with the upper surface 41A of the insulating layer 41 so that the upper surface 41A of the insulating layer 41 and the electrode pad forming surfaces 17B and 18B of the electronic components 17 and 18 are in contact with each other. The electrode pads 62 and 63 provided in the electronic component 17 and the vias 45 and 51 constituting the wiring patterns 33 and 34 are directly connected, and the electrode pads 65 and 66 provided in the electronic component 18 and the wiring are connected. Compared to the conventional semiconductor device in which the electronic component and the wiring pattern are electrically connected through bumps or metal wires by directly connecting the vias 46 and 56 constituting the patterns 33 and 35, the semiconductor. The size of the apparatus 11 in the thickness direction can be reduced.

また、電子部品１７，１８に設けられた電極パッド６２，６３，６５，６６と配線パターン３３〜３５とを直接接続することにより、電子部品１７，１８と配線パターン３３〜３５とを接続するバンプ（例えば、はんだバンプ）が不要となるため、配線パターン３３〜３５（具体的には、ビア４５，４６，５１，５６及び配線４７，５３，５８）を微細かつ高密度に配置することができる。   Further, the bumps for connecting the electronic components 17 and 18 and the wiring patterns 33 to 35 by directly connecting the electrode pads 62, 63, 65 and 66 provided on the electronic components 17 and 18 and the wiring patterns 33 to 35. Since (for example, solder bumps) are not required, the wiring patterns 33 to 35 (specifically, the vias 45, 46, 51, and 56 and the wirings 47, 53, and 58) can be finely and densely arranged. .

半導体装置１２は、半導体装置１１の上方に配置されており、配線基板８１と、電子部品８３と、モールド樹脂８５とを有する。配線基板８１は、基板本体９１と、パッド９３，９４と、配線パターン９６と、ソルダーレジスト層９８，９９とを有する。基板本体９１は、板状とされている。基板本体９１としては、例えば、複数の絶縁樹脂層が積層された積層体を用いることができる。   The semiconductor device 12 is disposed above the semiconductor device 11 and includes a wiring board 81, an electronic component 83, and a mold resin 85. The wiring substrate 81 includes a substrate body 91, pads 93 and 94, a wiring pattern 96, and solder resist layers 98 and 99. The substrate body 91 is plate-shaped. As the substrate body 91, for example, a laminate in which a plurality of insulating resin layers are laminated can be used.

パッド９３は、基板本体９１の上面９１Ａに設けられている。パッド９３は、金属ワイヤ８４（例えば、Ａｕワイヤ）の一方の端部及び配線パターン９６の上端と接続されている。パッド９３は、金属ワイヤ８４を介して、電子部品８３と電気的に接続されている。パッド９３の材料としては、例えば、Ｃｕを用いることができる。   The pad 93 is provided on the upper surface 91 </ b> A of the substrate body 91. The pad 93 is connected to one end of a metal wire 84 (for example, Au wire) and the upper end of the wiring pattern 96. The pad 93 is electrically connected to the electronic component 83 via the metal wire 84. As a material of the pad 93, for example, Cu can be used.

パッド９４は、基板本体９１の下面９１Ｂに設けられている。パッド９４は、配線パターン９６の下端及び内部接続端子１３と接続されている。パッド９４は、配線パターン９６を介して、パッド９３と電気的に接続されると共に、内部接続端子１３を介して、半導体装置１１と電気的に接続されている。パッド９４の材料としては、例えば、Ｃｕを用いることができる。   The pad 94 is provided on the lower surface 91 </ b> B of the substrate body 91. The pad 94 is connected to the lower end of the wiring pattern 96 and the internal connection terminal 13. The pad 94 is electrically connected to the pad 93 via the wiring pattern 96 and is also electrically connected to the semiconductor device 11 via the internal connection terminal 13. As a material of the pad 94, for example, Cu can be used.

配線パターン９６は、基板本体９１を貫通するように、基板本体９１に内設されている。配線パターン９６は、例えば、複数の配線及びビア（図示せず）により構成することができる。配線パターン９６の上端は、パッド９３と接続されており、配線パターン９６の下端は、パッド９４と接続されている。   The wiring pattern 96 is provided in the substrate body 91 so as to penetrate the substrate body 91. The wiring pattern 96 can be constituted by a plurality of wirings and vias (not shown), for example. The upper end of the wiring pattern 96 is connected to the pad 93, and the lower end of the wiring pattern 96 is connected to the pad 94.

ソルダーレジスト層９８は、基板本体９１の上面９１Ａに設けられている。ソルダーレジスト層９８は、パッド９３の上面を露出する開口部９８Ａを有する。   The solder resist layer 98 is provided on the upper surface 91 </ b> A of the substrate body 91. The solder resist layer 98 has an opening 98 </ b> A that exposes the upper surface of the pad 93.

ソルダーレジスト層９９は、基板本体９１の下面９１Ｂに設けられている。ソルダーレジスト層９９は、パッド９４の下面を露出する開口部９９Ａを有する。   The solder resist layer 99 is provided on the lower surface 91 </ b> B of the substrate body 91. The solder resist layer 99 has an opening 99 </ b> A that exposes the lower surface of the pad 94.

電子部品８３は、複数の電極パッド１００を有する。電子部品８３は、電極パッド１００が形成されていない側の電子部品８３の面とソルダーレジスト層９８の上面とが接触するように、ソルダーレジスト層９８上に接着されている。電極パッド１００は、金属ワイヤ８４の他方の端部と接続されている。これにより、電子部品８３は、金属ワイヤ８４を介して、配線基板８１と電気的に接続されている。電子部品８３としては、例えば、メモリ用の半導体チップを用いることができる。   The electronic component 83 has a plurality of electrode pads 100. The electronic component 83 is bonded onto the solder resist layer 98 so that the surface of the electronic component 83 on the side where the electrode pad 100 is not formed and the upper surface of the solder resist layer 98 are in contact with each other. The electrode pad 100 is connected to the other end of the metal wire 84. Thereby, the electronic component 83 is electrically connected to the wiring board 81 via the metal wire 84. As the electronic component 83, for example, a semiconductor chip for memory can be used.

モールド樹脂８５は、電子部品８３及び金属ワイヤ８４を覆うように、パッド９３の上面及びソルダーレジスト９８の上面に設けられている。モールド樹脂８５は、電子部品８３及び金属ワイヤ８４を封止するための樹脂である。モールド樹脂８５の材料としては、例えば、エポキシ樹脂を用いることができる。   The mold resin 85 is provided on the upper surface of the pad 93 and the upper surface of the solder resist 98 so as to cover the electronic component 83 and the metal wire 84. The mold resin 85 is a resin for sealing the electronic component 83 and the metal wire 84. As a material of the mold resin 85, for example, an epoxy resin can be used.

内部接続端子１３は、半導体装置１１と半導体装置１２との間に配置されると共に、貫通電極２１〜２３のうちのいずれか１つの電極の上端及びパッド９４と接続されている。これにより、内部接続端子１３は、半導体装置１１と半導体装置１２とを電気的に接続している。先に説明したように、半導体装置１２と対向する半導体装置１１の上面は、平坦な面とされているため、内部接続端子１３の高さ方向のサイズを小さくすることが可能である。内部接続端子１３の高さ方向のサイズは、例えば、３０μｍとすることができる。内部接続端子１３としては、例えば、はんだボールを用いることができる。   The internal connection terminal 13 is disposed between the semiconductor device 11 and the semiconductor device 12, and is connected to the upper end of any one of the through electrodes 21 to 23 and the pad 94. Thereby, the internal connection terminal 13 electrically connects the semiconductor device 11 and the semiconductor device 12. As described above, since the upper surface of the semiconductor device 11 facing the semiconductor device 12 is a flat surface, the size of the internal connection terminal 13 in the height direction can be reduced. The size of the internal connection terminal 13 in the height direction can be set to 30 μm, for example. As the internal connection terminal 13, for example, a solder ball can be used.

本実施の形態の電子装置によれば、同一平面上に配置された電子部品１７，１８の背面１７Ａ，１８Ａ、絶縁部材１９の上面１９Ａ、及び貫通電極２１〜２３の上端面を有し、半導体装置１２と対向する面が平坦な面とされた半導体装置１１と、半導体装置１１の上方に配置された半導体装置１２と、を内部接続端子１３を介して電気的に接続することにより、内部接続端子１３の高さ方向のサイズを小さくすることが可能となるため、電子装置１０の高さ方向のサイズの小型化を図ることができる。   According to the electronic device of the present embodiment, it has the back surfaces 17A and 18A of the electronic components 17 and 18 arranged on the same plane, the upper surface 19A of the insulating member 19, and the upper end surfaces of the through electrodes 21 to 23. By electrically connecting the semiconductor device 11 having a flat surface facing the device 12 and the semiconductor device 12 disposed above the semiconductor device 11 via an internal connection terminal 13, internal connection is achieved. Since the size in the height direction of the terminal 13 can be reduced, the size in the height direction of the electronic device 10 can be reduced.

図３〜図１４は、本発明の第１の実施の形態に係る半導体装置の製造工程を示す図である。図３〜図１４において、第１の実施の形態の半導体装置１１と同一構成部分には同一符号を付す。   3 to 14 are views showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention. 3 to 14, the same components as those of the semiconductor device 11 of the first embodiment are denoted by the same reference numerals.

図３〜図１４を参照して、第１の実施の形態の半導体装置１１の製造方法について説明する。始めに、図３に示す工程では、支持体１０１の上面１０１Ａに接着剤１０２を形成した後、接着剤１０２により、電子部品１７，１８と支持体１０１とを接着させる（電子部品接着工程）。   A method for manufacturing the semiconductor device 11 according to the first embodiment will be described with reference to FIGS. First, in the process shown in FIG. 3, after the adhesive 102 is formed on the upper surface 101 </ b> A of the support 101, the electronic components 17 and 18 and the support 101 are bonded by the adhesive 102 (electronic component bonding process).

このとき、支持体１０１の上面１０１Ａと電極パッド６２，６３，６５，６６の接続面６２Ａ，６３Ａ，６５Ａ，６６Ａとが接触するように、電子部品１７，１８と支持体１０１とを接着させる。なお、押圧により電子部品１７，１８が接着剤１０２に埋め込まれるようにし、電極パッド６２，６３，６５，６６の接続面６２Ａ，６３Ａ，６５Ａ，６６Ａが支持体１０１の上面１０１Ａと接触するようにするとよい。   At this time, the electronic components 17 and 18 and the support body 101 are bonded so that the upper surface 101A of the support body 101 and the connection surfaces 62A, 63A, 65A, and 66A of the electrode pads 62, 63, 65, and 66 are in contact with each other. The electronic parts 17 and 18 are embedded in the adhesive 102 by pressing, and the connection surfaces 62A, 63A, 65A, and 66A of the electrode pads 62, 63, 65, and 66 are in contact with the upper surface 101A of the support 101. Good.

この段階での電子部品１７，１８は、薄板化されていない。このような薄板化されていない電子部品１７，１８は、薄板化された電子部品１７，１８よりもハンドリングしやすいため、支持体１０１の所定の位置に電子部品１７，１８を精度良く接着することができる。薄板化前の電子部品１７，１８の厚さは、例えば、７００μｍとすることができる。   The electronic components 17 and 18 at this stage are not thinned. Since the electronic components 17 and 18 that are not thinned are easier to handle than the electronic components 17 and 18 that are thinned, the electronic components 17 and 18 are bonded to a predetermined position of the support 101 with high accuracy. Can do. The thickness of the electronic components 17 and 18 before thinning can be set to 700 μm, for example.

電子部品１７，１８としては、例えば、半導体チップを用いることができる。具体的には、電子部品１７，１８としてＣＰＵ（Central Processing Unit）用の半導体チップを用いる場合や、電子部品１７，１８のどちらか一方にＣＰＵ（Central Processing Unit）用の半導体チップを用い、他方にメモリ用の半導体チップを用いる場合や、電子部品１７，１８のどちらか一方にＣＰＵ（Central Processing Unit）用の半導体チップを用い、他方にＧＰＵ（Graphics Processing Unit）用の半導体チップを用いる場合がある。   As the electronic components 17 and 18, for example, semiconductor chips can be used. Specifically, when a semiconductor chip for CPU (Central Processing Unit) is used as the electronic components 17 and 18, a semiconductor chip for CPU (Central Processing Unit) is used for one of the electronic components 17 and 18, and the other In some cases, a semiconductor chip for memory is used, or a semiconductor chip for CPU (Central Processing Unit) is used for one of the electronic components 17 and 18, and a semiconductor chip for GPU (Graphics Processing Unit) is used for the other. is there.

支持体１０１としては、例えば、ガラス基板、シリコン基板、金属板（例えば、Ｃｕ板）等を用いることができる。支持体１０１の厚さは、例えば、３００〜６００μｍとすることができる。接着剤１０２としては、例えば、接着性を有したポリイミド樹脂テープ（例えば、厚さ１〜２０μｍ）を用いることができる。   As the support 101, for example, a glass substrate, a silicon substrate, a metal plate (for example, a Cu plate), or the like can be used. The thickness of the support body 101 can be 300-600 micrometers, for example. As the adhesive 102, for example, an adhesive polyimide resin tape (for example, a thickness of 1 to 20 μm) can be used.

次いで、図４に示す工程では、接着剤１０２の上面１０２Ａに、電子部品１７，１８の側面の一部を封止する絶縁部材１９を形成する（絶縁部材形成工程）。絶縁部材１９としては、例えば、モールド樹脂（例えば、エポキシ樹脂よりなるモールド樹脂）を用いることができる。絶縁部材１９は、例えば、トランスファーモールド法により形成することができる。絶縁部材１９は、薄板化後の電子部品１７，１８の背面１７Ａ，１８Ａよりも上方に絶縁部材１９の上面が位置するように形成する。この段階での絶縁部材１９の厚さは、例えば、３００μｍとすることができる。   Next, in the step shown in FIG. 4, the insulating member 19 that seals part of the side surfaces of the electronic components 17 and 18 is formed on the upper surface 102A of the adhesive 102 (insulating member forming step). As the insulating member 19, for example, a mold resin (for example, a mold resin made of an epoxy resin) can be used. The insulating member 19 can be formed by, for example, a transfer mold method. The insulating member 19 is formed such that the upper surface of the insulating member 19 is positioned above the rear surfaces 17A and 18A of the electronic components 17 and 18 after being thinned. The thickness of the insulating member 19 at this stage can be set to 300 μm, for example.

次いで、図５に示す工程では、図４に示す構造体の上面側（電子部品１７，１８の背面１７Ａ，１８Ａ側）から、電子部品１７，１８及び絶縁部材１９を研削（例えば、バックサイドグラインダによる研削）することで、電子部品１７，１８を薄板化すると共に、薄板化された電子部品１７，１８の背面１７Ａ，１８Ａと研削された絶縁部材１９の上面１９Ａとを同一平面上に配置させる（研削工程。）。   Next, in the step shown in FIG. 5, the electronic components 17 and 18 and the insulating member 19 are ground (for example, a backside grinder) from the upper surface side (the back surfaces 17A and 18A side of the electronic components 17 and 18) of the structure shown in FIG. The electronic parts 17 and 18 are made thin, and the back surfaces 17A and 18A of the thinned electronic parts 17 and 18 and the grounded upper surface 19A of the insulating member 19 are arranged on the same plane. (Grinding process).

これにより、図５に示す構造体の上面は、平坦な面となる。薄板化された電子部品１７，１８の厚さ（接着剤１０２上に配置された部分の電子部品１７，１８の厚さ）は、例えば、２００μｍとすることができる。この場合、研削後の絶縁部材１９の厚さは、例えば、２００μｍとすることができる。   Thereby, the upper surface of the structure shown in FIG. 5 becomes a flat surface. The thickness of the thinned electronic components 17 and 18 (the thickness of the electronic components 17 and 18 in the portion disposed on the adhesive 102) can be set to 200 μm, for example. In this case, the thickness of the insulating member 19 after grinding can be set to 200 μm, for example.

次いで、図６に示す工程では、絶縁部材１９の上面１９Ａ側から、絶縁部材１９及び接着剤１０２を貫通する貫通孔７１〜７３を形成する（貫通孔形成工程）。   Next, in the process illustrated in FIG. 6, through holes 71 to 73 that penetrate the insulating member 19 and the adhesive 102 are formed from the upper surface 19 </ b> A side of the insulating member 19 (through hole forming process).

貫通孔７１〜７３は、例えば、貫通孔７１〜７３の形成領域に対応する部分の絶縁部材１９及び接着剤１０２にレーザを照射することで形成できる。貫通孔７１〜７３は、支持体１０１の上面１０１Ａを露出している。貫通孔７１〜７３の直径は、例えば、２００μｍとすることができる。   The through holes 71 to 73 can be formed, for example, by irradiating a portion of the insulating member 19 and the adhesive 102 corresponding to the formation region of the through holes 71 to 73 with a laser. The through holes 71 to 73 expose the upper surface 101 </ b> A of the support 101. The diameter of the through holes 71 to 73 can be set to 200 μm, for example.

次いで、図７に示す工程では、貫通孔７１を充填する貫通電極２１、貫通孔７２を充填する貫通電極２２、及び貫通孔７３を充填する貫通電極２３を同時に形成する（貫通電極形成工程）。   Next, in the step shown in FIG. 7, the through electrode 21 filling the through hole 71, the through electrode 22 filling the through hole 72, and the through electrode 23 filling the through hole 73 are simultaneously formed (through electrode forming step).

このとき、貫通電極２１〜２３は、貫通電極２１〜２３の上端面、電子部品１７，１８の背面１７Ａ，１８Ａ、及び絶縁部材１９の上面１９Ａが同一平面上に配置されるように形成する。貫通電極２１〜２３は、例えば、めっき法や印刷法等により形成することができる。   At this time, the through electrodes 21 to 23 are formed so that the upper end surfaces of the through electrodes 21 to 23, the back surfaces 17A and 18A of the electronic components 17 and 18, and the upper surface 19A of the insulating member 19 are arranged on the same plane. The through electrodes 21 to 23 can be formed by, for example, a plating method or a printing method.

めっき法を用いて貫通電極２１〜２３を形成する場合、支持体１０１（例えば、シリコン基板、ガラス基板等）の上面１０１Ａに、スパッタ法によりＣｕ層（シリコン基板、ガラス基板の場合には給電層となる）を形成し、その後、先に説明した図３〜図６に示す工程と同様な処理を行った後、Ｃｕ層に給電して、貫通孔７１〜７３を充填するようにめっき膜を析出成長させることで、貫通電極２１〜２３を形成する。貫通電極２１〜２３の材料としては、例えば、Ｃｕを用いることができる。   When the through electrodes 21 to 23 are formed using a plating method, a Cu layer (a power supply layer in the case of a silicon substrate or a glass substrate) is formed on the upper surface 101A of the support 101 (for example, a silicon substrate or a glass substrate) by a sputtering method. After that, the same process as the process shown in FIGS. 3 to 6 described above is performed, and then the Cu film is fed to fill the through holes 71 to 73 with power. By penetrating and growing, the through electrodes 21 to 23 are formed. As a material for the through electrodes 21 to 23, for example, Cu can be used.

なお、支持体１０１として金属板（例えば、Ｃｕ板）を用いる場合、支持体１０１が給電層として機能するため上記Ｃｕ層の形成は不要となる。   In addition, when using a metal plate (for example, Cu board) as the support body 101, since the support body 101 functions as an electric power feeding layer, formation of the said Cu layer becomes unnecessary.

また、貫通電極２１〜２３を形成後、内部接続端子１３が接続される側の貫通電極２１〜２３の端面に、保護層（例えば、貫通電極２１〜２３の端面に、Ｎｉめっき層と、Ａｕめっき層とを順次積層させたＮｉ／Ａｕ積層膜）を設けてもよい。   Further, after forming the through electrodes 21 to 23, a protective layer (for example, an Ni plating layer and Au on the end surfaces of the through electrodes 21 to 23 is formed on the end surfaces of the through electrodes 21 to 23 on the side to which the internal connection terminal 13 is connected. A Ni / Au laminated film in which a plating layer is sequentially laminated may be provided.

次いで、図８に示す工程では、図７に示す電子部品１７，１８及び貫通電極２１〜２３が形成された絶縁部材１９から接着剤１０２及び支持体１０１を除去する（支持体除去工程）。   Next, in the step shown in FIG. 8, the adhesive 102 and the support 101 are removed from the insulating member 19 on which the electronic components 17 and 18 and the through electrodes 21 to 23 shown in FIG. 7 are formed (support removal step).

具体的には、例えば、図７に示す電子部品１７，１８及び貫通電極２１〜２３が形成された絶縁部材１９から、支持体１０１を機械的に剥がすことで、支持体１０１と共に、接着剤１０２を除去する。これにより、貫通電極２１〜２３及び電極パッド６２，６３，６５，６６は、接着剤１０２の厚さ分だけ、絶縁部材１９の下面１９Ｂから突出するが、多少突出していたとしても製造工程上問題は無い。また、貫通電極２１〜２３の下端面及び電極パッド６２，６３，６５，６６の接続面６２Ａ，６３Ａ，６５Ａ，６６Ａと絶縁部材１９の下面１９Ｂとは、完全な同一平面には配置されない。   Specifically, for example, the support 102 is mechanically peeled from the insulating member 19 in which the electronic components 17 and 18 and the through electrodes 21 to 23 shown in FIG. Remove. Accordingly, the through electrodes 21 to 23 and the electrode pads 62, 63, 65, and 66 protrude from the lower surface 19B of the insulating member 19 by the thickness of the adhesive 102, but even if they protrude slightly, there is a problem in the manufacturing process. There is no. Further, the lower end surfaces of the through electrodes 21 to 23 and the connection surfaces 62A, 63A, 65A, 66A of the electrode pads 62, 63, 65, 66 and the lower surface 19B of the insulating member 19 are not disposed on the same plane.

次いで、図９に示す工程では、絶縁部材１９の下面１９Ｂ、電極パッド６２，６３，６５，６６、電子部品１７，１８の電極パッド形成面１７Ｂ，１８Ｂ、及び貫通電極２１〜２３の下端面に、開口部１１１〜１１７を有した絶縁層４１を形成する。   Next, in the step shown in FIG. 9, the lower surface 19B of the insulating member 19, the electrode pads 62, 63, 65, 66, the electrode pad forming surfaces 17B, 18B of the electronic components 17, 18, and the lower end surfaces of the through electrodes 21-23. Then, the insulating layer 41 having the openings 111 to 117 is formed.

具体的には、絶縁層４１は、例えば、図８に示す構造体の下面に絶縁層４１の母材となる絶縁樹脂フィルム（例えば、エポキシ樹脂フィルム）を貼り付けた後、開口部１１１〜１１７に対応する部分の絶縁樹脂フィルムをレーザ加工することで形成する。   Specifically, for example, the insulating layer 41 is formed by attaching an insulating resin film (for example, an epoxy resin film) serving as a base material of the insulating layer 41 to the lower surface of the structure shown in FIG. A portion of the insulating resin film corresponding to is formed by laser processing.

開口部１１１は、接続面６２Ａを露出するように形成し、開口部１１２は、接続面６３Ａを露出するように形成する。また、開口部１１３は、接続面６５Ａを露出するように形成し、開口部１１４は、接続面６６Ａを露出するように形成する。また、開口部１１５は、貫通電極２１の下端面を露出するように形成し、開口部１１６は、貫通電極２２の下端面を露出するように形成する。さらに、開口部１１７は、貫通電極２３の下端面を露出するように形成する。   The opening 111 is formed so as to expose the connection surface 62A, and the opening 112 is formed so as to expose the connection surface 63A. The opening 113 is formed so as to expose the connection surface 65A, and the opening 114 is formed so as to expose the connection surface 66A. The opening 115 is formed so as to expose the lower end surface of the through electrode 21, and the opening 116 is formed so as to expose the lower end surface of the through electrode 22. Further, the opening 117 is formed so as to expose the lower end surface of the through electrode 23.

次いで、図１０に示す工程では、開口部１１１〜１１７及び絶縁層４１の下面４１Ｂに、ビア４５，４６，５１，５２，５６，５７，６１及び配線４７，５３，５８，６２を同時に形成する。これにより、電子部品１７に設けられた電極パッド６２，６３とビア４５，５１とが直接接続されると共に、電子部品１８に設けられた電極パッド６５，６６とビア４６，５６とが直接接続される。   Next, in the step shown in FIG. 10, vias 45, 46, 51, 52, 56, 57, 61 and wirings 47, 53, 58, 62 are simultaneously formed in the openings 111 to 117 and the lower surface 41 </ b> B of the insulating layer 41. . Thereby, the electrode pads 62 and 63 provided in the electronic component 17 and the vias 45 and 51 are directly connected, and the electrode pads 65 and 66 provided in the electronic component 18 and the vias 46 and 56 are directly connected. The

このように、電子部品１７，１８の電極パッド６２，６３，６５，６６とビア４５，４６，５１、５６とを直接接続することにより、バンプ或いは金属ワイヤを介して、電子部品と配線パターンとを電気的に接続させた従来の半導体装置と比較して、半導体装置１１の厚さ方向のサイズの小型化を図ることができる。   Thus, by directly connecting the electrode pads 62, 63, 65 and 66 of the electronic components 17 and 18 and the vias 45, 46, 51 and 56, the electronic components and the wiring pattern can be connected via bumps or metal wires. As compared with a conventional semiconductor device in which the semiconductor devices 11 are electrically connected, the size of the semiconductor device 11 in the thickness direction can be reduced.

ビア５２は、貫通電極２１の下端と直接接続され、ビア５７は、貫通電極２２の下端と直接接続される。また、ビア６１は、貫通電極２３の下端と直接接続される。   The via 52 is directly connected to the lower end of the through electrode 21, and the via 57 is directly connected to the lower end of the through electrode 22. The via 61 is directly connected to the lower end of the through electrode 23.

ビア４５，４６，５１，５２，５６，５７，６１及び配線４７，５３，５８，６２は、例えば、セミアディティブ法により形成することができる。ビア４５，４６，５１，５２，５６，５７，６１及び配線４７，５３，５８，６２の材料としては、例えば、Ｃｕを用いることができる。   The vias 45, 46, 51, 52, 56, 57, 61 and the wirings 47, 53, 58, 62 can be formed by, for example, a semi-additive method. As a material of the vias 45, 46, 51, 52, 56, 57, 61 and the wirings 47, 53, 58, 62, for example, Cu can be used.

次いで、図１１に示す工程では、先に説明した図９に示す工程と同様な処理を行うことにより、絶縁層４１の下面４１Ｂに、開口部１２１〜１２４を有した絶縁層４２を形成する。これにより、複数の絶縁層４１，４２が積層された積層体２７が形成される。開口部１２１は、配線４７の一部を露出するように形成し、開口部１２２は、配線５３の一部を露出するように形成する。開口部１２３は、配線５８の一部を露出するように形成し、開口部１２４は、配線６２の一部を露出するように形成する。上記絶縁層４２としては、例えば、エポキシ樹脂フィルムを用いることができる。   Next, in the process shown in FIG. 11, the insulating layer 42 having the openings 121 to 124 is formed on the lower surface 41 </ b> B of the insulating layer 41 by performing the same process as the process shown in FIG. 9 described above. Thereby, the laminated body 27 in which the plurality of insulating layers 41 and 42 are laminated is formed. The opening 121 is formed so that a part of the wiring 47 is exposed, and the opening 122 is formed so that a part of the wiring 53 is exposed. The opening 123 is formed so that a part of the wiring 58 is exposed, and the opening 124 is formed so that a part of the wiring 62 is exposed. As the insulating layer 42, for example, an epoxy resin film can be used.

次いで、図１２に示す工程では、先に説明した図１０に示す工程と同様な処理を行うことにより、開口部１２１〜１２４及び絶縁層４２の下面４２Ｂに、ビア４８，５４，５９，６３と、接続面３１−１Ａ，３１−２Ａ，３１−３Ａ，３１−４Ａを有した外部接続用パッド３１−１，３１−２，３１−３，３１−４とを同時に形成する。   Next, in the process shown in FIG. 12, vias 48, 54, 59, and 63 are formed in the openings 121 to 124 and the lower surface 42B of the insulating layer 42 by performing the same process as the process shown in FIG. The external connection pads 31-1, 31-2, 31-3, 31-4 having the connection surfaces 31-1A, 31-2A, 31-3A, 31-4A are formed simultaneously.

これにより、電子部品１７，１８と外部接続用パッド３１−１とを電気的に接続する配線パターン３３と、電子部品１７及び貫通電極２１と外部接続用パッド３１−２とを電気的に接続する配線パターン３４と、電子部品１８及び貫通電極２２と外部接続用パッド３１−３とを電気的に接続する配線パターン３５と、貫通電極２３と外部接続用パッド３１−４とを電気的に接続する配線パターン３６とが形成される。   Thereby, the wiring pattern 33 that electrically connects the electronic components 17 and 18 and the external connection pad 31-1, and the electronic component 17 and the through electrode 21 and the external connection pad 31-2 are electrically connected. The wiring pattern 34, the wiring pattern 35 that electrically connects the electronic component 18 and the through electrode 22, and the external connection pad 31-3, and the through electrode 23 and the external connection pad 31-4 are electrically connected. A wiring pattern 36 is formed.

ビア４８，５４，５９，６３及び外部接続用パッド３１−１，３１−２，３１−３，３１−４の材料としては、例えば、Ｃｕを用いることができる。   As a material of the vias 48, 54, 59, 63 and the external connection pads 31-1, 31-2, 31-3, 31-4, for example, Cu can be used.

次いで、図１３に示す工程では、絶縁層４２の下面４２Ｂに、開口部３８Ａ，３８Ｂ，３８Ｃ，３８Ｄを有したソルダーレジスト層３８を形成する。開口部３８Ａは、接続面３１−１Ａを露出するように形成し、開口部３８Ｂは、接続面３１−２Ａを露出するように形成する。開口部３８Ｃは、接続面３１−３Ａを露出するように形成し、開口部３８Ｄは、接続面３１−４Ａを露出するように形成する。なお、接続面３１−１Ａ，３１−２Ａ，３１−３Ａ，３１−４Ａに、Ｎｉめっき層と、Ａｕめっき層とを順次積層させ、Ｎｉ／Ａｕ積層膜よりなる保護層を設けてもよい。図９〜図１３に示す工程が、「多層配線構造体形成工程」に相当する工程である。   Next, in a step shown in FIG. 13, a solder resist layer 38 having openings 38A, 38B, 38C, and 38D is formed on the lower surface 42B of the insulating layer 42. The opening 38A is formed so as to expose the connection surface 31-1A, and the opening 38B is formed so as to expose the connection surface 31-2A. The opening 38C is formed so as to expose the connection surface 31-3A, and the opening 38D is formed so as to expose the connection surface 31-4A. Note that a Ni plating layer and an Au plating layer may be sequentially laminated on the connection surfaces 31-1A, 31-2A, 31-3A, and 31-4A to provide a protective layer made of a Ni / Au laminated film. The steps shown in FIGS. 9 to 13 correspond to the “multilayer wiring structure forming step”.

次いで、図１４に示す工程では、接続面３１−１Ａ，３１−２Ａ，３１−３Ａ，３１−４Ａに、それぞれ１つの外部接続端子２４を形成する。外部接続端子２４としては、例えば、はんだボールを用いることができる。なお、図１４では、外部接続端子２４としてはんだボールを用いた場合を例に挙げて図示したが、はんだボールの代わりにピン端子を外部接続端子２４として用いてもよい。なお、外部接続端子２４として、はんだボール等を設ける代わりに、接続面３１−１Ａ，３１−２Ａ，３１−３Ａ，３１−４Ａ自体を外部接続端子として用いてもよい。   Next, in the process shown in FIG. 14, one external connection terminal 24 is formed on each of the connection surfaces 31-1A, 31-2A, 31-3A, and 31-4A. For example, a solder ball can be used as the external connection terminal 24. In FIG. 14, a case where a solder ball is used as the external connection terminal 24 is illustrated as an example, but a pin terminal may be used as the external connection terminal 24 instead of the solder ball. Instead of providing solder balls or the like as the external connection terminals 24, the connection surfaces 31-1A, 31-2A, 31-3A, 31-4A themselves may be used as external connection terminals.

本実施の形態の半導体装置の製造方法によれば、支持体１０１の上面１０１Ａと電子部品１７，１８に設けられた電極パッド６２，６３，６５，６６とが接触するように、接着剤１０２により、支持体１０１と電子部品１７，１８とを接着し、次いで、接着剤１０２の上面１０２Ａに電子部品１７，１８の周囲（側面）の一部を封止する絶縁部材１９を形成し、次いで、電子部品１７，１８及び絶縁部材１９を研削することにより、電子部品１７，１８を薄板化すると共に、薄板化された電子部品１７，１８の背面１７Ａ，１８Ａと絶縁部材１９の上面１９Ａとを同一平面上に配置し、次いで、絶縁部材１９を貫通する貫通電極２１〜２３を形成し、次いで、接着剤１０２及び支持体１０１を除去し、その後、絶縁部材１９の下面１９Ｂ、電極パッド６２，６３，６５，６６、電子部品１７，１８の電極パッド形成面１７Ｂ，１８Ｂ、及び貫通電極２１〜２３の下端面に、電極パッド６２，６３，６５，６６及び貫通電極２１〜２３の下端面と直接接続される配線パターン３３〜３６を形成することにより、バンプ或いは金属ワイヤを介して、電子部品と配線パターンとを電気的に接続させた従来の半導体装置と比較して、半導体装置１１の厚さ方向のサイズの小型化を図ることができる。   According to the manufacturing method of the semiconductor device of the present embodiment, the adhesive 102 is used so that the upper surface 101A of the support 101 and the electrode pads 62, 63, 65, 66 provided on the electronic components 17, 18 are in contact with each other. Then, the support member 101 and the electronic components 17 and 18 are bonded together, and then the insulating member 19 that seals a part of the periphery (side surface) of the electronic components 17 and 18 is formed on the upper surface 102A of the adhesive 102. By grinding the electronic components 17 and 18 and the insulating member 19, the electronic components 17 and 18 are thinned, and the back surfaces 17A and 18A of the thinned electronic components 17 and 18 and the top surface 19A of the insulating member 19 are the same. Then, the through electrodes 21 to 23 penetrating the insulating member 19 are formed, then the adhesive 102 and the support 101 are removed, and then the lower surface 19B of the insulating member 19 and the electric The electrode pads 62, 63, 65, 66 and the through electrodes 21 to 23 are formed on the pads 62, 63, 65 and 66, the electrode pad forming surfaces 17 B and 18 B of the electronic components 17 and 18, and the lower end surfaces of the through electrodes 21 to 23. A semiconductor device as compared with a conventional semiconductor device in which an electronic component and a wiring pattern are electrically connected through bumps or metal wires by forming wiring patterns 33 to 36 directly connected to the lower end surface. The size in the thickness direction of 11 can be reduced.

また、電子部品１７，１８に設けられた電極パッド６２，６３，６５，６６と配線パターン３３〜３５とを直接接続することにより、電子部品１７，１８と配線パターン３３〜３５とを接続するバンプ（例えば、はんだバンプ）が不要となるため、配線パターン３３〜３５（具体的には、ビア４５，４６，５１，５６及び配線４７，５３，５８）を微細かつ高密度に形成することができる。   Further, the bumps for connecting the electronic components 17 and 18 and the wiring patterns 33 to 35 by directly connecting the electrode pads 62, 63, 65 and 66 provided on the electronic components 17 and 18 and the wiring patterns 33 to 35. Since (for example, solder bumps) are not required, the wiring patterns 33 to 35 (specifically, vias 45, 46, 51, and 56 and wirings 47, 53, and 58) can be formed finely and with high density. .

（第２の実施の形態）
図１５は、本発明の第２の実施の形態に係る電子装置の断面図である。図１５において、第１の実施の形態の電子装置１０と同一構成部分には同一符号を付す。 (Second Embodiment)
FIG. 15 is a sectional view of an electronic device according to the second embodiment of the present invention. In FIG. 15, the same components as those of the electronic device 10 according to the first embodiment are denoted by the same reference numerals.

図１５を参照するに、第２の実施の形態の電子装置１３０は、第１の実施の形態の電子装置１０に設けられた半導体装置１１の代わりに半導体装置１３１を設けた以外は、電子装置１０と同様に構成される。   Referring to FIG. 15, the electronic device 130 of the second embodiment is the same as the electronic device except that a semiconductor device 131 is provided instead of the semiconductor device 11 provided in the electronic device 10 of the first embodiment. 10 is configured in the same manner.

半導体装置１３１は、第１の実施の形態で説明した半導体装置１１に設けられた絶縁部材１９の代わりに絶縁部材１３３及び封止樹脂１３４を設けた以外は、半導体装置１１と同様に構成される。   The semiconductor device 131 is configured in the same manner as the semiconductor device 11 except that an insulating member 133 and a sealing resin 134 are provided instead of the insulating member 19 provided in the semiconductor device 11 described in the first embodiment. .

絶縁部材１３３は、絶縁層４１の上面４１Ａに設けられている。絶縁部材１３３は、貫通孔１３６〜１３８と、貫通部１４１とを有する。貫通孔１３６は、ビア５２の上面を露出するように形成されている。貫通孔１３７は、ビア５７の上面を露出するように形成されている。貫通孔１３８は、ビア６１の上面を露出するように形成されている。貫通部１４１は、絶縁部材１３３を貫通するように形成されている。貫通部１４１は、多層配線構造体１５（具体的には、配線パターン３３〜３５）と電気的に接続された電子部品１７，１８を収容するための空間である。   The insulating member 133 is provided on the upper surface 41 </ b> A of the insulating layer 41. The insulating member 133 has through holes 136 to 138 and a through part 141. The through hole 136 is formed so as to expose the upper surface of the via 52. The through hole 137 is formed so as to expose the upper surface of the via 57. The through hole 138 is formed so as to expose the upper surface of the via 61. The penetration part 141 is formed so as to penetrate the insulating member 133. The through portion 141 is a space for accommodating the electronic components 17 and 18 electrically connected to the multilayer wiring structure 15 (specifically, the wiring patterns 33 to 35).

絶縁部材１３３は、絶縁層４１の上面４１Ａに配置された部分の電子部品１７，１８の厚さと略等しくなるように構成されている。絶縁層４１の上面４１Ａに配置された部分の電子部品１７，１８の厚さが２００μｍの場合、絶縁部材１３３の厚さは、例えば、２００μｍとすることができる。絶縁部材１３３の上面１３３Ａは、平坦な面とされている。絶縁部材１３３の上面１３３Ａは、電子部品１７，１８の背面１７Ａ，１８Ａと略面一となるように構成されている。これにより、絶縁部材１３３の上面１３３Ａ及び電子部品１７，１８の背面１７Ａ，１８Ａは、同一平面上に配置されている。上記構成とされた絶縁部材１３３としては、例えば、エポキシ樹脂層を用いることができる。   The insulating member 133 is configured to be substantially equal to the thickness of the electronic components 17 and 18 in the portion disposed on the upper surface 41 </ b> A of the insulating layer 41. When the thickness of the electronic components 17 and 18 in the portion disposed on the upper surface 41A of the insulating layer 41 is 200 μm, the thickness of the insulating member 133 can be set to 200 μm, for example. The upper surface 133A of the insulating member 133 is a flat surface. The upper surface 133A of the insulating member 133 is configured to be substantially flush with the rear surfaces 17A and 18A of the electronic components 17 and 18. Thus, the upper surface 133A of the insulating member 133 and the rear surfaces 17A and 18A of the electronic components 17 and 18 are arranged on the same plane. As the insulating member 133 configured as described above, for example, an epoxy resin layer can be used.

封止樹脂１３４は、電子部品１７，１８が収容された貫通部１４１を充填するように配置されている。封止樹脂１３４は、電子部品１７，１８の背面１７Ａ，１８Ａを露出している。封止樹脂１３４は、電子部品１７，１８の側面を覆っている。これにより、封止樹脂１３４は、電子部品１７，１８の側面部を封止している。封止樹脂１３４の上面１３４Ａは、平坦な面とされている。封止樹脂１３４の上面１３４Ａは、電子部品１７，１８の背面１７Ａ，１８Ａ及び絶縁部材１３３の上面１３３Ａと略面一になるように構成されている。封止樹脂１３４の厚さは、絶縁層４１の上面４１Ａに配置された部分の電子部品１７，１８の厚さ及び絶縁部材１３３の厚さと略等しい。封止樹脂１３４の厚さは、例えば、２００μｍとすることができる。封止樹脂１３４の材料としては、例えば、エポキシ樹脂を用いることができる。   The sealing resin 134 is disposed so as to fill the through portion 141 in which the electronic components 17 and 18 are accommodated. The sealing resin 134 exposes the back surfaces 17A and 18A of the electronic components 17 and 18. The sealing resin 134 covers the side surfaces of the electronic components 17 and 18. Thereby, the sealing resin 134 seals the side portions of the electronic components 17 and 18. An upper surface 134A of the sealing resin 134 is a flat surface. The upper surface 134A of the sealing resin 134 is configured to be substantially flush with the rear surfaces 17A and 18A of the electronic components 17 and 18 and the upper surface 133A of the insulating member 133. The thickness of the sealing resin 134 is substantially equal to the thickness of the electronic components 17, 18 and the thickness of the insulating member 133 disposed on the upper surface 41 </ b> A of the insulating layer 41. The thickness of the sealing resin 134 can be set to 200 μm, for example. As a material of the sealing resin 134, for example, an epoxy resin can be used.

上記構成とされた第２の実施の形態の半導体装置１３１は、第１の実施の形態の半導体装置１１と同様な効果を得ることができる。   The semiconductor device 131 of the second embodiment configured as described above can obtain the same effects as the semiconductor device 11 of the first embodiment.

本実施の形態の電子装置によれば、電子部品１７，１８の背面１７Ａ，１８Ａ、絶縁部材１３３の上面１３３Ａ、及び封止樹脂１３４の上面１３４Ａを同一平面上に配置することにより、半導体装置１２と対向する半導体装置１３１の上面が平坦な面となるため、半導体装置１３１と半導体装置１２との間に配置される内部接続端子１３の高さ方向のサイズを小さくすることが可能となるので、電子装置１３０の厚さ方向のサイズの小型化を図ることができる。   According to the electronic device of the present embodiment, the rear surfaces 17A and 18A of the electronic components 17 and 18, the upper surface 133A of the insulating member 133, and the upper surface 134A of the sealing resin 134 are arranged on the same plane. Since the upper surface of the semiconductor device 131 opposite to the semiconductor device 131 is a flat surface, the size of the internal connection terminal 13 disposed between the semiconductor device 131 and the semiconductor device 12 can be reduced. The size of the electronic device 130 in the thickness direction can be reduced.

また、内部接続端子１３の高さ方向のサイズを小さくすることにより、貫通電極２１〜２３を狭ピッチで配置することが可能となるので、半導体装置１３１と半導体装置１２との間における電気的接続箇所を増加させることができる（言い換えれば、半導体装置１３１と半導体装置１２との間に配置される内部接続端子１３の数を増加させることができる。）。   In addition, by reducing the size of the internal connection terminal 13 in the height direction, the through electrodes 21 to 23 can be arranged at a narrow pitch, so that electrical connection between the semiconductor device 131 and the semiconductor device 12 is achieved. The number of locations can be increased (in other words, the number of internal connection terminals 13 arranged between the semiconductor device 131 and the semiconductor device 12 can be increased).

さらに、はんだボール等の内部接続端子１３を小径化が可能となることにより、貫通電極２１〜２３を狭ピッチ化できる。   Furthermore, since the internal connection terminals 13 such as solder balls can be reduced in diameter, the through electrodes 21 to 23 can be narrowed.

図１６〜図２３は、本発明の第２の実施の形態に係る半導体装置の製造工程を示す図である。図１６〜図２３において、第２の実施の形態の半導体装置１３１と同一構成部分には同一符号を付す。   16 to 23 are views showing manufacturing steps of the semiconductor device according to the second embodiment of the present invention. 16 to 23, the same components as those of the semiconductor device 131 according to the second embodiment are denoted by the same reference numerals.

図１６〜図２３を参照して、第２の実施の形態の半導体装置１３１の製造方法について説明する。始めに、図１６に示す工程では、支持体１０１の上面１０１Ａに絶縁部材１３３を形成する。   A method for manufacturing the semiconductor device 131 according to the second embodiment will be described with reference to FIGS. First, in the step shown in FIG. 16, the insulating member 133 is formed on the upper surface 101 </ b> A of the support 101.

具体的には、絶縁部材１３３は、例えば、支持体１０１の上面１０１Ａに、樹脂（例えば、エポキシ樹脂）を塗布することで形成する。なお、図１６に示す絶縁部材１３３は、先に説明した図１５に示す絶縁部材１３３よりも厚さが厚くなるように形成する。この段階での絶縁部材１３３の厚さは、例えば、３００μｍにすることができる。   Specifically, the insulating member 133 is formed, for example, by applying a resin (for example, an epoxy resin) to the upper surface 101A of the support 101. Note that the insulating member 133 illustrated in FIG. 16 is formed to be thicker than the insulating member 133 illustrated in FIG. 15 described above. The thickness of the insulating member 133 at this stage can be set to 300 μm, for example.

次いで、図１７に示す工程では、絶縁部材１３３を貫通する貫通部１４１及び貫通孔１３６〜１３８を形成する。貫通部１４１及び貫通孔１３６〜１３８は、例えば、貫通部１４１及び貫通孔１３６〜１３８の形成領域に対応する部分の絶縁部材１３３にレーザを照射することで形成できる。なお、図１７に示す貫通部１４１及び貫通孔１３６〜１３８の深さは、先に説明した図１５に示す貫通部１４１及び貫通孔１３６〜１３８の深さ（例えば、２００μｍ）よりも深い。電子部品１７，１８の大きさが５ｍｍ×９ｍｍの場合、貫通部１４１の大きさは、例えば、１５ｍｍ×１４ｍｍとすることができる。また、貫通電極１３６〜１３８の直径は、例えば、２００μｍとすることができる。   Next, in the step shown in FIG. 17, the through portion 141 and the through holes 136 to 138 penetrating the insulating member 133 are formed. The through part 141 and the through holes 136 to 138 can be formed, for example, by irradiating a portion of the insulating member 133 corresponding to the formation region of the through part 141 and the through holes 136 to 138 with a laser. Note that the depths of the through part 141 and the through holes 136 to 138 shown in FIG. 17 are deeper than the depths (for example, 200 μm) of the through part 141 and the through holes 136 to 138 shown in FIG. When the size of the electronic components 17 and 18 is 5 mm × 9 mm, the size of the penetrating portion 141 can be, for example, 15 mm × 14 mm. The diameter of the through electrodes 136 to 138 can be set to 200 μm, for example.

次いで、図１８に示す工程では、貫通孔１３６を充填する貫通電極２１と、貫通孔１３７を充填する貫通電極２２と、貫通孔１３８を充填する貫通電極２３とを同時に形成する。貫通電極２１〜２３は、例えば、第１の実施の形態で説明した図７に示す工程と同様なめっき処理を行うことで形成できる。なお、この際、貫通部１４１にめっき膜が形成されないように、めっき処理の前に、貫通部１４１をめっき用レジストで被覆する。貫通電極２１〜２３の材料としては、例えば、Ｃｕを用いることができる。   Next, in the step shown in FIG. 18, the through electrode 21 filling the through hole 136, the through electrode 22 filling the through hole 137, and the through electrode 23 filling the through hole 138 are formed simultaneously. The through electrodes 21 to 23 can be formed, for example, by performing a plating process similar to the process shown in FIG. 7 described in the first embodiment. At this time, the through-hole 141 is covered with a plating resist before plating so that a plating film is not formed on the through-hole 141. As a material for the through electrodes 21 to 23, for example, Cu can be used.

次いで、図１９に示す工程では、貫通部１４１の形成領域に対応する部分の支持体１０１の上面１０１Ａと接続面６２Ａ、６３Ａ，６５Ａ，６６Ａとが接触するように、接着剤１０２により、電子部品１７，１８と支持体１０１とを接着する。図１９に示す電子部品１７，１８は、薄板化される前の電子部品１７，１８であり、先に説明した図１５に示す電子部品１７，１８の厚さよりも厚くなるように構成されている。このような薄板化されていない電子部品１７，１８は、薄板化された電子部品１７，１８よりもハンドリングしやすいため、支持体１０１の所定の位置に電子部品１７，１８を精度良く接着することができる。薄板化されていない電子部品１７，１８の厚さは、例えば、７００μｍとすることができる。   Next, in the step shown in FIG. 19, the electronic component is bonded by the adhesive 102 so that the upper surface 101 </ b> A of the support body 101 and the connection surfaces 62 </ b> A, 63 </ b> A, 65 </ b> A, 66 </ b> A corresponding to the formation region of the penetrating part 141 come into contact. 17 and 18 and the support body 101 are bonded together. The electronic components 17 and 18 shown in FIG. 19 are the electronic components 17 and 18 before being thinned, and are configured to be thicker than the thickness of the electronic components 17 and 18 shown in FIG. 15 described above. . Since the electronic components 17 and 18 that are not thinned are easier to handle than the electronic components 17 and 18 that are thinned, the electronic components 17 and 18 are bonded to a predetermined position of the support 101 with high accuracy. Can do. The thickness of the electronic components 17 and 18 that are not thinned can be set to 700 μm, for example.

電子部品１７，１８としては、例えば、半導体チップを用いることができる。具体的には、電子部品１７，１８としてＣＰＵ（Central Processing Unit）用の半導体チップを用いる場合や、電子部品１７，１８のどちらか一方にＣＰＵ（Central Processing Unit）用の半導体チップを用い、他方にメモリ用の半導体チップを用いる場合や、電子部品１７，１８のどちらか一方にＣＰＵ（Central Processing Unit）用の半導体チップを用い、他方にＧＰＵ（Graphics Processing Unit）用の半導体チップを用いる場合がある。   As the electronic components 17 and 18, for example, semiconductor chips can be used. Specifically, when a semiconductor chip for CPU (Central Processing Unit) is used as the electronic components 17 and 18, a semiconductor chip for CPU (Central Processing Unit) is used for one of the electronic components 17 and 18, and the other In some cases, a semiconductor chip for memory is used, or a semiconductor chip for CPU (Central Processing Unit) is used for one of the electronic components 17 and 18, and a semiconductor chip for GPU (Graphics Processing Unit) is used for the other. is there.

次いで、図２０に示す工程では、貫通部１４１を充填する封止樹脂１３４を形成する。これにより、電子部品１７，１８は、封止樹脂１３４により封止される。封止樹脂１３４は、例えば、トランスファーモールド法、圧縮形成法、ポッティング法等の手法により形成することができる。封止樹脂１３４の材料としては、例えば、エポキシ樹脂を用いることができる。   Next, in a step shown in FIG. 20, a sealing resin 134 that fills the through portion 141 is formed. Thereby, the electronic components 17 and 18 are sealed with the sealing resin 134. The sealing resin 134 can be formed by, for example, a transfer molding method, a compression forming method, a potting method, or the like. As a material of the sealing resin 134, for example, an epoxy resin can be used.

次いで、図２１に示す工程では、図２０に示す構造体から支持体１０１及び接着剤１０２を除去する。具体的には、例えば、支持体１０１を機械的に剥がすことで、支持体１０１と共に、接着剤１０２を除去する。これにより、電子部品１７，１８の電極パッド形成面１７Ｂ，１８Ｂ、電極パッド６２，６３，６５，６６、貫通電極２１〜２３の下端面、絶縁部材１３３の下面１３３Ｂ、及び封止樹脂１３４の下面１３４Ｂが露出される。   Next, in the step shown in FIG. 21, the support 101 and the adhesive 102 are removed from the structure shown in FIG. Specifically, for example, the adhesive 102 is removed together with the support 101 by mechanically peeling the support 101. Accordingly, the electrode pad forming surfaces 17B and 18B of the electronic components 17 and 18, the electrode pads 62, 63, 65, and 66, the lower end surfaces of the through electrodes 21 to 23, the lower surface 133B of the insulating member 133, and the lower surface of the sealing resin 134 134B is exposed.

なお、支持体１０１及び接着剤１０２を除去すると、封止樹脂１３４の下面１３４Ｂと電子部品１７，１８の電極パッド形成面１７Ｂ，１８Ｂが、絶縁部材１３３の下面１３３Ｂから、接着剤１０２の厚さ分だけ凹んだ構造となるが、製造工程上問題とならない。   When the support 101 and the adhesive 102 are removed, the lower surface 134B of the sealing resin 134 and the electrode pad forming surfaces 17B and 18B of the electronic components 17 and 18 extend from the lower surface 133B of the insulating member 133 to the thickness of the adhesive 102. Although the structure is recessed by the amount, there is no problem in the manufacturing process.

次いで、図２２に示す工程では、第１の実施の形態で説明した図９〜図１４に示す工程と同様な処理を行うことで、電子部品１７，１８の電極パッド形成面１７Ｂ，１８Ｂ、電極パッド６２，６３，６５，６６、貫通電極２１〜２３の下端面、絶縁部材１３３の下面１３３Ｂ、及び封止樹脂１３４の下面１３４Ｂに、電子部品１７，１８及び貫通電極２１〜２３と電気的に接続された多層配線構造体１５を形成する。   Next, in the process shown in FIG. 22, the electrode pad formation surfaces 17 </ b> B and 18 </ b> B of the electronic components 17 and 18 are formed by performing the same process as the process shown in FIGS. 9 to 14 described in the first embodiment. The electronic components 17, 18 and the through electrodes 21 to 23 are electrically connected to the pads 62, 63, 65, 66, the lower end surfaces of the through electrodes 21 to 23, the lower surface 133 B of the insulating member 133, and the lower surface 134 B of the sealing resin 134. The connected multilayer wiring structure 15 is formed.

このとき、配線パターン３３は、電極パッド６２，６５と直接接続されるように形成する。また、配線パターン３４は、貫通電極２１の下端及び電極パッド６３と直接接続されるように形成する。また、配線パターン３５は、貫通電極２２の下端及び電極パッド６６と直接接続されるように形成する。さらに、配線パターン３６は、貫通電極２３の下端と直接接続されるように形成する。   At this time, the wiring pattern 33 is formed so as to be directly connected to the electrode pads 62 and 65. The wiring pattern 34 is formed so as to be directly connected to the lower end of the through electrode 21 and the electrode pad 63. The wiring pattern 35 is formed so as to be directly connected to the lower end of the through electrode 22 and the electrode pad 66. Further, the wiring pattern 36 is formed so as to be directly connected to the lower end of the through electrode 23.

このように、電極パッド６２，６３，６５，６６と配線パターン３３〜３５とを直接接続することにより、バンプ或いは金属ワイヤを介して、電子部品と配線パターンとを電気的に接続させた従来の半導体装置と比較して、半導体装置１３１の厚さ方向のサイズの小型化を図ることができる。   Thus, by directly connecting the electrode pads 62, 63, 65, 66 and the wiring patterns 33 to 35, the conventional electronic component and the wiring pattern are electrically connected via the bumps or the metal wires. Compared with the semiconductor device, the size of the semiconductor device 131 in the thickness direction can be reduced.

次いで、図２３に示す工程では、図２２に示す構造体の上面側から、電子部品１７，１８、貫通電極２１〜２３、絶縁部材１３３、及び封止樹脂１３４を研削（例えば、バックサイドグラインダを用いた研削）することにより、電子部品１７，１８の薄板化を行う。これにより、第２の実施の形態の半導体装置１３１が製造される。   Next, in the process shown in FIG. 23, the electronic components 17 and 18, the through electrodes 21 to 23, the insulating member 133, and the sealing resin 134 are ground from the upper surface side of the structure shown in FIG. The electronic components 17 and 18 are thinned by grinding). As a result, the semiconductor device 131 of the second embodiment is manufactured.

また、上記研削により、図２２に示す貫通電極２１〜２３と比較して貫通電極２１〜２３の深さが浅くなると共に、貫通電極２１〜２３の上端面、電子部品１７，１８の背面１７Ａ，１８Ａ、絶縁部材１３３の上面１３３Ａ、及び封止樹脂１３４の上面１３４Ａが同一平面上に配置される。   Further, by the above grinding, the depths of the through electrodes 21 to 23 become shallower than those of the through electrodes 21 to 23 shown in FIG. 22, the upper end surfaces of the through electrodes 21 to 23, the back surfaces 17A of the electronic components 17 and 18, 18A, the upper surface 133A of the insulating member 133, and the upper surface 134A of the sealing resin 134 are arranged on the same plane.

絶縁層４１の上面４１Ａに配置された部分の薄板化後の電子部品１７，１８の厚さは、例えば、２００μｍにすることができる。この場合、貫通電極２１〜２３の深さは、例えば、２００μｍとすることができる。また、絶縁部材１３３及び封止樹脂１３４の厚さは、例えば、２００μｍとすることができる。   The thickness of the electronic components 17 and 18 after thinning the portion disposed on the upper surface 41A of the insulating layer 41 can be set to 200 μm, for example. In this case, the depth of the through electrodes 21 to 23 can be set to 200 μm, for example. Moreover, the thickness of the insulating member 133 and the sealing resin 134 can be set to 200 μm, for example.

なお、電子部品１７，１８の薄板化した後、内部接続端子１３が接続される側の貫通電極２１〜２３の端面に、保護層（例えば、貫通電極２１〜２３の端面に、Ｎｉめっき層と、Ａｕめっき層とを順次積層させたＮｉ／Ａｕ積層膜）を設けてもよい。   After the electronic components 17 and 18 are thinned, a protective layer (for example, an Ni plating layer on the end surfaces of the through electrodes 21 to 23 is formed on the end surfaces of the through electrodes 21 to 23 on the side to which the internal connection terminals 13 are connected. , A Ni / Au laminated film in which an Au plating layer is sequentially laminated may be provided.

本実施の形態の半導体装置の製造方法によれば、支持体１０１の上面１０１Ａに貫通孔１３６〜１３８及び貫通部１４１を有した絶縁部材１３３を形成し、次いで、貫通部１４１から露出された部分の支持体１０１の上面１０１Ａに、接着剤１０２により、接続面６２Ａ，６３Ａ，６５Ａ，６６Ａと支持体１０１の上面１０１Ａとが接触するように、電子部品１７，１８を接着し、次いで、貫通部１４１に電子部品１７，１８を封止する封止樹脂１３４を形成し、次いで、接着剤１０２及び支持体１０１を除去し、次いで、電子部品１７，１８の電極パッド６２，６３，６５，６６と配線パターン３３〜３５とが直接接続されるように多層配線構造体１５を形成することにより、バンプ或いは金属ワイヤを介して、電子部品と配線パターンとを電気的に接続させた従来の半導体装置と比較して、半導体装置１３１の厚さ方向のサイズの小型化を図ることができる。   According to the manufacturing method of the semiconductor device of the present embodiment, the insulating member 133 having the through holes 136 to 138 and the through part 141 is formed on the upper surface 101A of the support 101, and then the part exposed from the through part 141 The electronic parts 17 and 18 are bonded to the upper surface 101A of the support body 101 by the adhesive 102 so that the connection surfaces 62A, 63A, 65A and 66A and the upper surface 101A of the support body 101 are in contact with each other, 141, a sealing resin 134 for sealing the electronic components 17 and 18 is formed, then the adhesive 102 and the support 101 are removed, and then the electrode pads 62, 63, 65, and 66 of the electronic components 17 and 18 are By forming the multilayer wiring structure 15 so that the wiring patterns 33 to 35 are directly connected to each other, the electronic component and the wiring pattern are connected via the bumps or the metal wires. As compared with the conventional semiconductor device with electrically connected, it can be reduced in size in the thickness direction of the size of the semiconductor device 131.

また、電子部品１７，１８に設けられた電極パッド６２，６３，６５，６６と配線パターン３３〜３５とを直接接続することにより、電子部品１７，１８と配線パターン３３〜３５とを接続するバンプ（例えば、はんだバンプ）が不要となるため、配線パターン３３〜３５（具体的には、ビア４５，４６，５１，５６及び配線４７，５３，５８）を微細かつ高密度に形成することができる。   Further, the bumps for connecting the electronic components 17 and 18 and the wiring patterns 33 to 35 by directly connecting the electrode pads 62, 63, 65 and 66 provided on the electronic components 17 and 18 and the wiring patterns 33 to 35. Since (for example, solder bumps) are not required, the wiring patterns 33 to 35 (specifically, vias 45, 46, 51, and 56 and wirings 47, 53, and 58) can be formed finely and with high density. .

なお、本実施の形態では、多層配線構造体１５を形成後に、電子部品１７，１８の薄板化を行った場合を例に挙げて説明したが、図２０に示す工程の後に、研磨により電子部品１７，１８の薄板化を行い、次いで、支持体１０１を除去し、その後、多層配線構造体１５を形成してもよい。   In the present embodiment, the case where the electronic components 17 and 18 are thinned after the multilayer wiring structure 15 is formed has been described as an example. However, after the step shown in FIG. 17 and 18 may be thinned, and then the support 101 may be removed, and then the multilayer wiring structure 15 may be formed.

また、外部接続端子３９は、電子部品１７，１８の薄板化後に形成してもよい。   Further, the external connection terminal 39 may be formed after the electronic components 17 and 18 are thinned.

以上、本発明の好ましい実施の形態について詳述したが、本発明はかかる特定の実施の形態に限定されるものではなく、特許請求の範囲内に記載された本発明の要旨の範囲内において、種々の変形・変更が可能である。   The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to such specific embodiments, and within the scope of the present invention described in the claims, Various modifications and changes are possible.

例えば、第１及び第２の実施の形態の半導体装置１１，１３１では、２つの電子部品（電子部品１７，１８）を設けた場合を例に挙げて説明したが、多層配線構造体１５上に配置される電子部品の数はこれに限定されない。つまり、多層配線構造体１５上に配置される電子部品の数は、１つでもよいし、３つ以上でもよい。   For example, in the semiconductor devices 11 and 131 according to the first and second embodiments, the case where two electronic components (electronic components 17 and 18) are provided has been described as an example. The number of electronic components arranged is not limited to this. That is, the number of electronic components arranged on the multilayer wiring structure 15 may be one, or three or more.

１０，１３０ 電子装置
１１，１２，１３１ 半導体装置
１３ 内部接続端子
１６，８１ 多層配線構造体
１７，１８，８３ 電子部品
１７Ａ，１８Ａ 背面
１７Ｂ，１８Ｂ 電極パッド形成面
１９ 絶縁部材
１９Ａ，４１Ａ，４２Ａ，９１Ａ，１０１Ａ，１０２Ａ，１３３Ａ，１３４Ａ 上面
１９Ｂ，４１Ｂ，４２Ｂ，９１Ｂ，１３３Ｂ，１３４Ｂ 下面
２１〜２３ 貫通電極
２４ 外部接続端子
２７ 積層体
３１−１，３１−２，３１−３，３１−４ 外部接続用パッド
３１−１Ａ，３１−２Ａ，３１−３Ａ，３１−４Ａ 接続面
３３〜３６，９６ 配線パターン
３８，９８，９９ ソルダーレジスト層
３８Ａ，３８Ｂ，３８Ｃ，３８Ｄ，９８Ａ，９９Ａ，１１１〜１１７，１２１〜１２４ 開口部
４１，４２ 絶縁層
４５，４６，４８，５１，５２，５４，５６，５７，５９，６１，６３ ビア
４７，５３，５８，６２ 配線
６２，６３，６５，６６，１００ 電極パッド
６２Ａ，６３Ａ，６５Ａ，６６Ａ 接続面
７１〜７３，１３６〜１３８ 貫通孔
８４ 金属ワイヤ
８５ モールド樹脂
９１ 基板本体
９３，９４ パッド
１０１ 支持体
１０２ 接着剤
１４１ 貫通部 DESCRIPTION OF SYMBOLS 10,130 Electronic device 11, 12, 131 Semiconductor device 13 Internal connection terminal 16, 81 Multilayer wiring structure 17, 18, 83 Electronic component 17A, 18A Back surface 17B, 18B Electrode pad formation surface 19 Insulating member 19A, 41A, 42A, 91A, 101A, 102A, 133A, 134A Upper surface 19B, 41B, 42B, 91B, 133B, 134B Lower surface 21-23 Through electrode 24 External connection terminal 27 Laminate 31-1, 31-2, 31-3, 31-4 External Connection pads 31-1A, 31-2A, 31-3A, 31-4A Connection surfaces 33 to 36, 96 Wiring patterns 38, 98, 99 Solder resist layers 38A, 38B, 38C, 38D, 98A, 99A, 111 to 117 121-124 Openings 41, 42 Insulating layers 45, 46, 48, 51, 52 54, 56, 57, 59, 61, 63 Via 47, 53, 58, 62 Wiring 62, 63, 65, 66, 100 Electrode pad 62A, 63A, 65A, 66A Connection surface 71-73, 136-138 Through-hole 84 Metal wire 85 Mold resin 91 Substrate body 93, 94 Pad 101 Support body 102 Adhesive 141 Penetration part

Claims (9)

電極パッドが設けられた電極パッド形成面、及び該電極パッド形成面の反対側に位置する背面を有する半導体チップと、
前記電極パッド形成面を露出する第１の面、及び前記背面を露出する第２の面を有すると共に、前記第１の面から前記第２の面にかけて貫通し、前記半導体チップが収納された貫通部を有する絶縁部材と、
前記半導体チップの側面を封止するよう前記貫通部内に設けられた封止樹脂と、
前記絶縁部材の第１の面上及び前記電極パッド形成面上に積層された複数の絶縁層と配線パターンを有する多層配線構造体と、
前記絶縁部材を前記第１の面から前記第２の面にかけて貫通する貫通電極と、を有し、
複数の前記絶縁層は、前記第１の面及び前記電極パッド形成面を直接被覆する第１絶縁層を含み、
複数の前記配線パターンは、前記第１絶縁層の前記半導体チップと反対側の面上に設けられた配線と、前記第１絶縁層内に設けられたビアとが一体に形成された第１配線パターンを含み、
前記第１配線パターンの前記ビアが、前記電極パッド及び前記貫通電極と直接接続され、
前記絶縁部材の前記第１の面と、前記貫通電極の前記第１の面側の端面と、前記電極パッドの接続面とが面一であり、
前記半導体チップの前記電極パッド形成面と前記封止樹脂の前記第１の面側の端面とが面一である半導体装置。 A semiconductor chip having an electrode pad forming surface provided with electrode pads and a back surface located on the opposite side of the electrode pad forming surface;
A first surface that exposes the electrode pad formation surface and a second surface that exposes the back surface, and penetrates from the first surface to the second surface and accommodates the semiconductor chip. An insulating member having a portion;
A sealing resin provided in the through-hole to seal the side surface of the semiconductor chip;
A multilayer wiring structure having a plurality of insulating layers and a wiring pattern laminated on the first surface of the insulating member and the electrode pad forming surface;
A through electrode penetrating through the insulating member from the first surface to the second surface,
The plurality of insulating layers include a first insulating layer that directly covers the first surface and the electrode pad forming surface,
The plurality of wiring patterns include a first wiring in which a wiring provided on a surface of the first insulating layer opposite to the semiconductor chip and a via provided in the first insulating layer are integrally formed. Including patterns,
The via of the first wiring pattern is directly connected to the electrode pad and the through electrode ;
The first surface of the insulating member, the end surface on the first surface side of the through electrode, and the connection surface of the electrode pad are flush with each other,
The semiconductor chip of the electrode pad forming surface and the end surface of the first surface of the sealing resin and is flush der Ru semiconductor device. 前記多層配線構造体の最上層に、前記第１配線パターンと電気的に接続された外部接続用パッドが設けられている請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein an external connection pad electrically connected to the first wiring pattern is provided on an uppermost layer of the multilayer wiring structure. 前記絶縁部材の前記第２の面に露出する前記貫通電極の端面が、外部接続用の面である請求項１又は２記載の半導体装置。   3. The semiconductor device according to claim 1, wherein an end surface of the through electrode exposed on the second surface of the insulating member is a surface for external connection. 前記第１絶縁層には、前記貫通電極の端面と前記半導体チップの電極パッドを露出する開口部が設けられており、
前記ビアは、前記開口部内に設けられている請求項１乃至３の何れか一項記載の半導体装置。 The first insulating layer is provided with an opening exposing the end face of the through electrode and the electrode pad of the semiconductor chip,
The semiconductor device according to claim 1, wherein the via is provided in the opening. 前記絶縁部材の前記第２の面側の前記貫通電極の端面が、前記絶縁部材の前記第２の面及び前記半導体チップの背面に対して面一となるように形成されている請求項１乃至４の何れか一項記載の半導体装置。   The end surface of the through electrode on the second surface side of the insulating member is formed so as to be flush with the second surface of the insulating member and the back surface of the semiconductor chip. 5. The semiconductor device according to claim 4. 支持体の第１の面に接着剤を形成した後、電極パッドが設けられた電極パッド形成面、及び該電極パッド形成面の反対側に位置する背面を有する半導体チップを、前記支持体の第１の面と前記電極パッドの接続面とが触るよう、前記支持体上に接着する半導体チップ接着工程と、
前記支持体の第１の面に形成した前記接着剤上に、前記半導体チップの側面を封止する絶縁部材を形成する絶縁部材形成工程と、
前記半導体チップの背面側から、前記半導体チップ及び前記絶縁部材を研削することにより、前記半導体チップ及び前記絶縁部材を薄板化する研削工程と、
前記絶縁部材及び前記接着剤を貫通する貫通孔を形成する貫通孔形成工程と、
前記貫通孔を充填する貫通電極を形成する貫通電極形成工程と、
前記貫通電極形成工程後に、前記接着剤及び前記支持体を除去する支持体除去工程と、
前記電極パッド形成面上、及び該電極パッド形成面側に配置された前記絶縁部材の面上に複数の絶縁層と配線パターンを積層して多層配線構造体を形成する多層配線構造体形成工程と、を有し、
前記多層配線構造体形成工程では、前記電極パッド及び前記貫通電極と接続されるよう、前記配線パターンを形成する半導体装置の製造方法。 After forming the adhesive on the first surface of the support, the electrode pad forming surface on which the electrode pads are provided, and a semiconductor chip having a back surface positioned on the opposite side of the electrode pad forming surface, first of the support A semiconductor chip bonding step for bonding onto the support so that the surface of 1 and the connection surface of the electrode pad touch each other;
An insulating member forming step of forming an insulating member for sealing the side surface of the semiconductor chip on the adhesive formed on the first surface of the support;
Grinding the semiconductor chip and the insulating member by grinding the semiconductor chip and the insulating member from the back side of the semiconductor chip;
A through hole forming step of forming a through hole penetrating the insulating member and the adhesive ;
A through electrode forming step of forming a through electrode filling the through hole;
A support removing step for removing the adhesive and the support after the through electrode forming step;
A multilayer wiring structure forming step of forming a multilayer wiring structure by laminating a plurality of insulating layers and wiring patterns on the electrode pad forming surface and on the surface of the insulating member disposed on the electrode pad forming surface; Have
In the multilayer wiring structure forming step, the wiring pattern is formed so as to be connected to the electrode pad and the through electrode. 前記多層配線構造体形成工程では、前記電極パッド及び前記貫通電極と直接接続されるよう、前記配線パターンを形成する請求項６記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 6, wherein in the multilayer wiring structure forming step, the wiring pattern is formed so as to be directly connected to the electrode pad and the through electrode. 貫通部と、該貫通部の周囲に形成された貫通孔とを有する絶縁部材を、支持体の第１の面に形成する絶縁部材形成工程と、
前記貫通孔を充填する貫通電極を形成する貫通電極形成工程と、
電極パッドが設けられた電極パッド形成面、及び該電極パッド形成面の反対側に位置する背面を有する半導体チップを、前記支持体の第１の面と前記電極パッド形成面とが触るよう、前記貫通部から露出する前記支持体の第１の面に接着する半導体チップ接着工程と、
前記貫通部に、前記半導体チップを封止する封止樹脂を形成する封止樹脂形成工程と、
前記半導体チップの背面側から、前記半導体チップ、前記絶縁部材、前記封止樹脂、及び前記貫通電極を研削することにより、前記半導体チップを薄板化する研削工程と、
前記貫通電極及び前記封止樹脂が形成された後、前記支持体を除去する支持体除去工程と、
前記電極パッド形成面上、及び該電極パッド形成面側に配置された前記絶縁部材の面上に複数の絶縁層と配線パターンを積層して多層配線構造体を形成する多層配線構造体形成工程と、を有し、
前記多層配線構造体形成工程では、前記電極パッド及び前記貫通電極と接続されるよう、前記配線パターンを形成する半導体装置の製造方法。 An insulating member forming step of forming, on the first surface of the support, an insulating member having a through portion and a through hole formed around the through portion;
A through electrode forming step of forming a through electrode filling the through hole;
The first surface of the support and the electrode pad forming surface touch a semiconductor chip having an electrode pad forming surface provided with an electrode pad and a back surface located on the opposite side of the electrode pad forming surface. A semiconductor chip bonding step for bonding to the first surface of the support exposed from the penetrating portion;
A sealing resin forming step of forming a sealing resin for sealing the semiconductor chip in the penetrating portion;
From the back side of the semiconductor chip, a grinding step of thinning the semiconductor chip by grinding the semiconductor chip, the insulating member, the sealing resin, and the through electrode;
After the through electrode and the sealing resin are formed, a support removing step for removing the support,
A multilayer wiring structure forming step of forming a multilayer wiring structure by laminating a plurality of insulating layers and wiring patterns on the electrode pad forming surface and on the surface of the insulating member disposed on the electrode pad forming surface; Have
In the multilayer wiring structure forming step, the wiring pattern is formed so as to be connected to the electrode pad and the through electrode. 前記多層配線構造体形成工程では、前記電極パッド及び前記貫通電極と直接接続されるよう、前記配線パターンを形成する請求項８記載の半導体装置の製造方法。   9. The method of manufacturing a semiconductor device according to claim 8, wherein in the multilayer wiring structure forming step, the wiring pattern is formed so as to be directly connected to the electrode pad and the through electrode.
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