JP5672793B2 - Semiconductor device and method for controlling semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a method for controlling the semiconductor device.

  In recent years, there has been an increasing number of cases in which LSIs (Large Scale Integrated circuits) equipped with a power cut-off function (also referred to as Power Gating) are employed due to the demand for low power consumption.

  Such a semiconductor device is equipped with a power switch, and shuts off the leakage current by turning off the power switch during a time period (circuit stop period) when the internal circuit is not used. The power cut-off function is widely used in portable devices for communication and the like that are demanding to reduce power consumption during standby.

  Note that if the power switch is frequently turned on or off, the current consumption increases due to the current that flows during switch control. Therefore, if the circuit stop period that can be turned off is short, the power switch is not turned off so that the total power consumption is reduced. Techniques for reducing power are known.

  When the power switch is turned on from the off state, an inrush current flows to start recharging the power capacity of the internal circuit. When this inrush current passes through the power supply wiring inside the semiconductor device, the impedance of the power supply wiring responds and power supply noise is generated. Power supply noise can adversely affect circuits in the semiconductor device. For this reason, a technique for suppressing the generation of power supply noise by slowly performing a switch-on operation to suppress an inrush current is known.

JP 2009-231360 A JP 2008-218722 A JP 2008-65732 A

  However, there is a problem that the conventional power shut-off function cannot sufficiently reduce power consumption. For example, if the power cut-off function that does not turn off the power switch when the circuit stop period is short is applied, the system that has many short circuit stop periods has fewer opportunities to turn off the power switch, and the power consumption cannot be reduced sufficiently. was there.

  According to one aspect of the invention, a power switch for switching whether to supply power to a circuit and a circuit operation schedule are input, and a start time or an end of the circuit operation period so that a plurality of circuit operation periods are continuous There is provided a semiconductor device including a circuit operation schedule correction unit that corrects time and a power switch control unit that turns on or off the power switch according to the corrected circuit operation schedule.

  According to the disclosed semiconductor device and the semiconductor device control method, power consumption can be reduced.

It is a figure which shows an example of the semiconductor device of 1st Embodiment. 3 is a flowchart illustrating an example of the operation of the semiconductor device according to the first embodiment. It is a figure which shows an example of a circuit operation schedule. It is a figure which shows an example of correction | amendment of a circuit operation schedule. It is a figure which shows an example of the power consumption according to the operation state of a circuit. It is a figure which shows an example of the semiconductor device of 2nd Embodiment. 6 is a flowchart illustrating an example of the operation of the semiconductor device according to the second embodiment. It is a figure which shows an example of the determination reference time Tmin. It is a figure which shows an example of the semiconductor device of 3rd Embodiment. It is a figure which shows an example of the power consumption according to the circuit operation at the time of use environment high temperature. It is a figure which shows an example of the power consumption according to the circuit operation at the time of a use environment low temperature. It is a figure which shows an example of a leak current detector. It is a timing chart which shows operation | movement of an example of a leak current detector. It is a figure which shows an example of a power switch, and the detail of the peripheral part. It is a timing chart which shows the example of a measurement of a power supply return period. It is a figure which shows an example of a Tmin generator. It is a figure which shows an example of a circuit operation schedule holding | maintenance part. It is a timing chart which shows an example of operation | movement of a circuit operation schedule holding | maintenance part. It is a figure which shows an example of a power switch control schedule register. It is a timing chart which shows the mode of operation of an example of a power switch control schedule register. It is a figure which shows an example of a circuit operation schedule. It is a figure which shows an example of circuit schedule correction | amendment, and an example of scheduled time data. It is a figure which shows an example of correction | amendment of the circuit operation schedule in four circuits, and an example of scheduled time data. 6 is a diagram illustrating an example of input / output data of a circuit operation schedule correction unit when a circuit operation schedule is corrected for the circuit 60. FIG. It is a figure which shows an example of operation | movement of PMU. It is the flowchart which put together an example of operation | movement of PMU. It is a figure which shows an example of the semiconductor device of 4th Embodiment. It is a flowchart which shows the flow of a task production | generation process. It is a figure which shows an example of the produced | generated task sequence.

Embodiments of a semiconductor device and a semiconductor device control method according to the present invention will be described below with reference to the drawings.
(First embodiment)
FIG. 1 is a diagram illustrating an example of the semiconductor device according to the first embodiment.

  The semiconductor device 10 according to the first embodiment includes a power switch 12 that switches whether to supply power VDD to the circuit 11, a circuit operation schedule holding unit 13, a circuit operation schedule correction unit 14, and a power switch control unit. 15.

The power switch 12 is on / off controlled under the control of the power switch control unit 15, and supplies the power voltage from the power supply VDD to the circuit 11 when the power switch 12 is in the on state.
The circuit operation schedule holding unit 13 holds a circuit operation schedule such as an operation period or a stop period of the circuit 11.

  The circuit operation schedule correction unit 14 inputs a circuit operation schedule and corrects the start time or end time of the circuit operation period so that a plurality of circuit operation periods included in the circuit operation schedule are continued.

The power switch control unit 15 turns the power switch 12 on or off according to the corrected circuit operation schedule.
Hereinafter, the operation of the semiconductor device 10 will be described.

FIG. 2 is a flowchart illustrating an example of the operation of the semiconductor device according to the first embodiment.
Step S1: The circuit operation schedule holding unit 13 receives a circuit operation schedule from, for example, a microcontroller (not shown) outside the semiconductor device 10 or an internal circuit 11 (or another circuit (not shown)). And hold.

FIG. 3 is a diagram illustrating an example of a circuit operation schedule. The horizontal axis indicates time.
In FIG. 3, a plurality of circuit operation periods are indicated by tasks Tsk1, Tsk2, Tsk3, Tsk4, and Tsk5. Further, the startable times TS1, TS2, TS3, TS4, TS5 of the scheduled tasks Tsk1 to Tsk5, end deadlines times TC1, TC2, TC3, TC4, TC5, and processing times TD1, TD2, TD3, TD4, TD5 An example is shown. The time between each task is a circuit stop period Tsp1, Tsp2, Tsp3, Tsp4.

  The circuit operation schedule holding unit 13 holds startable times TS1 to TS5, end deadline times TC1 to TC5, and processing times TD1 to TD5 of the tasks Tsk1 to Tsk5 as described above.

Step S2: The circuit operation schedule correction unit 14 corrects the circuit operation schedule.
FIG. 4 is a diagram illustrating an example of correction of the circuit operation schedule. The horizontal axis indicates time. Here, a case where the circuit operation schedule shown in FIG. 3 is corrected is shown.

  The correction of the circuit operation schedule is performed so that the circuit operation period of each task Tsk1 to Tsk5 is included from the startable time TS1 to TS5 to the end deadline time TC1 to TC5 determined in each task Tsk1 to Tsk5.

  In the example illustrated in FIG. 4, the circuit operation schedule correction unit 14 corrects the start time and end time of the circuit operation period indicated by the task Tsk2 so as to be continuous with the circuit operation period indicated by the task Tsk3. Since the correction of the task Tsk2 is performed between the start possible time TS2 of the task Tsk2 and the end deadline time TC2, the restriction is satisfied.

  Similarly, the circuit operation schedule correction unit 14 corrects the start time and end time of the circuit operation period indicated by the task Tsk4 so as to be continuous with the circuit operation period indicated by the task Tsk5. Since the correction of the task Tsk4 is performed between the start possible time TS4 of the task Tsk4 and the end deadline time TC4, the restriction is satisfied.

  By such correction, the circuit stop period between the task Tsk1 and the task Tsk2 is extended to Tsp1 + Tsp2. Further, the circuit stop period between the task Tsk3 and the task Tsk4 extends to Tsp3 + Tsp4.

Step S3: Next, the power switch controller 15 turns the power switch 12 on or off according to the corrected circuit operation schedule.
According to the circuit operation schedule corrected in the process of step S2, a plurality of circuit operation periods are continued, so that the number of operations of the power switch 12 can be reduced. For example, in the case of the example shown in FIG. 4, if the circuit operation period of tasks Tsk2 and Tsk3 is continued, the power switch 12 is turned off between the tasks Tsk2 and Tsk3, and then turned on, the operation becomes unnecessary.

Thereby, when the power switch 12 is turned on from off, energy loss (see FIG. 5 described later) when the power is restored can be reduced, and power consumption can be reduced.
(Second Embodiment)
The circuit stop period between tasks as shown in FIGS. 3 and 4 includes a power shut-off period and a power return period required to turn on the power to execute the next circuit operation period.

FIG. 5 is a diagram illustrating an example of power consumption according to the operation state of the circuit. The horizontal axis represents time, and the vertical axis represents power consumption.
FIG. 5 shows power consumption during two circuit operation periods, a power shut-off period Toff during the circuit stop period, and a power recovery period Ton. Of the regions 20 and 21 indicated by hatching, the region 20 indicates energy Er obtained by cutting off the power supply to the circuit. A region 21 indicates energy Em that is lost due to electric power generated when the power is restored.

  By turning off the power switch during the circuit stop period, if the energy Er obtained during the power shut-off period Toff is smaller than the energy Em consumed when the power is restored, the power consumption can be suppressed without turning off the power switch.

In the semiconductor device of the second embodiment described below, the power switch is controlled in consideration of the power recovery period Ton in the circuit stop period as shown in FIG.
FIG. 6 is a diagram illustrating an example of a semiconductor device according to the second embodiment.

The same elements as those of the semiconductor device 10 according to the first embodiment shown in FIG.
The semiconductor device 30 according to the second embodiment includes a determination reference time generation unit 31 that generates a determination reference time Tmin as to whether or not to turn on the power switch 12 during a circuit stop period.

  The determination reference time generation unit 31 has a reference circuit stop period in which the energy gain (energy Er) in the power cut-off period in the circuit stop period as shown in FIG. 5 is equal to the energy loss (energy Em) in the power return period. It is generated as the determination reference time Tmin.

  The circuit operation schedule correction unit 14a receives the determination reference time Tmin generated by the determination reference time generation unit 31, and, for example, the circuit stop period and the determination reference time of the circuit operation schedule corrected as shown in FIG. Compare with Tmin. Then, the circuit operation schedule correction unit 14a determines whether or not to turn off the power switch 12 during the circuit stop period.

  The power switch control unit 15a turns the power switch 12 on or off according to the correction result of the circuit operation schedule by the circuit operation schedule correction unit 14a and the determination as to whether or not to turn on the power switch 12 during the circuit stop period.

Hereinafter, the operation of the semiconductor device 30 will be described.
FIG. 7 is a flowchart illustrating an example of the operation of the semiconductor device according to the second embodiment.
Step S5: The process of step S5 is the same as the process of step S1 shown in FIG. 2, and the circuit operation schedule holding unit 13 receives and holds the circuit operation schedule.

Step S6: The determination reference time generator 31 generates and outputs a determination reference time Tmin.
FIG. 8 is a diagram illustrating an example of the determination reference time Tmin. The horizontal axis represents the circuit stop period Tsp, and the vertical axis represents energy.

The energy Em consumed during the power recovery period Ton shown in FIG. 5 can be expressed as Em = Cp × Vdd ^{2 where} the value of the power supply capacity of the circuit 11 is Cp and the power supply voltage is Vdd. In addition, the energy Er obtained by power shutoff during the power shutoff period Toff can be expressed as Er = Vdd × Ioff × Toff, where Ioff is the leakage current of the circuit 11 when the power is not shut off.

  Here, Toff_min can be expressed as Toff_min = Cp × Vdd / Ioff, where Toff_min is a power cutoff period Toff where Er = Em (intersection of energy Em and Er shown in FIG. 8). Therefore, the determination reference time Tmin can be expressed as Tmin = Ton + VDD × Cp / Ioff from Tmin = Ton + Toff_min.

  Step S7: For example, as shown in FIG. 4, the circuit operation schedule correction unit 14a corrects the circuit operation schedule so that a plurality of circuit operation periods are continued, and the power switch 12 is turned on / off during the circuit stop period. To decide.

  Specifically, the circuit operation schedule correction unit 14a receives the determination reference time Tmin generated by the determination reference time generation unit 31, and corrects the circuit operation schedule as shown in FIG. And the determination reference time Tmin. When the circuit stop period is longer than the determination reference time Tmin, the circuit operation schedule correction unit 14a determines that the power consumption reduction effect is higher when the circuit 11 is turned off, and turns off the power switch 12. The information of is output. On the contrary, when the circuit stop period is equal to or less than the determination reference time Tmin, the circuit operation schedule correction unit 14a determines that the power consumption increases instead of shutting off the power supply of the circuit 11, and indicates that the power switch 12 is not turned off. Output.

  Step S8: Thereafter, the power switch control unit 15a turns on the power switch 12 according to the determination of whether or not to turn off the power switch 12 during the circuit stop period, together with the correction result of the circuit operation schedule in the circuit operation schedule correction unit 14a. Control.

  Note that the determination reference time generation process of step S6 may be performed before the process of step S5. As will be described later, the determination reference time generation process is controlled by, for example, a unique timer.

  The semiconductor device 30 as described above has the same effect as the semiconductor device 10 of the first embodiment. Further, in the semiconductor device 30, the determination reference time is generated in consideration of the energy lost in the power recovery period in the circuit stop period, and it is determined whether or not the power switch 12 should be turned off based on that. It is possible to reduce the probability of making an erroneous decision to turn off.

  In the semiconductor device 30, one circuit stop period can be extended by correcting the circuit operation schedule. Therefore, the opportunity to turn off the power switch 12 during the circuit stop period is increased, and the power consumption can be further reduced. Become.

(Third embodiment)
Hereinafter, a semiconductor device capable of reducing power consumption will be described in more detail as a third embodiment.

FIG. 9 is a diagram illustrating an example of a semiconductor device according to the third embodiment.
The semiconductor device 50 of the third embodiment includes circuits 60, 61, 62, 63, power switches 70, 71, 72, 73, and a PMU (Power Management Unit) 80. On / off control is possible independently for .about.63. The number of power switches and circuits is not limited to four.

  The PMU 80 includes a circuit operation schedule holding unit 81, a circuit operation schedule correction unit 82, a power switch control schedule register 83, a determination reference time generation unit 84, and a power switch control unit 85.

  The power switches 70 to 73 are on / off controlled by control signals ga, gb, gc, gd output from the power switch control unit 85, respectively. Further, the power switches 70 to 73 have a function of notifying the PMU 80 of the end of the ON operation by the notification signals ea, eb, ec, and ed.

For example, the circuit operation schedule holding unit 81 inputs and holds circuit operation schedule information as task information Tsk from an external microcomputer (not shown).
The circuit operation schedule correction unit 82 corrects the circuit operation schedule held in the circuit operation schedule holding unit 81 so that, for example, a plurality of circuit operation periods are continued as shown in FIG. Further, the circuit operation schedule correction unit 82 inputs the determination reference time Tmin generated by the determination reference time generation unit 84, and compares the circuit stop period in the circuit operation schedule with the determination reference time Tmin. Then, the circuit operation schedule correction unit 82 determines whether to turn off the power switches 70 to 73 during the circuit stop period. The circuit operation schedule correction unit 82 plans to perform on / off control of the power switches 70 to 73 based on the corrected circuit operation schedule and the content determined whether or not to turn off the power switches 70 to 73 during the circuit stop period. Generate time data. The circuit operation schedule correction unit 82 stores the scheduled time data in the power switch control schedule register 83.

  The power switch control schedule register 83 stores scheduled time data for on / off control of the power switches 70 to 73, and further supplies the power switches 70 to 73 to the power switch control unit 85 according to the stored scheduled time data. An on / off instruction signal is supplied. The power switch control schedule register 83 also supplies the above-described on / off instruction signal to the determination reference time generation unit 84.

The determination reference time generation unit 84 includes a leak current detector 84a, a Ton measurement unit 84b, and a Tmin generator 84c.
The leak current detector 84a detects a leak current Ioff that occurs in the current circuit 60 to 63 during the circuit stop period using a simulation circuit that simulates the generation of the leak current in the circuits 60 to 63. Furthermore, the leak current detector 84a calculates the power cutoff period Toff_min in which the energy Er and the energy Em described above are equal from the leak current Ioff.

  The Ton measuring unit 84b receives an on / off instruction signal from the power switch control schedule register 83, and receives notification signals ea, eb, ec, ed from the power switches 70-73. Then, the time from when the on / off instruction signal is input to when the notification signals ea, eb, ec, ed are input is output as the power recovery period Ton.

  The Tmin generator 84c outputs, as the determination reference time Tmin, the sum of the power cutoff period Toff_min in which the energy Er and the energy Em are equal and the power recovery period Ton as shown in FIG.

  The power switch control unit 85 generates control signals ga, gb, gc, and gd in response to the on / off instruction signal from the power switch control schedule register 83, and controls the power switches 70 to 73 on and off.

  The power supply VDD is connected to the power switches 70 to 73 and the PMU 80 and supplied with the power supply voltage Vdd. The reference power supply VSS is connected to the circuits 60 to 63 and the PMU 80.

  The clock signal clk is input to the PMU 80. Each part of the PMU 80 operates in synchronization with the clock signal clk. In addition, the actual operation start signal go input to the PMU 80 causes the PMU 80 to perform processing before the actual circuit operation (preparation stage) such as holding and correction of the circuit operation schedule, or to perform actual circuit operation. This is a signal for designating whether or not to be performed (details will be described later). The actual operation start signal go is input from, for example, an external microcomputer (not shown).

Hereinafter, the details of the main part of the semiconductor device 50 will be described.
(Details of leak current detector 84a)
First, the reason for considering the leakage current Ioff in generating the determination reference time Tmin will be described.

  FIG. 10 is a diagram illustrating an example of power consumption according to circuit operation when the usage environment is high. FIG. 11 is a diagram illustrating an example of power consumption corresponding to circuit operation when the usage environment is low. 10 and 11, the upper graph shows the power consumption when the power switches 70 to 73 are turned on even during the circuit stop period, and the lower graph shows the power consumption when the power switches 70 to 73 are turned off during the circuit stop period. It shows a state. The horizontal axis represents time, and the vertical axis represents power consumption.

  The leakage current Ioff varies greatly depending on the usage environment (particularly temperature) of the circuits 60 to 63. For example, when the usage environment is high, the leakage current Ioff is large, and the energy Er is large as shown in the lower side of FIG. Therefore, it is better to turn off the power switch 70 to 73 so that the energy Er is not consumed than to keep the power switch 70 to 73 turned on during the circuit stop period. On the other hand, when the usage environment is low, the leakage current Ioff is small, and as shown in the lower side of FIG. 11, the energy Er is small, and the loss energy Em is large. Therefore, it is better to keep the power switches 70 to 73 on as shown in the upper side of FIG. 11 than to turn off the power switches 70 to 73 during the circuit stop period.

That is, in generating the determination reference time Tmin, it is desirable to consider the leakage current Ioff that varies depending on the operating environment.
FIG. 12 is a diagram illustrating an example of a leak current detector.

  The leak current detector 84a has a timer 90, a differential amplifier 91, a counter 92, and a capacitor Cpd. Furthermore, the leak current detector 84a includes p-channel MOSFETs (Metal-Oxide Semiconductor Field Effect Transistors) (hereinafter referred to as PMOS transistors) Pct and Pmd, and n-channel MOSFETs (hereinafter referred to as NMOS transistors) Nmd.

  The capacitance Cpd is a simulation of the power supply capacity of the circuits 60 to 63, and is set to a capacity value of about 1/100 of the actual power supply capacity, for example. The capacitor Cpd is connected between the negative input terminal (hereinafter referred to as the monitor terminal prem) of the differential amplifier 91 and the reference power supply VSS.

  The NMOS transistor Nmd and the PMOS transistor Pmd function as a simulation circuit that simulates the circuits 60 to 63 through which the leakage current Ioff flows. The NMOS transistor Nmd and the PMOS transistor Pmd are designed to generate a leakage current that is about 1/100 of the actual leakage current Ioff, for example.

  The drain of the NMOS transistor Nmd is connected to the monitor terminal prem, and the source and gate are connected to the reference power supply VSS. The source and gate of the PMOS transistor Pmd are connected to the monitor terminal prem, and the drain is connected to the reference power supply VSS.

  The PMOS transistor Pct is for charging (precharging) the capacitor Cpd as a preparatory stage for measuring the power cutoff period Toff_min in which the energy Er and the energy Em are equal. The source of the PMOS transistor Pct is connected to the power supply VDD, and the signal cnt from the timer 90 is input to the gate. The drain is connected to the monitor terminal prem.

  The timer 90 generates a signal cnt of an L level pulse of one shot periodically (for example, at a rate of about once per second) in order to follow the temperature change of the leakage current value, etc., and the PMOS transistor Pct and Output to the counter 92.

  When measuring the power cutoff period Toff_min, the differential amplifier 91 detects whether or not the capacitor Cpd is sufficiently discharged (discharged) by a leak current flowing through the NMOS transistor Nmd and the PMOS transistor Pmd. Then, the differential amplifier 91 outputs the result to the counter 92 as a signal mout. The positive input terminal of the differential amplifier 91 is connected to the reference power supply VSS.

  The counter 92 measures the time from when the signal cnt from the timer 90 changes from L level to H level until the signal mout is inverted. Specifically, the counter 92 receives the clock signal clk, and the number of clocks from when the signal cnt transitions to the H level until the signal mout is inverted is defined as a power cutoff period Toff_min in which the energy Er and Em are equal. Output.

FIG. 13 is a timing chart showing the operation of an example of the leak current detector. From the top, the signal cnt, the potential of the monitor terminal prem, and the state of the signal mout are shown.
First, when the timer 90 outputs a one-shot L-level pulse signal cnt, the PMOS transistor Pct is turned on during the pulse period, and the capacitor Cpd connected to the monitor terminal prem is charged to the power supply voltage Vdd. . As a result, the potential of the monitor terminal prem is raised. Thereafter, when the signal cnt returns to the H level, the PMOS transistor Pct is turned off, the charge of the capacitor Cpd starts to be discharged by the leakage current of the PMOS transistor Pmd and the NMOS transistor Nmd, and the potential of the monitor terminal prem starts to decrease.

  When the potential of the monitor terminal prem drops to a predetermined level (for example, a reference potential), the differential amplifier 91 detects it and inverts the signal mout. As shown in FIG. 13, the leakage current is large at a high temperature, the potential of the monitor terminal prem is quickly lowered, and the signal mout is inverted earlier than at a low temperature. Therefore, the power cutoff period Toff_min at the high temperature is shorter than that at the low temperature.

When the timer 90 outputs the signal cnt of the L level pulse for one shot again, the same processing is performed.
(Details of the power switch 70, the Ton measuring unit 84b, and the power switch control unit 85)
FIG. 14 is a diagram illustrating an example of a power switch and details of the peripheral portion thereof.

  Here, an example of the power switch 70 provided between the circuit 60 and the power supply VDD is shown. Similar circuits are used for the other power switches 71 to 73. Although not shown in FIG. 9, the capacitor CpA indicates the power supply capacitor of the circuit 60.

  The power switch 70 is divided into a plurality of PMOS transistors sw1, sw2, sw3, sw4,. A control signal ga from the power switch controller 85 is input to the gates of the PMOS transistors sw1 to swn after being delayed by one or a plurality of delay circuits 93, and the timing at which the PMOS transistors sw1 to swn are turned on is shifted. ing. As a result, the inrush current (charging current to the capacitor CpA) when the power is turned on is controlled so as not to flow at once.

FIG. 15 is a timing chart showing an example of measurement of the power recovery period.
FIG. 15 shows the on / off instruction signal order_a of the circuit 60 from the power switch control schedule register 83 shown in FIG. 9 and the gate signals of the PMOS transistors sw1 to swn.

  A clock signal clk (not shown in FIG. 15) and an on / off instruction signal order_a are input to the Ton measuring unit 84b. The power switch controller 85 also receives an on / off instruction signal order_a.

  The Ton measuring unit 84b has the same counter as the leak current detector 84a as shown in FIG. 12, and when an on / off instruction signal order_a for turning on the circuit 60 is input as shown in FIG. Start counting. On the other hand, at this time, the power switch control unit 85 outputs an L level control signal ga. The control signal ga is input to the gate of the PMOS transistor sw1, and is delayed by the delay circuit 93 and input to the gates of the PMOS transistors sw2 to swn. As a result, the PMOS transistors sw1 to swn on the left side in FIG. 14 are sequentially turned on, and the capacitor CpA is slowly charged so that power supply noise does not occur.

  When the signal input to the gate of the PMOS transistor swn becomes L level, all the PMOS transistors sw1 to swn are turned on, and the operation of the circuit 60 is started.

  Further, a signal input to the PMOS transistor swn is input to the Ton measuring unit 84b as the notification signal ea. The Ton measurement unit 84b stops counting when the notification signal ea becomes L level, and outputs the count result as the power supply return period Ton_a of the circuit 60. That is, the Ton measuring unit 84b outputs a value normalized with the period of the clock signal clk as the power recovery period Ton_a.

(Details of Tmin generator 84c)
FIG. 16 is a diagram illustrating an example of a Tmin generator.
The Tmin generator 84c includes adders 94a, 94b, 94c, and 94d.

  The Tmin generator 84c inputs the power cutoff period Toff_min from the leak current detector 84a, and inputs the power recovery periods Ton_a, Ton_b, Ton_c, Ton_d of the circuits 60 to 63 from the Ton measuring unit 84b.

  The adder 94a adds the power cutoff period Toff_min and the power recovery period Ton_a of the circuit 60, and outputs a determination reference time Tmin_a. The adder 94b adds the power cutoff period Toff_min and the power recovery period Ton_b of the circuit 61, and outputs a determination reference time Tmin_b. The adder 94c adds the power cutoff period Toff_min and the power recovery period Ton_c of the circuit 62, and outputs a determination reference time Tmin_c. The adder 94d adds the power cutoff period Toff_min and the power recovery period Ton_d of the circuit 63, and outputs a determination reference time Tmin_d.

As described above, the Tmin generator 84c generates the determination reference time Tmin as shown in FIG. 8 for each of the circuits 60 to 63.
(Details of the circuit operation schedule holding unit 81)
FIG. 17 is a diagram illustrating an example of the circuit operation schedule holding unit.

  The circuit operation schedule holding unit 81 includes task register groups rg1, rg2, rg3, and rg4 that hold circuit operation schedules of the circuits 60 to 63. For example, the task register group rg1 is used for the circuit 60, the task register group rg2 is used for the circuit 61, the task register group rg3 is used for the circuit 62, and the task register group rg4 is used for the circuit 63.

  Each of the task register groups rg1 to rg4 holds startable times TS1 to TSn, processing times TD1 to TDn, and end deadline times TC1 to TCn of the tasks N1, N2, N3,.

FIG. 18 is a timing chart illustrating an example of the operation of the circuit operation schedule holding unit.
The circuit operation schedule holding unit 81 receives the task information Tsk from, for example, an external microcomputer (not shown) during the period when the actual operation start signal go is at the L level. At this time, startable times TS1 to TSn, processing times TD1 to TDn, and end deadline times TC1 to TCn are received as task information Tsk in order from the first task N1 every clock. When the reception of the task information Tsk for the circuit 60 is completed, the task information Tsk for the circuits 61, 62, and 63 is similarly received. The received task information Tsk is sequentially held in the registers of the corresponding task register groups rg1 to rg4. When the actual operation start signal go becomes H level, the circuit operation schedule holding unit 81 stops receiving the task information Tsk and holds the information of the task register groups rg1 to rg4.

(Details of power switch control schedule register 83)
FIG. 19 is a diagram illustrating an example of the power switch control schedule register.
The power switch control schedule register 83 includes register groups srg1, srg2, srg3, srg4, a real-time counter 95, and data comparators 96a, 96b, 96c, and 96d.

  The register group srg1 holds a time value included in the scheduled switch-on / off time data pln_a of the power switch 70 output from the circuit operation schedule correction unit 82. The register group srg2 holds a time value included in the scheduled time data pln_b for turning on / off the power switch 71. The register group srg3 holds a time value included in the scheduled time data pln_c for turning on / off the power switch 72. The register group srg4 holds a time value included in the scheduled time data pln_d for switching on / off of the power switch 73.

  The scheduled time data pln_a, pln_b, pln_c, and pln_d are stored in the register groups srg1 to srg4 when the actual operation start signal go, which is the previous stage of the actual circuit operation, is at the L level.

  When the actual operation start signal go becomes H level, the real time counter 95 inputs the count value count to the data comparators 96a, 96b, 96c, and 96d via the count of the clock signal clk.

  The data comparators 96a, 96b, 96c, and 96d compare the switch on / off time values held in the registers RA1, RA2, RA3,..., RAn of the register groups srg1 to srg4 with the count value count. . When the two match, the data comparators 96a, 96b, 96c, 96d invert the on / off instruction signals order_a, order_b, order_c, order_d. That is, the data comparators 96a, 96b, 96c, and 96d instruct to turn on if the previous state of the power switches 70 to 73 is off, and turn off if the previous state is on. To do.

FIG. 20 is a timing chart showing the operation of an example of the power switch control schedule register.
FIG. 20 shows the state of the clock signal clk, the actual operation start signal go, the count value count, and the on / off instruction signal order_a output from the data comparator 96a. When the actual operation start signal go is at L level, the real-time counter 95 is stopped and the count value count remains zero. At this time, the scheduled time data pln_a, pln_b, pln_c, and pln_d are stored in the register groups srg1 to srg4.

  When the actual operation start signal go becomes H level, the real time counter 95 starts operation, and the count value count is incremented in synchronization with the clock signal clk. For example, when the count value count reaches any one of the registers RA1 to RAn of the register group srg1, the data comparator 96a inverts the on / off instruction signal order_a. In the example of FIG. 20, when the count value count reaches the values of the registers RA1, RA2, and RA3, the on / off instruction signal order_a is changed from the state instructing to turn off from the state instructing to turn off. It is reversed to the state that indicates ON. When the actual operation start signal go becomes L level, the real-time counter 95 is reset, and the on / off instruction signal order_a is instructed to turn off.

  In this way, according to the time value stored in the power switch control schedule register 83, the power switch control unit 85 performs the actual on / off operation of the power switches 70 to 73.

(Details of the circuit operation schedule correction unit 82)
Hereinafter, an example of the circuit operation schedule based on the task information Tsk held in the circuit operation schedule holding unit 81 is shown.

FIG. 21 is a diagram illustrating an example of a circuit operation schedule.
The horizontal axis is time. FIG. 21 shows a circuit operation schedule when the tasks N1 to N4 are executed in the circuits 60 to 63, respectively. In FIG. 21, the shaded area indicates a scheduled circuit stop period.

  When there are many short circuit stop periods, there is a possibility that the determination reference time Tmin, which is a reference for turning off the power switches 70 to 73, is not exceeded, and the opportunity for turning off the power switches 70 to 73 may be reduced.

  Therefore, the circuit operation schedule correction unit 82 corrects the start time and end time of the circuit operation period so that a plurality of tasks are continued as shown in FIG. This extends the circuit stop period. As described above, there are restrictions in correcting the start time and end time. In other words, there is a constraint that processing is started between the task startable times TS1 to TSn and end deadline times TC1 to TCn received by the task information Tsk, data processing is performed, and processing is ended. The circuit operation schedule is corrected within this constraint.

FIG. 22 is a diagram illustrating an example of circuit schedule correction and an example of scheduled time data.
The horizontal axis is time. An example of circuit operation schedule correction is shown on the upper side of FIG. The circuit operation schedule correction unit 82 corrects the data processing to be performed continuously with the even-numbered tasks N4 and N6 by delaying the start time and end time of the odd-numbered tasks N3 and N5.

  Based on the circuit operation schedule corrected in this way, the circuit operation schedule correction unit 82 compares each circuit stop period with the determination reference time Tmin. The circuit operation schedule correction unit 82 generates scheduled time data pln_a, pln_b, pln_c, and pln_d for turning off the power switches 70 to 73 during a circuit stop period longer than the determination reference time Tmin. The circuit operation schedule correction unit 82 generates scheduled time data pln_a, pln_b, pln_c, and pln_d for keeping the power switches 70 to 73 turned on during a circuit stop period shorter than the determination reference time Tmin.

  In the example shown on the lower side of FIG. 22, the scheduled time data pln_a for the circuit 60 is shown. In the example shown in FIG. 22, it is determined that the circuit stop period Tsp2 + Tsp3 is longer than the determination reference time Tmin, and the scheduled time data pln_a for turning off the power switch 70 is generated. On the other hand, the circuit stop period Tsp4 + Tsp5 is determined to be shorter than the determination reference time Tmin, and the scheduled time data pln_a for keeping the power switch 70 on is generated.

  When the power switch 70 returns from the off state to the on state, the circuit operation schedule correction unit 82 schedules the power switch 70 to be turned on earlier than the start time of each task by the power return period Ton_a. By doing so, for example, the data processing of the task N2 can be started smoothly without delay from the intended start time of the second task N2 in FIG.

FIG. 23 is a diagram illustrating an example of correction of a circuit operation schedule and an example of scheduled time data in four circuits.
The horizontal axis is time. On the upper side of FIG. 23, a correction example of the circuit operation schedule in the circuits 60 to 63 is shown. An example is shown in which the tasks N1 and N2 and the tasks N3 and N4 are corrected so as to be performed successively. On the lower side of FIG. 23, an example of scheduled time data pln_a, pln_b, pln_c, and pln_d is shown. As described above, when returning from the off state to the on state, the power switches 70 to 73 are scheduled to be turned on earlier by the power return periods Ton_a, Ton_b, Ton_c, and Ton_d.

  When the circuit stop periods Tspa, Tspb, Tspc, and Tspd are set between the task N2 and the task N3, the circuit operation schedule correction unit 82 sets these and the determination reference times Tmin_a, Tmin_b, Tmin_c, and Tmin_d in the circuits 60 to 63. Compare.

  In the example of FIG. 23, a case where Tspa> Tmin_a, Tspb> Tmin_b, Tspc> Tmin_c, and Tspd> Tmin_d is shown. In this case, the circuit operation schedule correction unit 82 outputs the scheduled time data pln_a for turning off the power supply of the circuit 60 during the circuit stop period Tspa of the circuit 60. The circuit operation schedule correction unit 82 outputs scheduled time data pln_b and pln_d for turning off the power supply to the circuits 61 and 63 during the circuit stop periods Tspb and Tspd of the circuits 61 and 63. On the other hand, the circuit operation schedule correction unit 82 outputs the scheduled time data pln_c that keeps the power supply of the circuit 62 turned on during the circuit stop period Tspc of the circuit 62.

FIG. 24 is a diagram illustrating an example of input / output data of the circuit operation schedule correction unit when the circuit operation schedule is corrected with respect to the circuit 60.
The circuit operation schedule correction unit 82 calculates startable times TS1 to TSn, processing times TD1 to TDn, and end deadline times TC1 to TCn of the tasks N1 to Nn stored in the task register group rg1 as shown in FIG. input. Then, for example, the circuit operation schedule correction unit 82 delays the start times of the tasks N1 and N3 so that the end times of the odd-numbered tasks N1 and N3 are continuous with the start times of the next tasks N2 and N4.

  The start time of data processing in a task is TCm-TDm for the mth task (m is an odd number). As a result of the correction, the circuit stop period per time is extended. For example, as shown in FIG. 24, the circuit stop period Tspa that occurs from the end time of task N2 to the start time of task N3 is Tspa = TC3-TD3-TS2-TD2.

  Whether or not to turn off the power switch 70 for this circuit stop period Tspa is determined according to the comparison result with the determination reference time Tmin_a. As shown in FIG. 24, when Tspa> Tmin_a, the circuit operation schedule correction unit 82 schedules the power switch 70 to be turned off.

Further, the circuit operation schedule correction unit 82 stores the scheduled time data pln_a in consideration of the power recovery period Ton_a of the circuit 60 in the power switch control schedule register 83.
In the case of the example illustrated in FIG. 24, the circuit operation schedule correction unit 82 sets TC1-TD1-Ton_a as the power switch control schedule register as illustrated in FIG. 19 as the time when the circuit 60 is turned on to execute the task N1. It is stored in the register RA1 of 83. Further, the circuit operation schedule correction unit 82 stores TS2 + TD2 in the register RA2 of the power switch control schedule register 83 as the time at which the task N2 ends and the circuit 60 is turned off. Further, the circuit operation schedule correction unit 82 stores TC3-TD3-Ton_a in the register RA3 of the power switch control schedule register 83 as the time when the circuit 60 is turned on to execute the task N3. Further, the circuit operation schedule correction unit 82 stores TS4 + TD4 in the register RA4 of the power switch control schedule register 83 as the time at which the task N4 ends and the circuit 60 is turned off.

  In the above description, the start time of the odd-numbered task is delayed. However, the start time and the end time may be corrected so that the even-numbered task is continuously executed with the odd-numbered task.

The overall operation of the PMU 80 in the semiconductor device 50 of the present embodiment will be briefly described below.
FIG. 25 is a diagram illustrating an example of the operation of the PMU.

  The horizontal axis is time. In FIG. 25, a hatched period 100 is a period during which a preparatory stage operation is performed, and the above-described actual operation start signal go is at an L level. In this period 100, the task information Tsk is received, the circuit operation schedule correction unit 82 performs scheduling, and the like. A period 101 between the hatched periods 100 is a period in which an actual circuit operation is performed, and an actual operation start signal go is an H level period. In this period 101, the power switches 70 to 73 are turned on / off according to the scheduled circuit operation schedule, and the processing of each task is performed by the circuits 60 to 63. In both periods 100 and 101, the PMU 80 operates in synchronization with the clock signal clk.

FIG. 26 is a flowchart summarizing an example of the operation of the PMU.
Step S10: The circuit operation schedule holding unit 81 receives the task information Tsk and stores it in the register.

  Step S11: The determination reference time generation unit 84 generates the determination reference time Tmin by adding the calculation result of the power cut-off period Toff_min in which the energy Er, Em is equal to the power supply return period Ton. The process of step S11 is independently controlled by the timer 90 of the leak current detector 84a, and the determination reference time Tmin is updated.

  Step S12: The circuit operation schedule correction unit 82 corrects the circuit operation schedule based on the task information Tsk. Then, the circuit operation schedule correction unit 82 generates scheduled time data for turning on / off the power switches 70 to 73 according to the comparison result between the determination reference time Tmin and the corrected power-off period of the circuit operation schedule. The generated scheduled time data is stored in the power switch control schedule register 83 as shown in FIG.

  Step S13: The power switch control schedule register 83 determines whether or not the actual operation start signal go is at the H level. Here, when the actual operation start signal go is at the L level, the processing from step S10 is repeated.

  Step S14: When the actual operation start signal go becomes H level, the power switch control schedule register 83 operates the real time counter 95, and sends an on / off instruction signal according to the scheduled time data held in the register. 85. The power switch control unit 85 turns on or off the power switches 70 to 73 by the control signals ga, gb, gc, and gd according to the on / off instruction signal.

  Step S15: The power switch control schedule register 83 determines whether or not the actual operation start signal go is at the H level. Here, when the actual operation start signal go remains at the H level, the process of step S14 is continued. When the actual operation start signal go becomes L level, the operation of the real time counter 95 is stopped and the processing from step S10 is repeated again.

  As described above, according to the semiconductor device 50 of the present embodiment, by repeating the circuit operation period between a plurality of tasks, the number of operations of the power switches 70 to 73 can be reduced and energy loss can be reduced. Power consumption can be reduced. Further, since it is possible to control to extend the circuit stop period per one time, the opportunity to switch off the power switches 70 to 73 in each circuit stop period increases, and further power consumption can be reduced.

  In addition, when generating the reference time Tmin for determining whether or not to switch off the power switches 70 to 73 during the circuit stop period, the power switch 70 to 73 is determined to be switched off by considering the power recovery period Ton. The probability of error can be lowered.

  In the semiconductor device 50 described above, the circuit operation schedule (task information) is received from the outside of the semiconductor device 50. However, a circuit generated by an internal circuit may be used.

Hereinafter, such a semiconductor device will be described as a fourth embodiment.
(Fourth embodiment)
FIG. 27 is a diagram illustrating an example of a semiconductor device according to the fourth embodiment.

  In the semiconductor device 50a of the fourth embodiment, unlike the semiconductor device 50 shown in FIG. 9, a circuit 60a inside the semiconductor device 50a generates task information Tsk and an actual operation start signal go. In the present embodiment, for example, the circuit 60a functions as a master and the circuits 61 to 63 function as slaves.

Hereinafter, task generation processing by the circuit 60a will be described.
FIG. 28 is a flowchart showing the flow of task generation processing.
Step S20: The circuit 60a receives the data processing request information via the user interface (user I / F).

  Step S21: The circuit 60a performs task division processing based on the received data processing request information. Here, the circuit 60a provides the above-described startable time and end deadline time for each task, and calculates the processing time of each task in consideration of the data processing capability of the slave circuits 61-63.

Step S22: The circuit 60a generates a task sequence according to the result of the task division process.
FIG. 29 is a diagram illustrating an example of the generated task sequence.

  The circuit 60a generates task sequences 110, 111, 112, and 113 for the circuits 60a and 61 to 63, respectively. Each of the task columns 110 to 113 includes startable times TS1 to TS3, processing times TD1 to TD3, and end deadline times TC1 to TC3 of the tasks N1 to N3.

  Step S23: The circuit 60a issues an L-level actual operation start signal go, and transfers task sequences 110 to 113 as shown in FIG. 29 to the circuit operation schedule holding unit 81 as task information Tsk.

  According to the semiconductor device 50a of the fourth embodiment as described above, the same effects as those of the first to third semiconductor devices 10, 30, and 50 described above can be obtained, and task information Tsk is provided outside the semiconductor device 50a. It is not necessary to provide a microcomputer or the like for generating the data.

As described above, one aspect of the semiconductor device and the method for controlling the semiconductor device of the present invention has been described based on the embodiments, but these are merely examples and are not limited to the above description.
The following additional notes are disclosed with respect to the plurality of embodiments described above.

(Supplementary note 1) a power switch for switching whether to supply power to the circuit;
A circuit operation schedule correction unit that inputs a circuit operation schedule and corrects a start time or an end time of the circuit operation period so as to continue a plurality of circuit operation periods;
A power switch controller for turning on or off the power switch according to the corrected circuit operation schedule;
A semiconductor device comprising:

  (Additional remark 2) The said circuit operation schedule correction | amendment part correct | amends the said start time or the said end time so that the said circuit operation period may be included from the predetermined start possible time to the end time limit. 1. The semiconductor device according to 1.

(Supplementary Note 3) A reference circuit stop period in which the energy gain during the power-off period by turning off the power switch and the energy loss during the power recovery period are equal is output as a reference time for determining whether to turn off the power switch. A determination reference time generation unit to
The circuit operation schedule correction unit determines whether to turn off the power switch during the circuit stop period according to a comparison result between the determination reference time and the corrected circuit stop period of the circuit operation schedule. The semiconductor device according to appendix 1 or 2, wherein:

  (Additional remark 4) The said determination reference time production | generation part produces | generates the said determination reference time according to the said leak current using the simulation circuit which simulates generation | occurrence | production of the leak current in the said circuit. Semiconductor device.

  (Additional remark 5) The said circuit operation schedule correction | amendment part correct | amends the said circuit operation schedule so that the ON operation of the said power switch may be started earlier by the power supply return period of the said circuit from the said start time. 5. The semiconductor device according to any one of 4.

(Supplementary note 6) The semiconductor device according to any one of supplementary notes 3 to 5, wherein the determination reference time generation unit includes a timer and periodically updates the determination reference time.
(Supplementary note 7) The semiconductor device according to any one of supplementary notes 1 to 6, further comprising a circuit that generates the circuit operation schedule.

(Supplementary Note 8) The circuit operation schedule correction unit inputs the circuit operation schedule, corrects the start time or the end time of the circuit operation period so that a plurality of circuit operation periods are continued,
A method of controlling a semiconductor device, wherein the power switch control unit turns on or off a power switch that switches whether to supply power to the circuit according to the corrected circuit operation schedule.

(Supplementary Note 9) Whether or not the determination reference time generation unit turns off the power switch during a reference circuit stop period in which the energy gain in the power cut-off period due to turning off the power switch is equal to the energy loss in the power recovery period Is output as the judgment reference time,
The circuit operation schedule correction unit determines whether to turn off the power switch during the circuit stop period according to a comparison result between the determination reference time and the corrected circuit stop period of the circuit operation schedule. The method for controlling a semiconductor device according to appendix 8, wherein:

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Circuit 12 Power switch 13 Circuit operation schedule holding | maintenance part 14 Circuit operation schedule correction | amendment part 15 Power switch control part

Claims (6)

A power switch for switching whether to supply power to the circuit;
Type the first circuit operation schedule, as described above plurality of circuit operation period included in the first circuit operation schedule continuous, second circuit operation schedule obtained by correcting the start time or end time of the circuit operation period A circuit operation schedule correction unit for generating
According to the previous SL second circuit operation schedule, a power switch controller for turning on or off the power switch,
A semiconductor device comprising: A determination reference time for outputting a reference circuit stop period in which the energy gain in the power cut-off period by turning off the power switch and the energy loss in the power recovery period are equal as the reference time for determining whether to turn off the power switch Having a generator,
The circuit operation schedule correcting section determines said reference time, before SL in accordance with the comparison result of the circuit stop period of the second circuit operation schedule, whether to turn off the power switch to the circuit outage The semiconductor device according to claim 1.   3. The semiconductor device according to claim 2, wherein the determination reference time generation unit generates the determination reference time according to the leak current using a simulation circuit that simulates generation of a leak current in the circuit. The circuit operation schedule correcting section to claim 1, characterized in that to correct the first circuit operating schedule to initiate the power supply recovery period earlier on the operation of the power switch of the circuit than the start time The semiconductor device described.   The circuit operation schedule correction unit corrects the first circuit operation schedule so as to start the ON operation of the power switch earlier than the start time by the power recovery period. The semiconductor device described. Circuit operation schedule corrector, enter the first circuit operation schedule, so that a plurality of circuit operation period included in the first circuit operation schedule consecutive correct the start time or end time of the circuit operation period Generated second circuit operation schedule ,
Control method of a semiconductor device power switch controller, according to the previous SL second circuit operation schedule, and wherein the turning on or off the power switch for switching whether to supply power to the circuit.

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