JP5665504B2 - Vertical cavity surface emitting laser and vertical cavity surface emitting laser array - Google Patents

Description

  The present invention relates to a vertical cavity surface emitting laser and a vertical cavity surface emitting laser array.

A vertical cavity surface emitting laser (VCSEL) is a laser that emits laser light in a direction perpendicular to a substrate.
This vertical cavity surface emitting laser has advantages such as low power consumption and easy two-dimensional array formation at high density, and is applied to optical communication, various sensors, electrophotographic light sources, etc. Has been put to practical use.
In general, a semiconductor laser increases efficiency and lowers a threshold value by concentrating a driving current in a narrow range.
In the case of a surface emitting laser manufactured on a GaAs substrate, a current confinement layer is often realized by disposing an AlGaAs layer having a large Al composition inside the mesa structure and partially oxidizing it from the lateral direction. .
Specifically, after forming the mesa structure, the AlGaAs layer is partially oxidized with high-temperature water vapor from the lateral direction, leaving only the central part of the mesa structure conductive, thereby confining the current to this part, Reduction and improved luminous efficiency.
As a feature of the current confinement structure by such oxidation confinement, an oxidized portion and a non-oxidized portion having greatly different electric resistances can be easily manufactured, and the leakage current can be lowered to a level that can be almost ignored. it can.
In addition, since the refractive index difference can be realized at the same time, there is also an optical confinement effect.

In the surface emitting laser of the red band, the active layer material is composed of an AlGaInP-based material having a gain in the red band, but the current confinement layer oxidizes the above-mentioned AlGaAs by configuring the upper and lower DBRs with an AlGaAs-based material. It can be realized by the technique.
For example, Non-Patent Document 1 discloses a red VCSEL having an AlGaInP-based active layer sandwiched between a p-type DBR and an n-type DBR made of an AlGaAs-based material.
The structure of the red VCSEL disclosed in Non-Patent Document 1 will be described with reference to FIG. An n-type lower DBR 1002 in which Al _0.95 Ga _0.05 As layers 1010 having an optical thickness of ¼ wavelength and Al _0.5 Ga _{0.5 As} 1011 are alternately stacked is provided on a GaAs substrate 1001.
Further, an n-type cladding layer 1020, an active layer 1019 composed of four GaInP quantum wells, and a p-type cladding layer 1021 are formed thereon.
On the p-type cladding layer 1021, an Al _0.5 Ga _0.5 As layer 1015 and a current confinement layer (hereinafter, the current confinement layer before oxidation is also referred to as “selective oxide layer”) 1016 are formed. This selective oxidation layer 1016 is partially oxidized from the lateral direction after the mesa structure is formed to form an oxidized portion 1017 and a non-oxidized portion 1018, thereby realizing a current confinement structure.
On this current confinement layer, a layer constituting a p-type upper DBR 1005 in which an Al _0.95 Ga _0.05 As layer 1012 having an optical thickness of ¼ wavelength and Al _0.5 Ga _0.5 As1013 are alternately stacked. Is provided.
A contact layer 1014 for making electrical contact with the electrode is disposed on the layers constituting these p-type upper DBRs 1005.
In the above description, the Al _0.5 Ga _0.5 As layer 1015 is expressed as a separate member from the upper DBR 1005. However, a layer including the Al _0.5 Ga _0.5 As layer 1015 and the current confinement layer 1016 is considered as a DBR. Also good.
In this way, by combining the AlGaAs DBR and the AlGaInP active layer, it is possible to realize a surface emitting laser that emits red light using a current confinement method using a selective oxidation layer peculiar to an AlGaAs material.

M.M. Saarinen, et al, Electronics Letters, vol. 36, no. 14, 2000, pp1210

As described above, the performance improvement can be realized by introducing the current confinement structure by the oxidation constriction.
However, in the configuration shown in FIG. 5, in the Al _0.5 Ga _0.5 As layer 1015, the current concentrated in the central portion in the current confinement layer 1016 spreads again in the lateral direction.
As a result, the current once confined in the current confinement layer 1016 spreads as the current confinement layer 1016 flows from the current confinement layer 1016 to the active layer 1019, resulting in a problem that the light emission efficiency is lowered.
These will be further described. The laser oscillation region has the same width as that of the non-oxidized portion 1018 in the current confinement layer 1016, and the light emission efficiency is obtained by concentrating the current in the central portion of the active layer 1019. Can be raised.
Here, the hole mobility of the AlGaInP material constituting the p-type cladding layer 1021 is about 20 cm ² / V · s. On the other hand, the electron mobility of holes in the Al _0.5 Ga _0.5 As layer 1015 is about 80 cm ² / V · s.
That is, the mobility of the material constituting the p-type cladding layer 1021 is very small compared to the mobility of the p-type Al _0.5 Ga _0.5 As layer 1015 formed thereon.

For this reason, the electrical resistivity of the p-type cladding layer 1021 is much larger than the electrical resistivity of the p-type Al _0.5 Ga _0.5 As layer 1015. Therefore, the current collected in the non-oxidized portion 1018 in the current confinement layer 1016 spreads greatly in the lateral direction when passing through the p-type Al _0.5 Ga _0.5 As layer 1015 between the current confinement layer 1016 and the p-type cladding layer 1021. .
Therefore, it becomes difficult to collect current at the center of the active layer 1019, and the light emission efficiency is lowered.

Therefore, in the present invention, in view of the above problems, the current once confined in the current confinement layer is
It is an object of the present invention to provide a vertical cavity surface emitting laser and a vertical cavity surface emitting laser array that can be prevented from spreading again as they flow from the current confinement layer to the active layer, thereby suppressing a decrease in light emission efficiency.

The vertical cavity surface emitting laser of the present invention is
A lower DBR layer formed on the substrate;
A lower cladding layer formed on the lower DBR layer;
An active layer formed on the lower cladding layer;
An upper cladding layer formed on the active layer;
A current confinement layer formed on the upper cladding layer;
An upper DBR layer formed on the current confinement layer;
And a heterogeneous conduction type layer which is disposed between the upper cladding layer and the current confinement layer and is a semiconductor layer having a conductivity type different from that of a semiconductor constituting the upper DBR. .
The vertical cavity surface emitting laser array of the present invention is characterized in that the above-described vertical cavity surface emitting lasers are arranged in a one-dimensional or two-dimensional array.

  According to the present invention, a vertical cavity surface emitting device in which a current once confined in a current confinement layer is prevented from spreading again as it flows from the current confinement layer to the active layer, and a decrease in light emission efficiency can be suppressed. Laser and vertical cavity surface emitting laser arrays can be realized.

The figure explaining the structural example of the vertical cavity surface emitting laser in Example 1 of this invention. (A) is a figure which shows layer structure. (B) is a figure which shows the relationship between a p-type clad layer, a dissimilar conduction layer, a non-oxidation part, and the depletion layer which arises in those interfaces. (C) is a figure which shows the relationship of the depletion layer which arises in an interface with an oxidation part. The figure which shows the calculation result of the doping density | concentration of the n layer in Example 1 of this invention, and the depletion layer width | variety made into an n-type layer. The figure explaining the structural example of the vertical cavity surface emitting laser in Example 2 of this invention. The figure explaining the structural example of the vertical cavity surface emitting laser in Example 3 of this invention. The figure explaining the vertical cavity surface emitting laser in a prior art example. The figure explaining the structural example of the vertical cavity surface emitting laser in Example 4 of this invention.

A configuration example of the vertical cavity surface emitting laser according to the embodiment of the present invention will be described.
The vertical cavity surface emitting laser of this embodiment is configured by laminating a plurality of semiconductor layers including a lower DBR layer, a lower cladding layer, an active layer, an upper cladding layer, a current confinement layer, and an upper DBR layer on a substrate. Has been.
Specifically, it has a layer structure as shown in FIG.
That is, as shown in FIG. 1A, a low refractive index layer 514 made of AlAs and a high refractive index layer 515 made of Al _0.5 Ga _0.5 As are alternately stacked on a GaAs substrate 501. An n-type lower DBR 502 is provided. The thickness of each layer constituting the lower DBR 502 is, for example, an optical thickness of λ / 4.
On the lower DBR 502, an n-type cladding layer 511, an active layer 513, and a p-type cladding layer 512 are formed. The active layer 513 includes a quantum well using, for example, GaInP. The n-type cladding layer 511 and the p-type cladding layer 512 are made of an AlGaInP-based material.
On the p-type cladding layer 512, a current confinement layer 525 is provided. The current confinement layer 525 has a portion (oxidized portion) 526 that has been oxidized to become an Al _x O _Y insulator, and a portion (non-oxidized portion) 527 that remains unoxidized. On the current confinement layer 525, a p-type in which a low refractive index layer 530 composed of an Al _0.9 Ga _0.1 As layer and a high refractive index layer 531 composed of an Al _0.5 Ga _0.5 As layer are alternately stacked. The upper DBR 505 is provided.
Further, a different conductivity type layer 520 is disposed between the current confinement layer 525 and the p-type cladding layer 512.
Here, the different conductivity type layer 520 is a conductivity type layer different from the conductivity type of the DBR 505. For example, if the DBR 505 is composed of a p-type semiconductor layer, the different conductivity type layer 520 is an n-type conductivity layer. It is a semiconductor layer. Further, the different conductivity type layer 520 may be an i-type semiconductor layer. Here, the i-type semiconductor layer is a semiconductor layer in which free carriers are less than a predetermined value, for example, less than 1 × 10 ¹⁷ cm ⁻³ . The i-type semiconductor layer includes not only a semiconductor having no dopant but also a semiconductor in which the carrier concentration is effectively reduced by doping the same amount of p and n dopants. It is.

In the case where the different conductivity type layer 520 is n-type, it is preferable that the depletion layer formed at the interface between both the different conductivity type layer 520 and the upper and lower p-type layers has a concentration at which the different conductivity layer 520 is connected. . This is because, by connecting the depletion layer, holes flowing from the non-oxidized portion 527 of the current confinement layer can move by the internal electric field and diffusion.
Further, by making the lower side of the oxidized portion 526 n-type, if a current flows through this portion, a current flows in the reverse direction of n−p, and the current becomes very difficult to flow.

When the different conductivity type layer 520 is i-type, carriers flowing out of the different conductivity type layer 520 need to diffuse to the p-type layer on the opposite active layer side, so the thickness of the different conductivity type layer 520 is the diffusion length. The following is preferable.
In this case, since the diffusion length does not depend on the doping concentration of the current confinement layer 525, there is no restriction on the relationship with the diffusion length.
However, since the electrical resistance of the non-oxidized portion 527 is not greatly increased even when carriers are diffused, the doping concentration normally used in the VCSEL, specifically, about 1 × 10 ¹⁸ cm ⁻³ remains. Is desirable.
For this reason, the doping concentration of the current confinement layer 525 differs depending on the volume ratio between the different conductivity type layer 520 and the current confinement layer 525, but is preferably 3 × 10 ¹⁸ cm ⁻³ or more.
The current confinement method is the current confinement method by selective oxidation in the above. Similarly, a current that disturbs the semiconductor crystallinity of the portion that suppresses the current (the portion oxidized by selective oxidation) like proton injection. Even with the stenosis technique, the effects of the present embodiment can be achieved.

According to the configuration of the present embodiment, holes flow from the current confinement layer to a layer (heterogeneous conductivity type layer) existing between the current confinement layer and the active layer, and the heterogeneous conductivity type layer becomes a depletion layer. Or p-type.
However, in the current confinement layer, the portion oxidized in the lateral direction (oxidized portion 526) is not a semiconductor, so that carriers cannot be supplied to the immediately different heteroconductive layer 520. As a result, the carrier can be supplied only to the central portion that is not oxidized. Therefore, the ease of current flow differs between the central portion and the peripheral portion in the different conductive layer 520, and the spread of current passing through the peripheral portion located below the oxidized portion 526 can be suppressed.
In addition, the said structure of this embodiment is a structure for achieving the subject of this invention that the carrier constricted by the current confinement layer spreads. Therefore, the above-described example of the red surface emitting laser using AlGaInP as the active layer material is an example, and the configuration of the present invention is applied when current spread occurs between the current confinement layer and the resonator. Thus, the effects of the present invention can be achieved.

[Example 1]
As Example 1, a configuration example of a vertical cavity surface emitting laser to which the present invention is applied will be described with reference to FIG.
FIG. 1A is a schematic cross-sectional view of a red surface emitting laser structure according to this example.
The surface emitting laser structure in this embodiment includes an n-type GaAs substrate 501 and an n-type lower DBR 502 composed of an n-type AlAs layer 514 / Al _0.5 Ga _0.5 A layer 515.
On the n-type lower DBR 502, an n-type cladding layer 511, an active layer 513 including four undoped Ga _0.45 In _0.55 P / AlGaInP quantum wells, and a p-type cladding layer 512 are provided. The optical length of these three layers is 2λ (λ: oscillation wavelength).
Further, a different conductivity type layer 520 is disposed between the p-type cladding layer 512 and the current confinement layer 525.
The different conductivity type layer 520 is doped with an n-type of 1 × 10 ¹⁸ cm ⁻³ , and the current confinement layer 525 thereon is doped with a p-type of 1 × 10 ¹⁸ cm ⁻³ . The p-type cladding layer 512 in contact with the different conductivity type layer 520 is doped to 1 × 10 ¹⁸ cm ⁻³ .
The current confinement layer 525 is formed by oxidizing Al _0.98 Ga _0.02 As having a thickness of 30 nm from the side wall of the mesa structure.
Further, on the current confinement layer 525, a p-type upper DBR 505 including 30 pairs of a p-type Al _0.9 Ga _0.1 As layer 530 and an Al _0.5 Ga _0.5 As layer 531 is disposed.

  A contact layer 507 made of highly doped GaAs having a thickness of 10 nm is disposed on the upper DBR 505, and an upper electrode 510 is disposed on the contact layer 507 to ensure electrical contact. A lower electrode 509 on the back surface of the substrate is provided below the GaAs substrate 501 to ensure electrical contact with the GaAs substrate 501.

Below, the effect | action of the current confinement by the different conductivity type layer 520 is demonstrated.
FIG. 2 shows the calculation results of the doping concentration of the p-type layer and the width of the depletion layer formed in the n-type layer. FIG. 1B shows the relationship between the p-type cladding layer 512, the different conductivity type layer 520, the non-oxidized portion 527, and the depletion layers 550 and 551 generated at the interface between them.
Further, the relationship among the different conductivity type layer 520, the p-type cladding layer 512, and the oxidized portion 526 is similarly shown in FIG.
As shown in FIG. 1B, the different conductivity type layer 520 (doping concentration 1 × 10 ¹⁸ cm ⁻³ ) and the non-oxidized portion 527 (doping concentration 1 × 10 ¹⁸ cm ⁻³ ) at the doping concentration of this example. A depletion layer 551 is formed on the pn junction surface. The width of the depletion layer in the different conductivity type layer 520 is about 36.4 nm (FIG. 2).
Of the depletion layer 550 generated by the different conductivity type layer 520 and the p-type cladding layer 512 (1 × 10 ¹⁸ cm ⁻³ ), the width of the depletion layer generated in the different conductivity type layer 520 is about 36.4 nm.
On the other hand, the physical thickness of the optical thickness of λ / 4 near 680 nm of Al _0.9 GaAs is 50 nm, and the different conductivity type layer 520 has this thickness.
Therefore, in FIG. 1B, when the current confinement layer 525 and the depletion layer extending from the p-type cladding layer 512 are combined, the different conduction type layer 520 is entirely a depletion layer.

On the other hand, as shown in FIG. 1C, a depletion layer does not occur between the oxidized portion 526 and the different conductivity type layer 520 under the oxidized portion 526.
This is because the oxidized portion 526 is not a single crystal semiconductor and cannot supply holes.
The width of the depletion layer 550 generated between the different conductivity type layer 520 and the p-type cladding layer 512 is about 36 nm in the different conductivity type layer 520. Therefore, the n-type portion remains in the different conductivity type layer 520.
In the depletion layer, since an electric field is generated in the crystal growth direction (direction perpendicular to the substrate surface), holes that have entered the depletion layer can be smoothly moved to the p-type cladding layer by the electric field.
On the other hand, no electric field is generated in the in-plane direction (the same in-plane direction as the substrate surface). Therefore, it is faster to proceed vertically than to spread horizontally, and the spread of holes in the lateral direction can be suppressed.

Further, in the heteroconductive layer 520, the portion immediately below the non-oxidized portion 527 is connected to the two depletion layers that can form pn junctions above and below the heteroconductive layer 520 as shown in FIG. It is preferable that all the different conductivity type layers 520 are depletion layers.
This is because the carriers injected into the depletion layer are accelerated by the electric field generated in the depletion layer and can smoothly escape to the p-type cladding layer 512.
For this purpose, it can be seen from FIG. 2 that it can be realized by appropriately setting within the range of the following conditions.
The doping concentration of the different conductivity type layer is 0.5 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ , and the surrounding p-type layer is 0.5 × 10 ¹⁸ cm ⁻³ to 3 × 10 ¹⁸ cm. Set ^-3 as appropriate.
As a result, the layer thickness of the different conductivity type layer is in the range from about 40 nm to about 120 nm, and a state immediately below the non-oxidized portion 527 is a depletion layer, and a portion of the n-type portion remains immediately below the oxidized portion 526. It is possible to make.

Hereinafter, a manufacturing procedure of the element in this example will be described.
First, the semiconductor layer configuration of the GaAs substrate 501, lower DBR 502, n-type cladding layer 511, active layer 513, p-type cladding layer 512, different conductivity type layer 520, upper DBR 505, and contact layer 507 is formed by metal organic chemical vapor deposition or Grows with molecular beam epitaxy.
A dielectric film is formed on the wafer by sputtering.
Thereafter, a circular pattern for determining the mesa diameter is made with a photoresist by using a semiconductor lithography method.
Here, using the photoresist pattern, the dielectric film is partially removed, and then the semiconductor layer is dug up to the active layer portion by dry etching so that the selective oxide layer (current confinement layer) is exposed.
Here, as the selective oxidation layer (current confinement layer), an Al _x Ga _1-x As (x> 0.9) and an oxide thereof can be used.
Then, this selective oxidation layer is oxidized to form a non-oxidized portion. Specifically, the Al _0.98 Ga _0.02 As selective oxidation layer (current confinement layer) 525 is oxidized from the lateral direction in a water vapor atmosphere at about 450 ° C., but at this time, the oxidation for controlling the current and light is controlled by controlling the oxidation time. Portions 526 and non-oxidized portions 527 are created.
The oxidation time is controlled so that the diameter of the non-oxidized portion 527 is about 6 micrometers.
Thereafter, the resist is peeled off, and a dielectric film for passivation is formed over the entire wafer using a plasma CVD method.
A resist pattern having a hole in a ring shape for exposing the contact layer is formed, and a portion where the dielectric film and the GaAs contact layer 507 are exposed is formed using the resist pattern.
A p-side electrode 510 and an n-side electrode 509 are formed using a vacuum deposition method and a lithography method.
The p-side electrode 510 is formed with a circular window for taking out. In order to obtain good electrical characteristics, the device is completed by alloying the electrode and the semiconductor in a high-temperature nitrogen atmosphere.
In this embodiment, a current confinement method by partially oxidizing the selective oxidation layer (current confinement layer) 525 is used as a current confinement method, but the method is not limited to such a method. Similarly, in other confinement methods, for example, proton injection may be used as long as the current confinement method disturbs the crystallinity of the semiconductor in the portion for suppressing current (the portion oxidized by selective oxidation).
The same applies to the following embodiments.

[Example 2]
As Example 2, a vertical cavity surface emitting laser in which different conductivity type layers are formed of i layers will be described with reference to FIG.
The surface emitting laser of this example is the same as that of Example 1 except that the conductivity type of the different conductivity type layer 620 and the doping concentration of the current confinement layer 625 are different from those of Example 1.
Therefore, the same reference numerals as those in the first embodiment are given to the same members.
In this embodiment, since the different conductivity type layer 620 is i-type, it is desirable from the viewpoint of electrical resistance that the layer thickness be less than the diffusion length of holes.
In this embodiment, the different conductivity type layer 620 is made of an AlGaAs semiconductor. Specifically, since it is made of Al _0.9 Ga _0.1 As, its hole diffusion length is about 430 nm.
Therefore, it is desirable that the layer thickness of the different conductivity type layer be 400 nm or less. Since the layer thickness of the different conductivity type layer 620 of this embodiment is about 50 nm, it is sufficiently smaller than the diffusion length and is in a more preferable range.

In addition, the doping concentration of the current confinement layer 625 is 3 × 10 ¹⁸ cm ^−3, which is higher than that of the first embodiment.
This is to maintain a certain carrier density in the current confinement layer 625 and improve electrical conductivity even when carriers diffuse into the different conductivity type layer.
Note that 626 and 627 in FIG. 3 are an oxidized portion and a non-oxidized portion of the current confinement layer 625, respectively.
The manufacturing procedure of the device in the present embodiment is the same as that of the first embodiment except that the different conductivity type layer 620 is grown instead of the different conductivity type layer 520 at the time of crystal growth.
In addition, the i layer in this embodiment is a case where the carrier concentration is effectively lowered by doping the same amount of the p and n dopants in addition to the semiconductor in which the dopant for making the p or n type is not added. Including.

[Example 3]
As Example 3, a configuration example of a vertical cavity surface emitting laser having a different form from each of the above examples will be described with reference to FIG.
The surface emitting laser structure in this embodiment includes an n-type GaAs substrate 701, an n-type lower DBR 702 composed of an n-type AlAs layer 714 and a GaAs layer 715 located above the GaAs substrate 701.
On the lower DBR 702, an n-type cladding layer 711 made of Al _0.5 Ga _0.5 As, an active layer 713 including three undoped In _0.18 GaAs / GaAs quantum wells, and a p-type cladding layer 712 made of Al _0.5 GaAs. Is formed. The optical length of these three layers is one wavelength of the oscillation wavelength λ. The p-type cladding layer 712 is doped to 1 × 10 ¹⁸ cm ⁻³ .
Further, a different conductivity type layer 720 is disposed on the p-type cladding layer 712.
The different conductivity type layer 720 is doped to an n-type of 1 × 10 ¹⁸ cm ⁻³ .
A current confinement layer 725 made of Al _0.98 Ga _0.02 As having a thickness of 30 nm is formed on the different conductivity type layer 720. The current confinement layer 725 is divided into an oxidized portion 726 and a non-oxidized portion 727. This current confinement layer 725 is doped to 1 × 10 ¹⁸ cm ⁻³ .
The current confinement layer 725 includes a p-type upper DBR 705 in which 22 pairs of a low-refractive index layer 730 made of p-type Al _0.9 Ga _0.1 As and a high-refractive index layer 731 made of GaAs are stacked. Yes.
A contact layer 707 made of highly doped GaAs having a thickness of 10 nm is in contact with the upper DBR 705.
An upper electrode 710 is provided on the contact layer 707 and is in electrical contact with the contact layer 707.
A lower electrode 709 is provided under the GaAs substrate 701.

Since the present embodiment is a vertical cavity surface emitting laser composed of an active layer using an AlGaAs material, the spread of current between the current confinement layer and the active layer is the same as in the first and second embodiments. Small compared.
However, since there is a semiconductor having uniform conductivity in the vertical direction and in-plane direction under the current confinement layer 725, the confined current spreads in the lateral direction.
Therefore, even when the electrical resistivity of the material constituting the DBR layer having the current confinement layer and the active layer material is not greatly different as in this embodiment, the different conductivity type layer is separated from the current confinement layer and the p-type cladding. By providing between the layers, it is possible to prevent the confined current from spreading again.
As a result, the current can be efficiently confined in the central portion of the surface emitting laser. In this embodiment, the surface emitting laser is in the 980 nm band, but it may be used in surface emitting lasers in other wavelength bands.

[Example 4]
As Example 4, a configuration example of a vertical cavity surface emitting laser will be described with reference to FIG.
The surface emitting laser of this example is the same as that of Example 1 except that the configuration of the different conductivity type layer is different from that of Example 1. Therefore, the same reference numerals as those in the first embodiment are given to the same members.
This embodiment is different from the first embodiment in that a p-type semiconductor layer 821 is provided between a heteroconductive layer 820 doped in n-type and a current confinement layer 525. That is, a semiconductor having the same conductivity type as that of the upper DBR may be provided between the different conductivity type layer and the current confinement layer.
Here, the conductivity type of the different conductivity type layer 820 is n-type, the doping concentration is 0.5 × 10 ¹⁸ cm ⁻³ , and the thickness is 110 nm. The conductivity type of the semiconductor layer 821 is p-type, the doping concentration is 0.5 × 10 ¹⁸ cm ⁻³ , and the thickness is 30 nm.
The reason why the semiconductor layer 821 is provided in this embodiment is to increase the distance between the current confinement layer 525 and the active layer 513.
As shown in FIG. 2, there is a limit to the width of the depletion layer formed on the pn junction surface. However, in the surface emitting laser, there is a case where it is desired to make the distance between the oxide confinement layer and the lower cladding layer larger than a general 1 / 4λ (the conventional example is also 1 / 4λ).
For example, when some kind of atomic diffusion or internal stress adversely affects the reliability of the device due to the current confinement layer, it is necessary to separate the current confinement layer from the lower cladding layer. In such a case, as in Example 1 while maintaining a certain doping concentration (eg, 0.5 × 10 ¹⁸ cm ⁻³ or more) in order to maintain good reproducibility of electrical resistance and crystal growth. It is difficult to realize a depletion layer width of 100 nm or more using a single layer of different conductivity type.
Therefore, as in this embodiment, the current confinement layer and the active layer are composed of a plurality of layers, and one of them is a layer having a conductivity type different from that of the upper DBR, whereby the distance between the current confinement layer and the active layer is set. Can be increased.

In this embodiment, a depletion layer is formed between the p-type cladding layer 512 and the different conductivity type layer 820. The thickness of the depletion layer formed in the different conductivity type layer 820 is as shown in FIG. Is about 60 nm.
In addition, the depletion layer formed between the different conductivity type layer 820 and the semiconductor layer 821 is uniform in each layer and becomes about 55 nm if each layer is sufficiently thick.
However, since the actual layer thickness of the semiconductor layer 821 is as thin as 30 nm, the supply of holes from the semiconductor layer 821 alone cannot make all of the different conductivity type layers 820 a depletion layer.
However, since the lower portion of the non-oxidized portion 527 has additional carrier supply from the non-oxidized portion 527, a depletion layer having an original thickness of 55 nm can be formed, and the inside of the different conductivity type layer 820 is completely depleted. can do.
On the other hand, since the lower portion of the oxidized portion 526 cannot supply additional carriers from the current confinement layer 525, the entire inside of the different conductivity type layer 820 cannot be a depletion layer, and a part of the n-type is formed. The part will remain.
As a result, the area between the active layer 513 and the current confinement layer 525 becomes a depletion layer only directly under the non-oxidized portion 527, and the spread of current can be suppressed as described in the first embodiment.

[Other Examples]
The vertical cavity surface emitting laser array described in the above embodiments may be arranged in a one-dimensional or two-dimensional array to form a vertical cavity surface emitting laser array.
Further, the doping amount and thickness of each semiconductor layer and the thickness of the depletion layer described above are merely examples, and the design can be changed as appropriate.
In addition, “B formed on A” does not necessarily require A and B to be in contact with each other.

501: substrate,
502: Lower DBR
505: Upper DBR
507: contact layer 509: lower electrode 510: upper electrode 511: lower cladding layer 512: upper cladding layer 513: active layer 514: low refractive index layer 515: high refractive index layer 520: heteroconductive layer 525: current confinement layer ( Oxidation selective layer)
526: oxidized portion 527: non-oxidized portion 530: low refractive index layer 531: high refractive index layer 550: depletion layer 551 generated at pn junction interface between 512 and 520 1: depletion layer generated at pn junction interface between 520 and 527

Claims (8)

A lower DBR layer formed on the substrate;
A lower cladding layer formed on the lower DBR layer;
An active layer formed on the lower cladding layer;
An upper cladding layer formed on the active layer;
A current confinement layer formed on the upper cladding layer;
A vertical cavity surface emitting laser having an upper DBR layer formed on the current confinement layer,
The portion including the center of the current confinement layer and the upper cladding layer are formed of a p-type or n-type semiconductor,
When the semiconductor that constitutes the portion including the center and the upper cladding layer is p-type, an n-type semiconductor layer is provided between the portion including the center of the current confinement layer and the upper cladding layer, In the case where the semiconductor forming the portion including the center and the upper cladding layer is n-type, a p-type semiconductor layer is provided between the portion including the center of the current confinement layer and the upper cladding layer. vertical cavity surface emitting laser characterized by there. The current confinement layer is composed of Al _X Ga _1-X As (x> 0.9) and an oxide of the Al _X Ga _1-X As (x> 0.9). Item 2. The vertical cavity surface emitting laser according to Item 1. A semiconductor conductivity type is p-type constituting the upper DBR layer, between portion and the upper clad layer that includes the center of the current confinement layer, and wherein Rukoto n-type semiconductor layer is not provided The vertical cavity surface emitting laser according to claim 1 or 2. A semiconductor layer provided between the portion and the upper clad layer that includes the center of the current confinement layer, between the current confinement layer, from the same conductivity type as the semiconductor conductivity type constituting the upper DBR layer The vertical cavity surface emitting laser according to claim 1, wherein a semiconductor layer is provided. 5. The semiconductor layer according to claim 1, wherein a semiconductor layer provided between a portion including the center of the current confinement layer and the upper clad layer is made of an AlGaAs semiconductor. Vertical cavity surface emitting laser. 4. The vertical cavity surface according to claim 3, wherein the semiconductor layer provided between the portion including the center of the current confinement layer and the upper cladding layer has a thickness of 40 nm to 120 nm. Light emitting laser. The layer thickness of the semiconductor layer provided between the portion including the center of the current confinement layer and the upper clad layer is an optical thickness (λ: oscillation wavelength) of λ / 4. Item 7. The vertical cavity surface emitting laser according to any one of Items 1 to 6 . The vertical cavity surface emitting laser according to any one of claims 1 7, 1-dimensional or a vertical cavity surface emitting laser, wherein a which are arranged in an array in a two-dimensional array.

Images