JP5661863B2 - System and method for data transfer in an execution device - Google Patents

Description

  The present disclosure relates generally to systems and methods for data transfer within an execution device.

  In a typical processor, instruction execution may require multiple stages. Within a program sequence, data dependent instructions are usually split and the result is written to a register before executing a second instruction that uses the result from the first instruction and the time that the first instruction is processed through each of the stages. Make time available. In this case, multiple data-independent instructions are used to divide the data-dependent instructions in the instruction sequence and allow time to create and save the results before the results are needed for subsequent instruction execution. . By dividing data-dependent instructions using data-independent instructions, the processor pipeline can be in full operation or close to it, and pipeline stalls can be reduced.

  Modern compilers try to reduce execution pipeline stalls by executing instructions out of sequence. In particular, data-independent instructions and / or instructions that are ready to execute are prior to instructions that are not yet ready (ie, data-dependent instructions whose data has not yet been determined by another executing instruction). Placed in. Typically, a compiler application can be used to recognize the data-dependent instruction, and the compiler application can include the data-dependent instructions in the program sequence by spacing the corresponding data-generating instructions in the program sequence. Can be organized to reduce pipeline stalls.

  In certain embodiments, in an execution pipeline in an interleaved multithreaded (IMT) processor having multiple execution units, writing to a register file by execution of a first instruction during a write back phase in the execution unit A method is disclosed that includes comparing a write identifier associated with a result to be read with a read identifier associated with a second instruction. When the write identifier matches the read identifier, the method further includes storing the result in the local memory of the execution device for use by the execution device in a subsequent read stage.

  In another particular embodiment, a method is disclosed that includes identifying a second address associated with a second instruction packet with a first address associated with the first instruction packet. The carry bit of the data device's adder is examined to determine if the second address has crossed the boundary of the cache line associated with the multi-directional cache. When the boundary is not crossed, the multi-directional cache is accessed and the second using the tag array data and translation index buffer (TLB) search data associated with the first address specified by the previous tag array search operation. Data is extracted from the address.

  In yet another specific embodiment, a multithreaded processor is disclosed that includes an execution device having a local memory that stores one or more data values. The execution device further includes logic circuitry adapted to determine whether the read address associated with the read operation matches the write back address associated with the previous write back operation. The logic circuit is adapted to store one or more data values in local memory when the read address matches the write back address.

  In yet another specific embodiment, in an execution pipeline in an interleaved multithreaded (IMT) processor having multiple execution units, a write identifier associated with a result written to a register file by execution of a first instruction packet is provided. , A processor including means for comparing with a read identifier associated with a second instruction packet is disclosed. The processor further includes means for selectively locally storing the result on the execution unit for use in executing the second instruction packet when the write identifier matches the read identifier.

  One particular advantage provided by an embodiment of a processor having data transfer logic and local memory is that the results from the execution of the first instruction are stored locally and the second instruction is executed without performing a register file read operation. It can be used when doing so. By selectively omitting the register file read operation, the power consumption of the register file can be reduced.

  Another particular advantage is that the tag array search operation can be selectively omitted when the second address of the second instruction is associated with the same cache line as the first address of the first instruction. In this example, the tag array search operation for the second address can be omitted, and the tag array information specified by the previous search operation associated with the first address can be reused. By selectively omitting the tag array search operation, overall power consumption can be reduced.

  Yet another unique advantage is that the same logic can be used to selectively transfer data and selectively omit tag array search operations and TLB search operations. In addition, the instruction packet is arranged using an assembler or compiler, the data is transferred (ie, intra-slot forwarding), the tag array information is reused (ie, the tag array search operation is omitted). And an opportunity for selective omission of TLB search operations. Such data transfer and selective omission of tag search operations and / or TLB search operations can reduce the total number of read operations and reduce power consumption.

  Other aspects, advantages and features of the present disclosure will become apparent after reviewing the entirety of the application, including the following brief description of the drawings, detailed description and claims section.

FIG. 1 is a block diagram illustrating a particular illustrative embodiment of a system that includes an execution device adapted to transfer data. FIG. 2 is a block diagram illustrating a particular illustrative embodiment of an execution device adapted to transfer data. FIG. 3 is a block diagram illustrating a specific embodiment of a system including a shared controller having a data transfer logic and a tag array search / transform index buffer (TLB) search skip logic. FIG. 4 illustrates a specific embodiment of a processor that includes programmable logic (PLC) adapted to selectively transfer data and selectively omit tag array search operations and translation index buffer (TLB) operations. FIG. FIG. 5 is a timing diagram illustrating an exemplary embodiment of a process in an execution pipeline adapted to transfer data. FIG. 6 is a diagram illustrating a specific illustrative embodiment of a transfer logic circuit in an execution pipeline. FIG. 7 is a timing diagram illustrating an exemplary embodiment of a process in an execution pipeline adapted to omit tag array search operations. FIG. 8 is a block diagram illustrating a system specific exemplary embodiment adapted to selectively transfer data and selectively omit a tag array search operation or a translation index buffer (TLB) search operation. . FIG. 9 is a flow diagram illustrating a specific illustrative embodiment of a method for transferring data within an execution device. FIG. 10 is a flow diagram illustrating a specific illustrative embodiment of a method for selectively omitting a tag sequence search operation. FIG. 11 is a flow diagram illustrating a specific illustrative embodiment of a method for selectively omitting a tag array search operation and / or a translation index buffer (TLB) search operation. FIG. 12 is a block diagram illustrating a particular illustrative embodiment of a communication device that includes an execution unit having a transfer logic circuit and a search skip logic circuit.

Detailed description

  FIG. 1 is a block diagram illustrating a particular illustrative embodiment of a processing system 100 that includes at least one execution unit having transfer logic and local memory. Processing system 100 includes memory 102 adapted to communicate with instruction cache 106 and data cache 112 via bus interface 104. Instruction cache 106 is coupled to sequencer 114 by bus 110. In addition, the sequencer 114 is adapted to receive an interrupt, such as a general purpose interrupt 116, that may be received from the interrupt register. The sequencer 114 is also coupled to a supervisory control register 132 and a global control register 134.

  In certain embodiments, instruction cache 106 is coupled to sequencer 114 via a plurality of current instruction registers, which may be coupled to bus 110 and associated with a particular thread of processing system 100. In certain embodiments, processing system 100 is an interleaved multithreaded processor that includes six threads.

  The sequencer 114 is coupled to the first instruction execution unit 118, the second instruction execution unit 120, the third instruction execution unit 122, and the fourth instruction execution unit 124. Each instruction execution unit 118, 120, 122, and 124 may be coupled to the general purpose register file 126 via the second bus 128. The general purpose register file 126 can also be coupled to the sequencer 114, the data cache 112 and the memory 102 via the third bus 130. The supervisory control register 132 and the global control register 134 can store bits that can be accessed by control logic in the sequencer 114 to determine whether to accept interrupts and to control instruction execution.

  The first execution device 118 includes a transfer logic circuit 136 and a local memory 138. The second execution device 120 includes a transfer logic circuit 140 and a local memory 142. The third execution unit 122 includes a transfer logic circuit 144 and a local memory 146. The fourth execution unit 124 includes a transfer logic circuit 148 and a local memory 150. Although each of execution units 118, 120, 122, and 124 is shown to include transfer logic (ie, transfer logic 136, 140, 144, 148, respectively), in certain embodiments, such as transfer logic 136, It should be understood that the transfer logic can be shared with other execution devices, such as execution devices 120, 122, and 124. For example, in certain embodiments, execution device 118 may include transfer logic 136 and local memory 138, and other execution devices 120, 122, and 124 may include local memory 142, 146 and 150, and transfer logic 136 can be shared. In certain embodiments, one or more of the execution devices 118, 120, 122 and 124 may share local memory. For example, execution devices 118 and 120 can share local memory 138, and execution devices 122 and 124 can share local memory 146. In another particular embodiment, transfer logic 136 may reside external to execution device 118 and may communicate with execution devices 118, 120, 122, and 124, including controller 406 of FIG. As illustrated for execution devices 408, 410, 412 and 414.

  In certain embodiments, the processing system 100 receives a first instruction packet that is executable by the execution devices 118, 120, 122, and 124, and receives a second instruction packet that depends on a result from the first instruction packet. It is adapted to. The first instruction packet can include four instructions, which can be provided to execution units 118, 120, 122 and 124. Execution units 118, 120, 122, and 124 can process instructions from the first instruction packet through multiple stages including a decode stage, a register file access stage, a multiple execution stage, and a write back stage. In the write back phase, the transfer logic 136 of the execution unit 118 may determine that the read address of the second instruction packet matches the write back address of the first instruction packet, and write back the data to the general register file 126. Sometimes stored locally in memory 138. In an alternative embodiment, execution unit 118 may decode at least a portion of the instructions in each received instruction packet to determine the read address and write back address for each instruction. The transfer logic circuit 136 compares the read address of the second packet with the write-back address of the first command packet, and transmits a data transfer control signal to other execution devices (such as the command execution devices 120, 122, and 124). Can be adapted to be stored locally (ie, in respective local memories 142, 146 and 150). Data can be retrieved from the memories 138, 142, 146 and 150 and used in executing instructions from the second (subsequent) instruction packet.

  In a particular example, transfer logic 136 can discover that the instruction in the second instruction packet uses the result from the first instruction packet. In particular, the first instruction writes data in the same location as the second instruction reads data. In this example, transfer logic 136 is adapted to locate that the result of the instruction in the first instruction packet is utilized by the instruction in the second instruction packet. As a non-limiting example for illustration, transfer logic 136 may receive signals from control logic (not shown) that can access future instructions via instruction cache 106 or sequencer 114. Or the transfer logic 136 can detect a transfer indicator such as a designated bit in the first packet that can be set by an assembler, compiler, sequencer 114 or other circuit, or the transfer logic 136 can Depending on the type of instruction, the use of the result of the instruction can be predicted at least in part. In another embodiment, the transfer logic circuit 136 can be configured to operate in a first mode in which all instruction results are stored locally for use by subsequent instructions, or in a second mode in which no instruction results are stored. In addition to writing the execution result to the general-purpose registration file 126 via the bus 128, the transfer logic circuit 136 causes the execution device 118 to store the result in the local memory 138. When a data dependent instruction from the second instruction packet is provided to the execution unit 118, the transfer logic 136 skips the register read operation, accesses the result stored in the local memory 138, and from the second instruction packet. The execution device 118 is caused to use the result when executing the instruction. Therefore, the execution device 118 uses the transfer logic circuit 136 to reduce the number of read operations for the general-purpose register file 126.

  By compiling the instruction packet so that the data dependent instructions are ordered in adjacent packets in the program sequence, the compiled application takes advantage of the transfer logic circuits 136, 140, 144, and 148 of the execution units 118, 120, 122, and 124. Power savings can be increased. Data generated by previous instructions can be stored in local memory 138, 142, 146 or 150, such as buffers, latches, flip-flops, local registers or other memory elements, to perform register reads for adjacent packets It can be used by neighboring packets without doing so. In an illustrative embodiment where data can be transferred between non-adjacent packets, the local memory 138, 142, 146 or 150 can store data while one or more intervening packets are being processed. Can include one or more registers for temporary local storage. In particular, by ordering the data-dependent instructions in adjacent instruction packets, the compiler increases the potential for data transfer, thereby increasing the number of skipped read operations and reducing overall power consumption.

In a particular example, execution unit 118 includes transfer logic 136 for transferring operands (and / or data) from one instruction packet to the next instruction packet. Such data transfer reduces the total number of register file read operations and reduces the overall power consumption of the register file. An example of a data dependent instruction packet pair is provided in Table 1 below.

  In this example, the particular instruction executed is not relevant to this disclosure, but the exception is stored in the register pair R7: 6 created by the execution unit during execution of the VALIGNB instruction associated with the first instruction packet. The value is used by the execution unit during execution of the VDMPY instruction associated with the second packet. In a particular example, the assembler or compiler can arrange the instructions so that both VALIGNB and subsequent VDMPY are executed in the same execution slot, such as execution unit 118. Additionally, the assembler or compiler can arrange the second instruction packet immediately following the first instruction packet in the program sequence.

  FIG. 2 is a block diagram of a portion of a system 200 that includes an execution unit 202 having a transfer logic circuit 220 and a memory 222. The system 200 includes a storage device 204 that is external to the execution unit 202 and has a plurality of storage locations 208, 210, 212, 214, 216 and 218. Each of storage locations 208, 210, 212, 214, 216, and 218 may be associated with a storage address that is accessible to execution unit 202 via bus 206. In general, storage locations 208, 210, 212, 214, 216, and 218 are separated from execution unit 202 by different lengths of bus trace. In addition, each time the execution device 202 accesses a particular storage location in the memory 204, power is consumed. In general, execution unit 202 receives an instruction, decodes the instruction, accesses the register file in memory 204 to retrieve the data, executes the instruction using the retrieved data, and writes the data back to memory 204 Is adapted to be.

  The execution device 202 includes a transfer logic circuit 220 and a local memory 222. Transfer logic 220 is adapted to detect when data generated by execution of a particular instruction is used in executing the next instruction in a program sequence. In this case, the execution unit 202 is adapted to use the transfer logic 220 to store the results from the execution of the first instruction in the local memory 222. Execution unit 202 can bypass the register file read operation or memory read operation during execution of the next instruction and can utilize the data stored in local memory 222, thereby avoiding the memory read operation and saving power. can do. In general, reducing all memory accesses can selectively avoid power consuming memory read operations and save power consumption.

  FIG. 3 is a block diagram of a system 300 that includes a shared controller 304 having a data transfer logic circuit 306 and a search skip logic circuit 308. System 300 includes an instruction cache 302 coupled to shared controller 304. Shared controller 304 is coupled to service device 314, storage device 316 and data device 318. The shared controller 304 is also coupled to a source register file 312 that communicates with the instruction device 310. In addition, the instruction device 310 and the data device 318 communicate via a bus device 322, which is coupled to a memory 324 such as a multi-directional cache memory. Service device 314, storage device 316 and data device 318 are coupled to a destination register file 320.

  In certain illustrative embodiments, the system 300 can receive an instruction packet and the instruction can be executed by the data device 318 to produce a result. Shared controller 304 is adapted to utilize data transfer logic 306 to determine whether the result is used by subsequent instruction packets. Shared controller 304 is adapted to communicate with service device 314, storage device 316 and data device 318 to omit subsequent register file read operations. Additionally, the shared controller 304 communicates with the data device 314 to store the results in the local memory, such as the memory 222 shown in FIG. 2 or the local memories 138, 142, 146 and 150 illustrated in FIG. It is adapted to instruct the data device 314. Shared controller 304 is also adapted to control service device 314, storage device 316 and data device 318 to utilize locally stored data during execution of subsequent instruction packets. In certain embodiments, service device 314, storage device 316 and data device 318 jointly perform processing operations similar to the operations performed by execution devices 118, 120, 122 and 124 shown in FIG. .

  In another specific embodiment, shared controller 304 utilizes search skip logic 308 to use a second storage address in which the first storage address associated with the first instruction is associated with the second instruction in memory. Is adapted to determine whether the tag array search operation should be omitted, such as when in the same cache line. In a particular example, the system 300 can operate in an “auto-increment address” mode when the data device 318 can identify the first storage address and calculate the second storage address based on the first storage address. For example, the data device 318 can identify the first storage address (A) and calculate the second storage address (A + 8). In this particular example, data device 318 receives at least one instruction associated with the first instruction packet. Data device 318 is adapted to determine a storage address associated with the instruction and to calculate a second storage address.

  In a particular example, the storage address may be a virtual storage address related to a physical storage address in the n-directional cache memory. In this example, data device 318 can perform a translation from a virtual address to a physical address by performing a translation index buffer (TLB) search operation to identify the physical storage address. Data device 318 may perform tag array search operations to identify tag data that identifies a direction in the data array related to a physical storage address. Data device 318 can retrieve data from the n-directional cache memory using the tag data and physical storage address information. Tag data (including the direction associated with the multi-directional cache) can be stored in local memory along with a second storage address. When the second storage address is retrieved for use by data device 318, data device 318 can determine whether the second storage address and the first storage address are in the same cache line. If the first storage address and the second storage address are associated with the same cache line in the n-direction cache memory, the search skip logic 308 omits a subsequent tag array search operation for the data device 318, and The direction from the first storage address is used to instruct to access data in the n-direction cache memory associated with the second storage address. When the first storage address and the second storage address are associated with different cache lines in the n-direction cache memory, the search skip logic 308 performs a tag array search operation without performing a translation index buffer (TLB) search operation. Is adapted to instruct the data device 318 to perform. If the data device 318 determines that the second storage address has crossed the page boundary (ie, has exceeded the page size), the search skip logic 308 performs a TLB search operation and a tag array search operation to perform the second storage. Data device 318 is instructed to identify the physical address and tag data associated with the address.

  In a particular example, the n-directional cache memory page has a size larger than the cache line. For example, a cache line may contain 32 bytes and a page may be about 4096 bits (about 4 kilobits). In this case, if the auto-increment address increases by 8 bytes, the tag array data can be reused three times before the auto-increment address calculation proceeds to the next cache line (assuming that the cache line is accessed by sequential operation). ), For example, page conversions from the first TLB search operation can be reused many times (ie, about 511 times) before another TLB search operation needs to be performed.

  In particular, if the storage address accessed by the subsequent instruction is associated with the same cache line as the previous memory access, the tag array data obtained in the previous tag array search operation is reused for the subsequent storage address. So that subsequent tag sequence search operations can be avoided. In another particular example, the TLB search operation can be selectively performed only when crossing a page boundary, thereby reducing the number of times the TLB is accessed and reducing overall power consumption.

  FIG. 4 is a block diagram of the processor system 400. The processor system 400 includes an instruction device 402 and an interrupt register 404 that are coupled to a controller 406. Controller 406 is coupled to a plurality of execution devices 408, 410, 412 and 414. Each of execution devices 408, 410, 412 and 414 may include local memories 426, 428, 430 and 432, respectively.

  The controller 406 includes a decoder 416, a control register file 418, a general purpose register file 420, a programmable logic controller (PLC) circuit 422 and an in-silicon debugger (ISDB) circuit 424. The ISDB circuit 424 provides a hardware debugger based on a JTAG (joint test action group) that can be used to debug software during execution of the processor system 400. In certain embodiments, the ISDB circuit 424 supports individual debugging of threads, allows thread execution to stop, and monitors and changes instruction and data memory, including the control register file 418 and the general register file 420. to enable.

  In certain exemplary embodiments, decoder 416 receives and decodes instructions. Decoder 416 communicates data related to the decoded instruction to PLC circuit 422, which detects logic when the first instruction packet generates a result used by the second instruction packet in the sequence of instruction packets. Can be included. With the detection of such data dependency between successive instruction packets, the PLC circuit 422 executes the data generation instructions 408 to store the results in the respective local memory 426, 428, 430 or 432, Adapted to generate a control signal for at least one of 410, 412 and 414. The PLC 422 controls the general register file 420 and the decoder 416 to route data dependent instructions from the subsequent instruction packet to the selected execution device (eg, execution device 408) so that the execution device is executing the subsequent instruction. Are adapted to make available locally stored data (ie, data stored in local memory 426). In this example, the PLC 422 also controls the execution unit 408 and bus 434 to prevent the execution unit 408 from accessing memory (such as the general purpose register file 420) when the results are stored locally, It can be taken out.

  In a particular example, execution unit 408 may receive a data generation instruction from controller 406, execute the instruction, and write the result back to general register file 420. Execution device 408 can also store the results in local memory 426 in response to control signals received from PLC 422 of control device 406. The execution unit 408 can receive the next instruction from the control unit 406 that uses the saved result from the local memory 426. The execution unit 408 can access the local memory 426 to retrieve the stored result and execute the next instruction using the retrieved result. In this particular example, execution unit 408 can execute the next instruction without reading back the result from general register file 420, thereby omitting register file read operations and saving power. it can.

  In another specific embodiment, the controller 406 is adapted to selectively reuse tag sequence data identified by a tag sequence search operation. For example, when calculating the second address from the first address using the auto-increment function, the PLC 422 examines the carry bit to determine when the second address is associated with a different cache line than the first address. Can do. For example, if the cache line is 32 bytes wide, the fifth bit of the second address represents a carry bit. When the carry bit changes, the second address is associated with the next cache line in the cache memory. In general, the PLC 422 is configured to re-use the tag array data from the previous tag array search operation until the carry bit indicates that the second address is associated with a different cache line than the first instruction. Commands 412 and 414. In this case, the PLC 422 causes the execution devices 408, 410, 412 and 414 to execute a new tag array search operation without executing a translation index buffer (TLB) search operation.

  In yet another specific embodiment, the controller 406 is adapted to selectively perform a translation index buffer (TLB) search operation. In particular, the PLC 422 examines the carry bit from the calculation of the second storage address to determine when the calculated storage address indicates that the page boundary has been exceeded. For example, if the page size of the memory array is approximately 4096 bits (ie, 4 kilobits), the 11th bit of the second storage address may represent a carry bit. Thus, when the 11th bit of the second storage address changes, the page boundary is crossed and the PLC 422 causes one of the execution devices 408, 410, 412 or 414 to initiate a TLB search operation followed by a tag array search operation. be able to. In this example, tag sequence search operations occur more frequently than TLB search operations. The PLC 422 is adapted to selectively omit one or both of the tag sequence search operation and the TLB search operation to reduce overall power consumption.

  FIG. 5 is a diagram illustrating a specific example of an instruction cycle 500 for an execution unit that includes data transfer logic. In general, instruction cycle 500 represents multiple stages of an execution device in terms of a particular thread. The execution unit generally includes one or more stages including a write back stage 502, a decode stage 504, a register read stage 506, one or more execution stages 508, 510 and 512 and a second write back stage 514. To process data and instructions. It should be understood that instruction cycle 500 includes only one write-back stage (write-back stage 514) and then the execution cycle is repeated beginning with decode stage 504. Writeback stage 502 is illustrated for illustrative purposes.

  In general, in the write back stage 502, at 516, the results from the previously executed instruction are written back to a register such as a general purpose register file. At 518, the next instruction packet (which may include one to four instructions) is received and the read identifier of the received packet is compared to the write identifier associated with the write result written to the register. When the read identifier matches the write identifier, the write result is stored locally on the execution unit (at 520) and similarly written back to the register at 516. In this case, register reading (at 506) can be omitted at 522, and data stored locally in the execution unit can be used. At 524, the instruction is executed using at least one of the data read in the register read stage (506) or data stored locally on the execution unit. Thus, when the read identifier and the write identifier match (at 518), the register read step (at 506) can be omitted, and the locally stored data can be used, resulting in data transfer. become.

  In a particular illustrative embodiment, the execution unit stages 504, 506, 508, 510, 512 and 514 illustrated in FIG. 5 represent execution unit cycles within an interleaved multithreaded processor. Additionally, the write back stage 502 represents the final stage of the execution cycle of the preceding instruction. The data from the preceding instruction can be retrieved from the local memory of the execution unit (at 522) without performing a register file read operation at file read stage 506 (ie, one or more execution stages). 508, 510 and 512) can be processed with the next instruction. In certain exemplary embodiments, each of stages 504, 516, 508, 510, 512 and 514 may represent a clock cycle in which a particular operation is performed.

  FIG. 6 is a block diagram illustrating a particular illustrative embodiment of data transfer logic 600 in a processor execution unit. In this case, the data transfer logic 600 is shown with respect to the write back stage 602, the decode stage 604 and the register file read stage 606. In the illustrative embodiment, data transfer logic 600 represents a single processing slot of a plurality of slots, such as representative slot 2, and is read using the representative registers “S” and “T” of the register file. And write operations can be performed.

  With respect to write-back stage 602, transfer logic 600 includes comparators 608 and 610, OR gate 611, inverters 614 and 616, AND gates 618 and 620, and register file 612. The transfer logic 600 also includes a transferable flip-flop circuit 636 and a transfer data flip-flop circuit 638. Comparator 608 receives the next packet register “S” (Rs) read identifier information 622 and current packet write identifier information 624 as inputs and provides an output coupled to the input of inverter 614. The output of inverter 614 is coupled to a first input of AND gate 618, and a second input of AND gate 618 is coupled to slot 2 register “S” readable (s 2 RsRdEn) input 632. AND gate 618 also includes an output coupled to the slot 2 register of register file 612. Comparator 610 receives next packet register “T” (Rt) read identifier information 626 (which may be the same as next packet read identifier information 622) and current packet write identifier information 628 and provides output. The output is coupled to the input of the AND gate 620 via the inverter 616. The AND gate 620 also receives the slot 2 register “T” readable (s2RtRdEn) input 634 at the second input and provides an output coupled to the slot 2 register of the register file 612. The outputs of comparators 608 and 610 are also provided as inputs to transferable flip-flop 636 and as inputs to OR gate 611, which provides an enable input to transfer data flip-flop 638. Transfer data flip-flop 638 also receives data from execution unit data writeback 630.

  At the decode stage 604 of transfer logic 600, the output of transferable flip-flop 636 is provided as an input to second transferable flip-flop 640 and as an enable input to second transfer data flip-flop 642. Transfer data flip-flop 638 provides a data input to second transfer data flip-flop 642.

  In the register file read stage 606, the second transferable flip-flop 640 provides a transfer enable signal to the selection input of the first multiplexer 644 and to the selection input of the second multiplexer 646. The first multiplexer 644 receives the transferred data at the first input, the register (s) data at the second input, and the transferred data or register (s) data for use in executing the next instruction packet. An output 648 is provided that includes any of the following: The second multiplexer 646 receives the transferred data at the first input, the register (t) data at the second input, and the transferred data or register (t) data for use in executing the next instruction packet. An output 650 is provided that includes any of the following:

  In general, comparator 608 is adapted to receive next packet read identifier information 622 and current packet write identifier information 624. Comparator 610 is adapted to receive next packet read identifier information 626 and current packet write identifier information 628. If one of the next packet read identifiers 622 and 626 matches one of the current packet write identifiers 624 and 628, the comparator that identified such a match (eg, one of comparators 608 and 610) , Provide a logic 1 value at the output, enable transfer data flip-flop 638, and disable the corresponding register readable state via each inverter 614 or 616 and each AND gate 618 or 620.

  In a particular illustrative embodiment, when the next packet read identifier 622 matches the current packet write identifier information 624, the comparator 608 provides a logic high output as an input to the transfer data flip-flop 638. Inverter 614 inverts the logic high output, provides a logic low value as an input to AND gate 618, and disables the slot 2 register (s) readable state to register file 612. The transfer data flip-flop 638 receives data from the execution unit via the write-back input 630 and stores the data. In the decoding stage 604, the data is transferred to the second transfer data flip-flop 642. The transferred data is provided to the first multiplexer 644 and the second multiplexer 646 and is output to one of the first output 648 and the second output 650 based on the output from the second transferable flip-flop 640. Provided selectively. The second transferable flip-flop 640 provides the output of the comparator 608 to the first multiplexer 644 and provides the output of the comparator 610 to the second multiplexer 646, from the second transfer data flip-flop 642. One of the transferred data or the register data is selected.

  Transfer logic 600 is adapted to selectively allow register read operations based on read / write identifier matches. Transfer logic 600 can also be used to selectively cache tag array data (such as direction information) associated with a storage address in preparation for reuse in subsequent instructions. In a particular example, transfer logic 600 or similar logic examines the carry bit associated with the calculated address, and the calculated address is associated with the next cache line (ie, led to a tag array search operation and translated). The index buffer (TLB) search operation can be omitted). In another specific example, transfer logic or similar logic examines the carry bit associated with a calculated address and if the calculated address crosses a page boundary (ie, a translation index buffer (TLB) search operation and tag). Can be adapted to identify (if it leads to a sequence search operation). If the transfer logic 600 or similar logic determines that the tag array data is still valid (i.e., the cache lines of the first and second storage addresses are the same), the tag array data is sent to the TLB search operation and / or It can be latched with a data latch, such as transfer data flip-flops 638 and 642, for use in accessing the second storage location without performing a tag array search operation.

  FIG. 7 is a diagram illustrating a specific example of an execution unit instruction cycle 700 that includes data transfer logic and is adapted to selectively omit a search operation. The instruction cycle 700 generally includes multiple stages including a write back stage 702, a decode stage 704, a register read stage 706, one or more execution stages 708, 710 and 712 and a second write back stage 714. It should be understood that instruction cycle 700 includes only one write-back stage (write-back stage 714), and then the execution cycle is repeated beginning with decode stage 704. Writeback stage 702 is illustrated for illustrative purposes.

  In general, in the execution stage of execution of the preceding instruction (such as execution stage 708), the first storage address and the second storage address can be calculated, and the second storage address is stored in the local memory (the local memory illustrated in FIG. 1). 138). During the write back phase 702, at 716, the results from the previously executed instruction are written back to a register, such as a cache address or a general purpose register file. At 718, the second storage address can be retrieved from the local memory. At 720, the value of one or more carry bits associated with the second storage address is used to determine whether one or more carry bits indicate a carry value from an auto-increment operation. Be examined. If the value of the first carry bit of one or more carry bits did not indicate that the second storage address is associated with a different cache line than the first storage address, the translation index buffer (at 722) The TLB) search operation and tag array search operation are omitted, and the previous tag array value is used to retrieve data from memory. If the value of the first carry bit of one or more carry bits indicates a carry value and the second carry bit of one or more carry bits does not indicate a carry value, for example, a second store When the address is associated with a different cache line in the same page as the previous storage address, at 724, the TLB search operation is omitted, but the tag array search operation is performed and the tag array value is retrieved to retrieve data from memory. Take out. If each of the one or more carry bits indicates a carry value, a TLB search operation and a tag array search operation are performed as indicated at 726.

  In a particular example, the tag array search operation can be omitted, and the tag array data determined by the previous tag array search operation can be used to access an address in memory. In particular, by using tag sequence data, the storage address can be accessed without searching the tag sequence data and without performing a TLB search operation.

  In certain exemplary embodiments, stages 704, 706, 708, 710, 712 and 714 illustrated in FIG. 7 may represent stages of an execution unit within an interleaved multithreaded processor. Additionally, in certain embodiments, stages 704, 706, 708, 710, 712, and 714 may represent clock cycles.

  FIG. 8 illustrates a particular illustrative embodiment of a system 800 that includes a circuit device 802 having a controller 806 for selectively transferring data using local memories 809 and 811 within execution units 808 and 810, respectively. FIG. Controller 806 is also adapted to selectively omit search operations related to tag array 826 or transform index buffer (TLB) device 862. In a particular example, the controller 806 may detect tag alignment information and / or translation index buffer (TLB) from a previous search operation when the calculated address is in the same cache line or in the same page as the previously calculated address. ) By transferring information, the search operation in the tag array 826, the search operation in the TLB device 862, or a combination thereof can be omitted.

  In general, circuit device 802 includes a data device 804 that communicates with a controller 806, a bus device 812, and a joint translation look-aside buffer (TLB) device 813. Bus device 812 communicates with a level 2 tightly coupled memory (TCM) / cache memory 858. The control unit 806 also communicates with the first execution unit 808, the second execution unit 810, the instruction unit 814, and the in-silicon debugger (ISDB) unit 818. Command device 814 communicates with combined TLB device 813 and ISDB device 818. The circuit device 802 also includes an embedded trace unit (EU) 820 and a memory built-in self test (BIST) or design for testability (DFT) device 822. ISDB device 818, EU 820 and memory BIST device 822 provide a means for testing and debugging software running on circuit device 802.

  Controller 806 includes register files 836 and 838, control logic 840, interrupt control circuit 842, control register 844 and instruction decoder 848. In general, the controller 806 schedules threads, requests instructions from an instruction unit (IU) 814, decodes the instructions and decodes three execution units: data unit 804 (execution slots 1 and 0, 830 and 832 respectively). To the execution device 808 and the execution device 810. The instruction unit 814 includes an instruction translation index buffer (ITLB) 864, an instruction address generation unit 866, an instruction control register 868, an instruction packet alignment circuit 870, and an instruction cache 872. An instruction unit (IU) 814 may be a front end of a processor pipeline that is responsible for fetching instructions from main memory or instruction cache 872 and providing the fetched instructions to controller 806.

  Data device 804 includes a data array 824 containing cacheable data. In certain embodiments, the data array 824 may be a multi-directional data array arranged in 16 sub-array memory banks, each bank including 16 sets of 16 directions. Each storage location in the sub-array can be adapted to store double words or 8 bytes of data. In a particular example, the subsequence can include 256 doublewords (ie, 16 × 16 doublewords). Data device 804 also includes a tag array 826 that stores physical tags associated with data array 824. In certain embodiments, tag array 826 is static random access memory (SRAM). Data device 804 also includes a state array 828 adapted to store the state associated with the cache line. In a particular example, state array 828 provides a cache direction for replacement in response to a cache miss event. Data device 804 also includes execution unit (slot 1) 830 and execution unit (slot 0) 832, which generally perform load and save operations. Data device 804 includes a control circuit 834 that controls the operation of data device 804.

  In general, the data device 804 communicates with the control device 806 to receive instructions to be executed by the execution devices 830 and 832. Data device 804 also communicates with bus device 812 for bus service requests and communicates with combined TLB device 813 for combined TLB main memory device conversion.

  Bus device 812 includes a bus queue unit 850, a level 2 tag array 854, an asynchronous first in first out (FIFO) device 852, and a level 2 interface 856. Level 2 interface 856 communicates with level 2 TCM / cache 858. The combined TLB device 813 includes a combined TLB table 862 that includes control registers 860 and 64 entries.

  In certain exemplary embodiments, the controller 806 receives a first command packet and a second command packet. The controller 806 can provide instructions from the first instruction packet to the execution unit 808 for execution. Execution unit 808 may execute the first instruction from the first instruction packet and determine a first address associated with the first instruction. In a particular example, execution unit 808 can calculate a first virtual address based on the first instruction and can calculate a second virtual address based on the first virtual address (ie, with an auto-increment function). The execution unit 808 can communicate with the data unit 804 via the control unit 808 and can perform a translation index buffer (TLB) search operation via the TLB unit 813. Data device 804 can control TLB search operations by communicating with TLB device 813 and performs tag array search operations via tag array 826 to determine the direction in multi-directional memory such as data array 824. You can also The TLB page conversion information and the tag arrangement data can be provided to the execution device 808 via the control device 806. The control device 806 can instruct the execution device 808 to save the tag array information and / or the TLB page conversion information in the memory 809. The execution device 808 can retrieve data from the storage location based on the tag arrangement information.

  In a particular example, if the second virtual address is associated with the same cache line as the first virtual address, the execution unit 808 uses the saved tag array information from the memory 809 to perform a tag array search operation and a TLB. Physical memory such as data array 824 can be directly accessed without performing page translation. In certain embodiments, the control logic 840 of the controller 806 can instruct the execution unit 808 to use the saved tag array information. If the second virtual address is associated with a different cache line than the first virtual address, the execution unit 808 communicates with the data unit 804 via the control unit 806 without performing a TLB search operation (ie, A tag array search operation can be performed to determine tag information related to the second virtual address (without performing a conversion from a virtual page to a physical page).

  In a particular illustrative embodiment, execution units 808 and 810 may determine a memory array that determines when to omit a tag array search operation and / or a TLB search operation, such as search skip logic circuit 308 illustrated in FIG. Includes search skip logic. In another particular illustrative embodiment, the control logic 840 can control the execution units 808 and 810 to selectively omit the tag sequence search, the TLB search, or a combination thereof. Execution devices 808 and 810 can also include a data transfer logic circuit, such as transfer logic circuit 136 shown in FIG. In certain illustrative embodiments, the control logic 840 controls the execution units 808 and 810 to selectively transfer data from the first instruction to the second instruction for use in executing subsequent instructions. Adapted to store the data in respective memories 809 and 811.

FIG. 9 is a block diagram illustrating a specific illustrative embodiment of a method for data transfer. At 902, in an interleaved multithreaded processor having multiple execution units, a write identifier associated with data written to a register file during a write back phase of the execution unit is read in a subsequent read phase of the execution pipeline. Compared with identifier. Proceeding to 904, if the write identifier does not match the read identifier, the method proceeds to 906 where the data resulting from the execution of the first instruction packet is written to one location in the register file and the data is executed. Do not save locally on the device. Alternatively, if the write identifier matches the read identifier at 904, the method proceeds to 908 and the data is written to a register file and stored locally on the execution device for use by the execution device in a subsequent read stage. The Proceeds from 908 to 910, the method includes retrieving or data from the local storage Place. Alternatively, proceeding from 906 to 912, the method includes retrieving data from a register file location. Proceeding to 914 , the method includes performing a subsequent read step using the retrieved data. In a particular example, the method includes executing an instruction packet at the execution device using data stored locally at the execution device. The method ends at 916 .

  In a particular example, the method includes identifying one or more zero-value bits included in the data to determine whether the write identifier matches the read identifier. Based on the zero value bits, the method can include generating an indicator to reduce power to the data path in the execution unit associated with one or more zero value bits. In another specific example, the method compares a cache line address of a multi-directional cache associated with a data device with a cache line address associated with a write identifier, and a cache line associated with the write identifier. Retrieving data from the multi-directional cache without reading the translation index buffer (TLB) tag when the address matches the cache line address associated with the data device.

  FIG. 10 is a block diagram illustrating a specific illustrative embodiment of a method for selectively omitting a tag sequence search operation. At 1002, a second storage address is calculated from the first storage address using an auto-increment function. Subsequently, at 1004, the first carry bit associated with the second storage address is examined. In an illustrative embodiment, the carry bit is an address bit associated with the size of the cache line to determine whether the second address is in the same cache line as the first address. For example, the lower bits 0000, 0001,. . . If the consecutive address with 0111 is in a single cache line, but the next consecutive address with low bit 1000 is in a different cache line, then the bit that changes from 0 to 1 (ie, the 4th least significant address bit) ) Is the carry bit examined at 1004. In the following example, when the second address is generated by auto-incrementing the first address, the carry value is indicated when the fourth least significant address bit changes value. At 1006, if the first carry bit indicates a carry value, the method proceeds to 1008 and performs a tag array search operation to retrieve tag array information associated with the second storage address. Proceeding to 1010, the tag array information is stored in local memory. Proceeding to 1012, data is retrieved from the cache memory using the tag array information.

  Returning to 1006, if the first carry bit does not indicate a carry value, the method proceeds to 1014 where the tag sequence information is identified in a previous tag sequence search operation, such as the search operation associated with the first storage address. Tag array information is extracted from the local memory. The method ends at 1016.

  FIG. 11 is a flow diagram illustrating a specific illustrative embodiment of a method for selectively omitting (bypassing) a tag array search operation, a translation index buffer (TLB) search operation, or a combination thereof. At 1102, a TLB search operation is performed to convert the virtual storage address to a physical storage address. Subsequently, at 1104, a tag array search operation is executed to determine tag information associated with the physical address. Proceeding to 1106, the tag array information is stored in the local memory. Proceeding to 1108, a second storage address calculated from the first storage address using the auto-increment function is received. In a particular example, the second storage address can be calculated from the first storage address by incrementing the first storage address. Subsequently, at 1110, the cache line carry bit associated with the second storage address is examined to identify the carry value (ie, the carry bit value). In a particular example, for example, the carry bit may be the fifth address bit associated with a 32-bit cache. If the cache line carry bit does not indicate a carry value at 1112, the method proceeds to 1114 where the tag information stored in local memory is retrieved. Subsequently, at 1116, data is extracted from the second storage address of the memory based on the extracted tag information. Returning to 1112, if the cache line carry bit indicates a carry value, the method proceeds to 1118 where the page boundary carry bit is examined to determine the carry value. At 1120, if the page boundary carry bit indicates a carry value, the method returns to 1102 to perform a TLB search operation to convert the storage address to a physical address. Returning to 1120, if the page boundary bit does not indicate a carry value, the method proceeds to 1104 where a tag array search operation is performed to determine tag information associated with the physical address, and no TLB search operation is performed.

  FIG. 12 is a block diagram illustrating an exemplary wireless communication device 1200 that includes a processor that includes logic circuitry that selectively omits register read operations and / or translation index buffer (TLB) search operations. The wireless communication device 1200 can include a digital signal processor (DSP) 1210 that includes data transfer / search skip logic 1264 that communicates with one or more execution units 1268. Each of the one or more execution units 1268 includes a local memory 1270. Data transfer / search skip logic 1264 may operate to transfer data by controlling execution unit 1268 to store data locally in local memory 1270 for use by subsequent instruction packets. The wireless communication device 1200 also includes a memory 1232 that can access the DSP 1210. Data transfer / search skip logic 1264 also controls execution unit 1268 to utilize previously determined tag sequence information (from previous tag sequence search operations associated with different storage addresses) and a translation index buffer ( It is adapted to omit both TLB) search operations and tag sequence search operations. The previously determined tag sequence information can be used to access a memory such as memory 1232 without performing other tag sequence search operations. In another specific embodiment, as described with respect to FIGS. 1-11, the page translation information of the first address determined by the previous TLB search operation is used to perform the tag without performing another TLB search operation. Sequence search operations can be performed. In certain embodiments, the data transfer and / or TLB search skip logic 1264 can provide a data transfer function, a tag sequence search skip function, a TLB search skip function, or any combination thereof.

  In certain embodiments, the wireless communication device 1200 can include both a data transfer circuit and a search skip logic circuit. In another specific embodiment, the wireless communication device 1200 can include only data transfer circuitry. In yet another specific embodiment, search skip logic may be included. In yet another specific embodiment, a logic circuit adapted to determine whether data should be transferred is used to determine whether to omit a tag array search operation, a TLB search operation, or a combination thereof. Can be determined.

  FIG. 12 also shows a display controller 1226 coupled to the digital signal processor 1210 and the display 1228. A coder / decoder (CODEC) 1234 may also be coupled to the digital signal processor 1210. A speaker 1236 and a microphone 1238 can be coupled to the CODEC 1234.

  FIG. 12 also illustrates that the wireless controller 1240 can be coupled to the digital signal processor 1210 and the wireless antenna 1242. In certain embodiments, an input device 1230 and a power source 1244 are coupled to the on-chip system 1222. Further, in certain embodiments, the display 1228, input device 1230, speaker 1236, microphone 1238, wireless antenna 1242, and power source 1244 are external to the on-chip system 1222 as illustrated in FIG. However, each is coupled to a component of on-chip system 1222.

  Data transfer and / or TLB search skip logic 1264, one or more execution units 1268 and local memory 1270 are shown as separate components of digital signal processor 1210, but data transfer and / or TLB search Omission logic 1264, one or more execution units 1268 and local memory 1270 may be connected to a wireless controller 1240, CODEC 1234, display controller 1226, other processing components (such as a general purpose processor not shown) or any combination thereof. It should be understood that other processing components can be incorporated.

  Those skilled in the art further understand that the various illustrative logic blocks, configurations, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or a combination of both. Understand what can be done. To illustrate this interchangeability of hardware and software, various illustrative components, blocks, configurations, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Those skilled in the art can implement the aforementioned functions in various ways for each particular application, but such implementation decisions should not be construed as departing from the scope of the present disclosure.

  The method or algorithm steps described in connection with the embodiments disclosed herein may be directly embodied in hardware, software modules executed by a processor, or a combination of the two. Software modules reside in RAM memory, flash memory, ROM memory, PROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM or other form of storage medium known in the art Can do. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a computing device or user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a computing device or user terminal.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the disclosed embodiments. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. can do. Accordingly, this disclosure is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with this principle and the novel features defined by the following claims.
Hereinafter, the invention described in the scope of claims of the present application will be appended.
[C1] In an execution pipeline in an interleaved multi-thread (IMT) processor having multiple execution units, associated with the result written to the register file by execution of the first instruction during the write-back phase in the execution unit Comparing the write identifier with a read identifier associated with a second instruction; and when the write identifier matches the read identifier, the result is provided for use by the execution device in a subsequent read step. Storing in the local memory of the execution device.
[C2] The method of C1, further comprising writing the result to the register file without storing the result in the local memory when the write identifier does not match the read identifier. .
[C3] The method of C1, further comprising executing an instruction packet at the execution unit using the result stored in the local memory.
[C4] identifying one or more zero-value bits included in the write identifier; and power to a data path in the execution unit associated with the one or more zero-value bits Generating a label to reduce the amount of C1.
[C5] generating a data transferable output indicator when the write identifier matches the read identifier; selectively disabling a register file slot according to the data transferable output indicator; The method according to C1, further comprising:
[C6] generating a selection signal related to the data transferable output indicator, and executing the second instruction with one of the output from the register file or the result from the local memory C5. The method of C5, further comprising: selectively providing to the execution device for ready use.
[C7] The carry bit of the second storage address of the second instruction calculated from the first storage address of the first instruction is related to the cache line in which the second storage address and the first storage address are one. Checking to determine whether the second cache line address associated with the second storage address matches the first cache line address associated with the first storage address; The method of C1, further comprising retrieving data from the multi-directional cache without performing the operation.
[C8] Determining the second address associated with the second instruction packet from the first address associated with the first instruction packet and the carry bit of the data device adder associated with the multi-directional cache Checking to determine if the second address has crossed a cache line boundary; and if not, the tag associated with the first address determined by a previous tag array search operation Accessing the multi-directional cache to retrieve data from the second address using sequence data and translation index buffer (TLB) search data.
[C9] If a cache line boundary is crossed, the method performs a tag array search operation to determine tag array information associated with the second instruction without performing a translation index buffer (TLB) search operation. The method of C8, further comprising:
[C10] The method of C9, further comprising reading data from the multi-directional cache using the tag sequence information.
[C11] The method of C8, wherein the first address comprises a first memory read address and the second address comprises a second memory read address.
[C12] comparing the second address with a first write address associated with a result determined by execution of the first instruction packet; and when the first write address matches the second address; The method of C8, further comprising storing the result in a local memory within the execution unit for use in executing the second instruction packet.
[C13] The method according to C12, further comprising: retrieving the result from the local memory; and executing the second instruction packet using the retrieved result.
[C14] When crossing a page boundary, the method performs a translation index buffer (TLB) search operation to translate the second address to a physical address associated with the multi-directional cache; The method of C8, further comprising: performing a tag array search operation to determine information; and accessing a memory based on the tag information and the physical address.
[C15] The method of C8, wherein the second address is determined from the first address using relative addressing.
[C16] local memory storing one or more data values and determining whether the read address associated with the read operation matches the write back address associated with the previous write back operation. A logic circuit adapted to store the one or more data values in the local memory when the read address matches the write-back address. A multi-thread processor comprising an execution device.
[C17] When the logic circuit is adapted to read data from a memory location outside the execution unit and the read address does not match the write-back address, the memory location is A multithread processor according to C16 corresponding to the read address.
[C18] The multithread processor according to C16, wherein the execution device includes a plurality of execution stages including a write-back stage, a decoding stage, and a register file reading stage.
[C19] The logic circuit includes one or more comparators, and the one or more comparators compare the read address information with the write address information and create a result for data transfer. The multithreaded processor according to C18, adapted to selectively enable.
[C20] The multithreaded processor according to C16, wherein the local memory includes one or more data latches in the execution unit.
[C21] The multithreaded processor according to C20, wherein the one or more data latches are selectively activated by a data transfer logic circuit to selectively enable data transfer.
[C22] When at least a portion of the read address associated with the instruction matches a portion of the read address associated with the preceding instruction, the storage address in the multi-directional cache memory is determined without performing a tag array search operation. The multithreaded processor according to C16, further comprising a second logic circuit adapted to determine.
[C23] In an execution pipeline in an interleaved multithread (IMT) processor having a plurality of execution devices, a write identifier associated with a result written to a register file by execution of the first instruction packet is set as a second instruction packet. Means for comparing with an associated read identifier; and, when the write identifier matches the read identifier, selectively localizing the result to an execution device for use in executing the second instruction packet. A processor comprising means for storing.
[C24] means for determining a second address associated with the second instruction packet from a first address associated with the first instruction packet; and a cache line boundary of a cache line associated with the multi-directional cache. Means for examining a carry bit of a data device adder to determine whether the second address has been exceeded, and without accessing a translation index buffer (TLB) or tag array; The processor of C23, further comprising means for translating a virtual address to a physical address associated with the multi-directional cache using locally stored physical address data and direction data associated with the first address.
[C25] means for comparing a write identifier associated with the result written to the register file by execution of the first instruction packet with a read identifier associated with the second instruction packet, wherein the write identifier and the read identifier are Receiving a first comparator adapted to provide a first output indicating whether the write identifier and the read identifier match; receiving the write identifier and the second read identifier; A second comparator adapted to provide a second output indicating whether a write identifier and the second read identifier match; and based on the first output and the second output, the second output Local stored data or register data for use when executing two instruction packets And a logic circuit adapted to selectively provide one of the execution devices to the execution unit.

Claims (8)

Determining a second address associated with a second packet of instructions from a first address associated with the first packet of instructions;
Examining the carry bit of the adder of the data device to determine whether the second address has crossed a cache line boundary associated with the multi-directional cache;
In response to determining that the second address has crossed the boundary of the cache line, to determine whether the second address has crossed a page boundary associated with the multi-directional cache, A second carry bit of the adder is examined and associated with the second address without performing a translation index buffer (TLB) search operation in response to determining that the page boundary has not been exceeded. to determine the tag sequence information, and want to consider performing some of the tag sequence search operation,
In response to determining that the boundary of the cache line has not been crossed by the second address, using tag array data and translation index buffer (TLB) search data associated with the first address Accessing the multi-directional cache to retrieve data from a second address, the tag array data being a result of a previous tag array search operation;
A method comprising: Further comprising that use the tag sequence information reading data from the multi-way cache, the method according to claim 1.   The method of claim 1, wherein the first address comprises a first memory read address and the second address comprises a second memory read address. Comparing the second address to a first write address associated with a result determined by execution of the first packet of instructions;
Storing the result in local memory within the execution unit for use in executing the second packet of instructions when the first write address matches the second address;
The method of claim 1, further comprising: Retrieving the result from the local memory;
Using the retrieved result to execute the second packet of instructions;
The method of claim 4 , further comprising: When a page boundary is crossed by the second address,
The method
Said second address, in order to convert the physical address associated with the multi-way cache, and performing the translation lookaside buffer (TLB) search operations,
To determine the tag information, and performing the tag sequence search operation,
Accessing the memory based on the tag information and the physical address;
The method of claim 1, further comprising:   The method of claim 1, wherein the second address is determined from the first address using relative addressing. When executed by the processor
Determining a second address associated with a second packet of instructions from a first address associated with the first packet of instructions;
Examining the carry bit of the adder of the data device to determine whether the second address has crossed a cache line boundary associated with the multi-directional cache;
In response to determining that the second address has crossed the boundary of the cache line, to determine whether the second address has crossed a page boundary associated with the multi-directional cache, A second carry bit of the adder is examined and associated with the second address without performing a translation index buffer (TLB) search operation in response to determining that the page boundary has not been exceeded. to determine the tag sequence information, and want to consider performing some of the tag sequence search operation,
In response to determining that the boundary of the cache line has not been crossed by the second address, tag array data and translation index buffer associated with the first address determined from a previous tag array search operation (TLB) using search data to access the multi-directional cache to retrieve data from the second address;
A computer-readable storage medium having a program code for causing the processor to execute.

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