JP5660597B2 - Multiple reflection compensation circuit - Google Patents

Description

  The present invention is a method for suppressing or compensating for multiple reflections that occur when a high-speed signal is transmitted to a load via a plurality of lines having different characteristics connected in cascade, and to supply a waveform without disturbance to the load end. About.

  When distributing high-speed signals, especially signals that emphasize signal quality, such as clock signals, in consideration of waveform disturbance due to reflection due to impedance mismatching and timing deviation between signals, that is, skew, There is a need to suppress them. In general, the following three methods are often used for the distribution of these signals.

  As shown in FIG. 1, the first is a system in which transmission is performed on a one-to-one basis with respect to a load from the same number (hereinafter n) of drive circuits (drivers) as the load. In this case, if a method such as appropriately selecting the output impedance of each driver with respect to the characteristic impedance of the line is taken, the waveform disturbance due to reflection can be avoided, but the signal timing shift between a plurality of drivers, that is, Skew occurs. Further, there are disadvantages in that the number of parts is increased by using a plurality of drivers and the wiring area is occupied.

As shown in FIG. 2, the second is a so-called tournament system in which wiring is performed by one line from one driver to a plurality of loads, branching from the middle, and distributing to a plurality of loads. This circuit includes 141, 142,. . . , 14n when the delay times of all the lines are equal, an equivalent circuit in which the two lines in FIG. 2 on the driver side in FIG. 2 and the lines 141, 142,. . . The characteristic impedance of 14n, both when the _{Z 0,} 141 and 142,. . . , 14n connected in parallel, the characteristic impedance of the load-side line 14 in FIG. 3 is equivalent to 1 / n Z ₀ / n. For this reason, in FIG. 3, reflection due to mismatch of characteristic impedance occurs at the connection point 13 between the line 12 and the line 14, and as a result, the waveform is disturbed. 141, 142,. . . When the delay times of the 14n lines are not equal to each other, new complicated reflection occurs and waveform disturbance occurs. Therefore, normally, such different delay times are not selected.

  As shown in FIG. 4, the third is a fly-by system in which signals are sequentially transmitted by sequentially connecting loads to an equation based on wiring. In this case, if the impedance matching is performed accurately, waveform disturbance at each load point can be avoided, but there is a time difference due to the delay due to the wiring length in the signal that reaches the load. There is.

  In the above conventional technologies, there are problems to be solved, and it is necessary to find a compromise by comparing mounting density with performance or cost. For example, the clock supply method to the memory module, which is a typical application field of the present technology, used the second tournament method until DDR2, but in the next generation DDR3, the waveform accompanying the increase in speed Although the disturbance cannot be dealt with and complicated adjustment of the delay amount is required, the third fly-by method has been adopted in favor of the waveform quality.

  The second tournament method described in the prior art is an economical distribution method in which the circuit is simple and the wiring area is small, although waveform distortion occurs, and has been widely used in the case where a clock is supplied to a memory element so far. It was. Although this method causes extremely complicated waveform disturbances due to multiple reflection, finding the way to avoid it by elucidating the cause of multiple reflection is the biggest challenge. A waveform can be obtained. Further, as shown in FIG. 3, this system is equivalently replaced with a cascade connection of lines having different characteristic impedances. Therefore, the solution of the problem of the wiring method is not limited to the clock distribution by the tournament method, but also a general cascade connection line.

The response of the signal transmission from the signal source to the load is determined by a so-called transfer function. The transfer function is often expressed as a frequency function. When the frequency characteristic of the transfer function is flat, the time function is not disturbed. Conversely, when the frequency function is not flat, the time function is also disturbed. FIG. 5 shows a frequency characteristic of a certain transmission system, and FIG. 6 shows a time response corresponding to the frequency characteristic of FIG. In both figures, the response when the output resistance R _{1 of the} driver is changed to 11Ω, 33Ω, and 50Ω with respect to the characteristic impedance Z ₀ = 50Ω of the line, the frequency response and time as R ₁ becomes closer to Z _0. It can be seen that the response is less disturbed. The frequency response and the time response can be mutually converted by Fourier transform.

  By flattening the frequency response by multiplying the original transfer function of the non-flat frequency response by its reciprocal, it has long been a deemphasis to pre-emphasis to suppress high-frequency noise during broadcasting and tape recording. It has already been applied in emphasis systems and equalizer circuits for correcting the frequency characteristics of lines during high-speed transmission.

  The transfer function when a plurality of lines having different characteristic impedances are cascade-connected as in the present invention is complex, and its inverse function can be obtained mathematically, but it is difficult to apply to an actual circuit at first glance. I can see. However, this inverse function is a simple expression expressed only by addition and subtraction with a time delay and a weight added, and it has been found that flat frequency characteristics and waveform transmission without disturbance can be performed.

FIG. 7 shows the simplest example of the second method described in the prior art with the number of loads being 2, and FIG. 8 is an equivalent circuit thereof. In FIG. 7, it is assumed that the characteristic impedance of the driver-side line 30 is Z ₁ , the propagation delay time is τ ₁ , the characteristic impedances of the load-side lines 51 and 52 are both Z ₂₀ , and the propagation delay time is both τ _2. , the characteristic impedance of the load side line in the equivalent circuit of Figure 8, half of the characteristic impedance of the load side of the line of Figure 7, i.e., becomes _{Z 2 =} Z 20/2, due to the difference in the characteristic impedance at the connection point Waveform disturbance occurs due to reflection.

となる。この伝達関数は、

と級数展開される。信号源をＶ_１０（ω）、受信端（レシーバ入力）の波形をＶ_１５（ω）とすると、

である。［数２］において、ｅ^{−ｊωｎτ}は、ｎτの時間遅れを表すので、これを時間軸で考える。Ｖ_１０（ω）およびＶ_１５（ω）の時間応答を、それぞれ、ν_１０（ｔ）、ν_１５（ｔ）とすると、

となって、受信端の波形は、２τ遅延した元の信号と、２τの時間ごとに、符号を含めた各係数を乗じた振幅が加算されて、減衰しながら振動する反射波形を形成する。In order to solve the above technical problem, in the circuit in which two lines having different characteristic impedances shown in FIG. For simplicity, one-third the output resistance R ₁ of the driver of a characteristic impedance, i.e., to select the R 1 _{= Z 0/3,} the load side open, and τ equal propagation delay time of each line . Expressing the transfer function F (ω) as a function of the angular frequency ω = 2πf with respect to the frequency f, F (ω) is

It becomes. This transfer function is

And series expansion. If the signal source is V ₁₀ (ω) and the waveform at the receiving end (receiver input) is V ₁₅ (ω),

It is. In [ ^Equation 2], e ^−jωnτ represents the time delay of nτ, and this is considered on the time axis. When the time responses of V ₁₀ (ω) and V ₁₅ (ω) are ν ₁₀ (t) and ν ₁₅ (t), respectively,

Thus, the waveform at the receiving end is added with the original signal delayed by 2τ and the amplitude obtained by multiplying each coefficient including the sign every 2τ to form a reflected waveform that vibrates while being attenuated.

を乗じると、

となり、その時間応答は、

となって、受信端の信号は、元の信号の単純な時間遅れのみとなる。すなわち、Ｆ（ω）×Ｇ（ω）であらわされる伝達関数は単純な遅延ｅ^{−ｊω２τ}のみとなる。ここで、伝達関数Ｆ（ω）の、時間遅れ分を差し引いた関数の逆数Ｇ（ω）を反射補償信号と名付ける。Since the transfer function is mainly used for obtaining the reflected waveform, the purpose was to obtain the series of [Formula 2] and the [Formula 4] of its time response. The inventor noted that the denominator of [Equation 1] has a simple shape. Since e ^−jω2τ of the numerator of [ ^Equation 1] means a delay of the propagation time 2τ from the driver to the load, the denominator of [ ^Equation 1], that is,

Multiply

And the time response is

Thus, the signal at the receiving end is only a simple time delay of the original signal. That is, the transfer function represented by F (ω) × G (ω) is only a simple delay e ^−jω2τ . Here, the reciprocal number G (ω) of the transfer function F (ω) minus the time delay is named the reflection compensation signal.

となり、元の信号と２τおよび４τの時間遅れ、および、１／２の係数を含む加減算のみで表される単純な波形となる。Here, considering V ₂₂ (ω) = G (ω) × V ₁₀ (ω), V ₂₂ (ω) is obtained by multiplying the original signal V ₁₀ (ω) by the reflection compensation signal G (ω). When G (ω) in [Equation 5] is used, its time response ν ₂₂ (t) is

Thus, a simple waveform represented by only the addition and subtraction including the original signal, the time delay of 2τ and 4τ, and the coefficient of 1/2.

  The invention according to claim 1 is a circuit including a driver, a line in which at least two lines having different characteristic impedances are connected in cascade, and a receiver, and a transfer function of the line including the driver is included in a signal to be transmitted from the driver. In principle, by multiplying the reciprocal of the function obtained by subtracting the time delay, that is, the reflection compensation signal, the signal at the load end is only the time delay of the original signal, that is, the waveform distortion caused by the transmission is eliminated. And

となり、やや複雑にはなるものの、２つの遅延τ_１、τ_２およびその遅延の和τ_１＋τ_２と加減算のみで表される。［数５］は、［数９］において、Ｒ_１＝Ｚ_１／３、Ｒ_２＝∞、Ｚ_２＝Ｚ_１／２、τ_１＝τ_２＝τとおいたものである。Or the R 1 _{= Z 0/3,} or equal all wiring length, or the number of load 2, or, or to open the load side is intended for easy description of the present invention It is not a restriction for realization. The output resistance of the driver is R ₁ , the termination resistance on the load side is R ₂ , and the characteristic impedance and propagation delay of the driver side line and the load side line are Z ₁ , τ ₁ and Z ₂ , τ ₂ , respectively. Time delay of a general transfer function F (ω) in the case of a two-stage cascaded circuit

Although it becomes somewhat complicated, it is expressed by only _two delays τ ₁ , τ ₂ and the sum τ ₁ + τ _{2 of the} delays and addition / subtraction. [Equation 5] are those placed _{in, R 1 = Z 1/3} , R 2 = ∞, Z 2 = Z 1/2, τ 1 = τ 2 = τ and [Expression 9].

Further, even when the distribution is performed in two or more stages, the reflection compensation signal G (ω) can be realized by delay and addition / subtraction. For example, in the case of two stages, if the delays of the three types of lines from the driver side to the load side are τ ₁ , τ ₂ and τ ₂ , the required delays are 2τ ₁ , 2τ ₂ , 2τ ₃ , 2 (τ ₁ + τ ₂ ), 2 (τ ₂ + τ ₃ ), 2 (τ ₃ + τ ₁ ) and 2 (τ ₁ + τ ₂ + τ ₃ ) at maximum.

The final amplitude of G (ω) in [Equation 5] or ν ₂₂ (t) in [Equation 7] is 1, but a general reflection compensation signal [Equation 9] when the distribution is in two stages. ], The final amplitude is 1 + R ₁ / R ₂ and exceeds 1, so that a so-called dynamic range, that is, a limitation on the signal amplitude determined from the power supply voltage of the circuit occurs. For this reason, it is necessary to keep the signal amplitude of the reflection compensation signal low so that the signal amplitude falls within the dynamic range. Conversely, when there is a margin in the dynamic range, there is a demand for increasing the amplitude. The second aspect of the invention is based on the principle that a signal obtained by multiplying the reciprocal of the transfer function minus the time delay by a fixed value is used as the reflection compensation signal in order to obtain the required signal amplitude.

  Multiplying the original signal by G (ω) in [Equation 5] subtracts a signal having half the amplitude of the original waveform with a delay of 2τ as shown in [Equation 8], This means that half amplitude signals are added with a delay of 4τ. The generalized [Equation 9] also means that a constant multiple of the original waveform is added or subtracted for each delay time corresponding to the delay time of the line. Of course, if the sign of this constant is positive, it is addition, and if it is negative, it is subtraction. The third aspect of the invention is based on the principle that it is realized by delay and addition / subtraction in order to obtain an intended reflection compensation signal.

  The invention according to claim 4 is characterized in that at least one of the plurality of cascade-connected lines is a line in which a plurality of lines are connected in parallel. In the case of simple cascade connection, it is relatively easy to select the characteristic impedance of each line equally. However, since the equivalent characteristic impedance when multiple lines are connected in parallel is inversely proportional to the number of lines, it is cascaded. It is not easy to select equal characteristic impedances between connected lines. In such a case, the present invention is greatly effective.

  The function of time included in the reflection compensation signal includes a time term that is an integral multiple of the delay time of a plurality of cascaded lines and their sum. These times are obtained by using a plurality of signals having the same wiring length as a plurality of cascade-connected lines. The invention of claim 5 uses a plurality of lines having the same delay time per unit length as that of at least two lines constituting the circuit in order to obtain a reflection compensation signal, and realizes a delay by a combination thereof. It is a feature.

As an example of the prior art, in the circuit of FIG. _{8, R 1 = Z 1/} 3, R 2 = ∞, Z 2 = Z 1/2, when the τ ₁ = τ ₂ = τ, the time width (hereinafter simply FIG. 9 shows the time response when a wide rectangular wave is applied, and FIG. 10 shows the time response when a narrow rectangular wave is applied. Due to the influence of reflection at the connection point of the two lines, the waveform is greatly disturbed. In particular, in the case of a rectangular wave having a narrow width, the reflection and the repetition period overlap, and an extremely unique time response is exhibited. FIGS. 11 and 12 show time responses for a wide pulse width and a narrow pulse width when the delay time τ ₂ of the load-side wiring 14 is 0.6 times the delay time τ ₁ of the driver-side wiring 12. is there. More complicated waveform disturbance occurs than when τ ₁ = τ ₂ = τ.

  FIG. 13 illustrates [Equation 3]. First, it rises at amplitude 1 at time 0, subtracts 1/2 amplitude at time 2τ, and further adds 1/2 amplitude at time 4τ. When this waveform is multiplied by a signal scheduled to be transmitted from the driver, the result is as shown in FIG. 14. When the signal of FIG. 14 is added to the signal source 10 of FIG. 8, the waveform of the load end 15 is completely as shown in FIG. There will be no waveform distortion. FIGS. 16, 17, and 18 are examples in which the pulse widths of FIGS. 13, 14, and 15 are narrowed, respectively.

FIG. 19 shows a reflection compensation signal when the delay time τ ₂ of the load-side wiring 14 is half the delay time τ ₁ of the driver-side wiring 30. Compared to FIG. 13, although the compensation timing is increased by one, it is still a very simple waveform.

FIG. 20 shows the most basic embodiment. [ ^Equation 3] A reflection compensation signal obtained by adding 201 corresponding to 1 on the right side, 202 corresponding to −1 / 2e− ^jω2τ on the right side, and 203 corresponding to 1 / 2e− ^jω4τ on the right side. 21 is multiplied by the signal 10 of the original waveform to obtain a signal 22 sent from the driver. The reflection compensation signal 21 corresponds to, for example, FIG. 13 or FIG. 16, and the signal 22 sent from the driver corresponds to FIG. 14 or FIG. The signal 23 at the load end 15 is only a time delay of the original signal 10, that is, a signal from which waveform distortion caused by transmission is eliminated.

Since the present invention can be realized only by delay and addition / subtraction, its implementation is also easy. There are gate delay and DLL (Delay Locked Loop) methods for obtaining the delay, but the delay time required to implement the present invention is, for example, a cascade connection of two lines having the same propagation delay time. In this case, since it can be determined by two wiring delays of 2τ and 4τ with respect to the propagation delay τ of the original wiring, it can be easily realized with extremely high reproducibility. In FIG. 21, the original signal is delayed by 2τ by two wirings 121 and 122 having the same delay as the propagation delay τ of the wiring 12 on the driver side, multiplied by −½, and the two wirings 123, 124, and 143 are similarly delayed. And 144, the original signal is delayed by 4τ, multiplied by ½, and combined with 1 time of the original signal and added by the adder 8 to obtain 20 signals. When three lines are connected in cascade, similarly, 2τ ₁ , 2τ ₂ , 2τ ₃ , 2 (τ ₁ + τ ₂ ), 2 combining the propagation delays τ ₁ , τ ₂ and τ ₃ of the original wiring. Since it can be determined by seven wiring delays of (τ ₂ + τ ₃ ), 2 (τ ₃ + τ ₁ ), and 2 (τ ₁ + τ ₂ + τ ₃ ), it can be easily realized with extremely high reproducibility.

  FIG. 22 shows a basic example in which a multiplication type digital-to-analog converter (hereinafter referred to as a DA converter) is used for multiplying a signal to be transmitted from a driver and a reflection compensation signal. The signal 1 to be transmitted from the driver is added to the reference input 25 of the DA converter, and the reflection compensation signal is used as the digital input 26. If the digital input is a fixed value 1, the signal to be transmitted from the driver is output as it is to the DA converter output, and an arbitrary reflection compensation signal can be obtained by giving timing and amplitude. The product of the signal to be transmitted from the driver and the reflection compensation signal is obtained.

  FIG. 23 shows an embodiment using a differential amplifier. The delay is used in units of twice the line used in the actual circuit, and the addition / subtraction is performed in an analog manner by a differential circuit.

  FIG. 24 shows another embodiment in which current sources that are equal to each other are shunted by resistors. Off-the-shelf products can be used for the current switch circuit.

  As a clock supply method to the memory module, which is a typical application field of the present technology, a tournament method is used until DDR2. The driver's driving ability and termination resistance were selected optimally, and the design was limited to minimize waveform disturbance. However, when the next-generation high-speed DDR3 is reached, the limit of this method is reached and timing adjustment is required. The standard fly-by method was set as a standard. This field is used continuously by the generation of the technology once a standard is set in the industry, and the standard is rarely changed along the way. However, in applications that do not use a memory module, for example, a part of a notebook personal computer or an embedded computer that does not use a memory module, there is a high possibility that it will be applied because it is not tied to the standard.

First conventional example: a method of distributing one-to-one with a plurality of drivers Second conventional example: Distributing in the tournament method from the middle Equivalent circuit of FIG. Third conventional example: distribution by fly-by method Example of frequency characteristics of transmission system Time response to the frequency characteristics of FIG. The simplest example of the number of loads of the second method described in the prior art Equivalent circuit of FIG. Time response when a rectangular wave with a wide pulse width is added to FIG. Time response when a narrow rectangular wave is applied Time response of Fig. 9 when the wiring delays on the driver side and load side are different Time response of FIG. 10 when the wiring delays on the driver side and load side are different Wide pulse width reflection compensation signal for FIG. 7 when simplified most Signal waveform obtained by multiplying the signal scheduled to be transmitted from the driver by the reflection compensation signal shown in FIG. The time response of FIG. 7 when the signal of [FIG. 14] with a wide pulse width is added. Narrow pulse width reflection compensation signal for FIG. 7 when simplified most A signal waveform obtained by multiplying the signal to be transmitted from the driver by the reflection compensation signal shown in FIG. The time response of FIG. 7 when a reflection compensation signal is added for a narrow pulse width. Reflection compensation signal with a wide pulse width for FIG. 7 when the wiring delays on the driver side and load side are different The most basic embodiment of the present invention Other embodiment using wiring delay of wiring to be used Example using DA converter Example using differential amplifier Example using differential amplifier with equal current source and resistor shunt

  10 is an original signal to be transmitted, 11, 111, 112, and 11n are drivers that send out the original signal, 12, 121, 122, and 12n are lines connected to the driver, and 13, 131, 132, and 13n are connected to the driver. Are connected to the receiver, 14, 141, 142, 14n are connected to the receiver, 15, 151, 152, 15n are receiver inputs, 16, 161, 162, 16n are receivers, 17, 171, 172, and 17 n are connected lines, 18 is an adder, 19 is a multiplier, 20, 201, 202, and 20 n are signals delayed by applying a coefficient to the original signal, and 21 is an added signal , 22 is a multiplied signal, 23 is a receiver input signal, 24 is a DA converter, 25 is a reference input of the DA converter, and 26 is a digital signal of the DA converter. Le inputs, 27 outputs of the DA converter, 28,281,282,283 and 291, 292, and 293 is a buffer.

Claims (7)

In a circuit including a driver, a line in which at least two lines having different characteristic impedances are connected in cascade, and a receiver, a function to be transmitted from the driver is obtained by subtracting a time delay from the transfer function of the line including the driver. A transmission circuit that avoids the effects of reflection due to cascade connection by multiplying by the inverse of. The transmission circuit according to claim 1, wherein a function obtained by multiplying a reciprocal of a transfer function of a line including a driver by subtracting a time delay is multiplied by a fixed value. 3. The transmission according to claim 1, wherein an operation of multiplying a signal scheduled to be transmitted from a driver by a reciprocal of a function obtained by subtracting a time delay from the transfer function is realized by delay and addition / subtraction. circuit. 4. The transmission circuit according to claim 1, wherein at least one of the at least two lines is a parallel connection of a plurality of lines. 5. The transmission circuit according to claim 1, wherein a delay is realized by using a plurality of lines having the same delay time per unit length as at least two lines constituting the circuit, and combining them. . Wiring the driver with one line from one line to the middle of multiple loads, branching at least once from the middle, and the signal from the branching point with multiple lines with the same delay time In a circuit including a group of lines to be distributed and a receiver, the influence of reflection due to cascade connection is obtained by multiplying the signal to be transmitted from the driver by the inverse of the function obtained by subtracting the time delay from the transfer function of the line including the driver. Avoid the transmission circuit. Wiring the driver with one line from one line to the middle of multiple loads, branching at least once from the middle, and the signal from the branching point with multiple lines with the same delay time In a circuit including a group of lines to be distributed and a receiver, a signal to be transmitted from the driver is multiplied by a function obtained by multiplying the inverse of the function obtained by subtracting the time delay from the transfer function of the line including the driver by a fixed value. A transmission circuit that avoids the influence of reflection due to cascade connection.

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