JP5637978B2 - A / D converter - Google Patents

Description

  The present invention relates to an A / D converter that converts an analog signal into a digital signal, and more particularly to a technique for detecting an abnormality in a circuit on an input side.

  FIG. 7 shows an example of a conventional A / D conversion device 50. Analog signals output from sensors or the like (not shown) are input to the plurality of input terminals T1 to Tn, respectively. The input resistors R1 to Rn and the capacitors C1 to Cn constitute a filter circuit that removes noise components from the analog signals input to the input terminals T1 to Tn. The output of the filter circuit is input to the ports P1 to Pn of the CPU 11.

  The multiplexer 12 selects one of the analog signals input to the input terminals T <b> 1 to Tn by sequentially switching the ports P <b> 1 to Pn and outputs the selected analog signal to the sample hold circuit 13. The sample hold circuit 13 samples the selected analog signal, holds the voltage, and outputs the voltage to the A / D converter 14. The A / D converter 14 compares the voltage input from the sample hold circuit 13 with a reference voltage, and generates a digital signal corresponding to the voltage level of the analog signal based on the result.

  Co represents a parasitic capacitance (floating capacitance) of the sample hold circuit 13. Such a parasitic capacitance Co affects the output of the sample hold circuit 13 and causes an error in the A / D conversion value calculated by the A / D converter 14. Therefore, in order to minimize the influence of the parasitic capacitance Co, the capacitances of the capacitors C1 to Cn are selected to be sufficiently larger than the parasitic capacitance Co.

  By the way, in the A / D conversion device 50 of FIG. 7, an open failure in which the input resistors R1 to Rn are disconnected may occur due to poor soldering or the like. For example, if the input resistor R2 has an open failure, an analog signal is not input to the port P2 even if the port P2 is selected. Therefore, the CPU 11 should recognize that the input voltage is 0 [V] based on the calculation result of the A / D converter 14.

  However, the parasitic capacitance Co described above actually exists, and the electric charge stored at the time of processing the previous analog signal (analog signal input to the port P1) remains in the parasitic capacitance Co. That is, the output of the A / D converter 14 has a voltage value corresponding to the voltage of the previous analog signal. For this reason, since the CPU 11 does not recognize the input voltage as 0 [V], it is difficult for the CPU 11 to detect that the input resistor R2 has an open failure.

  In Patent Documents 1 to 3 described later, by discharging the electric charge stored by the previous analog signal through a discharge circuit constituted by a switch or the like, by performing A / D conversion on the current analog signal, It describes that the effect of stored charge is avoided. Patent Document 1 does not mention detection of open faults, but Patent Documents 2 and 3 describe detection methods of open faults.

  In Patent Document 2, if an A / D conversion value after discharge is equal to or less than a preset threshold value, it is determined that an open failure has occurred on the input side. Further, in Patent Document 3, when an A / D conversion value after discharging is a ground potential level, it is determined that an open failure has occurred on the input side.

  When an open failure on the input side is detected by the methods of Patent Documents 2 and 3, when an analog signal of 0 [V] or a level near it is input even when it is normal, the A / D conversion value of the signal is There is a risk that it may be erroneously determined that an open failure has occurred because the voltage is below the threshold value or the ground potential.

JP 2001-7689 A Japanese Utility Model Publication No. 7-33033 JP 11-278237 A

  An object of the present invention is to provide an A / D conversion device capable of accurately detecting whether or not an abnormality has occurred on the input side.

  An A / D converter according to the present invention includes a plurality of input terminals to which analog signals are input, a signal selection circuit that selects and outputs one of the analog signals input to each input terminal, and the signal selection circuit An A / D converter that converts an analog signal output from the digital signal into a digital signal, a switching circuit that switches between a state where each input terminal is grounded via a pull-down resistor and a state where each input terminal is not grounded, an input terminal, and a signal selection circuit; Determining means for determining whether or not an abnormality has occurred during the period. The determination means includes a first conversion value calculated by the A / D converter for the analog signal selected by the signal selection circuit in a state where the switching circuit does not ground the input terminal of the analog signal via the pull-down resistor, With the switching circuit grounded via the pull-down resistor, the analog signal input terminal is compared with the second conversion value calculated by the A / D converter, and the first conversion value and the second conversion value are compared. Whether or not an abnormality has occurred is determined based on the degree of deviation.

  According to such a configuration, if no abnormality occurs between the input terminal and the signal selection circuit, the input terminal can be input regardless of whether it is grounded via the pull-down resistor or not. Based on the analog signal thus obtained, the A / D converter outputs a comparable A / D conversion value. That is, the degree of deviation between the first conversion value and the second conversion value is small. On the other hand, if an abnormality has occurred between the input terminal and the signal selection circuit, the input terminal is grounded via a pull-down resistor and is not grounded due to the residual charge of the parasitic capacitance. Thus, a difference occurs in the A / D conversion value output from the A / D converter. That is, the degree of deviation between the first conversion value and the second conversion value increases. Therefore, the presence / absence of an abnormality can be detected based on the magnitude of the difference between the two conversion values. In addition, since an abnormality is detected based on the relative relationship between the first conversion value and the second conversion value, even if an analog signal whose normal level is 0 [V] or in the vicinity thereof is input, Can be avoided, and the reliability is improved.

  In the present invention, the determination means calculates a difference between the first conversion value and the second conversion value, and determines that no abnormality has occurred when the difference is smaller than a predetermined threshold, The first conversion value may be adopted as the output of the A / D converter, and when the difference is equal to or greater than a predetermined threshold, it is determined that an abnormality has occurred and a predetermined abnormality process may be performed. .

  In the present invention, the determination means may be constituted by a CPU, the signal selection circuit, the A / D converter, and the switching circuit may be built in the CPU, and the pull-down resistor may be externally attached to the CPU. . In this case, the CPU may have a port to which the switching circuit is connected, and the pull-down resistor may be connected between the input terminal and the port.

  In the present invention, the determination means may be constituted by a CPU, and the signal selection circuit, A / D converter, switching circuit, and pull-down resistor may be incorporated in the CPU.

  In the present invention, the signal selection circuit and the A / D converter are built in the CPU, the pull-down resistor and the switching circuit are externally attached to the CPU, and the switching circuit performs a switching operation based on a signal from the CPU. May be adopted.

  According to the present invention, an A / D conversion device capable of accurately detecting whether or not an abnormality has occurred on the input side can be obtained.

1 is a circuit diagram of an A / D conversion device according to an embodiment of the present invention. 3 is a flowchart showing the operation of the A / D conversion device of FIG. 1. It is the figure which showed the relationship between the A / D conversion value in this invention, and a threshold value. It is the figure which showed the relationship between the A / D conversion value and threshold value in a comparative example. It is a circuit diagram of the A / D conversion device concerning other embodiments of the present invention. It is a circuit diagram of the A / D conversion device concerning other embodiments of the present invention. It is a circuit diagram of the conventional A / D converter.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing, the same reference numerals are given to the same parts or corresponding parts.

  First, the configuration of the A / D conversion device will be described with reference to FIG. The A / D conversion apparatus 100 includes a plurality of input terminals T1 to Tn, input resistors R1 to Rn, capacitors C1 to Cn, pull-down resistors RD1 to RDn, and CPU1.

  Analog signals SG1 to SGn output from sensors or the like (not shown) are input to the input terminals T1 to Tn, respectively. The input resistors R1 to Rn and the capacitors C1 to Cn constitute a filter circuit that removes noise components from the analog signals input to the input terminals T1 to Tn. The output of the filter circuit is input to the ports P1 to Pn of the CPU1.

  The pull-down resistors RD1 to RDn are externally attached to the CPU1. One ends of the pull-down resistors RD1 to RDn are connected to the input terminals T1 to Tn via the input resistors R1 to Rn, respectively, and the other ends are connected to the ports Q1 to Qn of the CPU1, respectively. Ports P1 to Pn are A / D conversion ports, and ports Q1 to Qn are general-purpose ports. Note that the resistance values of the pull-down resistors RD1 to RDn are sufficiently larger than the resistance values of the input resistors R1 to Rn.

  The CPU 1 includes a multiplexer 2, a sample hold circuit 3, an A / D converter 4, and a switch circuit 5. Although the CPU 1 includes other circuits, they are not shown in the figure because they are not directly related to the present invention. Co is a parasitic capacitance (floating capacitance) of the sample hold circuit 3.

  The multiplexer 2 selects one of the analog signals SG1 to SGn input to the input terminals T1 to Tn by sequentially switching the ports P1 to Pn, and outputs them to the sample hold circuit 3. The sample hold circuit 3 samples the selected analog signal, holds the voltage, and outputs the voltage to the A / D converter 4. The A / D converter 4 compares the voltage input from the sample hold circuit 3 with a reference voltage, and generates a digital signal corresponding to the voltage level of the analog signal based on the result.

  The switch circuit 5 includes a plurality of switches SW1 to SWn, and switches between a state where the input terminals T1 to Tn are grounded via the pull-down resistors RD1 to RDn and a state where they are not grounded. Therefore, one ends of the switches SW1 to SWn are connected to the ports Q1 to Qn, respectively, and the other end is grounded to the ground GND. The switches SW1 to SWn are composed of transistors, FETs, and the like. In the initial state, the switches SW1 to SWn are OFF.

  In the above configuration, the CPU 1 is an example of the “determination unit” in the present invention. The multiplexer 2 is an example of the “signal selection circuit” in the present invention. The switch circuit 5 is an example of the “switching circuit” in the present invention.

  Next, the operation of the A / D conversion apparatus 100 will be described with reference to the flowchart of FIG. Each step of the flowchart is executed by the CPU 1.

  In step S1, the multiplexer 2 switches the ports P1 to Pn of the CPU 1 and selects one of the analog signals SG1 to SGn input to the input terminals T1 to Tn. The selected analog signal is hereinafter referred to as “selection signal”. When the analog signal input to the input terminal Ti (i = 1, 2,... N) is selected, the selection signal is represented by SGi (i = 1, 2,... N).

  In step S2, the A / D converter 4 performs the first A / D conversion on the selection signal SGi. The A / D conversion value at this time is Xi (i = 1, 2,... N). This Xi is temporarily stored in a buffer memory (not shown).

  In the first A / D conversion, the switch SWi (i = 1, 2,... N) corresponding to the input terminal Ti is OFF, so that the pull-down resistor RDi is between the input terminal Ti and the ground GND. (I = 1, 2,... N) are not connected. That is, the input terminal Ti is not grounded via the pull-down resistor RDi.

  In step S3, the switch SWi corresponding to the input terminal Ti is turned on, and the pull-down resistor RDi is connected between the input terminal Ti and the ground GND. That is, the input terminal Ti is grounded via the pull-down resistor Ri.

  In step S4, the A / D converter 4 performs the second A / D conversion on the selection signal SGi. The A / D conversion value at this time is Yi (i = 1, 2,... N). This Yi is temporarily stored in a buffer memory (not shown).

  In step S5, a difference (absolute value) | Xi−Yi | between the A / D conversion value Xi calculated in step S2 and the A / D conversion value Yi calculated in step S4 is calculated, and the value is determined in advance. It is determined whether it is smaller than the threshold value α.

  Here, when no abnormality occurs in the circuit between the input terminals T1 to Tn and the ports P1 to Pn (multiplexer 2), the analog signal SGi input to the input terminal Ti is normally taken into the CPU 1. . In the first A / D conversion, since the input terminal Ti is not grounded to the ground GND via the pull-down resistor RDi, the A / D conversion value Xi is a value corresponding to the analog signal SGi. In the second A / D conversion, the input terminal Ti is grounded via the pull-down resistor RDi. Since the resistance value of the pull-down resistor RDi is sufficiently large as described above, the A / D conversion value Yi Although there is a slight error, the value is almost the same as the A / D conversion value Xi. Therefore, the difference (absolute value) between the A / D conversion value Xi and the A / D conversion value Yi is smaller than the threshold value α.

  On the other hand, if, for example, the input resistance Ri (i = 1, 2,... N) has an open failure (disconnection) between the input terminals T1 to Tn and the ports P1 to Pn (multiplexer 2), the input is input to the input terminal Ti. The analog signal SGi is not taken into the CPU 1. In the first A / D conversion, since the input terminal Ti is not grounded via the pull-down resistor RDi, the A / D conversion value Xi is the charge remaining in the parasitic capacitance Co due to the previous analog signal. It becomes a corresponding value. In the second A / D conversion, the input terminal Ti is grounded via the pull-down resistor RDi, so that the residual charge of the parasitic capacitance Co is discharged. Therefore, the A / D conversion value Yi is 0 [V ] Close to the value. Therefore, the difference (absolute value) between the A / D conversion value Xi and the A / D conversion value Yi is equal to or greater than the threshold value α.

  Thus, when the circuit is normal, the first A / D conversion value Xi and the second A / D conversion value Yi are the same regardless of whether or not the pull-down resistor RDi is connected between the input terminal Ti and the ground GND. , Almost the same value. On the other hand, when the input resistor Ri fails, the first A / D conversion value Xi and the second A / D conversion value Xi are determined depending on whether the pull-down resistor RDi is connected between the input terminal Ti and the ground GND. Deviation occurs from the D conversion value Yi. Therefore, the presence / absence of an open failure can be determined based on the comparison result between the difference between the two conversion values Xi and Yi and the threshold value α.

  FIG. 3 shows the relationship between the A / D conversion value of the analog signal SGi and the threshold value α. When the circuit is normal, the change in the A / D conversion value between when the pull-down resistor RDi is connected and when it is not connected falls within the range of the threshold value α. On the other hand, when the input resistor Ri has an open failure, the change in the A / D conversion value between when the pull-down resistor RDi is connected and when it is not connected does not fall within the range of the threshold value α.

  In step S5 of FIG. 2, if the difference (absolute value) between the A / D conversion values Xi and Yi is smaller than the threshold value α (step S5; YES), it is determined that no open failure has occurred, and the process proceeds to step S6. In step S6, the first A / D conversion value Xi is adopted as the output (A / D conversion value) of the A / D converter 4. The second A / D conversion value Yi is not adopted because it includes an error as described above.

  Then, it progresses to step S7 and turns off switch SWi. As a result, the pull-down resistor RDi is not connected between the input terminal Ti and the ground GND (the input terminal Ti is not grounded).

  When the process of step S7 is completed, the process returns to step S1, the ports 2 to Pn of the CPU 1 are switched to the next port by the multiplexer 2, and the processes of steps S2 to S7 are executed for the next analog signal.

  On the other hand, if the difference (absolute value) between the A / D conversion values Xi and Yi is greater than or equal to the threshold value α (step S5; NO) in step S5, it is determined that an open failure has occurred, and the process proceeds to step S8. Process. In this abnormality process, the CPU 1 outputs, for example, an alarm signal or an operation stop signal to be controlled.

  By the way, in detecting an open failure, a method of determining the presence / absence of a failure depending on whether or not the A / D conversion value in the state where the pull-down resistor RDi is connected is near 0 [V] is also conceivable. However, in this method, when an analog signal having a level of 0 [V] or in the vicinity thereof is input even under normal conditions, as shown in FIG. 4, the A / D conversion value is opened in a region smaller than the threshold value β. It is erroneously determined that a failure has occurred.

  On the other hand, according to the above-described embodiment, the relative value between the first A / D conversion value Xi (first conversion value) and the second A / D conversion value Yi (second conversion value). An abnormality is detected based on the relationship. For this reason, even when an analog signal SGi having a normal level of 0 [V] or in the vicinity thereof is input, it can be avoided that it is erroneously determined to be abnormal, and reliability is improved.

  FIG. 5 shows an A / D conversion device 200 according to another embodiment. 5 is different from FIG. 1 in that pull-down resistors RD1 to RDn are built in the CPU1. Other configurations are the same as those in FIG. Further, since the operation of the A / D conversion apparatus 200 is the same as that in FIG. 2, the description thereof is also omitted. Also according to this embodiment, the same effect as that of the A / D conversion device 100 of FIG. 1 can be obtained.

  FIG. 6 shows an A / D conversion apparatus 300 according to another embodiment. 6 differs from FIG. 1 in that pull-down resistors RD1 to RDn and switches SW1 to SWn are externally attached to the CPU 1, and signals that the switches SW1 to SWn are output from the ports U1 to Un of the CPU1. Based on the above, it is configured to perform an ON / OFF operation. Other configurations are the same as those in FIG. Further, since the operation of the A / D conversion apparatus 300 is the same as that of FIG. 2, the description thereof is also omitted. Also according to this embodiment, the same effect as that of the A / D conversion device 100 of FIG. 1 can be obtained.

  In the present invention, various embodiments can be adopted other than the above-described embodiments. For example, in the above embodiment, the difference between the two conversion values Xi and Yi is used as the degree of divergence between the first A / D conversion value Xi and the second A / D conversion value Yi. The ratio of both converted values Xi and Yi may be used.

  In the above embodiment, the case where an open failure has occurred in the input resistors R1 to Rn between the input terminals T1 to Tn and the ports P1 to Pn has been described as an example. The invention can be applied. For example, even when a disconnection occurs at a place other than the input resistors R1 to Rn, or a short circuit occurs at the input terminals T1 to Tn, a situation where the analog signals SG1 to SGn cannot be normally input to the CPU 1 occurs. The present invention is effective.

1 CPU
2 Multiplexer 3 Sample hold circuit 4 A / D converter 5 Switch circuit 100, 200, 300 A / D converter T1-Tn Input terminal R1-Rn Input resistance C1-Cn Capacitor RD1-RDn Pull-down resistance SG1-SGn Analog signal P1 ~ Pn, Q1 ~ Qn, U1 ~ Un Port SW1 ~ SWn Switch

Claims (6)

A plurality of input terminals to which analog signals are input;
A signal selection circuit that selects and outputs one of the analog signals input to each of the input terminals;
An A / D converter that converts an analog signal output from the signal selection circuit into a digital signal;
A switching circuit that switches between a state where each of the input terminals is grounded via a pull-down resistor and a state where the input terminal is not grounded;
Determination means for determining whether an abnormality has occurred between the input terminal and the signal selection circuit,
The determination means includes
For the analog signal selected by the signal selection circuit, the switching circuit does not ground the input terminal of the analog signal via a pull-down resistor, and the first conversion value calculated by the A / D converter, With the switching circuit grounding the input terminal of the analog signal via a pull-down resistor, the switching circuit compares the second conversion value calculated by the A / D converter,
An A / D conversion apparatus that determines whether or not the abnormality has occurred based on a degree of deviation between the first conversion value and the second conversion value. The A / D conversion device according to claim 1,
The determination means includes
Calculating a difference between the first converted value and the second converted value;
When the difference is smaller than a predetermined threshold, it is determined that the abnormality has not occurred, and the first conversion value is adopted as the output of the A / D converter,
When the difference is equal to or greater than a predetermined threshold, it is determined that the abnormality has occurred, and predetermined abnormality processing is performed. In the A / D conversion device according to claim 1 or 2,
The determination means is constituted by a CPU,
The signal selection circuit, the A / D converter, and the switching circuit are built in the CPU,
The A / D conversion device, wherein the pull-down resistor is externally attached to the CPU. The A / D conversion device according to claim 3,
The CPU has a port to which the switching circuit is connected,
The A / D conversion device, wherein the pull-down resistor is connected between the input terminal and the port. In the A / D conversion device according to claim 1 or 2,
The determination means is constituted by a CPU,
The A / D converter characterized in that the signal selection circuit, the A / D converter, the switching circuit, and the pull-down resistor are built in the CPU. In the A / D conversion device according to claim 1 or 2,
The determination means is constituted by a CPU,
The signal selection circuit and the A / D converter are built in the CPU,
The pull-down resistor and the switching circuit are externally attached to the CPU,
The A / D conversion device, wherein the switching circuit performs a switching operation based on a signal from the CPU.

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