JP5610551B2 - Data processor - Google Patents

Description

  The present invention relates to a data processor such as a microprocessor or a microcomputer, and relates to a technique that enables efficient code allocation to instructions.

Microprocessors have been mainly 32-bit processors since 68020, developed by Motorola in 1984. This is because 2 ³² B = 4 GB that can be specified by 32 bits has been a sufficiently large address space for about 20 years. However, due to the increase in required memory capacity accompanying the improvement in system performance and the decrease in memory unit price, in recent years, 64-bit processors capable of handling a space exceeding 4 GB are becoming widespread in the PC / server field. Even in the embedded processor, it is predicted that 64-bit conversion will proceed with a delay of several to ten years following the PC / server field.

  Unlike the PC / server processor with the highest priority on performance, the embedded processor is required to have both high efficiency and high performance. As a result, RISC (Reduced Instruction Set Computer) type embedded processors having a 16-bit fixed length instruction set capable of realizing high code efficiency have become widespread. High code efficiency is indispensable for the effective use of on-chip cache, RAM, and ROM even in the present when the capacity of off-chip memory has increased. However, efficient use of the 16-bit fixed-length instruction code space is indispensable for making such a processor 64-bit.

  In addition, as the result of the era of 32-bit processors for a long time, the basic operation has become 32 bits, and 8-bit and 16-bit data can be handled as being expanded to 32 bits on the processor register, or four 8-bit data and It has become common to handle two 16-bit data in units of 32 bits. Even in a 64-bit processor, it is necessary to support an arithmetic system based on 32 bits in addition to a 64-bit arithmetic system. For this reason, in existing 64-bit processors, both 32-bit and 64-bit operation instructions are defined for the same operation as necessary. As a result, the number of operation instructions increases in a 64-bit processor, and the code space required to define them also increases.

Japanese Patent Laid-Open No. 06-337783

PowerPC User Instruction Set Architecture Book I Version 2.02, Internet URL <http://www.ibm.com/developerworks/power/library/pa-archguidev2>, January 23, 2008 search SH-4A Extended Function Software Manual, Internet URL <http://documentation.renesas.com/jpn/products/mpumcu/rjj09b0235_sh4asm.pdf>, January 23, 2008 search AMD64 Architecture Programmer ’s Manual Volume 1: Application Programming, Revision 3.11, Internet URL <http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24592.pdf>, search January 23, 2008

  As described above, in order to make a 16-bit fixed-length instruction code RISC type embedded processor 64-bit, efficient use of an instruction code space (also simply referred to as an instruction code space) is indispensable. In particular, a 32-bit processor only needs to support a 32-bit arithmetic system, whereas a 64-bit processor needs to support both 32-bit and 64-bit arithmetic systems. For this reason, when both 32-bit and 64-bit operation instructions are defined for the same operation as in an existing 64-bit processor, the 16-bit fixed-length instruction set compresses the instruction code space, and the existing 32-bit It is difficult to construct a 64-bit arithmetic system that is equivalent to the arithmetic system. For example, when there are 256 types of operation codes of an instruction set having a 32-bit operation system that can be expressed by 8 bits, if a plurality of 64-bit operation instructions are simply added, the number of bits of the operation code is set to at least 1 It becomes necessary to increase the number of bits, the instruction code space becomes large, and the existing instruction system for 32-bit operations cannot be maintained.

  In particular, even when the lower 32 bits of the result of the 64-bit operation are the same as those of the 32-bit operation, it is necessary to define different instructions if the flags generated from the operation result are different between the 32-bit and 64-bit operations. When only the flags to be generated are different, the number of instructions for generating a flag can be reduced by increasing the number of flags to be generated by one instruction. For example, PowerPC in Document 1 generates multiple types of flags such as positive, negative, zero, overflow, and carry with one instruction. Further, in Document 2, a plurality of types of flags for a plurality of sizes are generated. That is, a flag “number of types” × “number of sizes” is generated. In Document 2, “4 types” × “2 sizes” = “8 flags”.

  However, if the number of flags generated by one instruction is increased, it is necessary to increase the number of instructions using the flag. For example, the branch condition of a conditional branch instruction is generally determined by a combination of “which flag is used” and “whether the flag to be used is set or cleared”. The conditional branch instruction in Document 2 takes 5 bits in the field for specifying how to use the flag, and 32 types can be specified. Therefore, the number of conditional branch instructions is 32 × “the number of variations other than flags”. Possible variations other than flags include the presence / absence of a delay slot and a branch destination address designation method.

  Thus, “increasing the number of flags” contributes to “reducing the number of instructions that generate flags (flag generation instructions)”, but causes “increase in the number of instructions using flags (flag using instructions)”. Therefore, if the number of flags is increased as in Document 2, the number of instructions cannot always be reduced. Document 2 is predicated on CISC (Complicated Instruction Set Computer), and there are a large number of arithmetic instructions, which are main flag generation instructions, because memory operands can also be specified. Then, the number of instructions could be reduced by increasing the number of flags and performing “reduction of the number of flag generation instructions”. On the other hand, general RISC is a 32-bit fixed-length instruction set, and there is a margin in the instruction code space, so the need for reducing the number of instructions is small. For this reason, there is no example of adjusting the number of flags in RISC to minimize the number of instructions. However, when the 16-bit fixed-length instruction set is made into a 64-bit processor of RISC, there is no room in the instruction code space. RISC has fewer flag generation instructions than CISC. For this reason, an optimization point cannot be found only by increasing the number of flags. It is important to adopt a system that improves the balance between the number of flag generation instructions and the number of flag use instructions.

  The first problem to be solved by the present invention is to reduce the number of instructions by adjusting the number of flags in an instruction set with a small number of flag generation instructions, and to minimize the code space necessary to define them. This is to enable a 64-bit processor having a sufficient instruction code space, such as RISC having a 16-bit fixed length instruction set.

  In general, even if the number of flags is increased, there are few examples of using a plurality of flags generated by one instruction, and only one is often used. On the other hand, if a combination of flags generated by a plurality of instructions is used, the program may be made efficient. However, if a plurality of flags are updated each time an instruction is executed, a flag generated by a preceding instruction is overwritten by a subsequent instruction, and it is difficult to use a combination of flags. For this reason, the generated flag is sequentially transferred to the register and logically operated on the register and then returned to the flag. The result of the logical operation on the register is determined as a numerical value to generate a flag, or a flag is generated. It is necessary to perform conditional branching and conditional execution each time. In these methods, the number of executed instructions increases and the branch frequency increases, so that the efficiency is low and the performance is lowered.

  In particular, when a certain piece of data is regarded as an operation target, there are no two types of sizes, and one of the two types of sizes is not necessary even if flags for a plurality of types are generated. With appropriate sign extension or zero extension, it is possible that flags for multiple sizes will have the same value and either can be used, but one is not required. Therefore, when a plurality of flags are defined, it is also effective to update only the necessary ones, leave the flags that are desired to remain, and enable the calculation between the flags, rather than updating them simultaneously. However, to realize this, it is necessary to specify both the type and location of the flag updated by the flag generation instruction and the flag used by the flag use instruction, and the largest instruction code space is required.

  The second problem to be solved by the present invention is to use a plurality of flags defined mainly for the purpose of minimizing the instruction code space without using a large instruction code space and to combine flags generated by a plurality of instructions. It is possible to do.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  In the present invention, when the number of flag generation instructions is large, the number of flags generated by one instruction is increased, so that the decrease in the number of flag generation instructions exceeds the increase in the number of flag use instructions. Based on this viewpoint, a means for defining an instruction for generating a plurality of flags according to the data size of the operand is adopted. In short, in a reduced instruction set computer type data processor, arithmetic processing is possible for operands of multiple data sizes, and processing equivalent to arithmetic processing for operands of small data sizes is applied to the lower side of operands of large data sizes. An instruction for generating a flag corresponding to each data size is added to the instruction set regardless of the data size of the operand to be processed.

  As a second aspect, in order to define a plurality of flags and update only the necessary ones, leave the flags that you want to keep, and enable operations between flags, the flags generated by the flag generation instruction and the flags used A means of specifying both types and locations of flags used by the instruction is adopted. That is, in addition to specifying a flag to be updated by a flag generated by a subsequent instruction among flags corresponding to each data size generated by the instruction, specifying a flag to be used among flags generated by a subsequent instruction to be modified; and A prefix instruction for specifying a logical operation between two specified flags is added to the instruction set.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to the invention of the first aspect, the types of instructions (the number of instructions) constituting the instruction set are reduced as a whole. Therefore, it is possible to contribute to the reduction of the code space of the instruction code in the RISC type data processor having no room for the instruction code space. For example, it becomes possible to make a 64-bit processor having a sufficient instruction code space, such as a 16-bit fixed-length instruction set RISC.

  The invention according to the second aspect makes it possible to use a plurality of flags defined mainly for the purpose of minimizing the instruction code space without using a large instruction code space, and to use a combination of flags generated by a plurality of instructions. Become.

It is a block diagram which illustrates roughly the composition of the processor core in the data processor concerning the present invention. FIG. 2 is a block diagram schematically illustrating an execution unit of a processor core according to the first embodiment of the present invention. It is explanatory drawing which illustrates schematically the flag update prefix instruction which concerns on Embodiment 2 of this invention. It is a block diagram which illustrates schematically the instruction decode unit of the processor core which concerns on Embodiment 2 of this invention. It is a block diagram which illustrates schematically the execution unit of the processor core which concerns on Embodiment 2 of this invention. It is explanatory drawing which illustrates schematically operation | movement of the processor core which concerns on Embodiment 2 of this invention. 1 is a block diagram illustrating a schematic configuration of a data processor according to the present invention.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  First, each of the above viewpoints will be specifically described. First, regarding the first aspect, the number of flag generation instructions of a 16-bit fixed length instruction set RISC type 32-bit processor is, for example, 17-4 for an instruction with an 8-bit operand field in the SH-4A processor core of Reference 3. The instruction is 12. Note that an instruction to be updated using a flag is counted as a flag generation instruction. Also, floating point instructions not related to the 64-bit processor are excluded. On the other hand, the number of instructions using a flag is 4 for an 8-bit instruction in the operand field and 1 for a 4-bit instruction. The number of flags is 1. Since the number of flag generation instructions increases and the number of flag use instructions decreases as the number of flags decreases, in the SH-4A processor core, 29 instructions versus 5 instructions and the number of flag generation instructions are about six times as many. Of the 29 flag generation instructions, 26 instructions have different operations depending on the operand size. Therefore, simply adding a 64-bit instruction increases 26 instructions. As a result, the ratio between the number of flag generation instructions and the number of flag use instructions is 55: 5, which is 11 times.

  When the number of flag generation instructions is large in this way, the number of instructions can be reduced by changing the ratio by increasing the number of flags generated by one instruction. As a method of increasing, a method of defining flags according to (1) flag type, (2) operand size, or (3) both can be considered.

  First, consider a method of defining a flag according to the type of flag (1). The types of flags of the SH-4A processor core include signed large / small, unsigned large / small, zero, overflow, carry, shift-out bit, and the like. Since the flag is 1 bit, the meaning changes depending on which flag is set. When different types of flags are set for different operations, the number of instructions does not decrease even if the number of types of flags is increased. Therefore, focusing on the case where only the flags generated by the same operation are different, comparison instructions are candidates. The comparison instruction can be changed from 18 instructions to 8 instructions by changing the three flags of signed size, unsigned size, and zero to different flags. Other instructions generate zero, overflow, carry, shift-out bits, etc., but since the operations are different, there is no effect in reducing the number of instructions even if the flags are divided by type. On the other hand, the number of instructions using the flag is tripled according to the number of flag types, from 5 instructions to 15 instructions. As a result, the number of instructions related to the flag is reduced by 10 instructions from 60 instructions and increased by 10 instructions, so it remains 60 instructions.

  Next, consider a method of defining a flag according to the operand size in (2). If a flag is provided for each of the 32-bit and 64-bit operand sizes, among the 29 instructions whose operations differ depending on the operand size, 15 instructions having the same operation in the lower 32 bits may be used as common instructions for 32 bits and 64 bits. it can. On the other hand, since the flag is doubled, the number of instructions using the flag is changed from 5 instructions to 10 instructions. As a result, the number of instructions related to the flag decreases by 15 instructions from 60 instructions and increases by 5 instructions, and thus decreases to 50 instructions.

  Further, consider a method of defining a flag corresponding to both (3). First, by using three kinds of flags, the comparison instruction can be changed from 18 instructions to 8 instructions. Furthermore, 8 instructions can be changed to 4 instructions by defining a flag for each size. Further, among the flag generation instructions other than the comparison instruction, it is possible to reduce six instructions having the same operation in the lower 32 bits. On the other hand, the number of flag use instructions is 6 times according to the number of flag types, from 5 instructions to 30 instructions. As a result, the number of instructions related to the flag increases from 65 instructions by 20 instructions to 25 instructions and thus increases to 65 instructions.

  As described above, when the number of flags is optimized from the viewpoint of minimizing the number of instructions, it has become clear that (2) the method of defining flags according to the operand size is the best.

  The instruction code space consumed by the instruction varies greatly depending on the number of bits used by the instruction in the operand field. With N bits, the space of 1 / (16−N) times of the entire instruction code space is consumed. For example, a space of 1/256 is consumed for 8 bits, and 1/4096 space is consumed for 4 bits. Therefore, what is important is a reduction in the number of instructions in the 8-bit operand field.

  Therefore, if the above consideration is limited to an instruction having an 8-bit operand field (also simply referred to as an 8-bit operand field instruction), the flag-related 8-bit operand field instruction of the 32-bit processor has 17 generation instructions and use instructions. Conditional branch instruction 4 is a total of 21 instructions. Of these, instructions whose operations differ depending on the operand size are 15 generated instructions. Therefore, if a 64-bit instruction is simply added, the generated instructions are increased by 15 instructions to 32 instructions. There are 36 instructions.

  First, in the method of defining a flag according to the type of flag (1), the comparison instruction can be changed from 17 instructions to 6 instructions by changing the flag to 3 types, but the conditional branch instruction is changed from 4 instructions to 12 instructions. Since the number increases, the number of instructions related to the flag decreases by 8 instructions from 36 instructions and increases by 8 instructions, so it remains 36 instructions.

  Next, in the method of defining a flag according to the operand size in (2), among the 15 instructions whose operations differ depending on the operand size, 10 instructions having the same operation in the lower 32 bits are shared by 32 bits and 64 bits. It can be. On the other hand, since the flag is doubled, the number of conditional branch instructions is changed from 4 instructions to 8 instructions. As a result, the number of instructions related to the flag is reduced to 30 instructions because it is reduced by 10 instructions from 36 instructions and increased by 4 instructions.

  Further, consider a method of defining a flag corresponding to both (3). First, by using three types of flags, the comparison instruction can be changed from 14 instructions to 6 instructions. Furthermore, 6 instructions can be changed to 3 instructions by defining a flag for each size. In addition, among the flag generation instructions other than the comparison instruction, it is possible to reduce three instructions having the same operation in the lower 32 bits. On the other hand, the number of flag use instructions is 6 times according to the number of flag types, from 4 instructions to 24 instructions. As a result, the number of instructions related to the flag increases by 14 instructions from 36 instructions to 20 instructions and increases to 42 instructions.

  As described above, it can be understood that the method of defining the flag in accordance with the operand size in (2) is the best even when limited to the 8-bit operand field instruction having a large influence on the instruction code space consumption. On the other hand, when applied to CISC in Document 2, the method (3), which was best for minimizing the code size of instructions, is the worst method in RISC.

  The first problem of the present invention is to reduce the number of instructions by adjusting the number of flags in an instruction set with a small number of flag generation instructions, to minimize the code space required to define them, and to have a fixed length of 16 bits Enabling a 64-bit processor having no instruction code space like RISC of the instruction set is achieved by defining a flag according to the operand size. Specifically, a flag is provided for each of the 32-bit and 64-bit operand sizes, and instructions with the same low-order 32-bit operation are integrated in 32-bit and 64-bit operand instructions, conditional branching according to an increase in the number of flags, etc. This is achieved by increasing the number of flags using instructions. As a result, the types of instructions (instruction numbers) constituting the instruction set are reduced as a whole.

  Regarding the second point of view, as described in the section above, in order to define a plurality of flags and update only the necessary ones, leave the flags you want to keep, and enable operations between flags, generate a flag. It is necessary to specify the type and location of both the flag updated by the instruction and the flag used by the flag using instruction, and the largest instruction code space is required.

  In order to solve this problem, it is only necessary to define a prefix instruction that is an instruction that modifies the subsequent instruction. The implementation of the prefix instruction is similar to the implementation of the variable-length instruction set, and there are conventional processors that use the prefix instruction as described from page 87 of Document 4. And if it is an engineer of ordinary skill in this field, it can be implemented. And what kind of prefix instruction is defined is important. In the present invention, as a flag update prefix instruction, a flag to be updated is specified, a flag to be used among flags generated by a subsequent instruction, and a logical operation between two specified flags are specified. If there are two types of flags and eight types of operations, they can be specified by a 5-bit operand field, and a large instruction code space is not required. Since a logical operation can also be specified, a logical operation between flags can be executed with the same number of instructions as when a logical operation is performed with another instruction in an instruction set that can suppress the update of a flag to be retained. As a result, a plurality of flags defined mainly for the purpose of minimizing the instruction code space can be used without using a large instruction code space, and flags generated by a plurality of instructions can be used in combination.

  A typical embodiment will be described based on the above viewpoint.

  [1] Reduced instruction set A computer-type data processor can perform arithmetic processing on operands having a plurality of data sizes, and performs processing equivalent to arithmetic processing on operands having a small data size on the lower side of an operand having a large data size. The instruction set has a first instruction for generating a flag (newU, newT) corresponding to each data size regardless of the data size of the operand to be processed. As a result, the types of instructions (instruction numbers) constituting the instruction set are reduced as a whole. Therefore, it is possible to contribute to the reduction of the instruction code space in the RISC type data processor in which the instruction code space has no room. For example, it becomes possible to make a 64-bit processor having a sufficient instruction code space, such as a 16-bit fixed-length instruction set RISC.

  [2] The data processor according to [1] further includes, for example, a second instruction in the instruction set that selects and uses a flag generated by the first instruction.

  [3] The data processor according to item 1, for example, includes a prefix instruction that qualifies the subsequent instruction that specifies a flag to be updated by a flag generated by a subsequent instruction among flags corresponding to each data size generated by the first instruction. Furthermore, it has in the said instruction set. Thereby, a plurality of flags can be defined and only necessary ones can be updated.

  [4] In the data processor according to item 1, for example, in addition to specifying a flag to be updated by a flag generated by a subsequent instruction among flags corresponding to each data size generated by the first instruction, a subsequent instruction to be generated is generated The instruction set further includes a prefix instruction for specifying a flag to be used among the flags to be used and specifying a logical operation between the two specified flags. Thereby, it is possible to define a plurality of flags and update only necessary ones, leave the flags to be left, and enable operations between the flags. Therefore, it is possible to use a plurality of flags defined mainly for the purpose of minimizing the instruction code space without using a large instruction code space and to combine flags generated by a plurality of instructions.

  [5] In the data processor according to item 1, for example, the plurality of data sizes are 32 bits and 64 bits.

  [6] In the data processor according to item 2, for example, the flag is a signed size, unsigned size, zero, overflow, carry, or shift-out bit for each of a plurality of data sizes.

  [7] Another data processor of the reduced instruction set computer type having an instruction execution unit (EXU) is a first instruction for executing a process involving generation of a flag and a process for using the flag. Has two instructions in the instruction set. The instruction execution unit includes arithmetic circuits (ALU, SFT), a flag latch circuit (U, T), and a flag selection circuit (FMUX) that perform processing according to the instruction decode result. The arithmetic circuit is capable of performing arithmetic processing on operands having a plurality of data sizes according to the decoding result of the first instruction, and performing processing equivalent to arithmetic processing on operands having a small data size on the lower side of the operand having a large data size A flag corresponding to each data size is generated irrespective of the data size of the operands that are operated on. The flag latch circuit latches the flag generated by the arithmetic circuit according to the decoding result of the first instruction. The flag selection circuit selects a flag latched by the flag latch circuit according to a decoding result of the second instruction.

  [8] In the data processor according to item 7, for example, the arithmetic circuit generates a flag of signed size, unsigned size, zero, overflow, carry, and shift-out bit for each data size, and one type of flag is generated from the generated flag. A flag is selected by the first instruction and latched in the flag latch circuit for each operand size.

  [9] In the data processor according to item 8, for example, the plurality of data sizes are 32 bits and 64 bits.

  [10] Still another data processor specifies a flag to be updated by a flag generated by a subsequent instruction among a plurality of flags generated by the calculation instruction, together with a calculation instruction capable of performing calculation processing and generating a plurality of flags. The instruction set has a prefix instruction that modifies the subsequent instruction.

  [11] Still another data processor is configured to designate a flag to be updated by a flag generated by a subsequent instruction among a plurality of flags generated by the calculation instruction, together with a calculation instruction capable of performing calculation processing and generating a plurality of flags. In addition, the instruction set includes a prefix instruction for designating a flag to be used among flags generated by a subsequent instruction to be modified and a logical operation between the two designated flags.

2. Details of Embodiments Embodiments will be further described in detail. The best mode for carrying out the present invention will be described below in detail with reference to the drawings. Note that members having the same function are denoted by the same reference symbols throughout the drawings for describing the best mode for carrying out the invention, and the repetitive description thereof will be omitted.

Embodiment 1
FIG. 7 illustrates a data processor DPU according to the present invention. The data processor DPU mainly includes a processor core CPU such as a central processing unit, and includes a nonvolatile memory ROM, a volatile memory RAM, an input / output interface circuit IOC, an external bus interface circuit EBIF and the like connected to the processor core CPU. For example, it is formed on one semiconductor substrate such as single crystal silicon by a complementary MOS correction circuit manufacturing technique. The nonvolatile memory ROM is used as a storage area for programs executed by the processor core CPU, and the volatile memory RAM is used as a work area for the processor core CPU.

  FIG. 1 schematically illustrates a block configuration of a processor core CPU. For example, the processor core CPU includes an instruction cache IC, an instruction fetch unit IFU, an instruction decode unit IDU, an execution unit EXU, a load store unit LSU, a data cache DC, and a bus interface unit unit BIU.

  The instruction fetch unit IFU outputs the instruction address IA to the instruction cache IC, and the instruction cache IC returns the instruction FI fetched from the address specified by the instruction address IA to the instruction fetch unit IFU. When a cache miss occurs, the missed address is output to the bus interface unit unit BIU as the external instruction address EIA, and after receiving the external fetch instruction EI, the instruction FI is returned to the instruction fetch unit IFU.

  The instruction decode unit IDU receives the instruction OP from the instruction fetch unit IFU and outputs a branch control signal BRC. In addition, the instruction OP is decoded, and the execution control information EXC and the load / store control information LSC are output to the execution unit EXU and the load / store unit LSU, respectively, and the register file RF is accessed to execute the execution operands EXA and EXB in the execution unit EXU. The load store address operands LSA and LSB and the store data SD are supplied to the load store unit LSU. Further, the execution result EXO is received from the execution unit EXU, and the load data LD is received from the load store unit LSU, and stored in the register file RF.

  The execution unit EXU receives the execution control information EXC and the execution operands EXA and EXB from the instruction decode unit IDU, performs an operation according to the execution control information EXC, and then returns an execution result EXO to the instruction decode unit IDU.

  The load / store unit LSU receives the load / store control information LSC, the load / store address operands LSA and LSB, and the store data SD from the instruction decode unit IDU, executes load / store in accordance with the load / store control information LSC, and then decodes the load data LD. Return to unit IDU. In addition, the data address DA is output to the data cache DC during the load store, and the data cache store data DCSD is also output during the store. The data cache DC returns the data cache load data DCLD when loading, and stores the data cache store data DCSD when storing. In the case of a cache miss, the missed address is output to the bus interface unit unit BIU as the external data address EDA, and after receiving the external load data ELD, the data cache load data DCLD is returned to the load store unit LSU. In addition, when data is copied back due to a cache miss or when data that is not cached is externally stored, the data is output as external store data ESD and the address of the data is output as an external data address EDA.

  The bus interface unit BIU receives the external instruction address EIA or the external data address EDA from the instruction cache IC or the data cache DC, outputs the external address EA outside the processor core CPU, requests the data, and receives it as the external data ED. , Output as external fetch instruction EI or external load data ELD, respectively. Further, the external data address EDA and the external store data ESD are received from the data cache DC, and are output as the external address EA and the external data ED outside the processor core CPU to issue a store request.

  FIG. 2 schematically illustrates an execution unit EXU of the processor according to the first embodiment of the present invention. The execution unit EXU includes an arithmetic logic unit ALU, a shifter SFT, a 32-bit flag multiplexer FM32, a 64-bit flag multiplexer FM64, a 32-bit shift-out multiplexer M32, a 64-bit shift-out bit multiplexer M64, an output multiplexer OMUX, and a 32-bit operation flag T. , A 64-bit operation flag U and a flag multiplexer FMUX. Although not shown, execution control information EXC from the instruction decode unit IDU is input to each component to control them.

  The arithmetic logic unit ALU receives the execution operands EXA and EXB from the instruction decode unit IDU, executes various arithmetic logic operations according to the execution control information EXC, and then executes the execution result ALO, a 32-bit flag group (signed large GT32, unsigned) A large GU32, zero Z32, overflow V32, carry C32) and 64-bit flag group (signed large GT64, unsigned large GU64, zero Z64, overflow V64, carry C64) are output.

  The shifter SFT receives the execution operands EXA and EXB from the instruction decode unit IDU, executes various shift operations according to the execution control information EXC, and then executes an execution result SFO, a 32-bit left shift-out bit SL32, a 64-bit left shift-out bit SL64, And the right shift-out bit SR is output. Then, the 32-bit shift-out bit multiplexer M32 selects the 32-bit left shift-out bit SL32 or the right shift-out bit SR according to the direction of the shift operation, and the 32-bit shift-out flag SF32, which is one of the 32-bit flag groups. Output as. Further, the 64-bit shift-out bit multiplexer M64 selects the 64-bit left shift-out bit SL64 or the right shift-out bit SR according to the direction of the shift operation, and is a 64-bit shift-out flag SF64 that is one of the 64-bit flag groups. Output as.

  The output multiplexer OMUX selects one of the execution result ALO and the execution result SFO according to the execution control information EXC, and outputs it as the execution result EXO.

  The 32-bit flag multiplexer FM32 selects a flag from the 32-bit flag group according to the type of instruction, generates a new 32-bit flag newT, and uses the 32-bit flag T as an input. Similarly, the 64-bit flag multiplexer FM64 selects a flag from the 64-bit flag group according to the type of instruction, generates a new 64-bit flag newU, and inputs it to the 64-bit flag U. The 32-bit flag T and the 64-bit flag U latch these inputs and output them to the flag multiplexer FMUX. The flag multiplexer FMUX selects one of the 32-bit flag T and the 64-bit flag U according to the instruction to be used, and outputs it as a flag output FO. The flag multiplexer FMUX uses the value after latch to select the flag to be used in the next instruction, and uses the value before latch as execution control information EXC from the instruction decode unit IDU (not shown). The control information of the next command can be received.

  According to the first embodiment, the types of instructions (the number of instructions) constituting the instruction set can be reduced as a whole. Therefore, it is possible to contribute to the reduction of the code space of the instruction code in the RISC type data processor having no instruction code space, and the 64-bit of the processor having no instruction code space like the RISC of the 16-bit fixed length instruction set. Can be realized.

<< Embodiment 2 >>
FIG. 3 schematically illustrates a flag update prefix instruction according to the second embodiment of the present invention. The flag update prefix instruction designates a flag to be updated, designates a flag to be used among flags generated by subsequent instructions, and designates a logical operation between the two designated flags. If there are two types of flags, a 32-bit flag T and a 64-bit flag U, 1 bit is used for designating a flag to be updated, and 1 bit is used for designating a flag to be used among flags generated by subsequent instructions. Also, assuming that there are six types of operations, 3 bits are used to specify a logical operation between two specified flags. Therefore, the flag update prefix instruction can be specified by a 5-bit operand field and does not require a large instruction code space.

  When the 16-bit fixed-length instruction set is defined, the flag update prefix instruction is designated in the 11-bit operation type designation field OPT as shown in FIG. 3, and the flag to be updated is designated in the 2-bit source destination designation field SD. Among the flags generated by the designation and subsequent instructions, the flag to be used is designated, and the logical operation between the two flags designated in the 3-bit logical operation designation field TYP is designated. There are six types of logical operations: logical product AND, logical sum OR, negative logical product ANDN, negative logical sum ORN, exclusive logical sum XOR, and new flag NEW, each of which is assigned 000 to 101 in the TYP field. The source and source destination flags are added to this type of operation to make it mnemonic. In the SD field, the higher order is the source, the lower order is the destination, 0 indicates the 32-bit flag T, and 1 indicates the 64-bit flag U. NewT in the action column is a 32-bit flag generated by the subsequent instruction, newU is a 64-bit flag generated by the subsequent instruction, & =, | =, ^ =, =, ~ are operators having the same meaning as in the C language, and & = Is the logical product of the value on the right side and the value on the left side and assigned to the variable on the left side. | = Is the logical sum of the value on the right side and the value on the left side and assigned to the variable on the left side. The exclusive OR of the value and the value on the left side is calculated and assigned to the variable on the left side, = indicates that the value on the right side is assigned to the variable on the left side, and ~ indicates that the value on the right side is logically inverted.

  For example, when SD = 00 and TYP = 000, the type of logical operation is logical AND, the update flag (destination flag) is a 32-bit flag T, and the flag (source flag) used among the flags generated by subsequent instructions Is a 32-bit flag T, the mnemonic is ANDTT, and the operation is T & = newT; U: unchanged, so the 32-bit flag is obtained by ANDing the 32-bit flag T and the 32-bit flag T among the flags generated by the subsequent instruction. The flag update prefix instruction is stored in T and the 64-bit flag U is not updated. Then, in the operation of the subsequent instruction, if there is no prefix instruction, the update of the 32-bit flag T and the 64-bit flag U with the generated flag is replaced with the operation of specifying the flag update prefix.

  Since a difference in configuration between the second embodiment and the first embodiment appears in the instruction decode unit IDU and the execution unit EXU, a typical block configuration of the processor core is shown in FIG. 1 as in the first embodiment.

  FIG. 4 schematically illustrates an instruction decode unit IDU of a processor according to the second embodiment of the present invention. An example of a scalar processor that issues one instruction per cycle is shown. However, a processor that uses a prefix instruction as in Reference 4 has existed in the past, and if it is an engineer of ordinary skill in this field, a superscalar of prefix decoding and issuing method Application to other issuance forms such as out-of-order is possible. Also, in this embodiment, it is assumed that only the flag update prefix instruction is a prefix instruction. However, it is possible for an engineer with ordinary skills in this field to extend it to handle other prefix instructions. .

  The instruction decode unit IDU includes a main decoder DEC and a prefix decoder PF-DEC. The main decoder DEC decodes the instruction OP supplied from the instruction fetch unit IFU, and uses the execution control information op-exc as a part of the effective control information EXC to the execution unit EXU. The 32-bit flag update control op-wrt and the 64-bit flag The U update control op-wru is output to the prefix decoder PF-DEC, the load / store control information LSC is output to the load / store unit LSU, and the register file control information RFC is output to the register file RF. Of the register file control information RFC, write information is supplied when the issued instruction reaches the register write stage.

  The file RF supplies the execution operands EXA and EXB to the execution unit EXU, the load / store address operands LSA and LSB, and the store data SD to the load / store unit LSU based on the register file control information RFC. Further, the execution result EXO is received from the execution unit EXU, and the load data LD is received from the load store unit LSU, and stored in the register file RF.

  The prefix decoder PF-DEC decodes the operation type designation field OPT of the instruction OP, sets a valid flag v if the instruction OP is a flag update prefix, and clears otherwise. The 2-bit source destination designation field SD is latched as prefix source flag designation information pfsrc and prefix destination flag information pfdst, respectively. Further, the logical operation designation field TYP is latched as prefix logical operation designation information pftyp. If the instruction OP is a flag update prefix instruction, it is also supplied to the main decoder DEC. At this time, the main decoder DEC regards the flag update prefix as a no operation code, and outputs control information such that the execution unit EXU and the load / store unit LSU do nothing.

  In the next cycle in which the instruction OP is a flag update prefix instruction, the main decoder DEC decodes the subsequent instruction and outputs various control information as described above. On the other hand, in the prefix decoder PF-DEC, the processing proceeds using the information latched in the previous cycle. Since the instruction OP is a flag update prefix instruction, the valid flag v is set, the logical operation designation information type, the 32-bit flag source information srt, the 64-bit flag source information sru, the 32-bit flag update control wrt, and the 64-bit flag update. As control wru, prefix logical operation designation information pftyp, prefix flag source designation information pfsrc, prefix flag source designation information pfsrc, prefix destination flag information pfdst is 0, and prefix destination flag information pfdst is 1 are output. To do. As a result, as the control information for generating the flag, the 32-bit flag update control op-wrt and the 64-bit flag update control op-wru from the coder are overridden mainly, and the information of the flag update prefix instruction is output.

  On the other hand, in the next cycle in which the instruction OP is not a flag update prefix instruction, the valid flag v is not raised, so that the logical operation designation information type, 32-bit flag source information srt, 64-bit flag source information sru, 32-bit flag update As control wrt and 64-bit flag update control wru, 101, 0, 1, 32-bit flag update control op-wrt and 64-bit flag update control op-wru are output, respectively. As a result, the output of the main decoder DEC is output as the instruction decode unit IDU. It should be noted that 101, 0, and 1 are output as the logical operation specifying information type, the 32-bit flag source information srt, and the 64-bit flag source information sru, respectively, without the main decoder DEC output, to specify the original operation of the instruction .

  The logical operation designation information type, 32-bit flag source information srt, 64-bit flag source information sru, 32-bit flag update control wrt and 64-bit flag update control wru are effective together with the execution control information op-exc generated by the main decoder DEC. It is output to the execution unit EXU as control information EXC.

  FIG. 5 schematically illustrates an execution unit EXU of the processor according to the second embodiment of the present invention. The common parts with the execution unit EXU of the processor according to the first embodiment illustrated in FIG. 2 have the same functions. The additional portions are a 32-bit flag source multiplexer S32, a 64-bit flag source multiplexer S64, a 32-bit flag logic operator FL32, and a 64-bit flag logic operator FL64.

  The 32-bit flag source multiplexer S32 selects a new 32-bit flag newT or a new 64-bit flag newU according to the 32-bit flag source information srt from the instruction decode unit IDU, and supplies it to the 32-bit flag logic unit FL32. The 32-bit flag logical operator FL32 performs a logical operation according to the logical operation designation information type from this and the 32-bit flag T, and sets the result as a new value latched in the 32-bit flag T. Similarly, the 64-bit flag source multiplexer S64 selects a new 32-bit flag newT or a new 64-bit flag newU according to the 64-bit flag source information srt from the instruction decode unit IDU, and sends it to the 64-bit flag logic operator FL64. The 64-bit flag logical operation unit FL64 supplies the 64-bit flag logical unit FL64 to the 64-bit flag U and performs a logical operation in accordance with the logical operation designation information type, and sets the result as a new value to be latched in the 64-bit flag U.

  As described above, by the instruction decode unit IDU and the execution unit EXU according to the second embodiment of the present invention, the flag update prefix instruction that does not require a large instruction code space is used to suppress the update of the flag that is to be retained, and between the flags generated by a plurality of instructions Can be logically operated.

  Next, the effect of the flag update prefix instruction will be described using a specific example. FIG. 6 schematically illustrates an example of the operation of the processor according to the second embodiment of the present invention. The C program in FIG. 6 is a program for executing the contents in {} when the 64-bit pointer p is not a NULL pointer and the 32-bit variable i is larger than 10. The NULL pointer is not pointing at anything, and the value is 0.

  When this C program is described in an assembler including a flag update prefix instruction, it is described in four instructions as shown in FIG. First, in a first step, the 64-bit pointer p and the NULL pointer value 0 are compared with a 64-bit size using CMP / EQ p, 0, and the comparison result is stored in the 64-bit flag U. A 64-bit flag U is set when the 64-bit pointer p is a NULL pointer. That is, U = (p == NULL). At this time, the result of comparing the 64-bit pointer p and the lower 32 bits of the NULL pointer value 0 is stored in the 32-bit flag T, but this is not used in this program. In the second step, the flag update prefix instruction ORNTU is decoded. In the third step, if the 32-bit variable i is greater than 10 in CMP / GT i, 10, a new 32-bit flag newT is set. Since U | = ˜newT is satisfied by the flag update prefix instruction ORNTU, U = (p == NULL) | ˜ (i> 10). At this time, the 32-bit flag T is unchanged. As a result, the 64-bit flag U contains the inverted value of the conditional expression of the “if” statement of the C program. In the fourth step, BT. If U is 1 by D_after_if_close, that is, if the conditional expression is not satisfied, the if statement is not executed because it jumps after the if statement.

  As described above, when the flag update prefix instruction is used, a plurality of comparison results can be collected, so that the condition determination is completed in one conditional branch. If the flag update prefix instruction is not used, it is necessary to perform a conditional branch every time the condition is determined, and it is difficult to increase the speed. Alternatively, when a logical operation is performed by transferring the generated flag to the general-purpose register, the U-flag generated by executing the flag transfer instruction MOVU R0 is transferred to the general-purpose register R1 instead of the flag update prefix instruction in the second step. Before the 4-step conditional branch, the T flag generated by executing the flag transfer instruction MOVT R0 is transferred to the general-purpose register R1, logically inverted by NOT R0, and the higher order is cleared by AND # 1, R0, and OR R0 , R1 (p == NULL) | to (i> 10). Further, (p == NULL) | to (i> 10) are stored in the 32-bit flag T by SHLR R1. Therefore, the number of instructions increases by 4 and doubles, thereby degrading performance. As described above, the flag update prefix instruction can speed up complicated condition determination.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof. For example, a flag update prefix instruction is represented by ORNTU, in addition to specifying a flag to be updated by a flag generated by a subsequent instruction, specification of a flag to be used among flags generated by the subsequent instruction, and two specified flags It has a function to specify each logical operation between them. The present invention is not limited to this, and may be an instruction having only a function of designating a flag to be updated by a flag generated by a subsequent instruction among flags corresponding to the respective data sizes generated previously.

IC instruction cache IFU instruction fetch unit IDU instruction decode unit EXU execution unit LSU load store unit DC data cache BIU bus interface unit unit IA instruction address EIA external instruction address OP instruction BRC branch control signal EXC execution control information LSC load store control information RF register File EXA, EXB Execution operand LSA, LSB Load store address operand SD store data EXO execution result DA data address DCSD data cache store data DCLD data cache load data ELD External load data EIA External instruction address EA External address ED External data EI External Fetch instruction ESD external store data ALU arithmetic logic Calculator SFT Shifter FM32 32-bit flag multiplexer FM64 64-bit flag multiplexer M32 32-bit shift-out multiplexer M64 64-bit shift-out bit multiplexer OMUX Output multiplexer T 32-bit operation flag U 64-bit operation flag newT New 32-bit flag newU New 64-bit flag FMUX flag multiplexer ALO, SFO execution result GT32 32-bit data size signed large flag GU32 32-bit data size unsigned large flag Z32 32-bit data size zero flag V32 32-bit data size overflow flag C32 32-bit Carry flag for data size GT64 Signed large flag for 64-bit data size G U64 64-bit data size unsigned large flag Z64 64-bit data size zero flag V64 64-bit data size overflow flag C64 64-bit data size carry flag SL32 32-bit left shift out bit SL64 64-bit left shift out bit SR right shift Out bit SF32 32-bit shift-out flag SF64 64-bit shift-out flag S32 32-bit flag source multiplexer S64 64-bit flag source multiplexer FL32 32-bit flag logic unit FL64 64-bit flag logic unit

Claims (1)

A data processor having, in an instruction set, an arithmetic instruction capable of performing arithmetic processing and generating a plurality of flags,
Among the plurality of flags generated by the arithmetic instruction, in addition to specifying the flag to be updated by the flag generated by the subsequent instruction, the flag to be used among the flags generated by the subsequent instruction to be modified, and between the two specified flags A data processor having, in the instruction set, a prefix instruction for designating each logical operation .

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