JP5610177B2 - Functional device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a functional device in which micromachines are stacked on an integrated circuit substrate and a manufacturing method thereof.

  Conventionally, when a micromachine (hereinafter referred to as MEMS (Micro Electro Mechanical System)) is incorporated into a so-called LSI substrate in which a large-scale integrated circuit (hereinafter referred to as LSI) is incorporated in a Si substrate. A method is known in which LSI and MEMS are simultaneously fabricated on a Si substrate by surface micromachining. In this method, annealing of a high-temperature process, for example, at 1000 ° C. or higher for 30 minutes is required to relieve the stress of polycrystalline silicon (Si) constituting the MEMS. Therefore, it is difficult to integrate fine LSIs having a small design rule, for example, about 1 μm or less.

  If polycrystalline silicon (Si) is changed to polycrystalline silicon germanium (SiGe), the process temperature can be lowered to about 400 ° C., but it is difficult to control the composition of polycrystalline SiGe. In addition, in the case of surface micromachining by metallization, a MEMS is produced by a sputtered metal film or a plating film, so that mechanical characteristics such as vibration are not good. In addition, packages need to be paid separately. Further, since the LSI and the MEMS are manufactured on the Si substrate at the same time, it is often impossible to entrust the manufacture of the LSI substrate to a general LSI foundry. Furthermore, since the MEMS cannot be formed directly on the LSI, the area efficiency of the Si substrate is lowered.

  On the other hand, a method is also known in which an LSI is formed on a part of an SOI (Silicon On Insulator) substrate, and a MEMS is manufactured in a region where no integrated circuit is formed by a low temperature process such as RIE or thin film deposition. ing. In this method, single-crystal Si having excellent mechanical characteristics can be used as the MEMS material, but similarly, the MEMS cannot be formed immediately above the LSI, so that the area efficiency of the Si substrate is lowered. Therefore, it is difficult to apply to an expensive advanced LSI from the viewpoint of cost. In addition, processing of MEMS is limited to those that do not damage the LSI. In this case, the package needs to be treated separately.

There is also known a method for manufacturing a MEMS by bonding single crystal silicon to an LSI substrate via a silicon oxide film (SiO ₂ ) or a spin-on glass serving as a sacrificial layer. In this method, the processing of the MEMS is similarly limited to that which does not damage the LSI, and the SiO ₂ disposed on the LSI substrate or the MEMS is etched when the sacrificial layer such as SiO ₂ is etched. There is a risk of damage, which is disadvantageous in terms of yield at the time of bonding, and the package needs to be treated separately.

  Furthermore, a method for embedding MEMS in a Si wafer and manufacturing an LSI on the MEMS is also known. In this method, since the Si grown for embedding the MEMS becomes polycrystalline suitable for LSI on the MEMS, the MEMS cannot be formed on the LSI as well. Therefore, the area efficiency of the Si substrate is lowered, and it is difficult to apply to an expensive advanced LSI from the viewpoint of cost. In addition, MEMS embedded in a Si wafer has many restrictions on materials and manufacturing processes.

  As described above, in any method, especially in the combination of the most advanced LSI and high-performance MEMS, it is necessary to consider the process consistency between the LSI and the MEMS, so that the MEMS that can be manufactured is limited. For example, MEMS that requires a high-temperature process such as PZT cannot be used, and the integration of two or more types of MEMS cannot be supported. Therefore, such MEMS are generally integrated and packaged at the chip level, and therefore there is a limit to miniaturization of the device. Due to parasitic capacitance, parasitic resistance, parasitic inductance, etc., high performance is achieved. There is a limit.

  By the way, a so-called LTCC (Low Temperature Coated Ceramic) substrate in which passive components such as an inductor, a resistor, and a capacitor are incorporated in the substrate is known. However, integration of such LTCC substrate, LSI substrate and MEMS has not been attempted at present.

  In contrast, Patent Document 1 discloses a first Si substrate including at least one MEMS and at least one germanium pattern layer, a second Si substrate including at least one aluminum layer and one electrical contact, There is disclosed a wafer structure characterized in that a germanium layer is bonded to an aluminum layer to produce strong electrical and mechanical contact.

  Patent Document 2 discloses a MEMS base device configured by sticking a MEMS to a micromachine chip by SLID (Solid Liquid Interdiffusion) bonding, and then sticking a lid to the MEMS chip by SLID bonding.

International Publication No. 2006/101769 Pamphlet US Pat. No. 6,793,829

The method disclosed in Patent Document 1 can solve the problems of the integration method using the surface micromachining and the integration method using the SOI substrate. However, it is difficult to integrate a plurality of devices in addition to LSI, that is, two or more types of MEMS, or MEMS and passive components. In particular, when integrating MEMS and passive components, it is necessary to form the MEMS and passive components on the same substrate at the same time, and it is necessary not only to consider the process consistency of these, but also a large chip area is required. There are also problems in terms of cost and cost.
In the wafer structure according to Patent Document 1, it is possible to integrate passive components formed simultaneously with the MEMS on the CMOS substrate, but parasitic capacitance is generated by the MEMS substrate or the adjacent LSI substrate. Characteristics will be impaired.
Further, when the LSI and MEMS take-out electrodes are exposed to the chip surface through the through-wiring and corresponding to surface mounting by solder reflow, a specific method is not described in Document 1, but structurally, It is necessary to manufacture the through electrode on the same substrate simultaneously with the MEMS, and it is necessary not only to consider the process consistency, but also parasitic capacitance generated between the wiring and the substrate becomes a problem.

  The MEMS base device according to Patent Document 2 uses the feature that once the SLID junction is joined, it does not remelt at the same junction temperature, but there is no detailed explanation about the MEMS chip, and an LSI substrate is not assumed. Therefore, the object, configuration and effect are different from the present invention. Even if it is applied to an LSI substrate, the same problem as in Patent Document 1 occurs.

  In view of the above problems, an object of the present invention is to provide a functional device capable of integrating an integrated circuit substrate and a micromachine, and an LTCC substrate serving as a cover at a wafer level, and a method for manufacturing the same. Yes.

In order to achieve the above object, a functional device of the present invention is provided with an integrated circuit substrate composed of an integrated circuit formed on the surface of a conductor substrate and a gap between the integrated circuit substrate and a thermal expansion coefficient substantially the same as that of a semiconductor substrate. A cover substrate made of the above material, a circumferential sealing portion for sealing a gap between the integrated circuit substrate and the cover substrate, and disposed between the integrated circuit substrate and the cover substrate and housed in the sealing portion. with and electrically connected to Ru micromachined integrated circuit board and / or the cover substrate, the metal pads in the extraction electrode for mounting are disposed on either of the cover substrate or integrated circuit substrate, the Te, the cover substrate Made of ceramic substrate or glass substrate, the micromachine is formed independently of the cover substrate and the integrated circuit substrate, and is mechanically bonded to the surface of the cover substrate facing the integrated circuit substrate And wherein the Rukoto.
Another functional device of the present invention includes an integrated circuit substrate made of an integrated circuit formed on the surface of a semiconductor substrate, and a cover made of a material having substantially the same thermal expansion coefficient as that of the semiconductor substrate. A substrate, a circumferential sealing portion that seals a gap between the integrated circuit substrate and the cover substrate, and an integrated circuit substrate disposed between the integrated circuit substrate and the cover substrate and housed in the sealing portion; And / or a micromachine that is electrically connected to the cover substrate, and a metal pad that is disposed on either the cover substrate or the integrated circuit substrate and serves as an extraction electrode for mounting. The cover substrate is a ceramic substrate or glass. The micromachine is formed of a substrate, is formed independently of the cover substrate and the integrated circuit substrate, and is mechanically bonded to the integrated circuit substrate.
In the above configuration, the micromachine is preferably bonded to the cover substrate by anodic bonding or metal bonding.
The micromachine is preferably bonded to the integrated circuit substrate by metal bonding.
The metal pad for mounting is preferably connected to a through wiring disposed on the cover substrate or the semiconductor substrate.
According to the first configuration, the integrated circuit board and the micromachine can be independently optimized and manufactured. That is, the integrated circuit board and the micromachine can be manufactured by entrusting each to a foundry.
Therefore, the micromachine can be processed at a high temperature, for example, without considering the manufacturing process of the integrated circuit substrate. Therefore, a micromachine using a material such as PZT can be manufactured.

The integrated circuit board, the micromachine, and the cover board can be manufactured integrally at the wafer level, and the micromachine can be disposed immediately above the integrated circuit in the integrated circuit board, so that the area efficiency is improved. It is possible to configure a small chip size package.
Further, since the cover substrate is made of a material having a low thermal expansion coefficient that is substantially the same as that of the Si substrate, when the cover substrate is bonded to the integrated circuit substrate, the entire device warps due to a thermal change based on the difference in the thermal expansion coefficient. In addition, the cover substrate is not peeled off from the integrated circuit substrate, and the reliability of the device is improved.
In particular, when the micromachine is bonded to the integrated circuit substrate or the cover substrate by anodic bonding, the distance between the electrodes with respect to the integrated circuit substrate or the cover substrate can be set with high accuracy. Suitable for switches.

In the above configuration, preferably, a circumferential sealing metal pad provided on the surface of the integrated circuit substrate and a circumferential sealing metal pad provided on the cover substrate corresponding to the sealing metal pad are provided. And are connected via a sealing portion provided on one or both of the metal pads for sealing.
According to the above configuration, the internal space defined by the integrated circuit substrate and the cover substrate is maintained in a vacuum, for example, or filled with an inert gas, so that the micromachine disposed in the internal space has an internal space. It can operate reliably without causing chemical change or adsorption due to moisture or the like.

In the above configuration, the integrated circuit substrate is preferably a ceramic substrate having a surface on which a metal pad for an extraction electrode from the integrated circuit is provided, a cover substrate containing passive components therein, and a micromachine joined thereto. The surface of the ceramic substrate is provided with a metal pad for bonding the passive component and the micromachine, and the metal pad of the cover substrate and the metal pad of the integrated circuit substrate are attached to one or both of the metal pads. It joins through the provided metal bump.
According to the above configuration, since the integrated circuit substrate, the micromachine, and the cover substrate are independently manufactured and then integrated, a device including the integrated circuit, the micromachine, and the passive component can be manufactured. Furthermore, since these three elements, that is, the integrated circuit substrate, the micromachine, and the cover substrate are laminated, the area efficiency can be increased.

In the above configuration, preferably, the integrated circuit substrate or the cover substrate includes a stopper portion that protrudes toward the opposing substrate surface in order to set the integrated circuit substrate and the cover substrate at a predetermined interval. The micromachine is bonded so as not to contact the surface of the cover substrate or the integrated circuit substrate.
The cover substrate may be a glass substrate, and the micromachine may be bonded to the glass substrate.
According to the above configuration, when the integrated circuit substrate and the cover substrate are joined, the gap between these substrates is maintained at a predetermined value or more, so that the operation space of the micromachine is secured and the micromachine can be operated reliably. is there.

  In order to achieve the above object, a method for manufacturing a functional device according to the present invention includes a first stage of fabricating a micromachine in a Si device layer formed on a sacrificial layer of a Si substrate, and a thermal expansion coefficient substantially the same as that of a Si substrate. A second step of forming a metal pad for sealing and bonding on the lower surface of the cover substrate made of material, and a metal for bonding and sealing on the upper surface of the integrated circuit substrate in which the integrated circuit is configured Forming a pad and forming a metal bump on the metal pad; a fourth step of forming a bonding layer and a sealing portion on the metal bump formed in the third step; A fifth stage in which the micromachine fabricated in step (2) is bonded to the cover substrate on which the metal pads are formed in the second step by anodic bonding, the sacrificial layer is etched to remove the Si substrate, and an integrated circuit Place the cover board on the board And a sixth step of joining the integrated circuit board and the cover substrate using a sealing portion and sealing a region between the integrated circuit board and the cover substrate. .

Another manufacturing method of the functional device of the present invention includes a first step of manufacturing a micromachine in a Si device layer formed on a sacrificial layer of a Si substrate, and a cover substrate made of a material having a thermal expansion coefficient substantially the same as that of the Si substrate. Forming a metal pad for sealing and bonding on the lower surface of the substrate, forming a bonding layer and a sealing portion on the metal pad, and an upper surface of the integrated circuit substrate in which the integrated circuit is configured Forming a metal pad for bonding and a metal pad for sealing, forming a metal bump on the metal pad, and bonding to the micromachine among the metal bumps formed in the third stage. The fourth stage of forming the bonding layer on the metal bump and the micromachine manufactured in the first stage are bonded to the integrated circuit substrate on which the bonding layer has been formed in the fourth stage by metal bonding. Etching the sacrificial layer a fifth step of removing the i-substrate, placing the cover substrate on the integrated circuit substrate, joining the integrated circuit substrate and the cover substrate using a sealing portion on the cover substrate, and integrating the integrated circuit substrate And a sixth stage for sealing the region between the cover substrates.
In another method of manufacturing a functional device of the present invention, preferably, the metal bump formed on the metal pad in the third stage is made of a material that does not become a liquid phase in the sixth stage.

  In the above configuration, the sacrificial layer is preferably made of Ge or resin. The sixth stage is preferably performed in any atmosphere of vacuum, inert gas and dry gas.

  In the above configuration, preferably, in the first stage, simultaneously with the fabrication of the micromachine, a stopper portion for forming a predetermined interval between the integrated circuit board and the cover substrate is formed, and in the third stage, the integrated circuit board is formed. Metal bumps are formed on the metal pads corresponding to the upper stopper portion, and in the fifth stage, this stopper portion is joined to the lower surface of the cover substrate together with the micromachine by anodic bonding. In the sixth step, the stopper portion is Abut against a corresponding metal pad on the integrated circuit board.

  In the above configuration, preferably, in the second stage, a ceramic substrate containing passive components therein is used as the cover substrate, and in the sixth stage, the passive components in the cover substrate are integrated into the integrated circuit in the integrated circuit substrate. Connect to.

  In the above configuration, preferably, the glass substrate is used as the cover substrate in the second stage, and the micromachine is transferred to the glass substrate in the fifth stage.

  In the above configuration, preferably, in the second stage, a glass substrate having a through wiring penetrating vertically is used as the cover substrate in the second stage, and in the sixth stage, the integrated circuit and the micromachine are taken out from the integrated circuit board. The electrode is exposed on the upper surface of the cover substrate through the through wiring.

  In the above configuration, preferably, in the third stage, an integrated circuit board provided with through-wirings extending vertically is used as the integrated circuit board, and in the sixth stage, the integrated circuit and the micromachine in the integrated circuit board are used. The extraction electrode is exposed on the lower surface of the integrated circuit board through the through wiring.

  According to the above configuration, the functional device can be manufactured by independently optimizing the integrated circuit substrate, the micromachine, and the cover substrate.

  According to the present invention, it is possible to configure a functional device that can be integrated by stacking an integrated circuit substrate and a micromachine, and a cover substrate that can also incorporate a passive circuit at the wafer level.

Hereinafter, the present invention will be described in detail based on the embodiments shown in the drawings.
(First embodiment)
FIG. 1 shows a first embodiment of a functional device 10 according to the invention.
In FIG. 1, a functional device 10 includes an integrated circuit substrate (hereinafter referred to as an LSI substrate) 11 on which an integrated circuit is disposed, a cover substrate 13 that covers the LSI substrate 11, an LSI substrate 11, and a cover substrate 13. A circumferential sealing portion 14 to be joined, and a micromachine 12 disposed between the LSI substrate 11 and the cover substrate 13 and electrically connected to either the LSI substrate 11 or the cover substrate 13 are provided. At least the micromachine 12 is sealed by the sealing portion 14.

  The LSI substrate 11 has a known configuration and includes an integrated circuit (hereinafter referred to as LSI) configured on the surface of the semiconductor substrate. That is, the LSI substrate 11 includes, for example, a multilayer wiring layer and various elements configured in these wiring layers or between the wiring layers. Further, the LSI substrate 11 is provided with a metal pad 11a as an extraction electrode from the LSI, a metal pad 11c for gap adjustment, and a circumferential metal pad 11b for sealing on the upper surface. On the metal pads 11a and 11c, metal bumps 11d and 11f are further formed on the surface by plating or the like. On the circumferential metal pad 11b for sealing, a circumferential metal bump 11e is formed on the surface by plating or the like. Here, the metal pad 11 b is provided on the surface of the LSI substrate 11 along the contour thereof and formed in a circumferential shape. For example, if the LSI substrate 11 is a quadrangle, the metal pad 11 b extends along the periphery of the LSI substrate 11. To form a rectangular frame.

  Here, the LSI substrate 11 of the present invention may be of any semiconductor type, integration scale, or minimum processing size. That is, any integrated circuit may be used as long as it has a function that can be used in combination with the micromachine 12.

  In the illustrated case, the MEMS 12 is an electrostatic variable capacitor, and includes two electrodes 12c and 12d formed in the recessed portion 12b of the device layer 12a, and is manufactured as described later.

  The MEMS 12 is bonded to the cover substrate by anodic bonding to the lower surface of the cover substrate 13 to be described later, and the electrodes 12c and 12d are bonded to the corresponding metal pads 13e provided on the lower surface of the cover substrate 13. It is mechanically fixed and electrically connected.

  Here, the MEMS 12 is formed on a substrate made of silicon (Si) or the like and then transferred (also referred to as transfer) to the cover substrate 13. When a later-described MEMS substrate is used and the device layer 12a to be the MEMS 12 is formed on the Si substrate, the stopper portion 12e may be simultaneously formed on the Si substrate. The stopper portion 12e is similarly transferred by anodic bonding to the lower surface of the cover substrate 13 when the MEMS 12 is transferred to the cover substrate 13.

The cover substrate 13 is a substrate made of a material having substantially the same coefficient of thermal expansion as that of the Si substrate. The cover substrate 13 can be a ceramic substrate, a glass substrate, or the like. In particular, a low-temperature-fired ceramic substrate (Low Temperature Coated Ceramics, hereinafter referred to as LTCC substrate) having a low thermal expansion coefficient can be used. Specifically, the LTCC substrate 13 is made of a low thermal expansion coefficient substrate that can be anodically bonded, that is, a material having a thermal expansion coefficient substantially equal to that of the Si substrate. The LTCC substrate 13 may be composed of a substrate 13a and passive components such as a vertical wiring and a horizontal wiring built in the substrate 13a, and an inductor 13b connected thereto.
Thereby, the electrostatic gap is formed with high accuracy on the LTCC substrate 13 by anodic bonding of the MEMS 12.

Further, the LTCC substrate 13 includes a mounting metal pad 13c on the upper surface and a metal pad 13d for bonding to the LSI substrate 11 and a metal pad 13e for bonding to the MEMS 12 on the lower surface. And a circumferential metal pad 13f for stopping.
Here, the metal pad 13f is provided on the surface (lower surface) of the LTCC substrate 13 along the contour thereof, and is formed in a circumferential shape. For example, if the LTCC substrate 13 is a quadrangle, the metal pad 13f is formed on the LTCC substrate 13. A rectangular frame is formed along the periphery. The metal pad 13f is provided on the surface (lower surface) of the LTCC substrate 13 so as to face the metal pad 11b of the LSI substrate 11.
As a result, the metal pads 13d and 13f of the LTCC substrate 13 are bonded to the metal pads 11a and 11b of the LSI substrate 11 by metal bonding such as so-called TLP (Transient Liquid Phase) bonding, high-temperature solder bonding, or metal diffusion bonding, respectively. Attached and sealed. Specifically, the LSI substrate 11 and the LTCC substrate 13 are bonded so as to hermetically seal the space between the LSI substrate 11 and the LTCC substrate 13 with a constant distance between the LSI substrate 11 and the LTCC substrate 13. It connects via the part 14 (it is also called the sealing part 14). At this time, the gap between the LSI substrate 11 and the LTCC substrate 13 is sealed by performing the sealing operation in a vacuum, in an inert gas atmosphere, or in a dry gas, so that the MEMS 12 is in a vacuum and in an inert gas. Or in a dry gas. In this case, the joint portion 14 may be provided on the outer peripheral portion of the integrated circuit substrate 11 and the integrated circuit substrate 11 may be sealed by the joint portion 14.

  Specifically, on the circumferential metal bump 11e of the LSI substrate 11, there is a circumferential frame made of metal, that is, a rectangular frame-shaped sealing portion 14 along the outer peripheral edges of the LSI substrate 11 and the LTCC substrate 13. On the metal bump 11d of the LSI substrate 11, a bonding layer 15 for connecting the LTCC substrate 13 and the metal pad 13d is formed. The sealing portion 14 and the bonding layer 15 can be formed in the same process. The LTCC substrate 13 is placed on the LSI substrate 11, and the LTCC substrate 13 is pressed against the LSI substrate 11 in a state where the sealing portion 14 and the bonding layer 15 are in a liquid phase by heating. At that time, the stopper portion 12e provided on the lower surface of the LTCC substrate 13 comes into contact with the metal bump 11f on the metal pad 11c on the LSI substrate 11, so that the gap between the LSI substrate 11 and the LTCC substrate 13 is less than a predetermined value. It is regulated not to become.

The functional device 10 according to the first embodiment of the present invention is configured as described above, and can be manufactured by the manufacturing method shown in FIGS.
2 and 3 are schematic cross-sectional views sequentially showing a method for manufacturing the functional device 10 of FIG.
In FIG. 2A, first, the MEMS 12 is formed on the MEMS Si substrate 21. Specifically, the MEMS 12 is manufactured using an SOI substrate 22 with a germanium (Ge) layer and a Si substrate 23 with an oxide film, as shown in FIGS. In the illustrated case, the MEMS Si substrate 21 includes a MEMS 12, a Ge layer 22d, a SiO ₂ layer 23b, a Si substrate 23, and a SiO ₂ including a stopper portion 12e formed in a Si device layer, which will be described later, from the top to the bottom of the drawing. It has a laminated structure composed of the layer 23a.
Here, if an SOI substrate alone is used as the MEMS Si substrate 21, the LTCC substrate 13 may be etched when the insulating layer is removed after the transfer to the LTCC substrate 13, so the SOI substrate is not used.
The stacked structure of the MEMS Si substrate 21 is expressed as Si device layer / Ge / SiO ₂ / Si substrate / SiO ₂ with diagonal lines between the above layers.

  Next, as shown in FIG. 2B, an LTCC substrate 13 is prepared, a metal pad 13c for mounting is formed on the upper surface of the LTCC substrate 13, a metal pad 13e for MEMS bonding is formed on the lower surface, and an LSI substrate. 11 bonding metal pads 13d and sealing metal pads 13f are formed.

Subsequently, as shown in FIG. 2C, the MEMS Si substrate 21 having the MEMS 12 and the LTCC substrate 13 are overlapped and bonded by anodic bonding. As a result, the electrodes 12c and 12d of the MEMS 12 are in contact with and electrically connected to the metal pad 13e of the LTCC substrate 13. In this case, the MEMS 12 is directly bonded to the LTCC substrate 13 by anodic bonding without passing through the sealing portion 14, so that the gap between the MEMS 12 and the LTCC substrate 13, that is, the electrodes 12c and 12d and the electrode pad 13e, It is possible to precisely control the distance between the two, and an electrostatic device such as an electrostatic variable capacitor can be configured with high accuracy.
Here, it is difficult to precisely control the gap when the MEMS 12 and the LTCC substrate 13 are provided with a sealing portion 14 that is in a liquid phase at the time of bonding. Therefore, in the case of a device in which the distance between the electrodes between the MEMS 12 and the LTCC substrate 13 needs to be set with high accuracy, it is preferable to join the MEMS 12 and the LTCC substrate 13 by anodic bonding.

Thereafter, as shown in FIG. 2D, the Si substrate 23 is removed from the MEMS Si substrate 21. In this case, when the MEMS Si substrate 21 is made of Si device layer / Ge / SiO ₂ / Si substrate / SiO ₂ , the Ge layer 22d is selectively etched with an etching solution such as hydrogen peroxide (H ₂ O ₂ ). The Si substrate 23 can be removed by etching. As a result, the MEMS 12 fabricated on the MEMS Si substrate 21 is transferred to the LTCC substrate 13.

  Next, as shown in FIG. 3A, an LSI substrate 11 is prepared, and a metal pad 11a as an extraction electrode from the LSI substrate 11, a metal pad 11b for sealing, and a metal pad for gap adjustment are provided on the upper surface. 11c is formed.

Subsequently, as shown in FIG. 3B, the metal bumps 11d, 11e are formed on the metal pads 11a, 11b, 11c on the LSI substrate 11 by plating or vapor deposition or sputtering when a barrier layer is required. , 11f.
Thereafter, as shown in FIG. 3C, on the metal bumps 11d, 11e for bonding and sealing among the metal bumps 11d, 11e, 11f, the sealing portion 14 and the bonding layer 15 are formed by plating or screen printing. Form.

  Here, as the material of the metal bumps 11d, 11e, and 11f, a material that does not become a liquid phase in a subsequent mounting process is used in relation to the material of the sealing portion 14 and the joint portion 15. As a combination of the metal bump 11d and the like and the sealing portion 14 or the bonding layer 15, for example, the metal bump 11d is made of Ni, and the sealing portion 14 is made of an alloy of Au and In. This combination is represented as a metal bump 11d | sealing portion 14, for example, Ni | Au / In. As other combinations of the metal bumps 11d and the like and the sealing portion 14, Ni | Ag / In, Ni / Pt | Ni / Sn, Ni / Pt | Cu / Sn, Ni / Pt | Au / Sn, Ni / Pt | Ni / Sn or the like can be used. In any combination, the sealing portion 14 and the joining portion 15 are a combination of Au, Ag, Ni, Cu and In, Sn that are low melting point metals. The sealing part 14 and the joining part 15 are in a liquid phase at 400 ° C. or lower. However, once the liquid phase is formed, the melting point becomes high when an alloy is formed. It will be able to withstand solder reflow during mounting. This is called a TLP junction.

Finally, as shown in FIG. 3D, the LTCC substrate 13 and the LSI substrate 11 are bonded at a temperature of, for example, 400 ° C. or less by a bonding method that can withstand solder reflow such as TLP bonding or high-temperature solder bonding. At this time, the sealing portion 14 and the bonding portion 15 are in a liquid phase, and the LTCC substrate 13 approaches the LSI substrate 11, but the stopper portion 12e fixed to the LTCC substrate 13 side is provided on the LSI substrate 11 side. It contacts the metal bump 11f. Therefore, the LTCC substrate 13 does not approach the LSI substrate 11 any more, and the gap between the LSI substrate 11 and the LTCC substrate 13 is regulated, that is, held by the height of the stopper portion 12e.
Thereby, the MEMS 12 does not come into contact with the surface of the LSI substrate 11, and a gap of a predetermined value or more can be held with respect to the LSI substrate 11, and a gap for the MEMS 12 can be secured. Further, the gap between the LSI substrate 11 and the MEMS 12 can be used for capacitance detection or electrostatic driving.

  The above joining operation is preferably performed in a vacuum or in an inert gas atmosphere. As a result, the internal space sealed between the LSI substrate 11 and the LTCC substrate 13 is evacuated or filled with an inert gas. Therefore, the humidity of the internal space between the LSI substrate 11 and the LTCC substrate 13 does not cause at least a part of the MEMS 12 to be chemically changed or adsorbed. The operation is not hindered, and the MEMS 12 can operate smoothly.

  Thus, the functional device 10 is completed. Furthermore, it is possible to thin the LSI substrate 11 by polishing the lower surface side of the Si substrate 11 in FIG.

The production of the MEMS 12 on the Si substrate 21 for MEMS composed of the Si device layer / Ge / SiO ₂ / Si substrate / SiO _{2 in} FIG.
4 and 5 are schematic cross-sectional views sequentially showing an example of a method for manufacturing the MEMS 12 shown in FIG.
That is, as shown in FIG. 4A, an SOI substrate 22 is prepared. The SOI substrate 22 includes an Si device layer 22a, an SiO ₂ layer 22b, and an Si handle layer 22c in order from the upper side. A Ge layer to be a sacrificial layer 22d is formed on the surface of the Si device layer 22a of the SOI substrate 22 by sputtering, vapor deposition, chemical vapor deposition, or the like. Moreover, you may planarize the surface of Ge layer 22d as needed. As a material for the sacrificial layer 22d, a heat-resistant resin such as a polyimide resin can be used in addition to Ge.

Next, as shown in FIG. 4B, a separate Si substrate 23 is prepared, and both surfaces of the Si substrate 23 are thermally oxidized to form SiO ₂ layers 23a and 23b.

  Next, as shown in FIG. 4C, the SOI substrate 22 is inverted and placed on the Si substrate 23 and directly bonded thereto. If necessary, plasma activation of the bonding surface is performed before bonding. Subsequently, as shown in FIG. 4D, the Si handle layer 22c of the SOI substrate 22 is removed by grinding, dry etching, or the like. Thereby, the Si substrate 21 for MEMS is completed.

Next, the MEMS 12 is formed on the Si device layer 22a on the sacrificial layer 22d of the MEMS Si substrate 21 as follows.
First, as shown in FIG. 4E, the SiO ₂ layer 22b exposed on the upper surface is patterned to produce a mask.
Next, as shown in FIG. 5A, the Si device layer 22a is etched with TMAH (tetramethylammonium hydroxide) or the like to form the recess 12b of the MEMS 12.
Next, as shown in FIG. 5B, the SiO ₂ layer 22b serving as a mask is etched to half the thickness with hydrogen fluoride (HF), and then the Si device layer 22a is formed with hydrogen fluoride and nitric acid (HNO _3). ) And acetic acid (CH ₃ OOH).

After that, as shown in FIG. 5C, the lower surface is protected with a photoresist (not shown), the mask of the upper SiO ₂ layer 22b is removed, and two electrodes 12c and 12d are formed in the recessed portion 12b by lift-off. Form.
Next, as shown in FIG. 5D, a resist pattern 24 is formed in the region of the MEMS 12 and the region of the stopper portion 12e, and etched by RIE to form the MEMS 12 and the stopper portion 12e.
Finally, as shown in FIG. 5E, the resist pattern 24 is removed.
Thereby, the MEMS 12 and the stopper portion 12e can be formed on the MEMS Si substrate 21 shown in FIG.

Since the functional device 10 according to the present invention is configured as described above and manufactured as described above, the LSI substrate 11, the MEMS 12, and the LTCC substrate 13 can be independently optimized and manufactured.
At this time, when the LTCC substrate 13 is stacked and integrated on the LSI substrate 11, if the LTCC substrate 13 is made of a substrate made of a material having substantially the same thermal expansion coefficient as that of the Si substrate, for example, Peeling, cracking, warping and the like based on the difference in expansion coefficient can be avoided. Further, when ions such as sodium ions and lithium ions that are movable at the time of temperature increase are added to the LTCC substrate 13 having the thermal expansion coefficient matched to the LSI substrate 11, the temperature is increased and a voltage is applied to join the substrate to the Si substrate or the like. Anodic bonding is possible. Since the anodic bonding is excellent in sealing properties and can be bonded without using the bonding portion 15, it is a bonding method that is excellent in terms of accuracy and reliability. Therefore, the reliability of the functional device 10 can be improved.
Therefore, for example, a material such as PZT that requires high temperature processing can be used for the MEMS 12. Further, the LSI substrate 11, the MEMS 12 and the LTCC substrate 13 can be manufactured by entrusting them to different foundries, and these members can be assembled by the steps shown in FIGS.
Further, the LSI substrate 11, the MEMS 12, and the LTCC substrate 13 can be integrally manufactured at the wafer level, and the MEMS 12 and the passive component 13b built in the LTCC substrate 13 are arranged on the LSI of the LSI substrate 11. Therefore, the area efficiency is improved and the chip can be configured as a small chip size package.

Since the metal pads 13c serving as mounting pads are exposed on the LTCC substrate 13, after completion at the wafer level, it can be divided into individual functional devices 10 by dicing and mounted directly on a printed circuit board or the like. In this case, since the LSI substrate 11 and the LTCC substrate 13 are joined by TLP joining, high-temperature solder joining, or metal diffusion joining, it is possible to withstand solder reflow when the functional device 10 is mounted.
Further, since the LTCC substrate 13 uses a substrate made of a material having a low coefficient of thermal expansion, even if it is bonded to the LSI substrate 11, the coefficient of thermal expansion is almost the same as that of the Si substrate constituting the LSI substrate 11. The functional device 10 is not stressed or warped by a thermal change, and the LTCC substrate 13 can be prevented from peeling off from the LSI substrate 11.

(Second Embodiment)
FIG. 6 shows the configuration of a second embodiment of the functional device 30 according to the present invention.
In FIG. 6, the functional device 30 has substantially the same configuration as the functional device 10 illustrated in FIG. 1, but the MEMS 12 is configured as a piezoelectric vibrator, and the MEMS 12 is not anodic bonded to the LTCC substrate 13. The structure differs only in that it is changed to TLP bonding or metal diffusion bonding.

In this case, metal bumps 13g for bonding to the integrated circuit are formed on the metal pads 13d and 13f on the LTCC substrate 13 side at the junction between the MEMS 12 and the LTCC substrate 13, and the bonding layer 15 is further formed on the metal bump 13g. Is formed. A circumferential sealing metal bump 13i is formed on the circumferential sealing metal pad 13f on the LTCC substrate 13 side, and a sealing portion 14 is further formed on the metal bump 13i.
Here, the sealing portion 14 is configured in the same manner as the sealing portion 14 described above, and is bonded to the metal bump 13i by TLP bonding or metal diffusion bonding.

According to the functional device 30 configured as described above, the sealing device 14 acts in the same manner as the functional device 10 shown in FIG. There is no liquid phase when the LSI substrate 11 and the LTCC substrate 13 are joined or when the functional device 30 is mounted.
Since the sealing portion 14 is in a liquid phase, it is difficult to precisely control the interelectrode distance between the MEMS 12 and the LTCC substrate 13, so that the interelectrode distance is used as an electrostatic gap. For example, an electrostatic capacitor is not suitable.

(Third embodiment)
FIG. 7 shows the configuration of the functional device 40 according to the third embodiment of the present invention.
In FIG. 7, the functional device 40 has substantially the same configuration as the functional device 30 shown in FIG. 6, but differs only in that the MEMS 12 is bonded to the LSI substrate 11. In this case, the stopper portion 12e is also bonded to the LSI substrate 11 side. According to the functional device 40 having such a configuration, it operates in the same manner as the functional device 30 shown in FIG.

(Fourth embodiment)
FIG. 8 shows a configuration of a fourth embodiment of the functional device 50 according to the present invention.
In FIG. 8, the functional device 50 has substantially the same configuration as the functional device 40 shown in FIG. 7, but differs only in that a glass substrate 51 is provided instead of the LTCC substrate 13. The glass substrate 51 is made of a material having a thermal expansion coefficient similar to that of the Si substrate of the LSI substrate 11. As a material for such a glass substrate 51, Pyrex (registered trademark) glass can be used.

  The glass substrate 51 includes a through wiring 51 b for connecting the bonding metal pad 51 a from the LSI substrate 11 to the mounting metal pad 51 a on the upper surface of the glass substrate 51. The glass substrate 51 includes a recessed portion 51c in a region corresponding to the MEMS 12 on the lower surface thereof. Thereby, when bonding the glass substrate 51 to the LSI substrate 11, the MEMS 12 does not contact the lower surface of the glass substrate 51 even if the sealing portion 14 is thinned. Therefore, the MEMS 12 does not need to include the stopper portion 12e.

  In the configuration in which the LTCC substrate 13 in the first embodiment shown in FIG. 1 is simply changed to the glass substrate 51, a gap for the MEMS 12 is secured by the stopper portion 12e. Good.

9 and 10 show a method for manufacturing the functional device 50 including the glass substrate 51 described above.
In FIG. 9A, first, the MEMS Si substrate 21 described with reference to FIGS. 4 and 5 is used, and the MEMS 12 is fabricated on the MEMS Si substrate 21. Here, a piezoelectric vibrator is shown as an example of the MEMS 12.

Next, as shown in FIG. 9B, an LSI substrate 11 is prepared, and a metal pad 11a as an extraction electrode from the LSI and a metal pad 11b for sealing are formed on the upper surface.
Subsequently, as shown in FIG. 9C, metal bumps 11d and 11e are formed on the metal pads 11a and 11b on the LSI substrate 11 by plating or vapor deposition or sputtering when a barrier layer is required. To do.
Thereafter, as shown in FIG. 9C, a sealing portion 52 is formed on the metal bump 11d for bonding the MEMS 12 by plating, sputtering, or the like. The sealing part 52 is formed in a circumferential shape so as to be provided along the contour of the surface (lower surface) of the MEMS 12. For example, if the MEMS 12 is a quadrangle, the sealing part 52 is formed in a rectangular frame shape along the periphery of the MEMS 12. It is formed.
Here, the material of the metal bumps 11d and the sealing portion 52 is TLP bonding or metal diffusion bonding (Au-Au bonding, Al-Al bonding, etc.) that does not remelt when the glass substrate 51 and the LSI substrate 11 described later are bonded. ) Is selected.
In the case of TLP bonding, since the sealing portion 52 is in a liquid phase, it is difficult to tightly control the distance between the electrodes of the MEMS 12 and the LSI substrate 11. The MEMS 12 used as a gap is not suitable.

  Next, as shown in FIG. 9D, the MEMS Si substrate 21 having the MEMS 12 is inverted and placed on the LSI substrate 11 and bonded by TLP bonding or metal diffusion bonding. Thereby, the MEMS 12 is electrically connected to the LSI substrate 11.

Next, as shown in FIG. 9E, the Si substrate 23 is removed from the MEMS Si substrate 21. In this case, when the MEMS Si substrate 21 is composed of Si device layer / Ge / SiO ₂ / Si substrate / SiO ₂ , the Ge layer 22d is selectively etched with H ₂ O ₂ or the like, whereby the Si substrate 23 Can be removed. As a result, the MEMS 12 fabricated on the MEMS Si substrate 21 is transferred to the LSI substrate 11.

  Next, as shown in FIG. 10A, a glass substrate 51 with a through wiring is prepared, and a metal pad 51a for mounting is formed in the area of the through wiring 51b on the upper surface, and the through wiring 51b on the lower surface is formed. A metal pad 51d for bonding the LSI substrate 11 is formed in the region, and a metal pad 51e for sealing is formed near the periphery.

Further, as shown in FIG. 10A, a recess 51c having a depth of, for example, about several μm to several tens of μm is processed into a region corresponding to the MEMS 12 on the lower surface of the glass substrate 51.
The recess 51c may be processed after the subsequent sealing portion 52 is formed.

Next, as shown in FIG. 10B, sealing portions 54a and bumps 54b are formed on the metal pads 51d and 51e on the lower surface of the glass substrate 51 by plating or screen printing, respectively.
Here, the sealing portion 54 a is formed in a square frame shape along the outer peripheral edge of the glass substrate 51.
Finally, as shown in FIG. 10C, the glass substrate 51 and the LSI substrate 11 are bonded at a temperature of 400 ° C. or less, for example, by a bonding method that can withstand solder reflow such as TLP bonding or high-temperature solder bonding.

  The joining operation is preferably performed in a vacuum or in an inert gas atmosphere. As a result, the internal space sealed between the LSI substrate 11 and the glass substrate 51 is evacuated or filled with an inert gas. Therefore, the humidity of the internal space between the LSI substrate 11 and the glass substrate 51 does not cause at least a part of the MEMS 12 to be chemically changed or adsorbed. The operation is not hindered, and the MEMS 12 can be operated smoothly.

(Fifth embodiment)
FIG. 11 shows the configuration of a fifth embodiment of a functional device 60 according to the present invention.
In FIG. 11, the functional device 60 has substantially the same configuration as the functional device 50 shown in FIG. 8, but the glass substrate 51 does not include the through wiring 51 b and the LSI substrate 11 includes the through wiring 61. In addition, an extraction electrode for mounting from the LSI substrate 11 is constituted by a metal pad 62 formed on the lower surface of the LSI substrate 11.

  According to the functional device 60 having such a configuration, since it is not necessary to provide the through wiring 15b in the glass substrate 51 that is difficult to process, the production of the glass substrate 51 may not be entrusted to a specialized manufacturer. On the other hand, since the technology for stacking the memory integrated circuit or the like can be used for the through wiring of the LSI substrate 11, the cost of the functional device 60 can be reduced.

(Sixth embodiment)
FIG. 12 shows the configuration of a sixth embodiment of a functional device 70 according to the present invention.
In FIG. 12, the functional device 70 has a configuration in which the functional device 10 shown in FIG. 1 and the functional device 40 shown in FIG. 7 are combined, that is, MEMS 71 and 72 are bonded to both the LTCC substrate 13 side and the LSI substrate 11 side. It has a different configuration only in that it is. In FIG. 12, the positions of the MEMS 71 and 72 in the substrate plane direction do not overlap, but they may overlap. In this case, the chip area can be further reduced.

  The MEMS 71 has the same configuration as the MEMS 12 in the functional device 30 shown in FIG. 6 and is configured as, for example, an electrostatic variable capacitor or an electrostatic switch, and the MEMS 72 has the same configuration as the MEMS 12 in the functional device 40 shown in FIG. For example, it is configured as a piezoelectric vibrator.

  FIG. 13 shows a method for manufacturing the functional device 70. In FIG. 13A, the LTCC substrate 13 including the MEMS 71 is manufactured in the same manner as shown in FIGS.

Next, as shown in FIG. 13B, the metal bumps 13g and 13i, the sealing portion 14 and the bonding layer 15 are formed on the bonding metal pads 13d and 13f of the LTCC substrate 13, respectively. At this time, a photoresist 73 is patterned on the LTCC substrate 13 excluding the metal pads 13d and 13f to form a mold for bump formation by plating.
Thereafter, as shown in FIG. 13C, the photoresist 73 is removed.

Next, in FIG. 13D, the LSI substrate 11 including the MEMS 72 is manufactured in the same manner as shown in FIGS. 9A to 9E.
Finally, the LTCC substrate 13 in FIG. 13C and the LSI substrate 11 in FIG. 13D are joined by TLP joining or high-temperature solder joining.
Thereby, the functional device 70 is completed.

  According to the functional device 70 having such a configuration, the MEMS 71 and 72 can be provided on both the LSI substrate 11 side and the LTCC substrate 13 side. Therefore, two types of MEMS 71 and 72, that is, MEMS 71 as an electrostatic variable capacitor or electrostatic switch, MEMS 72 as a piezoelectric vibrator, and passive component 13b provided on the LTCC substrate 13 are combined with the LSI substrate 11 together. It can be integrated into one functional device 70 and packaged at the wafer level.

  As described above, according to the present invention, an extremely excellent functional device 10, 30, 40, 50, 60 that can integrate the LSI substrate 11, the MEMS 12, and the LTCC substrate 13 at the wafer level. , 70 are provided.

  In the above embodiment, the metal pads 13c and the like of the cover substrate 13 and the metal pads 11a of the LSI substrate 11 are joined via the metal bumps 11d and the like, but the metal bumps 11d are the metal pads of the cover substrate 13 and so on. 13c, and can be provided on one or both of the metal pads 11a of the LSI substrate 11.

  The present invention can be implemented in various forms without departing from the spirit of the present invention. For example, in the above-described embodiment, the inductor is built in the LTCC substrate 13 as the passive component 13b. However, the present invention is not limited to this, and other passive components 13b, for example, resistors and capacitors can be built in. .

It is a schematic sectional drawing which shows the structure of 1st Embodiment of the functional device by this invention. FIG. 2 is a schematic cross-sectional view sequentially illustrating a method for manufacturing the functional device of FIG. 1 according to the present invention. FIG. 2 is a schematic cross-sectional view sequentially illustrating a method for manufacturing the functional device of FIG. 1 according to the present invention. FIG. 3 is a schematic cross-sectional view sequentially showing an example of a manufacturing method of the MEMS shown in FIG. FIG. 3 is a schematic cross-sectional view sequentially showing an example of a manufacturing method of the MEMS shown in FIG. It is a schematic sectional drawing which shows the structure of 2nd Embodiment of the functional device by this invention. It is a schematic sectional drawing which shows the structure of 3rd Embodiment of the functional device by this invention. It is a schematic sectional drawing which shows the structure of 4th Embodiment of the functional device by this invention. It is a schematic sectional drawing which shows the manufacturing method by this invention of the functional device of FIG. 8 sequentially. It is a schematic sectional drawing which shows the manufacturing method by this invention of the functional device of FIG. 8 sequentially. It is a schematic sectional drawing which shows the structure of 5th Embodiment of the functional device by this invention. It is a schematic sectional drawing which shows the structure of 6th Embodiment of the functional device by this invention. It is a schematic sectional drawing which shows the manufacturing method of the functional device of FIG. 12 in order.

Explanation of symbols

10, 30, 40, 50, 60, 70: Functional device 11: Integrated circuit board 11a, 11c: Metal pad 11b: Metal pad for sealing 11d, 11f: Metal bump 11e: Metal bump for sealing 12: Micromachine (MEMS) )
12a: Device layer 12b: Recessed portion 12c, 12d: Electrode 12e: Stopper portion 13: Cover substrate (LTCC substrate)
13a: substrate 13b: passive component (inductor)
13c, 13d, 13e: Metal pad 13f: Metal pad for sealing 13g: Metal bump for bonding 13i: Metal bump for sealing 14: Sealing part 15: Bonding layer 21: Si substrate for MEMS 22: SOI substrate 22a: Si Device layer 22b: SiO ₂ layer 22c: Si handle layer 22d: Sacrificial layer (Ge layer)
23: Si substrate 23a, 23b: SiO ₂ layer 24: Resist pattern 51: Glass substrate 51a, 51d, 51e: Metal pad 51b: Through wire 51c: Recessed portion 52: Sealing portion 61: Through wire 62: Metal pad 71, 72: MEMS
73: Photoresist

Claims (10)

A first stage of fabricating a micromachine in a Si device layer formed on a sacrificial layer of a Si substrate;
A second step of forming a metal pad for sealing and bonding on the lower surface of the cover substrate made of a material having substantially the same coefficient of thermal expansion as the Si substrate;
Forming a metal pad for bonding and sealing on the upper surface of the integrated circuit substrate in which the integrated circuit is configured, and forming a metal bump on the metal pad;
A fourth step of forming a bonding layer and a sealing portion on the metal bump formed in the third step;
The micromachine manufactured in the first stage is bonded to the cover substrate on which the metal pad is formed in the second stage by anodic bonding, and the sacrificial layer is etched to remove the Si substrate. And the fifth stage
The cover substrate is placed on the integrated circuit substrate, the integrated circuit substrate and the cover substrate are joined using the sealing portion, and a region between the integrated circuit substrate and the cover substrate is sealed. The sixth stage,
A method for manufacturing a functional device, comprising: A first stage of fabricating a micromachine in a Si device layer formed on a sacrificial layer of a Si substrate;
Forming a sealing and bonding metal pad on the lower surface of the cover substrate made of a material having substantially the same thermal expansion coefficient as the Si substrate, and forming a bonding layer and a sealing portion on the metal pad; ,
Forming a metal pad for bonding and a metal pad for sealing on an upper surface of an integrated circuit substrate in which an integrated circuit is configured; and forming a metal bump on the metal pad;
Of the metal bumps formed in the third step, a fourth step of forming a bonding layer on the metal bumps to be bonded to the micromachine,
The micromachine manufactured in the first step is bonded to the integrated circuit substrate having the bonding layer formed in the fourth step by metal bonding, and the sacrificial layer is etched to remove the Si substrate. Five stages,
The cover substrate is placed on the integrated circuit substrate, the integrated circuit substrate and the cover substrate are joined using a sealing portion on the cover substrate, and an area between the integrated circuit substrate and the cover substrate A sixth stage of sealing,
A method for manufacturing a functional device, comprising: The third stage metal bumps formed on the metal pad is, the sixth to in step, characterized by comprising a material that does not become a liquid phase, method of manufacturing a functional device according to claim 1 or 2. The sacrificial layer is characterized in that it consists of Ge or resin, method for producing a functional device according to any one of claims 1 to 3. It said sixth stage, a vacuum, characterized in that it is carried out in either an inert gas atmosphere and dry gas, the production method of the functional device according to any one of claims 1 to 4. In the first stage, simultaneously with the fabrication of the micromachine, a stopper portion for forming a predetermined interval between the integrated circuit substrate and the cover substrate is formed,
In the third stage, metal bumps are formed on the metal pads corresponding to the stopper portions on the integrated circuit substrate,
In the fifth stage, the stopper part is joined to the lower surface of the cover substrate together with the micromachine by anodic bonding,
6. The method of manufacturing a functional device according to claim 1, wherein the stopper portion is brought into contact with a corresponding metal pad on the integrated circuit substrate in the sixth stage. In the second stage, using a ceramic substrate containing passive components inside as the cover substrate,
In the sixth step, characterized by connecting a passive component in the cover substrate with respect to the integrated circuit of the integrated circuit board, method of manufacturing a functional device according to any of claims 1 to 5, . In the second stage, using a glass substrate as the cover substrate,
The method of manufacturing a device in which the micromachine and the integrated circuit are integrated, according to any one of claims 2 to 5 , wherein the micromachine is transferred to the glass substrate in the fifth stage. In the second stage, as the cover substrate, using a glass substrate provided with through wiring penetrating vertically,
9. The functional device according to claim 8 , wherein, in the sixth stage, the integrated circuit in the integrated circuit substrate and the extraction electrode of the micromachine are exposed on the upper surface of the cover substrate through the through wiring. Production method. In the third stage, as the integrated circuit board, using an integrated circuit board provided with a through wiring penetrating vertically,
9. The functional device according to claim 8 , wherein, in the sixth stage, an integrated circuit and an extraction electrode of the micromachine in the integrated circuit substrate are exposed to a lower surface of the integrated circuit substrate through the through wiring. Manufacturing method.

Images