JP5577619B2 - Logic circuit design device - Google Patents

Description

  The present invention relates to a logic circuit design apparatus.

  Conventionally, system designers have used RTL (Register Transfer Level) that can be synthesized by a system level design device and a clock-based model that cannot perform logic synthesis but exhibits the same functions as RTL. We are designing the level.

  Specifically, the system level design apparatus uses the co-design apparatus to divide the hardware part and the software part of the system, and automatically generates a database including architecture information, mapping information, address information, and the like. The system level design apparatus automatically generates a description for clock-based simulation from the information in the database using the top level description generation apparatus.

  In the system level design apparatus described above, a hardware generation apparatus that is an apparatus that performs hardware behavioral synthesis and generates an RTL and a clock-based model, and a software that is an apparatus that generates a CPU (Central Processing Unit) model A device is also used.

  In addition to the system level design apparatus described above, for example, an automatic generation apparatus that creates an input vector for testing when manufacturing an LSI equipped with a CPU is also disclosed. Specifically, the automatic generation apparatus extracts memory mapped register information for accessing the hardware circuit from software, and automatically converts it into a macro definition that can be used in C language. Thereafter, the automatic generation device automatically generates program source code according to a rule for sequentially accessing all memory mapped registers.

JP 2004-54755 A JP 2004-257822 A

  However, in the conventional technology, when designing the entire system including hardware and software, the number of man-hours is increased. As a result, there is a problem that many man-hours are required for designing the entire system. there were.

  Specifically, in the conventional technique, a database including a description for clock-based simulation, architecture information, mapping information, address information, and the like can be automatically generated. However, in order to design the entire system, it is necessary to further design a circuit configuration (hardware part) and a device driver (software part), and these must be designed manually. Particularly in the case of a large-scale system, a large amount of manual labor is required.

  In addition, in the conventional technology, program source code can be automatically generated according to a rule for sequentially accessing all memory-mapped registers, but all memory-mapped registers are accessed sequentially by an actual device driver or application. There is almost no. Therefore, such a method cannot be diverted to software development, and software development needs to be performed manually. Therefore, the entire system requires a lot of man-hours.

  The disclosed technique has been made in view of the above, and an object thereof is to provide a logic circuit design apparatus capable of reducing the man-hours required for designing the entire system.

  In one aspect, the logic circuit design apparatus disclosed in the present application analyzes register information of an input logic circuit block and acquires configuration information of the logic circuit, and a logic acquired by the register analyzing means. Based on the circuit configuration information, each of the register unit of the logical circuit, the core function unit model of the logic circuit, and the top module model including the register unit and the core function unit, hardware Based on the configuration information of the logic circuit acquired by the hardware description generating means for generating the source code and the register analyzing means, the software source code is generated for the template of the device driver function for initializing the logical circuit. Software description generation means.

  According to one aspect of the logic circuit design apparatus disclosed in the present application, it is possible to reduce the man-hours required for designing the entire system.

FIG. 1 is a block diagram illustrating the configuration of the logic circuit design apparatus according to the first embodiment. FIG. 2 is a diagram illustrating an example of a memory map setting screen. FIG. 3 is a diagram illustrating an example of information stored in the system memory map DB. FIG. 4 is a diagram showing an example of a screen for setting the access priority of the bus master. FIG. 5 is a diagram illustrating an example of access priorities stored in the system memory map. FIG. 6 is a diagram illustrating an example of information stored in the bus type DB. FIG. 7 is a diagram illustrating an example of a GUI that receives an input of a register list. FIG. 8 is a diagram illustrating an example of a register list input by the user. FIG. 9 is a diagram illustrating an example of register types. FIG. 10 is a diagram illustrating an example of information stored in the logic circuit register map list DB. FIG. 11 is a diagram illustrating an example of a GUI that receives input of register details. FIG. 12 is a diagram illustrating an example of information stored in the logic circuit register map detail DB. FIG. 13 is a diagram illustrating an example of information stored in the logic circuit interrupt information DB. FIG. 14 is a flowchart showing a flow of processing for generating a hardware source code of RTL description of a bus model. FIG. 15 is a diagram showing an example of a bus model template file. FIG. 16 is a diagram showing another example (Loop processing) of a bus model template file. FIG. 17 is a diagram illustrating an example of the hardware source code of the RTL description of the bus model that is finally created. FIG. 18 is a diagram showing a register map of the simple interrupt controller. FIG. 19A is a diagram illustrating an example of information stored in the logic circuit register map detail DB. FIG. 19B is a diagram of an example of information stored in the logic circuit interrupt DB. FIG. 20 is a diagram illustrating a definition file in which portions necessary for generating an interrupt processing function are extracted. FIG. 21 is a diagram illustrating an example in which an interrupt processing function is generated in a multi-stage configuration. FIG. 22 is a diagram illustrating an example of generating an entry function for interrupt processing. FIG. 23 is a diagram illustrating an example of an interrupt processing function in units of logic circuit blocks. FIG. 24 is a diagram showing the actual state of the generated interrupt processing function. FIG. 25 is a flowchart showing a flow of initialization function generation processing by the software description generation unit 22. FIG. 26 is a diagram illustrating an image of generating the initialization function. FIG. 27 is a diagram showing a definition file in which portions necessary for generating an initialization function are extracted. FIG. 28 is a diagram showing an example of the generated initialization function. FIG. 29 is a diagram illustrating a file group related to the pseudo CPU and the interrupt controller. FIG. 30 shows a file group related to the bus model and user logic. FIG. 31 is a diagram showing a group of files related to logic circuit blocks. FIG. 32 is a diagram showing a file group related to the test bench. FIG. 33 is a diagram illustrating a logical verification top and a device driver related file group. FIG. 34 is a diagram showing a logic verification test program and a logic verification related file group. FIG. 35 is a flowchart illustrating an overall processing flow performed by the logic circuit design device according to the first embodiment. FIG. 36 is a diagram illustrating a configuration of a system finally generated. FIG. 37 is a diagram illustrating a configuration example of a verification environment for accuracy verification. FIG. 38 is a diagram illustrating a configuration example of a verification environment for function verification. FIG. 39 is a diagram illustrating a configuration example of a single-use verification environment.

  Hereinafter, embodiments of a logic circuit design apparatus disclosed in the present application will be described in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

  The logic circuit design apparatus disclosed in the present application analyzes register information (register map) of an input logic circuit block and acquires configuration information of the logic circuit. Then, the logic circuit design device generates hardware source code for each of the register unit of the logic circuit and the template of the core function unit of the logic circuit based on the acquired configuration information of the logic circuit. The logic circuit design device also generates hardware source code for the top module template that includes the register unit and the core function unit. Furthermore, the logic circuit design device generates a software source code for the template of the device driver function for initializing the logic circuit based on the acquired configuration information of the logic circuit.

  That is, the logic circuit design apparatus disclosed in the present application, when receiving the register information of the logic circuit block, is used for hardware design such as a core function unit of the logic circuit and software design that can be diverted to device driver development for the logic circuit block. Source code can be created. Therefore, the designer can acquire the source code for hardware design and software design by inputting the register information of the logic circuit block to be designed into the logic circuit design apparatus disclosed in the present application. Logic circuit design can be performed using each source code.

  A logic circuit block is a collection of logic circuits (combination circuits and sequential circuits) for realizing a specific function. For example, a DMA controller, a timer, a UART, various encoders / decoders, etc. , Connected to the processor bus. In addition, the register part of the logic circuit block refers to the value of the sequential circuit that holds the setting value for appropriately realizing the function of the logic circuit block and the value of the sequential circuit that holds the internal information of the logic circuit block via the bus. It holds the configuration accessible to the processor. For example, the register portion of the logic circuit block is a portion described as a “register map” or the like in the device data sheet and accessible from software such as a device driver.

  In addition, the core function unit of the logic circuit block is a part in which an essential circuit that performs a specific function of the “logic circuit block” is mounted. For example, the behavior and output result change depending on the value set in the “register part”, and part of the output result and part of the internal state of the core function part are held in the “register part” and can be accessed from software. There is also a thing. The top module of the logic circuit block is a portion that is the highest layer of the “logic circuit block”. For example, a module that connects each of the “register unit”, “core function unit”, and “bus interface unit” (including connection to an internal RAM in some cases) and provides an external interface as a “logic circuit block” It is.

  As described above, the logic circuit design apparatus disclosed in the present application can create source codes of both hardware and software from the register information of the logic circuit block even when designing the entire system including hardware and software. . As a result, it is possible to reduce the man-hours for manual work by the designer as compared with the prior art, and therefore, the man-hours required for designing the entire system can be reduced.

  Next, the configuration of the logic circuit design apparatus according to the first embodiment will be described with reference to FIG. FIG. 1 is a block diagram illustrating the configuration of the logic circuit design apparatus according to the first embodiment.

  As shown in FIG. 1, the logic circuit design device 1 includes, as databases, a system memory map DB10, a bus type DB11, a logic circuit register map list DB12, a logic circuit register map details DB13, a logic circuit interrupt information DB14, and a verification type DB15. Have In addition, the logic circuit design apparatus 1 includes a hardware description generation unit (system related) 20, a hardware description generation unit (logic circuit related) 21, a software description generation unit 22, And a verification environment generation unit 25.

[Description of each database]
The system memory map DB 10 receives and stores a memory map of a system in which a space is divided for each block of a bus slave (logic circuit block) from a user (designer). Specifically, the system memory map DB 10 stores a start address and an end address for each bus slave so that the bus slave on the system can be accessed. In addition to the CPU, the system memory map DB 10 stores information on which bus slave the bus master can access when there is a logical circuit block that can be a bus master such as a DMA (direct memory access) controller. To do.

  For example, when receiving a logic circuit design request from a user, the logic circuit design apparatus 1 outputs a screen on which a basic information of a memory map can be set on a GUI as shown in FIG. 2 to a display unit such as a display. Then, the logic circuit design device 1 receives information such as a bus slave (Slave) and a bus master (Master) from the user on the GUI shown in FIG. As a result, the system memory map DB 10 stores “Slave_0, 0000_0000, 0001_fffe”, “Slave_1, 0002_0000, 0003_fffe”, etc. as “Slave_name, start_addr, end_addr” as shown in FIG.

  “Slave_name” stored here is information for identifying the bus slave, “start_addr” is the start address of the bus slave, “end_addr” is the end address of the bus slave, and any information is shown in FIG. 2 is information specified by the user using the GUI. 2 is a diagram illustrating an example of a memory map setting screen, and FIG. 3 is a diagram illustrating an example of information stored in the system memory map DB.

  The system memory map DB 10 also stores the priority of the bus master designated in FIG. Specifically, when the basic information of the memory map is registered in the system memory map DB 10 according to FIG. 2, the logic circuit designing device 1 displays a screen for setting the access priority of the bus master as shown in FIG. Display and accept the access priority setting from the user. As a result, as shown in FIG. 5, the system memory map DB 10 displays “Slave_0, Master_0, 1”, “Slave_0, Master_1, 0”, “Slave_0, Master_2, 2” as “Slave_name, master_name, priority”. Remember.

  “Slave_name” stored here is information for identifying a bus slave, “master_name” is information for identifying a bus master, “priority” is information indicating a priority, and any information This is information specified by the user through the GUI shown in FIG. In “priority” in FIG. 4, “0” has the highest priority, and “2” has the lowest priority. 4 is a diagram showing an example of a screen for setting the access priority of the bus master, and FIG. 5 is a diagram showing an example of the access priority stored in the system memory map.

  In this application, the bus type DB 11 generates a bus model and a bus interface of a logic circuit block, and stores the bus type used at that time. Specifically, the logic circuit design device 1 can allow the user to input the bus type using a GUI in the same manner as in FIG. 2 or FIG. 4. For example, the logic circuit design device 1 can provide a bus A simple drop-down list in which the type is presented can be selected by the user. As a result, as shown in FIG. 6, the bus type DB 11 stores “AMBA AHB”, “AMBA APB”, and the like as “bus_name” for specifying the bus type. FIG. 6 is a diagram illustrating an example of information stored in the bus type DB.

  The logic circuit register map list DB 12 stores register list information used in the logic circuit block. Specifically, the logic circuit design device 1 outputs a GUI as shown in FIG. 7 to the display unit, for example. Then, the logic circuit design device 1 accepts “address, name, read / write, function, initial value, mapping destination (type)”, etc. on the GUI shown in FIG. Information can be created. As a result, as shown in FIG. 9, the logic circuit register map list DB 12 has “Slave_name, address, reg_name, attribute, function, reset_value, init_value” as “Slave_0, 0x0010_0000, TEST, rw0, access test, 0000_0000, −”. And remember.

  “Slave_name” stored here is information for identifying the bus slave, “address” indicates the start address of the register, and “reg_name” is the name of the register designated by the user. “Attribute” is a register type specified by the user, and stores, for example, one specified from among the register types shown in FIG. “Function” indicates a register function, “reset_value” indicates an initialization value by hardware, and “init_value” indicates an initial value set by the device driver. Any of the above-described information is information input by the user using the GUI as shown in FIG.

  FIG. 7 is a diagram illustrating an example of a GUI that receives an input of a register list, and FIG. 8 is a diagram illustrating an example of a register list input by a user. FIG. 9 is a diagram illustrating an example of register types, and FIG. 10 is a diagram illustrating an example of information stored in the logic circuit register map list DB.

  The logic circuit register map detail DB 13 stores detailed information of registers used in the logic circuit block. Specifically, the logic circuit register map detail DB 13 stores register information in units of bits, and stores, for example, bit positions, widths, names, attributes, and the like. For example, when the register is clicked on the register list GUI shown in FIG. 8, the logic circuit design device 1 outputs a GUI as shown in FIG. 11 to the display unit. Then, the logic circuit design device 1 accepts “bit position, width, name, initial value, read / write, function, operation” and the like on the GUI shown in FIG. As a result, as shown in FIG. 12, the logic circuit register map detail DB 13 sets “Slave_0, 0x0010_0010, 0, 1, BUFFEMPTY as“ Slave_name, address, lsb, width, name, attribute, function, interrupt, reset_value, init_value ”. , Rw0, buffer empty, 0, 0, − ”and the like.

  “Slave_name” stored here is information for identifying the bus slave, “address” indicates the start address of the register, “lsb” indicates the least significant bit, and “width” Indicates the bit width. “Name” is the name of the register, “attribute” is the register type specified by the user, and “function” indicates the function of the register. In addition, “interrupt” indicates the presence or absence of an interrupt (for example, if it is 0), “reset_value” indicates an initialization value by hardware, and “init_value” indicates an initial value set by the device driver. The value is shown. Any of the above-described information is information input by the user using a GUI as shown in FIG.

  FIG. 11 shows a detailed setting example of the read / write operation mode setting register whose “address” is “7E10_0044”, “name” is “MODEB0”, and “initial value” is “0000_0000”. FIG. 11 is a diagram illustrating an example of a GUI that receives input of register details, and FIG. 12 is a diagram illustrating an example of information stored in the logic circuit register map detail DB.

  The logic circuit interrupt information DB 14 stores interrupt information used in the logic circuit block. Specifically, the logic circuit design device 1 extracts information in which a numerical value other than 0 is set in “interrupt” from the detailed register information shown in FIG. 12, and sets “reg_name” corresponding to the “address”. Extracted from FIG. 9 and output to the logic circuit interrupt information DB 14. As a result, as shown in FIG. 13, the logic circuit interrupt information DB 14 stores “Slave_0, 0x0010_0010, ISR, 0” and the like as “slave_name, address, regname, type”. “Type = 0” indicates an interrupt factor (interrupt status), “type = 1” indicates an interrupt enable (interrupt mask), and “type = 2” indicates an interrupt clear. Yes. FIG. 13 is a diagram illustrating an example of information stored in the logic circuit interrupt information DB.

  The verification type DB 15 stores a description format of hardware source code or software source code. Specifically, the verification type DB 15 stores types such as a TL description that can be operated at high speed for function verification and an RTL description that can be operated on a cycle basis and can be logically synthesized for performance verification. The RTL description is a source file described at a register transfer level, and the TL description is a source file described at a transaction level that describes communication between modules. is there.

[Hardware description generator (system related) 20]
The hardware description generation unit (system-related) 20 RTL describes the hardware source code 20a of the system-related bus model, the hardware source code 20b of the logic circuit bus I / F unit, and the hardware source code 20c of the simple interrupt controller. Or TL description. The bus model is an on-chip bus used inside an LSI (Large Scale Integration). The bus I / F unit (bus interface unit) logically connects the bus model of the logic circuit and the register unit. For example, the bus I / F unit (bus interface unit) absorbs a protocol specified by the bus model and registers Provides a unified interface (protocol) for the department.

  Here, referring to FIG. 14, the hardware description generator (system-related) 20 uses the template file (see FIG. 16) to create the bus model hardware source code 20a (see FIG. 17). Will be described. FIG. 14 is a flowchart showing a flow of processing for generating a hardware source code of RTL description of a bus model.

  As shown in FIG. 14, the hardware description generation unit (system-related) 20 reads the bus type specified by the user from the bus type DB 11 (step S101), and then stores the memory map stored by the user in the system memory map DB 10 (Step S102). Further, the hardware description generation unit (system related) 20 reads a template file for RTL description corresponding to the read bus type from a storage unit such as a memory (step S103).

  Then, the hardware description generation unit (system-related) 20 executes the processing from step S105 to step S108 until the last line (EOF) of the read template file is reached (step S104).

  Specifically, when the hardware description generation unit (system-related) 20 detects a keyword from the read template file (Yes at Step S105), it extracts information corresponding to the detected keyword from the system memory map DB 10 (Step S106). ). Then, the hardware description generation unit (system-related) 20 performs loop processing such as subtracting 1 from the number of bus slaves stored in the system memory map DB 10 (step S107). After that, the hardware description generation unit (system related) 20 creates the hardware source code 20a of the bus model by outputting one line of the extracted information (step S108).

  Next, the RTL description creation process of the hardware source code 20a of the bus model described above will be specifically described. The hardware description generation unit (system related) 20 stores a model file of a bus model corresponding to the bus type in a memory or the like. When the hardware description generation unit (system-related) 20 starts creating the source code, it acquires the bus type stored in the bus type DB 11 and stores the template file (see FIG. 15) corresponding to the acquired bus type. Read from etc. Thereafter, the hardware description generation unit (system-related) 20 uses the value obtained by subtracting 1 from the number of bus slaves (FIGS. 3 and 5) stored in the system memory map DB 10 to indicate “__SlaveNum__” in FIG. Rewrite. By implementing the above-described method, the hardware description generation unit (system-related) 20 can create the hardware source code 20a of the bus model.

  As the template file described above, not only the file shown in FIG. 15 but also a file as shown in FIG. 16, for example, can be used. The hardware description generation unit (system-related) 20 uses “__Start__SlaveNum__” and “__End_SlaveNum__” shown in FIG. 16 as a pair, and repeats the description surrounded by these two keywords by the number of “__SlaveNum__”. This is equivalent to a so-called “for-loop statement”. “__SlaveId__” corresponds to a so-called loop variable used in the above iterative process. The hardware description generation unit (system related) 20 repeats a value obtained by subtracting 1 from the bus slave (FIGS. 3 and 5) stored in the system memory map DB 10, and stores information corresponding to the keyword (such as __SlaveId__) in the system. Extracted from the memory map DB 10. As a result, the hardware description generation unit (system-related) 20 can create an RTL description (bus model hardware source code 20a) as shown in FIG. Further, for example, the hardware description generation unit (system related) 20 creates a hardware source code 20a having file names and directory names such as input_stage.v and output_stage.v.

  As described above, the hardware description generation unit (system-related) 20 can create the RTL description hardware source code 20a of the bus model by the method described with reference to FIGS. Also, a TL description hardware source code 20a of the bus model can be created by preparing a template file of TL description and executing the same processing as in FIG. Furthermore, although the bus model is shown as an example in the above, the simple interrupt controller 20c and the bus interface unit 20b of the logic circuit block can be similarly created. Specifically, when generating RTL descriptions and TL descriptions of other parts, they can be generated by preparing a template file in which rules necessary for generating each file are prepared in advance.

  The hardware description generation unit (system related) 20 can also generate a simple interrupt controller 20c. When a simple interrupt controller receives an interrupt notification from a logic circuit block, it calls an interrupt processing function generated for the logic circuit block, and performs processing for passing the subsequent processing to software. In general, an interrupt controller is often provided as a logic circuit block attached to a processor, or a user often makes it in accordance with a system.

  In the present application, the simple interrupt controller 20c can be automatically created in order to realize software / hardware cooperative verification at an early stage. When an interrupt is set in the register map in each logic circuit block, the hardware description generation unit (system-related) 20 estimates the terminal name of the interrupt based on the information and generates the top module of the simple interrupt controller 20c. To do. Specifically, the hardware description generation unit (system-related) 20 performs the logic shown in FIGS. 12 and 13 when a plurality of logical circuit blocks (Slave_0, Slave_1, and Slave_2) are defined on the memory map. Extracts circuit block interrupt information. Then, the hardware description generation unit (system related) 20 generates a data structure as shown in FIG. 18 using the extracted information as a register map of the simple interrupt controller 20c, and stores it in the database. Here, since the simple interrupt controller 20c does not notify itself of an interrupt, the “interrupt” field may be left blank. FIG. 18 is a diagram showing a register map of the simple interrupt controller.

[Hardware description generator (logic circuit related) 21]
Returning to FIG. 1, the hardware description generation unit (logic circuit related) 21 executes automatic generation of logic circuit related hardware source code. Specifically, the hardware description generation unit (logic circuit related) 21 creates the hardware source code 21a of the logic circuit register unit and the hardware source code template 21b of the logic circuit core functional block by RTL description or TL description. . In addition, the hardware description generation unit (logic circuit related) 21 creates a hardware source code template 21c of the logic circuit top module with an RTL description or a TL description.

  Note that a specific processing procedure can be created in the same flow as the hardware description generation unit (system-related) 20 described above, and detailed description thereof will be omitted. Briefly, the hardware description generation unit (logic circuit related) 21 stores the logic circuit register map list DB 12 (FIG. 9), the logic circuit register map details DB 13 (FIG. 12), and the logic circuit interrupt information DB 14 (FIG. 13). Read stored information. In addition, the hardware description generation unit (logic circuit related) 21 reads a template file of each of the hardware source codes 21a to 21c to be created from a memory or the like, and uses the template file and information of each DB, as shown in FIG. A similar flow is performed. As a result, the hardware description generation unit (logic circuit related) 21 can create the hardware source code 21a to 21c by RTL description or TL description.

[Software description generator 22]
The software description generating unit 22 executes automatic generation of a logic circuit interrupt processing function template 22a and an initialization function template 22b for each logic circuit block. Originally, an interrupt processing function (generally called an interrupt handler or the like) strongly depends on an OS (operating system) and a CPU (central processing unit), so it is difficult to make a general purpose one. In addition, since interrupt processing is a property that requires processing to be stopped until processing that is currently being executed is interrupted, interrupt processing functions are often implemented with priority given to processing speed.

  Therefore, the interrupt processing function template 22a and the initialization function template 22b generated by the software description generation unit 22 are mainly used for software / hardware cooperative verification and logic circuit block logic verification. That is, since the emphasis is on ease of verification and maintainability rather than processing speed, the function has a multi-stage configuration. In order to divert the generated interrupt processing function to the development of the divide driver (interrupt handler), it is only necessary to make changes such as consolidating the multi-stage parts into one function in order to improve the processing speed. .

(Generation of the interrupt processing function template 22a)
Specifically, the software description generation unit 22 generates various definition information shown in FIG. 21 in C language based on the information shown in FIG. 9 and FIG. For example, the case where the interrupt-related information is given by the values shown in FIGS. 19A and 19B will be described. In this case, the software description generation unit 22 acquires information from each of the system memory map DB10, the logic circuit register map list DB12, the logic circuit register map details DB13, and the logic circuit interrupt information DB14. And the software description production | generation part 22 produces | generates the source code (refer FIG. 20) which described the various definition information used with a software source code based on the information acquired from each DB. 19A is a diagram illustrating an example of information stored in the logic circuit register map detail DB, and FIG. 19B is a diagram illustrating an example of information stored in the logic circuit interrupt DB. FIG. 20 is a diagram illustrating a definition file in which portions necessary for generating an interrupt processing function are extracted.

  FIG. 21 shows an example in which an interrupt processing function is generated in a multistage configuration. In this case, first, “irq_hdlr ()” that is an entry function for interrupt processing is called from the simple interrupt controller. “Irq_hdlr ()” reads the register of the simple interrupt controller as shown in FIG. 22, and determines from which logic circuit block the interrupt is generated according to FIG. Then, the interrupt processing function of the logic circuit block is called. FIG. 23 shows an image of the interrupt processing function of each logic circuit block called from the entry function “irq_hdlr ()” of FIG. This function determines which interrupt factor is occurring in the logic circuit block and calls an interrupt processing function corresponding to the corresponding interrupt factor.

  Next, FIG. 24 shows an image of the actual state of the interrupt processing function called from the interrupt processing function of each logic circuit block of FIG. This function is a function that performs processing according to the interrupt factor.

  As described above, the software description generation unit 22 can generate a function group having the structure shown in FIG. 21 from a memory map, a register map, and interrupt information. In the actual state of the interrupt processing function of FIG. 24, the function text needs to be implemented in accordance with the operation specification of the interrupt, but this operation specification is known only to the designer of the logic circuit block. For this reason, an interrupt processing content body can be additionally implemented after the file is generated. The definition names in FIG. 20 and the bold portions in FIGS. 21 to 24 are extracted from the memory map, the register map, and the like. Therefore, the software description generation unit 22 prepares a part other than bold as a template file in advance and sets necessary keywords, and the files shown in FIGS. 20 to 21 to 24 based on the extracted data. Will be generated.

  FIG. 21 is a diagram illustrating an example in which an interrupt processing function is generated in a multistage configuration, and FIG. 22 is a diagram illustrating a generation example of an entry function for interrupt processing. FIG. 23 is a diagram illustrating an example of an interrupt processing function in units of logic circuit blocks, and FIG. 24 is a diagram illustrating an actual state of a generated interrupt processing function.

(Generation of initialization function template 22b)
Next, the generation of the initialization function template 22b will be described. Here, first, the flow of initialization function generation processing by the software description generation unit 22 will be described with reference to FIG. FIG. 25 is a flowchart showing a flow of initialization function generation processing by the software description generation unit 22.

  As shown in FIG. 25, the software description generation unit 22 reads one line of information stored in the logic circuit register map list DB 12 (step S201), and determines whether or not the read line is the last line (EOF) ( Step S202). Then, when a value is set in “init_value” of the read one line (initialization setting information is valid) (Yes in step S203), the software description generation unit 22 generates the initialization process described above. Output to a file (steps S204 and S205). If the initialization setting information is not valid (No at Step S203), the software description generation unit 22 reads the next line and executes the processes after Step S202. If the read line is the last line (Yes at Step S202), the software description generating unit 22 ends the process.

  Next, the process flow shown in FIG. 25 will be described in detail. The software description generation unit 22 acquires information from each of the system memory map DB 10, the logic circuit register map list DB 12, and the logic circuit register map details DB 13. Then, the software description generation unit 22 generates a template 22b of the initialization function based on the information acquired from each DB. For example, like the register IER of the address “0x0011_0014” in FIG. 26, a value set in the “init_value” column is a processing target, and the value set in the “init_value” column is set in the initialization function. This value is set in the register of the logic circuit block.

  And the software description production | generation part 22 produces | generates a file (FIG. 27) required for initialization function production | generation similarly to FIG. And the software description production | generation part 22 produces | generates a source code like FIG. 28 based on the information of FIG. As in the generation of the interrupt processing function, the bold portion in FIG. 28 is extracted from a memory map, a register map, or the like. Therefore, the software description generation unit 22 prepares parts other than bold as template files in advance and sets necessary keywords, and generates the file shown in FIG. 28 based on the extracted data. In addition, for example, the software description generation unit 22 creates a template 22b of an initialization function with file names and directory names such as init _ *. H and init _ *. C (* is the name of a logic circuit block or the like). To do.

  26 is a diagram illustrating an image of generating an initialization function, FIG. 27 is a diagram illustrating a definition file excerpted from a portion necessary for generating an initialization function, and FIG. It is the figure which showed the example of the optimization function.

[Verification environment generation unit 25]
Next, the verification environment generation unit 25 will be described. The verification environment generation unit 25 analyzes the information of the source code generated by the generation units 20 to 22 and constructs a verification environment (functional verification, performance verification). In addition, the verification environment generation unit 25 generates an environment for function verification and an environment for performance verification as necessary according to the verification purpose.

  Specifically, the verification environment generation unit 25 defines file name and directory name naming rules, directory hierarchy configuration rules, and the like in advance, and is generated by the generation units 20 to 22 according to the defined information. Create verification environment and verification environment file configuration from source code. For example, the verification environment generation unit 25 uses a rule such as “logic circuit block name_bt.v” for the bus interface unit and “logic circuit block name_rt.v” for the register unit. Define gender. Also, the regularity is defined as “logic circuit block name_core.v” in the case of the core function unit and “logic circuit block name.v” in the case of the top module. Also, for example, “init_logic circuit block name. [Ch]” for the initialization function template, “irq_logic circuit block name. [Ch]” for the interrupt processing function template, and “ It is defined as “reg_rw_logical circuit block name. [ch]” or the like.

  Examples of verification files created by the verification environment generation unit 25 in accordance with the regularity described above are shown in FIGS. FIG. 29 is a diagram illustrating a file group related to a pseudo CPU (Central Processing Unit) and an interrupt controller, FIG. 30 is a diagram illustrating a file group related to a bus model and a user logic, and FIG. It is a figure which shows the related file group. FIG. 32 shows a file group related to the test bench. FIG. 33 is a diagram showing a logical verification top and device driver related file group, and FIG. 34 is a logical verification test program and logical verification related file group.

[Flow of processing by logic circuit design equipment]
Next, the overall processing flow of the logic circuit design apparatus according to the first embodiment will be described with reference to FIG. FIG. 35 is a flowchart illustrating an overall processing flow performed by the logic circuit design device according to the first embodiment.

  As shown in FIG. 35, when the logic circuit design device 1 reads a register map or a memory map from each database (Yes at step S301), the logic circuit design device 1 analyzes the system configuration according to the read information (step S302). Analysis is performed (step S303). Information on the bus type used at this time is also acquired.

  Subsequently, the logic circuit design device 1 corresponds to the acquired bus type, and reads a source code template of hardware or software to be created (step S304). Then, the logic circuit design device 1 creates various source codes or source code templates based on the keywords specified in the read template and the information stored in the read register map or memory map (step S305). Further, the logic circuit design device 1 creates a verification environment based on the created source code or source code template and the regularity specified in advance (step S306).

  By executing the processing described above, the logic circuit design device 1 can generate a system as shown in FIG. That is, the logic circuit design device 1 can create a logic circuit block (logic circuit A to logic circuit C) by the hardware description generation unit (system related) 20 and the hardware description generation unit (logic circuit related) 21. it can. Furthermore, the logic circuit design device 1 can generate a bus driver and an interrupt controller by the hardware description generation unit (system related) 20 and the hardware description generation unit (logic circuit related) 21. Further, the logic circuit design device 1 can generate an initialization processing function template and an interrupt processing function template by the software description generation unit 22. FIG. 36 is a diagram illustrating a configuration of a system finally generated.

[Effects of Example 1]
Thus, according to the first embodiment, both hardware and software source codes can be created from the register information of the logic circuit block even when designing the entire system including hardware and software. As a result, it is possible to reduce the man-hours for manual work by the designer as compared with the prior art, and therefore, the man-hours required for designing the entire system can be reduced.

  Further, according to the first embodiment, since either or both of the TL description and the RTL description can be selected and generated, system-level verification, that is, software / hardware cooperative verification can be performed at high speed.

  In addition, according to the first embodiment, the initialization process and the interrupt process are considered in addition to the sequential access to the registers, and the generated files (functions) are divided for each of these processes. It can be easily used for developing software such as device drivers.

  Further, according to the first embodiment, when the system memory map, the register map of the logical circuit block, and the interrupt information are prepared, all logical parts other than the core function of the logical circuit block are generated by the apparatus disclosed in the present application. Therefore, the development man-hour for the logic circuit block can be dramatically reduced.

  Further, according to the first embodiment, a system memory map, a register map of the logical circuit block, and interrupt information can be prepared. As a result, all of the logic parts other than the core function of the logic circuit block are generated by the device disclosed in the present application, so that the quality of the logic circuit other than the core function can be guaranteed to a certain degree.

  Further, according to the first embodiment, a system memory map, a register map of the logical circuit block, and interrupt information can be prepared. As a result, a template file for device drivers such as initialization processing interrupt processing and register access necessary to control the logic circuit block is generated by the device disclosed in this application. Can be realized.

  Further, according to the first embodiment, it is possible to start the software / hardware cooperative verification of the system from an early stage of development. In addition, when the file is automatically generated, the file name conforming to the naming rule is set, so that the verification environment of the logic circuit block can be automatically constructed. Further, since the logic verification of the logic circuit block can be performed from the early stage of development, the quality improvement of the logic circuit block can be expected.

  By the way, the logic circuit design apparatus disclosed in the present application can automatically generate various verification environments in accordance with applications. In the second embodiment, an example of a verification environment that can be generated by the logic circuit design apparatus disclosed in the present application will be described.

(Verification environment for accuracy verification)
For example, the logic circuit design apparatus disclosed in the present application can create a verification environment for accuracy verification as shown in FIG. Specifically, the logic circuit design apparatus can create a verification environment for accuracy verification by using a source code or the like generated by RTL description that can be logically synthesized and is suitable for accuracy verification. In this case, the DMA controller (Direct Memory Access controller) can use an existing IP macro, and the initialization processing function template and the interrupt processing function template are used as test data (test driver). By creating such a verification environment, it is possible to verify all the register read / write operations, and to confirm the bus operation and the operation up to the register unit. FIG. 37 is a diagram illustrating a configuration example of a verification environment for accuracy verification.

(Verification environment for functional verification)
Further, the logic circuit design apparatus disclosed in the present application can create a verification environment for function verification as shown in FIG. Specifically, the logic circuit design device can create a verification environment for function verification by using source code generated with a TL description that can operate at high speed and is suitable for function verification. In this case, the DMA controller can use an existing IP macro, and the initialization processing function template and the interrupt processing function template are used as test data (test driver). By creating such a verification environment, it is possible to verify at high speed whether the system generated using the generated source code or the like operates normally. FIG. 38 is a diagram illustrating a configuration example of a verification environment for function verification.

(Single unit verification environment)
Further, the logic circuit design apparatus disclosed in the present application can create a single-use verification environment as shown in FIG. By creating such a verification environment, verification can be performed in units of logic circuit blocks generated using the generated source code or the like. As a result, the cause of the malfunction can be detected at an early stage of system construction. FIG. 39 is a diagram illustrating a configuration example of a single-use verification environment.

  Although the embodiments of the present invention have been described so far, the present invention may be implemented in various different forms other than the embodiments described above. Therefore, as shown below, (1) GUI, (2) template file, (3) hardware source code, (4) system configuration, etc., (5) programs are divided into different embodiments, and different embodiments will be described.

(1) GUI
For example, in the first embodiment, information such as a memory map is received from a user using a GUI and registered in each database. However, in the present application, a text file such as XML (eXtensible Markup Language), CSV (Comma Separated Value), YAML (YAML Ain't a Markup Language), or the like can be used without using the GUI.

(2) Template File For example, in the first embodiment, an example in which a template file is prepared and source code and the like are generated based on the template file and information on the memory map and the register map has been described. In the present application, a template file is not necessarily required, and source code or the like can be generated based on information of a memory map or a register map.

(3) Hardware source code For example, in the logic circuit design apparatus disclosed in the present application, the hardware source code can be created in HDL, or in a hardware description language other than HDL.

(4) System configuration etc. In addition, among the processes described in the present embodiment, all or part of the processes described as being automatically performed can be manually performed or manually performed. All or a part of the processing described as a thing can also be automatically performed by a known method. In addition, the processing procedure, control procedure, specific name, and information including various data and parameters shown in the above-described document and drawings can be arbitrarily changed unless otherwise specified.

  Each component of each device illustrated is only an example and does not necessarily need to be physically configured as illustrated. In other words, the specific form of distribution / integration of each device is not limited to that shown in the figure, and all or a part thereof may be functionally or physically distributed or arbitrarily distributed in arbitrary units according to various loads or usage conditions. Can be integrated and configured. Further, all or any part of each processing function performed in each device may be realized by a CPU and a program analyzed and executed by the CPU, or may be realized as hardware by wired logic.

(5) Program The logic circuit design method described in the present embodiment can be realized by executing a prepared program on a computer such as a personal computer or a workstation. This program can be distributed via a network such as the Internet. The program may be recorded on a computer-readable recording medium such as a hard disk, a flexible disk (FD), a CD-ROM, an MO, a DVD, or a flash memory, and executed by being read from the recording medium by the computer. it can.

  The following supplementary notes are further disclosed with respect to the embodiments including the above examples.

(Supplementary note 1) Register analysis means for analyzing register information of an input logic circuit block and acquiring configuration information of the logic circuit;
A top module including a register unit of the logical circuit, a model of a core function unit of the logic circuit, and the register unit and the core function unit based on configuration information of the logic circuit acquired by the register analyzing unit Hardware description generation means for generating hardware source code for each of the templates,
Based on the configuration information of the logic circuit acquired by the register analyzing means, software description generating means for generating software source code for a model of the device driver function for initialization of the logical circuit,
A logic circuit design apparatus comprising:

(Supplementary Note 2) The hardware description generation unit generates the hardware source code by rewriting the model of each hardware source code using the configuration information of the logic circuit acquired by the register analysis unit. ,
The software description generation unit generates the software source code by rewriting a model of the software source code using the configuration information of the logic circuit acquired by the register analysis unit. The logic circuit design device described.

(Additional remark 3) It further has a memory analysis means for receiving a memory map of a system having software and hardware, analyzing the received memory map, and acquiring configuration information of the system,
The hardware description generation unit generates the hardware source code for each of the system bus model and the logic circuit bus interface based on the system configuration information acquired by the memory analysis unit. The logic circuit design device according to appendix 1 or 2, characterized in that:

(Supplementary Note 4) The hardware description generation means generates the hardware source code in at least one of a transaction level description capable of logic verification and a register transfer level description capable of logic synthesis and capable of clock-based verification. The logic circuit design device according to appendix 1, wherein:

(Supplementary Note 5) The register analyzing means further acquires interrupt information of the logic circuit block,
The hardware description generation unit generates an interrupt controller using the interrupt information acquired by the register analysis unit,
The logic circuit design apparatus according to appendix 1, wherein the software description generation unit generates a template of an interrupt processing function using the interrupt information acquired by the register analysis unit.

(Supplementary note 6) The logic circuit design according to supplementary note 1, wherein the software description generation means generates the software source code by dividing a file for each processing function when generating the software source code. apparatus.

(Supplementary Note 7) A verification environment for verifying the hardware source code and the software source code by using the hardware source code generated by the hardware description generation unit and the software source code generated by the software description generation unit The logic circuit design device according to appendix 1, further comprising verification environment creation means for creating.

(Supplementary Note 8) The verification environment creation means creates a file or directory for the verification environment for the hardware source code and software source code according to a predetermined regularity, and creates a file or directory created according to the regularity. 8. The logic circuit design device according to appendix 7, wherein the directory is named.

(Additional remark 9) The register analysis procedure which analyzes the register information of the input logic circuit block and acquires the configuration information of the logic circuit;
Based on the logic circuit configuration information acquired by the register analysis procedure, a top module including a register unit of the logical circuit, a core function unit model of the logic circuit, and the register unit and core function unit For each of the templates, a hardware description generation procedure for generating hardware source code,
Based on the configuration information of the logic circuit acquired by the register analysis procedure, a software description generation procedure for generating a software source code for a model of the device driver function for initialization of the logical circuit,
A logic circuit design program that causes a computer as a logic circuit design apparatus to execute the program.

1 logic circuit design device 10 system memory map DB
11 Bus type DB
12 Logic Circuit Register Map List DB
13 logic circuit register map details DB
14 Logic circuit interrupt information DB
15 Verification type DB
20 Hardware description generator (system related)
20a Hardware source code of bus model 20b Hardware source code of logic circuit bus interface unit 20c Hardware source code of simple interrupt controller 21 Hardware description generation unit (related to logic circuit)
21a Hardware source code of logic circuit register part 21b Hardware source code of logic circuit core function block model 21c Hardware source code of logic circuit top module model 22 Software description generation part 22a Software source code of logic circuit interrupt processing function model 22b Software source code of logic circuit initialization function template 25 Verification environment generation unit

Claims (5)

Register analysis means for analyzing register information of a logic circuit block, which is an assembly of logic circuits that realize a specific function, and obtaining configuration information of the logic circuit;
Memory analysis means for receiving a memory map of a system having software and hardware, analyzing the received memory map, and acquiring configuration information of the system;
Based on the configuration information of the logic circuit acquired by the register analysis means, a model of a core function unit that is a circuit that executes the specific function of the logic circuit block, and the core function unit executes the specific function A logic unit that includes a register unit that holds a predetermined value or an output result obtained by executing the specific function, and the register unit and the core function unit. For each of the top module templates that provide an external interface as a circuit block, a hardware source code is generated , and based on the system configuration information acquired by the memory analysis unit, the bus model of the system, and for each of the bus interface logic, to generate the hardware source code And Dowea description generating means,
Based on the configuration information of the logic circuit acquired by the register analyzing means, software description generating means for generating software source code for a model of the device driver function for initialization of the logical circuit,
A logic circuit design apparatus comprising: The hardware description generation unit generates the hardware source code by rewriting the model of each hardware source code using the configuration information of the logic circuit acquired by the register analysis unit,
2. The software description generation unit generates the software source code by rewriting a model of the software source code using configuration information of a logic circuit acquired by the register analysis unit. The logic circuit design device described in 1.   The hardware description generation means generates the hardware source code in at least one of a transaction level description capable of logic verification and a register transfer level description capable of logic synthesis and capable of clock-based verification. The logic circuit design apparatus according to claim 1. The register analysis means further acquires interrupt information of the logic circuit block,
The hardware description generation unit generates an interrupt controller using the interrupt information acquired by the register analysis unit,
2. The logic circuit design apparatus according to claim 1, wherein the software description generation unit generates a template of an interrupt processing function using the interrupt information acquired by the register analysis unit. Register analysis means for analyzing register information of the input logic circuit block and obtaining configuration information of the logic circuit;
Memory analysis means for receiving a memory map of a system having software and hardware, analyzing the received memory map, and acquiring configuration information of the system;
A top module including a register unit of the logical circuit, a model of a core function unit of the logic circuit, and the register unit and the core function unit based on configuration information of the logic circuit acquired by the register analyzing unit For each of the models, a hardware source code is generated, and based on the system configuration information acquired by the memory analysis means, the bus model of the system and the bus interface of the logic circuit, Hardware description generation means for generating hardware source code;
Based on the configuration information of the logic circuit acquired by the register analyzing means, software description generating means for generating software source code for a model of the device driver function for initialization of the logical circuit,
A logic circuit design apparatus comprising:

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