JP5515273B2 - Semiconductor integrated circuit device and battery pack - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device and a battery pack, and more particularly to a semiconductor integrated circuit device and a battery pack having a function of obtaining a remaining battery level and transmitting it to a battery-using device.

  In recent years, lithium ion batteries have been installed in portable battery-powered devices such as mobile phones and digital cameras. In general, it is difficult for a lithium ion battery to detect the remaining battery level from its voltage. For this reason, a method of measuring the remaining battery level by integrating the charging / discharging current of the battery is employed.

  Conventionally, a fuel gauge IC for measuring the remaining battery level using the above method has been developed. This fuel gauge IC incorporates a CPU, a memory, etc., and converts the detected charge / discharge current into digital data. The remaining battery level is calculated, and the calculated remaining battery level is transmitted to a battery-operated device such as a mobile phone or a digital camera via a communication circuit.

  The fuel gauge IC is for measuring the battery remaining amount. However, since the fuel gauge IC itself supplies the operating power from the lithium ion battery, it is necessary to reduce the current consumption of the fuel gauge IC as much as possible.

Patent Document 1 describes that a battery remaining amount measurement mode is provided during the control mode of the data processing means, and control is performed to minimize the supply current from the battery during the measurement mode to save power. Has been.
JP 2005-12960 A

  In addition to the normal mode, the conventional fuel gauge IC has only a shutdown mode in which the clock is stopped or the power is shut off when left for a long period of time, depending on the connection state of the battery-powered device and the operating state of the battery-powered device. There have been problems such as that current consumption cannot be reduced, and that the remaining battery level cannot be determined in a long-term neglected state in which battery-operated equipment is not connected.

  The present invention has been made in view of the above points, can set various operation modes with different current consumption, can reduce the current consumption according to the connection state and the operation state of battery-operated equipment, and the battery It is an object of the present invention to provide a semiconductor integrated circuit device and a battery pack that can determine the remaining amount.

A semiconductor integrated circuit device according to an embodiment of the present invention is a semiconductor integrated circuit device having a function of using a battery as a power source and obtaining a remaining battery level and transmitting the battery remaining amount to a battery using device using the battery as a power source.
Clock generating means (21, 23) for generating a first clock and a second clock having a frequency higher than that of the first clock;
Selecting means (24) for selecting and outputting either the first clock or the second clock output from the clock generating means;
A calculating means (12) for operating the clock output from the selecting means to calculate the remaining battery capacity;
A communication means (16) for operating the clock output from the selection means and transmitting the remaining battery level calculated by the calculation means to the battery using device;
Only the first mode for operating the computing means (12), the second mode for pausing the computing means (12), and the time measuring means for pausing the computing means and using the clock output from the selecting means. Setting means (12, 22, 25, S1 to S6) for setting the third mode for operating
The first mode and the second mode, and during said first mode and the third mode Ri transition can der each other,
The setting means sets the first mode according to the connection state and the operating state of the battery using device if the battery using device is in an operating state, and the second mode if the battery using device is not in an operating state. Set the mode, and if the battery-powered device is not connected, set the third mode,
In the first mode, the operation means calculates the battery remaining amount including the decrease in the battery remaining amount in the third mode, whereby various operation modes with different current consumption can be set. Current consumption can be reduced and the remaining battery level can be determined according to the connection state and operating state of the equipment used.

In the semiconductor integrated circuit device,
The clock generation means (21, 23) includes a first oscillator (21) for generating a first clock;
A second oscillator (23) for generating a second clock synchronized with the first clock may be provided.

In the semiconductor integrated circuit device,
The clock generation means (21, 23) includes a first oscillator (21) that generates the first clock;
A second oscillator (23) that generates a second clock that is asynchronous with the first clock can be used.

  A battery pack according to an embodiment of the present invention includes the semiconductor integrated circuit device according to any one of claims 1 to 6 and the battery, so that various operation modes with different current consumption can be set. The current consumption can be reduced according to the connection state and operating state of the battery-operated device, and the remaining battery level can be obtained.

The Te semiconductor integrated circuit device smell,
The clock generation means includes a first oscillator (41) for generating a first clock and a second oscillator (23) for generating a second clock,
It said first oscillator (41) based on the frequency of the first clock generated by the first mode can be configured to lower the frequency of the first clock generated in the third mode.

In the semiconductor integrated circuit device,
The time counting means (15) may be configured to cause the setting means to transition to the first mode when a predetermined time elapses after the time is measured using the first clock in the third mode.

In the semiconductor integrated circuit device,
The time counting means (15) may be configured to allow the predetermined time to be changed.

  Note that the reference numerals in the parentheses are given for ease of understanding, are merely examples, and are not limited to the illustrated modes.

  According to the present invention, the activation of the signal processing means can be optimized according to the selected oscillation source.

<Configuration of semiconductor integrated circuit device>
FIG. 1 is a block diagram showing a semiconductor integrated circuit device according to an embodiment of the present invention. In the figure, the fuel gauge function module 10 includes an analog circuit unit 11, a CPU 12, a ROM 13, a RAM 14, a timer unit 15, and a communication unit 16, which are connected to each other by an internal bus (not shown). .

  The analog circuit unit 11 is provided with analog circuits such as a voltage sensor, a temperature sensor, a current sensor, and an AD converter, and the detection value of each sensor is digitized by the AD converter and supplied to the CPU 12 via the internal bus. The

  The CPU 12 executes various software stored in the ROM 13 and calculates the remaining battery level of the lithium ion battery by integrating the charge / discharge current of the lithium ion battery detected by the current sensor. The detection values of the voltage sensor and the temperature sensor are used for various corrections, the RAM 14 is used as a work area when the CPU 12 executes processing, and the ROM 13 includes an EEPROM as a nonvolatile memory.

  The timer unit 15 includes various timers including an interrupt timer and a timer, and signals generated by these timers are supplied to the CPU 12 as an interrupt signal and a measurement time, for example. The communication unit 16 transmits the remaining battery level calculated by the CPU 12 to the battery using device via the communication terminal 17 in response to a request supplied via the communication terminal 17 from the battery using device such as a mobile phone or a digital camera. .

  The oscillation circuit 21 is instructed to oscillate or stop according to the operation mode from the operation mode register 22, generates a low-speed clock with a frequency of 38.4 kHz, for example, according to the instruction of oscillation, and supplies it to the oscillation circuit 23 and the clock selector 24.

  The oscillation circuit 23 has a built-in PLL, for example, which is instructed by the operation mode register 22 for a multiplication number corresponding to the operation mode, and is synchronized with the clock from the oscillation circuit 21, for example, at a frequency of 5 MHz / 2.5 MHz / 1.25 MHz. Either medium high-speed clock is generated and supplied to the clock selector 24.

  Note that the oscillation circuit 21 and 23 may be operated asynchronously without supplying the clock output from the oscillation circuit 21 to the oscillation circuit 23.

  The clock selector 24 is instructed by the operation mode register 22 to select a clock according to the operation mode, selects one of the low-speed clock and the plurality of medium-high-speed clocks, and the analog circuit unit 11 in the fuel gauge function module 10. The CPU 12, the ROM 13, the RAM 14, the timer unit 15, and the communication unit 16 are supplied.

  The operation mode register 22 sets the operation mode from the CPU 12 and switches the operation mode when the CPU 12 executes a command (sleep command). Further, the CPU 12 sets permission / prohibition of clock reception of the analog circuit unit 11, the timer unit 15, and the communication unit 16 in the module stop register 25, and the module stop register 25 instructs permission / prohibition of the set clock reception. The signal is supplied to each of the analog circuit unit 11, the timer unit 15, and the communication unit 16. As a result, the analog circuit unit 11, the timer unit 15, and the communication unit 16 accept the clock supplied from the clock selector 24 only for those instructed to accept the clock.

<State transition>
FIG. 2 shows a state transition diagram of the semiconductor integrated circuit device shown in FIG. In the figure, the device enters an active mode (high speed) ACH by reset. Thereafter, transition from the active mode (high speed) ACH to the active mode (medium speed) ACM is performed by setting the operation mode register 22 and execution of the sleep command, and reverse transition is performed by setting the operation mode register 22 and execution of the sleep command. Do. Further, transition from the active mode (medium speed) ACM to the subactive mode SAC is performed by setting the operation mode register 22 and execution of the sleep command, and reverse transition is performed by setting the operation mode register 22 and execution of the sleep command. .

  The active mode (high speed) ACH is a mode in which the CPU 12 executes a program at a high speed with a clock of frequency 5 MHz, and the clock of frequency 5 MHz selected by the clock selector 24 is supplied to each part of the fuel gauge function module 10 to stop the module. In response to an instruction from the register 25, the analog circuit unit 11, the timer unit 15, and the communication unit 16 receive a clock and operate at high speed.

  The active mode (medium speed) ACM is a mode in which the CPU 12 executes a program at a medium speed by using a clock having a frequency of 2.5 MHz or 1.25 MHz, and a clock having a frequency of 2.5 MHz or 1.25 MHz selected by the clock selector 24. Is supplied to each part of the fuel gauge function module 10, and the analog circuit unit 11, the timer unit 15, and the communication unit 16 operate at a medium speed in response to an instruction from the module stop register 25.

  The sub-active mode SAC is a mode in which the CPU 12 executes a program at a low speed with a clock having a frequency of 38.4 kHz. The clock having a frequency of 38.4 kHz selected by the clock selector 24 is supplied to each part of the fuel gauge function module 10. In response to an instruction from the module stop register 25, the analog circuit unit 11, the timer unit 15, and the communication unit 16 receive a clock and operate at a low speed.

  Further, the sleep mode (high speed) SLH and the sleep mode (medium speed) SLM are set by setting the operation mode register 22 and executing the sleep command from the active mode (high speed) ACH, active mode (medium speed) ACM, and subactive mode SAC. , Transition to the sub-sleep mode SSL, and the reverse transition is performed by the occurrence of a program interrupt or a timer interrupt.

  In the sleep mode (high speed) SLH, the CPU 12 stops the operation, and the analog circuit unit 11, the timer unit 15, and the communication unit 16 accept the clock of the frequency 5 MHz selected by the clock selector 24 according to the instruction of the module stop register 25. It is a mode to do.

  In the sleep mode (medium speed) SLM, the CPU 12 stops the operation, and the analog circuit unit 11, the timer unit 15, and the communication unit 16 are selected by the clock selector 24 according to an instruction from the module stop register 25. In this mode, a clock of 25 MHz is received and operated.

  In the subsleep mode SSL, the CPU 12 stops the operation, and the analog circuit unit 11, the timer unit 15, and the communication unit 16 accept the clock of the frequency 38.4 kHz selected by the clock selector 24 according to the instruction of the module stop register 25. It is a mode to do.

  Also, transition from active mode (high speed) ACH, active mode (medium speed) ACM, subactive mode SAC to watch mode WTC and software standby mode SSB by setting of operation mode register 22 and execution of a sleep command causes program interrupt. Alternatively, a reverse transition is performed by the occurrence of a timer interrupt.

  The watch mode WTC is a mode in which the CPU 12 stops its operation and only the timer unit 15 receives the clock of the frequency 38.4 kHz selected by the clock selector 24 according to the instruction of the module stop register 25 and operates.

  The software standby mode SSB is a mode in which the CPU 12 stops its operation, and all of the analog circuit unit 11, the timer unit 15, and the communication unit 16 are stopped by an instruction from the module stop register 25.

  In the watch mode WTC and the software standby mode SSB, the analog circuit unit 11, the RAM 14, the operation mode register 22, the module stop register 25, etc. retain their internal states when the operation is stopped.

  Therefore, in the watch mode WTC, the timer unit 15 can measure the time during which the watch mode WTC is maintained, and the watch mode WTC returns to the active mode (high speed) ACH, active mode (medium speed) ACM, and subactive mode SAC. After that, the CPU 12 can estimate the charge / discharge current of the lithium ion battery from the watch mode maintenance time.

<Operation mode switching>
FIG. 3 shows a flowchart of an embodiment of the operation mode switching process executed by the CPU 12. When this process starts, an active mode (high speed) ACH or an active mode (medium speed) ACM is set in advance.

  In the figure, in step S1, the CPU 12 uses a battery pack equipped with its own device (semiconductor integrated circuit device) based on the type of request, status, or request frequency supplied from the battery using device to the communication unit 16. Is connected, the battery-operated device is in an operating state, or the battery-operated device is in a function stop state.

  For example, if a battery using device is connected to the battery pack, the voltage of the communication terminal 17 is at a predetermined level, so the connection of the battery using device can be determined. If the battery using device is in an operating state, the request frequency is higher than a predetermined value. If the battery-operated device is in the function stop state, the request frequency is lower than the predetermined value, so that the operation state / function stop state can be determined.

  In step S2, it is determined whether or not the battery using device is in an operating state from the determination result. If the battery using device is in an operating state, an active mode (high speed) ACH or an active mode (medium speed) ACM is detected in step S3. Set to the operation mode.

  On the other hand, if the battery-operated device is not in the operating state from the determination result in step S2, it is determined in step S4 whether or not the battery-operated device is in the function stop state. In step S5, the operation mode is switched to the sleep mode (high speed) SLH or the sleep mode (medium speed) SLM. When a predetermined time elapses after the switching, for example, the timer returns to the original active mode (high speed) ACH, active mode (medium speed) ACM, or subactive mode SAC.

  Furthermore, when the battery-operated device is not in a function stop state in step S4, that is, when the battery-utilized device is not connected to the battery pack, the operation mode is set to the subactive mode SAC, the subsleep mode SSL, or the watch mode WTC in step S6. Switch. When a predetermined time elapses after switching to the sub sleep mode SSL or watch mode WTC, for example, the timer returns to the original active mode (high speed) ACH, active mode (medium speed) ACM or sub active mode SAC.

  Whether active mode (high speed) ACH or active mode (medium speed) ACM is set in step S3, whether to switch to sleep mode (high speed) SLH or sleep mode (medium speed) SLM in step S5, step S6 Whether to switch to the subactive mode SAC, the subsleep mode SSL, or the watch mode WTC is determined in advance by the user and set in the EEPROM in the ROM 13.

  By the way, when the battery using device is connected to the battery pack and the battery using device is not in the operating state, as shown in FIG. 4A, the active mode (high speed) ACH [or active mode ( Medium speed) ACM], and the sleep mode (high speed) SLH [or sleep mode (medium speed) SLM] may be repeated for a predetermined time T2.

  Further, when no battery-using device is connected to the battery pack, as shown in FIG. 4B, the active mode (high speed) ACH [or active mode (medium speed) ACM or subactive mode is used for a predetermined time T1. SAC], and the watch mode WTC may be repeated for a predetermined time T3. As described above, the user can freely set which mode is used according to the state of the battery-powered device.

  Thus, according to the connection state and the operating state of the battery using device, if the battery using device is in the operating state, for example, the active mode is set, and if the battery using device is not in the operating state, the sleep mode is set. If is not connected, for example, the watch mode is set, so that current consumption can be reduced, and the remaining battery level can be determined in a state where the battery using device is not connected for a long time.

<Battery pack>
FIG. 5 is a perspective view of an embodiment of a battery pack to which the semiconductor integrated circuit device of the present invention is applied. In the figure, the battery pack 30 has a configuration in which a battery 31 and a semiconductor integrated circuit device 32 are accommodated in a case 33. The battery 31 is a lithium ion battery, and is connected to the semiconductor integrated circuit device 32 having the configuration shown in FIG. 1 through connection terminals 34a and 34b.

  The external terminals 35 a and 35 b provided on the case 33 are connected to the positive and negative electrodes of the battery 31, and the external terminal 35 c is connected to the communication terminal 17 of the semiconductor integrated circuit device 32.

In the above embodiment, the active mode is used as an example of the first mode, the sleep mode is used as an example of the second mode , and the watch mode is used as an example of the third mode .

<Other embodiments>
FIG. 6 is a block diagram showing another embodiment of the semiconductor integrated circuit device of the present invention. In the figure, the same parts as those in FIG. In the fuel gauge function module 10, an analog circuit unit 11, a CPU 12, a ROM 13, a RAM 14, a timer unit 15, and a communication unit 16 are provided, and these are connected to each other by an internal bus (not shown).

  The analog circuit unit 11 is provided with analog circuits such as a voltage sensor, a temperature sensor, a current sensor, and an AD converter, and the detection value of each sensor is digitized by the AD converter and supplied to the CPU 12 via the internal bus. The

  The CPU 12 executes various software stored in the ROM 13 and calculates the remaining battery level of the lithium ion battery by integrating the charge / discharge current of the lithium ion battery detected by the current sensor. The detection values of the voltage sensor and the temperature sensor are used for various corrections, the RAM 14 is used as a work area when the CPU 12 executes processing, and the ROM 13 includes an EEPROM as a nonvolatile memory.

  The timer unit 15 includes various timers including an interrupt timer and a timer, and signals generated by these timers are supplied to the CPU 12 as an interrupt signal and a measurement time, for example. The communication unit 16 transmits the remaining battery level calculated by the CPU 12 to the battery using device via the communication terminal 17 in response to a request supplied via the communication terminal 17 from the battery using device such as a mobile phone or a digital camera. .

  The variable oscillation circuit 41 is instructed by the operation mode register 22 to oscillate or stop at a frequency corresponding to the operation mode, and is oscillated at instruction 1 (active mode, subactive mode, sleep mode, subsleep mode), for example, at a frequency of 38.4 kHz. A low-speed clock is generated, and an ultra-low-speed clock having a frequency of, for example, 9.6 kHz or less is generated by an oscillation instruction 2 (watch mode) and supplied to the oscillation circuit 23 and the clock selector 24.

  Here, a sigma delta modulator is provided as an AD converter in the analog circuit unit 11, and an analog signal is PDM (pulse density modulation), that is, 1-bit digitally modulated by the sigma delta modulator and supplied to the CPU 12. There is a case in which the PDM signal is converted into a multi-bit digital value, that is, PCM (pulse code modulation) data. In this case, the CPU 12 can convert the PDM signal into PCM data if a low-speed clock with a frequency of 38.4 kHz is supplied. However, the ultra-low-speed clock with a frequency of 9.6 kHz can convert the PDM signal into the PCM data. Can not. That is, the ultra-low speed clock with a frequency of 9.6 kHz is so low that the CPU 12 cannot operate normally.

  FIG. 7 shows a circuit configuration diagram of an embodiment of the variable oscillation circuit 41. In the figure, p-channel MOS-FETs (metal oxide semiconductor-field effect transistors: hereinafter referred to as “MOS transistors”) M1 to M4 have sources connected to the power source Vcc, gates connected to terminals 42a to 42d, drains Are commonly connected. The sources of p-channel MOS transistors M5 and M6 are connected to the drains of the MOS transistors M1 to M4. The drain currents when the MOS transistors M1 to M4 are on are the same.

  The drain of the MOS transistor M5 is connected to the non-inverting input terminal of the comparator 43, the drain of the n-channel MOS transistor M7, and one end of the capacitor C1, and the source of the MOS transistor M7 and the other end of the capacitor C1 are grounded. The gates of the MOS transistors M5 and M7 are connected to the terminal d of the logic circuit 45. The reference voltage V1 is applied from the constant voltage source 46 to the inverting input terminal of the comparator 43, and the output terminal of the comparator 43 is connected to the terminal a of the logic circuit 45.

  The drain of the MOS transistor M6 is connected to the non-inverting input terminal of the comparator 44, the drain of the n-channel MOS transistor M8, and one end of the capacitor C2 (for example, C1 = C2), and the source of the MOS transistor M8 and the other end of the capacitor C2 are grounded. ing. The gates of the MOS transistors M6 and M8 are connected to the terminal e of the logic circuit 45. The reference voltage V1 is applied from the constant voltage source 46 to the inverting input terminal of the comparator 44, and the output terminal of the comparator 44 is connected to the terminal b of the logic circuit 45.

  Here, when the terminal e output of the logic circuit 45 is high level and the terminal d output is low level, the MOS transistor M5 is turned on, the MOS transistor M7 is turned off, the capacitor C1 is charged, and the non-inverting input terminal of the comparator 43 is charged. When the voltage gradually increases and exceeds the reference voltage V1, the output of the comparator 43 (that is, the terminal a input of the logic circuit 45) is switched from the low level to the high level. As a result, the terminal c output becomes high level, the terminal d output becomes high level, the MOS transistor M5 is turned off, the MOS transistor M7 is turned on, and the capacitor C1 is rapidly discharged.

  When the terminal d output of the logic circuit 45 becomes high level and the terminal e output becomes low level, the MOS transistor M6 is turned on, the MOS transistor M8 is turned off, the capacitor C2 is charged, and the voltage at the non-inverting input terminal of the comparator 44 gradually increases. When the voltage rises to exceed the reference voltage V1, the output of the comparator 44 (that is, the terminal b input of the logic circuit 45) is switched from the low level to the high level. As a result, the terminal c output becomes low level, the terminal e output becomes high level, the MOS transistor M6 is turned off, the MOS transistor M8 is turned on, and the capacitor C2 is rapidly discharged. In this way, the terminal c output of the logic circuit 45 is output from the terminal 47 as an oscillation signal.

  In the case of the oscillation instruction 1 instructing generation of a low-speed clock having a frequency of 38.4 kHz, low level signals are supplied to all of the terminals 42a to 42d, the MOS transistors M1 to M4 are turned on, and the drain currents of the MOS transistors M1 to M4 are The added value becomes the drain current of the MOS transistor M5 or M6, that is, the charging current of the capacitors C1 and C2.

  In the case of the oscillation instruction 2 for instructing the generation of an ultra-low-speed clock with a frequency of 9.6 kHz, only the terminal 42a is supplied with the low level and the high level signal is supplied to the terminals 42b to 42d, and only the MOS transistor M1 is turned on. The current becomes the drain current of the MOS transistor M5 or M6, that is, the charging current of the capacitors C1 and C2.

  In this way, in the oscillation instruction 2, the charging current of the capacitors C1 and C2 is set to ¼ that of the oscillation instruction 1, so that the oscillation frequency is approximately ¼.

  As the variable oscillation circuit 41, an oscillator that generates a low-speed clock and an oscillator that generates an ultra-low-speed clock may be prepared and switched to one of them.

  The oscillation circuit 23 has a built-in PLL, for example, which is instructed by the operation mode register 22 for a multiplication number corresponding to the operation mode, and is synchronized with the clock from the oscillation circuit 41, for example, at a frequency of 5 MHz / 2.5 MHz / 1.25 MHz. Either medium high-speed clock is generated and supplied to the clock selector 24.

  Note that the oscillation circuit 41 and 23 may be operated asynchronously without supplying the clock output from the oscillation circuit 41 to the oscillation circuit 23.

  The clock selector 24 is instructed by the operation mode register 22 to select a clock according to the operation mode, selects one of the low-speed clock and the plurality of medium-high-speed clocks, and the analog circuit unit 11 in the fuel gauge function module 10. The CPU 12, the ROM 13, the RAM 14, the timer unit 15, and the communication unit 16 are supplied.

  The operation mode register 22 sets the operation mode from the CPU 12 and switches the operation mode when the CPU 12 executes a command (sleep command). Further, the CPU 12 sets permission / prohibition of clock reception of the analog circuit unit 11, the timer unit 15, and the communication unit 16 in the module stop register 25, and the module stop register 25 instructs permission / prohibition of the set clock reception. The signal is supplied to each of the analog circuit unit 11, the timer unit 15, and the communication unit 16. As a result, the analog circuit unit 11, the timer unit 15, and the communication unit 16 accept the clock supplied from the clock selector 24 only for those instructed to accept the clock.

<State transition>
FIG. 8 shows a state transition diagram of the semiconductor integrated circuit device shown in FIG. In FIG. 8, the vertical direction represents the clock frequency. In the figure, the device enters an active mode (high speed) ACH by reset. Thereafter, transition from the active mode (high-speed) ACH to the subactive mode SAC is performed by setting the operation mode register 22 and execution of the sleep instruction, and reverse transition is performed by setting the operation mode register 22 and execution of the sleep instruction. .

  The active mode (high speed) ACH is a mode in which the CPU 12 executes a program at a high speed with a clock of frequency 5 MHz, and the clock of frequency 5 MHz selected by the clock selector 24 is supplied to each part of the fuel gauge function module 10 to stop the module. In response to an instruction from the register 25, the analog circuit unit 11, the timer unit 15, and the communication unit 16 receive a clock and operate at high speed.

  The sub-active mode SAC is a mode in which the CPU 12 executes a program at a low speed with a clock having a frequency of 38.4 kHz. The clock having a frequency of 38.4 kHz selected by the clock selector 24 is supplied to each part of the fuel gauge function module 10. In response to an instruction from the module stop register 25, the analog circuit unit 11, the timer unit 15, and the communication unit 16 receive a clock and operate at a low speed.

  In addition, transition from the active mode (high speed) ACH to the sleep mode (medium speed) SLM is performed by setting the operation mode register 22 and executing the sleep instruction, and reverse transition is performed by occurrence of a program interrupt or timer interrupt.

  In the sleep mode (medium speed) SLM, the CPU 12 stops the operation, and the analog circuit unit 11, the timer unit 15, and the communication unit 16 are selected by the clock selector 24 according to an instruction from the module stop register 25. In this mode, a clock of 25 MHz is received and operated.

  Also, the sub-active mode SAC makes a transition to the sub-sleep mode SSL by setting the operation mode register 22 and executing the sleep instruction, and makes a reverse transition by the occurrence of a program interrupt or a timer interrupt.

  In the subsleep mode SSL, the CPU 12 stops the operation, and the analog circuit unit 11, the timer unit 15, and the communication unit 16 accept the clock of the frequency 38.4 kHz selected by the clock selector 24 according to the instruction of the module stop register 25. It is a mode to do.

  The active mode (high-speed) ACH transitions to the watch mode WTC and the software standby mode SSB by setting the operation mode register 22 and executing the sleep instruction, and the reverse transition is performed by occurrence of a program interrupt or timer interrupt.

  The watch mode WTC is a mode in which the CPU 12 stops its operation, and only the timer unit 15 receives the clock of the frequency 9.6 kHz selected by the clock selector 24 according to the instruction of the module stop register 25 and operates.

  The software standby mode SSB is a mode in which the CPU 12 stops its operation, and all of the analog circuit unit 11, the timer unit 15, and the communication unit 16 are stopped by an instruction from the module stop register 25.

  In the watch mode WTC and the software standby mode SSB, the analog circuit unit 11, the RAM 14, the operation mode register 22, the module stop register 25, etc. retain their internal states when the operation is stopped.

  Therefore, in watch mode WTC, the timer unit 15 can measure the time during which the watch mode WTC is maintained, and after returning from the watch mode WTC to the subactive mode SAC, the CPU 12 recharges the lithium ion battery from the watch mode maintenance time. The discharge current can be estimated.

<Operation mode switching>
FIG. 9 shows a flowchart of another embodiment of the operation mode switching process executed by the CPU 12. When this process starts, an active mode (high speed) ACH or an active mode (medium speed) ACM is set in advance.

  In step S11, the CPU 12 uses a battery pack that has its own device (semiconductor integrated circuit device) based on the type of request, status, or request frequency supplied from the battery using device to the communication unit 16 in step S11. Is connected, the battery-operated device is in an operating state, or the battery-operated device is in a function stop state.

  For example, if a battery using device is connected to the battery pack, the voltage of the communication terminal 17 is at a predetermined level, so the connection of the battery using device can be determined. If the battery using device is in an operating state, the request frequency is higher than a predetermined value. If the battery-operated device is in the function stop state, the request frequency is lower than the predetermined value, so that the operation state / function stop state can be determined.

  In step S12, it is determined whether or not the battery using device is in the operating state from the determination result. If the battery using device is in the operating state, the operation mode is set to the active mode (high speed) ACH in step S13.

  On the other hand, if the battery-operated device is not in the operating state from the determination result in step S12, it is determined in step S14 whether or not the battery-operated device is in the function stopped state. In step S15, the operation mode is switched to the sleep mode (medium speed) SLM. When a predetermined time elapses after the switching, for example, the original active mode (high speed) ACH is restored by a timer interrupt.

  Furthermore, when the battery-operated device is not in a function stop state in step S14, that is, when the battery-utilized device is not connected to the battery pack, the operation mode is switched to the watch mode WTC in step S16. After switching to the watch mode WTC, the timer unit 15 counts an ultra-low-speed clock with a frequency of 9.6 kHz and when a predetermined time elapses, the timer interrupt from the timer unit 15 causes the original active mode (high-speed) ACH or subactive. Return to mode SAC.

  In step S16, it may be configured to switch to a subactive mode SAC or a subsleep mode SSL other than the watch mode WTC.

  In this embodiment, when a battery using device is not connected to the battery pack, as shown in FIG. 10, the sub-active mode SAC is set for a predetermined time T1, and the watch mode is set for a predetermined time N × T1 (N is a real number). The WTC is configured to repeat this.

  In this case, the default value of the variable N is set in the EEPROM in the ROM 13 at the time of manufacture. After that, when the battery using device is connected to the battery pack, the variable N can be set and changed from the battery using device. This makes it possible to freely change the duration of the watch mode WTC according to the state of the battery-powered device.

  As described above, in another embodiment, the current consumption can be reduced by using an ultra-low-speed clock having a frequency of 9.6 kHz or less in the watch mode, for example, no battery-using device is connected to the battery pack. Even in such a state, the battery can be calculated in the subactive mode periodically, and the life of the battery pack can be further extended by reducing the current consumption.

In other embodiments, the active mode or the subactive mode is used as an example of the first mode, and the watch mode is used as an example of the third mode.

1 is a block configuration diagram of an embodiment of a semiconductor integrated circuit device of the present invention. It is a state transition diagram of a semiconductor integrated circuit device. It is a flowchart of one Embodiment of an operation mode switching process. It is explanatory drawing of mode switching. It is a perspective view of one embodiment of a battery pack to which a semiconductor integrated circuit device of the present invention is applied. It is a block block diagram of other embodiment of the semiconductor integrated circuit device of this invention. It is a circuit block diagram of one Embodiment of a variable oscillation circuit. FIG. 7 is a state transition diagram of the semiconductor integrated circuit device shown in FIG. 6. It is a flowchart of other embodiment of an operation mode switching process. It is explanatory drawing of mode switching.

Explanation of symbols

10 Fuel Gauge Function Module 11 Analog Circuit Unit 12 CPU
13 ROM
14 RAM
DESCRIPTION OF SYMBOLS 15 Timer part 16 Communication part 21,23,41 Oscillator circuit 22 Operation mode register 24 Clock selector 25 Module stop register 30 Battery pack 31 Battery 32 Semiconductor integrated circuit device

Claims (7)

A semiconductor integrated circuit device having a function of obtaining a remaining amount of a battery using a battery as a power source and transmitting it to a battery using device using the battery as a power source,
Clock generating means for generating a first clock and a second clock having a frequency higher than that of the first clock;
Selecting means for selecting and outputting either the first clock or the second clock output from the clock generating means;
An operation means for operating the clock output from the selection means to calculate the remaining battery power,
A communication unit that operates according to a clock output from the selection unit and transmits a remaining battery level calculated by the calculation unit to the battery using device;
A first mode in which the computing means is operated; a second mode in which the computing means is paused; and a third mode in which only the timing means that pauses the computing means and uses the clock output from the selection means is operated. Setting means for setting
The first mode and the second mode, and during said first mode and the third mode Ri transition can der each other,
The setting means sets the first mode according to the connection state and the operating state of the battery using device if the battery using device is in an operating state, and the second mode if the battery using device is not in an operating state. Set the mode, and if the battery-powered device is not connected, set the third mode,
The semiconductor integrated circuit device according to claim 1, wherein the remaining battery level is calculated by the calculating means in the first mode, including a decrease in the remaining battery level in the third mode . The semiconductor integrated circuit device according to claim 1.
The clock generation means includes a first oscillator that generates a first clock;
A semiconductor integrated circuit device, comprising: a second oscillator that generates a second clock synchronized with the first clock. The semiconductor integrated circuit device according to claim 1.
The clock generation means includes a first oscillator that generates the first clock;
A semiconductor integrated circuit device comprising: a second oscillator that generates a second clock that is asynchronous with the first clock. A battery pack comprising the semiconductor integrated circuit device according to any one of claims 1 to 3 and the battery. The semiconductor integrated circuit device smell of claim 1 wherein Te,
The clock generation means includes a first oscillator that generates a first clock and a second oscillator that generates a second clock,
The semiconductor integrated circuit device according to claim 1, wherein the first oscillator lowers a frequency of the first clock generated in the third mode with respect to a frequency of the first clock generated in the first mode. The semiconductor integrated circuit device according to claim 5 .
The time measuring means measures the time using the first clock in the third mode and causes the setting means to transition to the first mode when a predetermined time elapses. The semiconductor integrated circuit device according to claim 6 .
2. The semiconductor integrated circuit device according to claim 1, wherein the time measuring means allows the predetermined time to be changed.

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