JP5512561B2 - Hall voltage detector - Google Patents

Description

  The present invention relates to a Hall voltage detection device that constitutes a magnetic sensor or the like that detects a magnetic variable using a Hall element.

As is well known, when a driving current is supplied in a direction orthogonal to the direction of the magnetic field acting on the Hall element, a Hall effect is generated, which is a phenomenon that generates an electromotive force (Hall voltage) in the direction orthogonal to the magnetic field and the driving current. It is a semiconductor element. Various techniques relating to a magnetic sensor that detects a magnetic variable (magnetic field) using the Hall element have been proposed.
The Hall voltage generated by the Hall element includes the offset voltage generated by the stress applied to the silicon substrate, the error in the shape of the diffusion region, and the variation in the impurity concentration of the diffusion region. It becomes a deterioration factor.

In recent years, various techniques for reducing the offset voltage have been proposed.
For example, two Hall elements are used, the respective drive currents for both Hall elements are supplied in the orthogonal direction, and the offset voltage associated with each Hall voltage obtained in this state is differentially acted, resulting in the offset voltage. Has been proposed (see Non-Patent Document 1, for example).

However, this method is insufficient in the effect of reducing the offset voltage, and there are few examples of practical use.
Further, in Non-Patent Document 1, in addition to the method described above, the direction of the drive current supplied to one Hall element is switched alternately in the orthogonal direction, and the Hall voltage and the offset voltage are frequency separated, A method called a spinning current method is also disclosed in which an offset voltage is reduced by performing an averaging process in a subsequent circuit.

FIG. 6 is a diagram illustrating a circuit configuration of the Hall voltage detection circuit when the above-described spinning current method disclosed in Non-Patent Document 1 is executed.
In this circuit, the output of the Hall element 600 is connected to the driving current source 630 and the operational amplifier 640 that amplifies the Hall voltage by the switching circuit 620 that performs switching operation based on the two-phase clock signal supplied from the control circuit 610. It has a configuration for switching the relationship. Then, the output of the operational amplifier 640 is demodulated by the demodulation circuit 650, and further, the detection output is obtained through the integrator 660 at the subsequent stage.

In response to the switching control signal from the control circuit 610, each corresponding switch of the switch array 621 in the switching circuit 620 is switched, so that k1−K′1 in a section where the first phase clock signal is H (half cycle φ1). , K2-K′2, k3-K′3, and k4-K′4 are connected to each other. In this connection state, a drive current flows between k1 and k2, and a Hall voltage proportional to the magnitude of the magnetic field is detected between k3 and k4.
Furthermore, in the section in which the second phase clock signal is H (half period φ2 following φ1), k3-K'1, k4-K'2, k1-K'3, and k2-K'4 are respectively Connected, a drive current flows between k3 and k4, and a Hall voltage is detected between k1 and k2.

  FIG. 7 is a diagram showing temporal changes in the Hall voltage and the offset voltage in the Hall voltage detection circuit of FIG. The connection of the switch array 621 in the switching circuit 620 is switched so that the polarity of the hall voltage is inverted in each of the half periods φ1 and φ2, and after being amplified by the operational amplifier 640, the hall voltage is converted into a DC component by the demodulating circuit 650 in the next stage. Is output. Then, the DC component from the demodulation circuit 650 is input to the integrator 660, where noise is suppressed and a detection output is obtained.

As for the offset voltage, components having approximately the same polarity are output in the sections of the above-described half periods φ1 and φ2, and after passing through the demodulation circuit 650, become AC components, and the integrator 660 covers the above-described half periods φ1 and φ2. By performing the averaging process for one period, the offset component modulated into the AC component is reduced.
In the method of merely switching the drive current direction alternately in two directions as in Non-Patent Document 1 described above, an offset voltage of the same magnitude is not generated in each of the half periods φ1 and φ2, A problem remains that the difference between the output voltages V1 and V2 before demodulation corresponding to the half periods φ1 and φ2 in FIG. 7 occurs as a residual offset voltage.

This phenomenon is attributed to the fact that the bias state of the Hall element changes in each of the half periods φ1 and φ2 when the direction of the drive current is switched to the orthogonal direction.
That is, the offset voltage caused by the non-uniformity of the diffusion region of the Hall element changes in magnitude depending on the bias state of the Hall element, and therefore cannot be sufficiently reduced by the above-mentioned Non-Patent Document 1. Are known.
A technique for further reducing the offset voltage remaining in the spinning current method as described above has already been proposed.
For example, the drive current of the hall element is switched between a predetermined forward direction and a reverse direction and supplied, and the influence of the offset voltage is performed by the subsequent calculation processing for each hall voltage (with an offset voltage) corresponding to the drive current in a different direction. A removal method has been proposed (see Patent Document 1).

FIG. 8 is a diagram illustrating a circuit configuration for carrying out the method disclosed in Patent Document 1. In FIG. In the circuit of FIG. 8, the driving current is sequentially switched in the four directions of the orthogonal direction and the opposite direction by the spinning current method to perform signal processing for offset reduction.
In this circuit, the output of the Hall element 800 is connected to the driving current source 830 and the operational amplifier 840 that amplifies the Hall voltage by the switching circuit 820 that performs switching operation based on the four-phase clock signal supplied from the control circuit 810. It has a configuration for switching the relationship. The output of the operational amplifier 840 is demodulated by the demodulation circuit 850, and further, a detection output is obtained via the integrator 860 at the subsequent stage.

Each corresponding switch of the switch array 821 in the switching circuit 820 is switched by a switching control signal from the control circuit 810.
By switching the corresponding switches of the switch array 821, k1-K'1, k2-K'2, k3-K'3, k4- in the section of φ1 where the first phase clock signal is H. K′4 is connected to each other, a drive current flows between k1 and k2, and a Hall voltage that is proportional to the magnitude of the magnetic field is detected between k3 and k4.

After φ1 above, k3-K'1, k4-K'2, k1-K'3, and k2-K'4 are connected in φ2 where the second phase clock signal is H. , A drive current flows between k3 and k4, and the Hall voltage is detected between k1 and k2.
Further, after the φ2 interval, in the φ3 interval where the third phase clock signal is H, the intervals between k2-K′1, k1-K′2, k4-K′3, and k3-K′4 are respectively Connected, the drive current flows between k2 and k1, and the Hall voltage is detected between k4 and k3.
Further, after the φ3 interval, in the φ4 interval where the fourth phase clock signal is H, the interval between k4-K′1, k3-K′2, k2-K′3, and k1-K′4 Each is connected, a drive current flows between k4 and k3, and the Hall voltage is detected between k2 and k1.

FIG. 9 is a diagram showing temporal changes in the Hall voltage and the offset voltage in the Hall voltage detection circuit of FIG.
It is a figure explaining the flow of a signal of Hall voltage and offset voltage. The Hall voltage has the same polarity in the sections φ1 and φ3, and the connection of the switch array 821 in the switching circuit 820 is switched so that the polarity is inverted in the sections φ2 and φ4, and is amplified by the operational amplifier 840 and then demodulated by the demodulator circuit 850. As a result, the polarities are inverted in the sections φ2 and φ4 and output as a DC component. Then, the DC component from the demodulation circuit 850 is input to the integrator 860, where noise is suppressed and a detection output is obtained.

  As for the offset voltage, the components having the same polarity are output in the sections φ1, φ2, φ3, and φ4 in the above-described sections φ1, φ2, φ3, and φ4. As shown in FIG. 9, the offset caused by the change in is an output inverted between the intervals φ1 and φ3, and an output inverted between the intervals φ2 and φ4.

With respect to such an offset voltage, the polarity is inverted by the demodulation circuit 850 in the sections φ2 and φ4, and the integrator 860 performs the averaging process through the sections φ1 to φ4. As a result, the offset voltage can be finally reduced to almost zero.
As described above, the residual offset that remains in the two-direction spinning current method in the technique described in Non-Patent Document 1 is orthogonal to the case where the drive current direction is passed in the opposite direction as in the technique described in Patent Document 1. It is possible to cancel the residual offset by sequentially adding and adjusting in the direction to be performed.

However, even in the technique described in Patent Document 1 in which a good offset reduction effect can be obtained, the number of switch elements necessary for switching the direction of the drive current is increased, and control for generating a four-phase control clock is performed. Since a circuit is required, it is inevitable that the configuration becomes complicated as a whole.
Further, the wiring for supplying the clock to the switching circuit 820 becomes complicated, and the Hall element easily picks up electromagnetic noise. As a result, the detection accuracy deteriorates due to this noise.

Furthermore, the time required for the above-mentioned averaging increases in proportion to the number of times the drive current is switched, and various problems such as a decrease in the detection speed of the magnetic field signal occur.
As a technique that is consistent with the technique described in Patent Document 1 as described above, a method of removing the influence of the residual offset voltage as a result by continuously rotating the direction in which the drive current is supplied has been proposed. (See Patent Document 2).

Furthermore, there has been proposed a method of removing the influence of the residual offset voltage as a result by switching and supplying the direction of the drive current so as to swing by 45 degrees (see Patent Document 3).
In any of the above prior arts (Patent Document 2 and Patent Document 3), by adopting the spinning current method and sequentially switching the direction in which the drive current is supplied, excellent characteristics are obtained with respect to the effect of reducing the residual offset. It is done.

However, as in the above-mentioned Patent Document 1, in either of the Patent Document 2 and Patent Document 3, an increase in the number of switch elements in the switching circuit for sequentially switching the direction of the drive current, and the multilayer As a result of an increase in the scale of a control circuit for generating the switch control signal, the overall configuration cannot be avoided.
Further, the averaging process for obtaining the detection result requires a lot of time, resulting in a demerit such as a decrease in responsiveness.

  On the other hand, two Hall elements are used, the other Hall element is rotated on the plane projection with respect to the arrangement on the plane projection of one Hall element, and the drive current is orthogonal to each Hall element. A method has been proposed in which the switch configuration is simplified and the effect of sufficiently reducing the offset voltage is obtained by sequentially switching and supplying in such a direction (see Patent Document 4).

FIG. 10 is a diagram illustrating a circuit configuration for performing the method disclosed in Patent Document 4. In FIG. In this method, two Hall elements 1001 and 1002 are arranged in parallel, and a driving current is alternately passed through the two Hall elements 1001 and 1002 in two orthogonal directions by a spinning current method.
This circuit includes a driving current source 1030 and an operational amplifier 1040 that amplifies a Hall voltage by a switching circuit 1020 that performs switching operation based on a two-phase clock signal supplied from the control circuit 1010. The connection relationship is switched. The output of the operational amplifier 1040 is demodulated by the demodulation circuit 1050, and further, the detection output is obtained via the integrator 1060 at the subsequent stage.

  In this case, the two Hall elements 1001 and 1002 are formed at positions adjacent to each other on the CMOS chip, and the other Hall element 1002 is arranged on the plane projection with respect to the arrangement on the plane projection of the one Hall element 1001. The terminals are rotated by 0 to 180 degrees (45 degrees in the example of FIG. 10), and the corresponding terminals of both Hall elements 1001 and 1002 are connected to each other.

Each corresponding switch of the switch array 1021 in the switching circuit 1020 is switched by a switching control signal from the control circuit 1010.
By switching the corresponding switches of the switch array 1021, k1-K'1, k2-K'2, k3-K'3, in the section where the first phase clock signal is H (half cycle φ1), k4-K'4 are connected to each other. In this connection state, a drive current flows between k1 and k2, and a Hall voltage proportional to the magnitude of the magnetic field is detected between k3 and k4.
Furthermore, in the section in which the second phase clock signal is H (half period φ2 following φ1), k3-K'1, k4-K'2, k1-K'3, and k2-K'4 are respectively Connected, a drive current flows between k3 and k4, and a Hall voltage is detected between k1 and k2.

  In the configuration of FIG. 10, as in the technique described in Non-Patent Document 1 described above with reference to FIG. 6, the drive current is switched in two directions for both Hall elements, and the switch is also driven in two phases. It is the same simple structure switched by. Further, two Hall elements are arranged in parallel at adjacent positions on the CMOS chip, and the other Hall element 1002 is rotated on the plane projection with respect to the arrangement on the plane projection of one Hall element 1001. By disposing, the offset reduction effect corresponding to the case where the drive current direction is switched to four directions and supplied can be obtained. As described above, the technique disclosed in Patent Document 4 has an advantage that an excellent offset reduction effect can be obtained without complicating the configuration.

  On the other hand, by forming a circular magnetic body on the integrated circuit and arranging two or more Hall elements near the end of the magnetic body, a magnetic field coming from a direction parallel to the magnetic sensitive surface of the Hall element. A technique has been proposed in which the magnetic field can be detected by bending the direction of the magnetic material so that a magnetic flux is incident perpendicularly to the magnetosensitive surface (Patent Document 5).

FIG. 11 is a diagram for explaining a technique of performing magnetic detection with a Hall element using a magnetic converging plate as in the technique described in Patent Document 5.
FIG. 11A is a top view showing the arrangement of the magnetic focusing plate and the Hall element, and FIG. 11B is a cross-sectional view showing the arrangement of the magnetic focusing plate and the Hall element.
11A and 11B, paired Hall elements 1101 and 1102 are formed on a CMOS chip 1100 at positions separated by several 10 to several 100 μm, and electrolytic plating or an adhesive is used thereon. The magnetic converging plate 1110 having a diameter of several tens to several hundreds μm and a thickness of several μm to several tens of μm is formed by a technique such as pasting.

  The positional relationship between the Hall elements 1101 and 1102 and the magnetic converging plate 1110 is such that one Hall element 1101 is arranged near the end of the magnetic converging plate 1110, and the other Hall element 1102 is positioned relative to the position of the one Hall element 1101. The magnetic converging plate 1110 is arranged at a symmetrical position from the center. As can be easily understood with reference to FIG. 11B, the CMOS chip 1100 is formed in the same semiconductor layer 1003 with both Hall elements 1101 and 1102 separated from each other, and a protective layer 1004 is provided thereon. Furthermore, a magnetic converging plate 1110 is disposed thereon.

The magnetic sensitive surfaces of these Hall elements 1101 and 1102 are perpendicular to the CMOS chip 1100. On the other hand, the magnetic convergence plate 1110 is made of a soft magnetic material such as permalloy and has a high magnetic permeability.
Therefore, when a magnetic field in the horizontal direction is input to the main surface of the chip 1100, the surrounding magnetic field is drawn near the end of the magnetic focusing plate 1110, and the main surface of the chip 1100, and thus both Hall elements 1101 and 1102. The magnetic field is converted into a magnetic field in the vertical direction.

In this case, the magnetic fields input to the magnetosensitive surfaces of both Hall elements 1101 and 1102 are vertically upward and the other is vertically downward, and the Hall voltages generated in both Hall elements 1101 and 1102 have opposite polarities. It becomes.
Then, by taking the difference in Hall voltage between the paired Hall elements 1101 and 1102 in the subsequent signal processing, it becomes possible to detect the magnitude of the horizontal magnetic field as described above.

JP 2010-54301 A US Pat. No. 6,064,202 US Pat. No. 6,768,301 JP-A-6-11556 US Pat. No. 6,545,462

R S Popovic Hall Effect Devices p284-p285 (ISBN-10: 0750308559) Inst of Physics Pub Inc

However, in the technique described in the above-mentioned Patent Document 4, the magnetic field parallel to the main surface of the chip on which the Hall element is formed as in the technique described in Patent Document 5, and thus the magnetic sensitive surface of the Hall element ( This method cannot be applied to detect a horizontal magnetic field by converting it into a vertical magnetic field using a magnetic converging plate.
FIG. 12 is a diagram for explaining a phenomenon in the case where the magnetic focusing plate described in Patent Document 5 is applied to the mutually connected Hall elements described in Patent Document 4; 12 (a) shows a state in a section (half cycle φ1) in which the first-phase clock signal described above is H with reference to FIG. 10 in the technique described in Patent Document 4, and FIG. FIG. 10 shows a state in a section (half cycle φ2) in which the second phase clock signal described above is H.

  In the section (half cycle φ1) in which the first phase clock signal is H in FIG. 12A, the Hall voltage generated in one Hall element 1201 is the drive current when this Hall element 1201 is an N-type semiconductor. When a magnetic field (magnetic flux B) is applied as shown, Lorentz force is generated in the direction from terminal 1201-4 to terminal 1201-2 in accordance with Fleming's left-hand rule, and between terminals 1201-4 and 1201-2. The Hall voltage generated at is a positive voltage.

  On the other hand, since the Hall voltage generated in the Hall element 1202 has a magnetic field (magnetic flux B) in a direction opposite to that of the Hall element 1201, a Lorentz force is generated in the direction from the terminal 1201-2 to the terminal 1201-4. The voltage generated between 1201-4 and the terminal 1201-2 is a negative voltage. Here, the two Hall elements 1201 and 1202 are electrically connected to the corresponding terminals (1201-1 and 1202-1, 1201-2 and 1202-2, 1201-3 and 1202-3, 1201-4 and 1202-4). It is the composition connected to. Accordingly, the Hall voltages between the terminals 1201-4 and 1201-2 of each Hall element have positive and negative polarities and cancel each other.

Similarly, in the section where the second phase clock signal is H (half cycle φ2 following half cycle φ1) as shown in FIG. 12B, the Hall voltages generated in the Hall elements 1201 and 1202 are mutually equal. It becomes the opposite polarity and cancels out.
As described with reference to FIGS. 12 (a) and 12 (b), the magnetic converging plate described in Patent Document 5 is applied to the mutually connected pair of Hall elements described in Patent Document 4. In such a case, the offset voltage is reduced, but the Hall voltage that is the original detection target is canceled out, which makes it impossible to detect.

  The present invention has been made in view of the above-described situation. The magnetic field parallel to the magnetic sensing surface of the Hall element (the magnetic field in the horizontal direction) is increased, and the number of switch elements in the switching circuit is increased and the control signal generation circuit is complicated. It is an object of the present invention to realize a Hall voltage detection device that can detect without causing a change and has a good residual offset reduction effect.

In order to achieve the above object, the following technologies are proposed here.
(1) A first Hall element having both electrode pairs, one electrode pair of two pairs of electrodes and another electrode pair facing each other in a direction crossing the facing direction of the one electrode pair, and the first The second Hall element paired with the Hall element and the direction change so that the magnetic flux parallel to each of the magnetic sensitive surfaces of the first Hall element and the second Hall element paired with the Hall element is linked to the magnetic sensitive surface. A magnetic flux direction changing element, a switching circuit unit that alternately switches the one electrode pair and the other electrode pair of each Hall element as a drive current supply electrode pair and a Hall voltage detection electrode pair over time, and the pair A Hall voltage detector comprising: a detection circuit unit that processes and outputs each Hall voltage generated by each Hall element so as to cancel out an offset voltage included therein,
The arrangement of the two Hall electrode pairs on the planar projection of the pair of first Hall elements in the pair of the two Hall electrode pairs is between the hall elements of the pair. A Hall voltage detection device, wherein the Hall voltage detection device is arranged in a mirror image relationship so as to be in a symmetrical position with respect to a passing virtual line.

  In the Hall voltage detector of (1) above, the magnetic flux direction change element causes the first Hall element and the second Hall element to form a pair by the incident magnetic flux and the drive current so as to be linked to the magnetic sensing surface. When the Hall voltage is processed so as to cancel the offset voltage included in each, the two Hall electrode pairs of the second Hall element with respect to the planar projection arrangement of the both electrode pairs in the paired first Hall element When the offset voltage is canceled by the processing, the arrangement on the plane projection is arranged in a mirror image relationship so as to be symmetric with respect to the virtual line passing between the pair of Hall elements. Are output without being canceled out.

(2) The magnetic flux direction changing element is a magnetic converging plate made of a magnetic material arranged so that each corresponding end of the magnetic flux direction changing element is passed to each magnetosensitive surface of the pair of Hall elements. (1) Hall voltage detector.
In the Hall voltage detection device of (2) above, in particular, in the Hall voltage detection device of (1), the magnetic flux direction changing element is different from each magnetosensitive surface of the Hall element in which each corresponding end portion thereof forms the pair. Since the magnetic concentrating plate is made of a magnetic material arranged so as to be passed, magnetic flux parallel to each of the magnetic sensitive surfaces of the first Hall element and the second Hall element of the pair is linked to the magnetic sensitive surface. The configuration for changing the direction is simple.

(3) The Hall voltage detecting device according to (1) or (2), wherein the pair of Hall elements is a plurality of pairs of Hall elements.
In the Hall voltage detection device according to (3) above, in particular, in the Hall voltage detection device according to (1) or (2), since the paired Hall elements are a plurality of pairs of Hall elements, the output of each pair of Hall elements is the same. Based on this, it is possible to obtain a highly reliable detection output.

  Magnetic field parallel to the magnetic sensing surface of the Hall element (horizontal magnetic field) can be detected without increasing the number of switch elements in the switching circuit or complicating the control signal generation circuit, and reducing the residual offset Therefore, it is possible to realize a Hall voltage detection device with good.

It is explanatory drawing for demonstrating the structure and effect | action of a Hall element part in the Hall voltage detection apparatus as embodiment of this invention. It is a figure showing the Hall voltage detection apparatus as embodiment of this invention which comprised the Hall element part as shown in FIG. It is a figure showing the time-dependent change of the Hall voltage of the 1st Hall element and the 2nd Hall element in FIG. 2, and an offset voltage. It is a figure showing the reduction effect of the offset voltage in embodiment. FIG. 5 is a diagram showing a Hall voltage detection device as another embodiment of the present invention when an arrangement different from the arrangement described above with reference to FIGS. 1 to 4 is adopted as the arrangement of the Hall elements. It is a figure showing the structure of the conventional Hall voltage detection circuit which performs a spinning current method. It is a figure showing the time-dependent change of a Hall voltage and an offset voltage in the Hall voltage detection circuit of FIG. It is a figure showing the circuit structure for implementing the conventional Hall voltage detection method. FIG. 9 is a diagram illustrating changes over time in the Hall voltage and the offset voltage in the Hall voltage detection circuit of FIG. 8. It is a figure showing the other circuit structure for implementing the conventional Hall voltage detection method. It is a figure for demonstrating the prior art which performs a magnetic detection with a Hall element using a magnetic converging plate. 11 is a diagram for explaining a phenomenon in the case where the magnetic flux concentrating plate of FIG. 11 is applied to the mutually connected Hall elements of FIG.

Hereinafter, the present invention will be clarified by describing embodiments of the present invention in detail with reference to the drawings.
FIG. 1 is an explanatory diagram for explaining the configuration and operation of the Hall element unit 1 in the Hall voltage detection device according to the embodiment of the present invention.
FIG. 1A shows a section (half cycle φ1) in which the first phase clock signal 100 and the second hall element 200 forming a pair of the hall element section 1 are H, which will be described later. Represents a state. FIG. 1B shows a state in a section (half cycle φ2) in which the second phase clock signal described later of the first Hall element 100 and the second Hall element 200 forming a pair is H. .

FIG. 1C is a top view showing the arrangement of the first Hall element 100 and the second Hall element 200 that form a pair with the magnetic flux concentrating plate. FIG. 1D is a cross-sectional view showing the arrangement of the first Hall element 100 and the second Hall element 200 that form a pair with the magnetic flux concentrating plate.
With reference to FIG. 1C and FIG. 1D, the structure of the Hall element portion 1 will be described.

  The first Hall element 100 and the second Hall element 200 forming a pair are formed as N-type Hall elements on the same CMOS chip 10 with a distance of several tens to several hundreds μm apart. The magnetic converging plate 20 having a diameter of several tens to several hundreds μm and a thickness of several μm to several tens of μm is applied to the first Hall element 100 and the second Hall element 200 by a technique such as electrolytic plating or bonding using an adhesive. Is formed. More specifically, as easily understood with reference to FIG. 1 (d), the first Hall element 100 and the second Hall element 200 overlap with a substantially majority region of the magnetic sensitive surface which is the main surface of each. In this manner, the magnetic flux concentrating plate 20 is formed between the first Hall element 100 and the second Hall element 200. That is, the magnetic flux concentrating plate 20 is arranged such that each corresponding end portion of the magnetic converging plate 20 is passed to the magnetic sensitive surfaces of the first Hall element 100 and the second Hall element 200 that form the pair. Yes.

  In other words, the first Hall element 100 is disposed in the vicinity of the end of the magnetic focusing plate 20, and the second Hall element 200 is symmetrical from the center of the magnetic focusing plate 20 with respect to the position of the first Hall element 100. It is arranged at the position. As can be easily understood with reference to FIG. 1D, the CMOS chip 10 is formed by separating the first Hall element 100 and the second Hall element 200 in the same semiconductor layer 11 and separating them. A protective layer 12 is provided thereon, and a magnetic flux concentrating plate 20 is further disposed thereon.

The magnetic sensitive surfaces of the first Hall element 100 and the second Hall element 200 are parallel to the main surface of the CMOS chip 10. On the other hand, the magnetic flux concentrating plate 20 is made of a soft magnetic material such as permalloy, which is a magnetic material, and has a high magnetic permeability. That is, the magnetic flux concentrating plate 20 is a magnetic flux direction changing element that changes the direction of the magnetic flux parallel to the magnetic sensitive surfaces of the Hall elements 100 and 200 forming a pair so as to be linked to the magnetic sensitive surfaces.
For this reason, when a magnetic field in a direction parallel to the main surface of the CMOS chip 10, that is, in the horizontal direction in FIG. 1D is input, the surrounding magnetic field is drawn in the vicinity of the end of the magnetic convergence plate 20. The main surface of the chip 10, and thus each magnetic sensitive surface of the first Hall element 100 and the second Hall element 200, is converted into a magnetic field in the vertical direction.

In this case, one of the magnetic fields input to the magnetic sensitive surfaces of the first hall element 100 and the second hall element 200 is vertically upward and the other is vertically downward. The Hall voltages generated in the second Hall element 200 have opposite polarities.
Then, by adding the Hall voltage between the first Hall element 100 and the second Hall element 200 (addition considering the polarity) in the subsequent signal processing, as a result, the above-described horizontal magnetic field is obtained. Can be detected.

Next, with reference to FIG. 1A and FIG. 1B, regarding the configuration, arrangement, and operation of the first Hall element 100 and the second Hall element 200 in the Hall element portion 1 in the planar projection. explain.
The first Hall element 100 includes four electrodes 101, 102, 103, and 104. Of these electrodes, one electrode pair (diagonal electrodes 101 and 103) and the other electrode pair (diagonal electrodes 102 and 104) are driven in pairs in sequential time intervals, as will be described later. The current supply end and the pair of Hall voltage detection ends are used alternately.

As described above, the second Hall element 200 includes four electrodes 201, 202, 203, and 204. Among these electrodes, one electrode pair (diagonal electrodes 201 and 203) and the other electrode pair (diagonal electrodes 202 and 204) are paired in sequential time intervals, as will be described later. Are used alternately as a drive current supply terminal and a pair of Hall voltage detection terminals.
The first Hall element 100 and the second Hall element 200 are arranged in a mirror image relation (mirror symmetry) so that the mutual arrangement in the planar projection of the first Hall element 100 and the second Hall element 200 is symmetric with respect to the virtual line VL between the opposing edges. Has been.

  In the mirror-symmetric arrangement as described above, the first Hall element 100 and the second Hall element 200 have electrodes 101 and 103 positioned diagonally to the first Hall element 100 so that the second Hall element 200 Diagonal electrodes 201 and 203 are connected to the corresponding ones in the order described above, and electrodes 102 and 104 located diagonally to the first Hall element 100 are diagonally connected to the second Hall element 200. The electrodes 202 and 204 are connected correspondingly in the order described above.

The 1st Hall element 100 and the 2nd Hall element 200 take the composition which uses a spinning current method to two directions in the above arrangement and connection relation.
That is, in the section in which the first phase clock signal is H (half period φ1) and the section in which the second phase clock signal is H (half period φ2 following the above φ1), the first Hall element 100 and the second A driving current is supplied to the second Hall element 200 in a direction rotated by 90 degrees.

As shown in FIG. 1A, in the time interval φ1, the Hall voltage of the first Hall element 100 is supplied with a drive current as shown by an arrow in the figure and a magnetic field is applied in the direction shown in the figure. According to Fleming's left-hand rule, Lorentz force is generated in the direction from the electrode 104 to the electrode 102, and the Hall voltage generated between the electrode 104 and the electrode 102 becomes a positive voltage.
In addition, the Hall voltage in the second Hall element 200 also generates a Lorentz force in the direction from the electrode 204 to the electrode 202, and the Hall voltage generated between the electrode 204 and the electrode 202 becomes a positive voltage.

Accordingly, in the state of the time interval φ1 shown in FIG. 1A, the Hall voltage has the same polarity between the first Hall element 100 and the Hall element 2.
On the other hand, in the state of the time interval φ2 shown in FIG. 1B, similarly, the Hall voltage has the same polarity between the first Hall element 100 and the second Hall element 200, and the first Hall element 100 has the same polarity. Even if the corresponding electrodes of the second Hall element 200 are connected as described above, there is no problem that the Hall voltage is canceled as in the conventional example described above.

Furthermore, even if the magnetic fields input to the first Hall element 100 and the second Hall element 200 are in opposite directions, the first Hall element 100 and the second Hall element 200 are mirror-symmetric as described above. Due to the arrangement, the Hall voltage having the same polarity is obtained in both the time interval φ1 and the time interval φ2.
Further, in the spinning current method applied to the embodiment of FIG. 1, the driving current supply direction and the Hall voltage detection direction are mutually different for each of the first Hall element 100 and the second Hall element 200. A mode in which switching is performed between two orthogonal directions is applied. That is, in the embodiment of FIG. 1, the directions of the drive currents flowing through the first Hall element 100 and the second Hall element 200 are four directions in 90 degree increments including the orthogonal direction and the opposite direction. It has become.
For this reason, the characteristic when the direction of the drive current is four directions can be obtained without complicating the configuration of the changeover switch.

FIG. 2 is a diagram showing a Hall voltage detector as an embodiment of the present invention in which the Hall element portion is configured as shown in FIG.
In this embodiment, the output of the first Hall element 100 and the second Hall element 200 is driven by a switching circuit 220 that performs a switching operation based on a two-phase clock signal supplied from the control circuit 210. 230 and the operational amplifier 240 for amplifying the Hall voltage are switched. Then, the output of the operational amplifier 240 is demodulated by the demodulation circuit 250, and further, a detection output is obtained via the integrator 260 at the subsequent stage.

  Then, the control circuit 210, the drive current source 230, the operational amplifier 240, and the demodulation circuit 250 make one electrode pair of the Hall element and the other electrode pair as a drive current supply electrode pair and a Hall voltage detection electrode pair over time. The detection circuit unit is configured to alternately switch and use each Hall voltage generated by the paired Hall elements so as to cancel out the offset voltage included in each Hall voltage.

The mutual arrangement and connection relationship of the first Hall element 100 and the second Hall element 200 are as described above with reference to FIGS. 1 (a) and 1 (b).
Then, each corresponding switch of the switch array 221 in the switching circuit 220 is switched by a switching control signal from the control circuit 210.
By switching the corresponding switches of the switch array 221, the k1-K'1, k2-K'2, k3-K'3, k1-K'1, k2-K'3, in the section where the first phase clock signal is H (half cycle φ1), k4-K'4 are connected to each other. In this connection state, a drive current flows between k1 and k2, and a Hall voltage proportional to the magnitude of the magnetic field is detected between k3 and k4.

Furthermore, in the section in which the second phase clock signal is H (half period φ2 following φ1), k3-K'1, k4-K'2, k1-K'3, and k2-K'4 are respectively Connected, a drive current flows between k3 and k4, and a Hall voltage is detected between k1 and k2.
FIG. 3 is a diagram illustrating temporal changes in the Hall voltage and the offset voltage of the first Hall element 100 and the second Hall element 200 in FIG. Since the mutual arrangement and connection relationship of the first Hall element 100 and the second Hall element 200 are as described above with reference to FIGS. 1A and 1B, the Hall voltage obtained is An average value of the first Hall element 100 and the second Hall element 200 is output and input to the operational amplifier 240.

Since the wiring is connected so that the polarity of the hall voltage is inverted in the time intervals φ1 and φ2, the Hall voltage is amplified by the operational amplifier 240, and then output as a DC component by the demodulation circuit 250, and further integrated for noise suppression. Is input to the device 260.
On the other hand, with respect to the offset voltage, components having approximately the same polarity are output in the time intervals φ1 and φ2, and after passing through the demodulation circuit 250, become AC components, and are averaged over the time interval φ1 to φ2 by the integrator 260. The offset component modulated into the AC component is reduced.
When the first Hall element 100 and the second Hall element 200 are individually viewed, an offset component remains, but when viewed from the average of the two Hall elements 100 and 200, as described above, the offset is Reduced to almost zero.

As described above with reference to FIGS. 1, 2, and 3, the switching circuit 220 includes one electrode pair and another electrode pair of each Hall element for driving current supply electrode pairs. Further, a switching circuit unit that alternately switches over time as a pair of Hall voltage detection electrodes is formed.
Further, the corresponding functions of the switching circuit 220, the demodulating circuit 250, and the integrator 260 cancel each offset voltage included in each Hall voltage of each pair of Hall elements by their cooperation. A detection circuit unit for processing and outputting is formed.

FIG. 4 is a diagram showing the effect of reducing the offset voltage in the embodiment of the present invention in comparison with the prior art (Non-Patent Document 1) already described with reference to FIG.
FIG. 4A shows the detection result of the prior art offset voltage already described with reference to FIG. 6, and FIG. 4B shows the detection result of the offset voltage in the embodiment of the present invention.
The offset voltages in FIGS. 4A and 4B are examples in the case where the following Hall element portion is applied. That is, an N-type, 30-um square Si Hall element is formed on a CMOS chip at a position 200 μm away from each other, as shown in FIGS. 11 and 1C. This is a detection result in a state in which a magnetic convergence plate having a diameter of 200 μm is formed by electrolytic plating.

FIG. 4A shows the result of using the spinning current method for two Hall directions orthogonal to each other as shown in FIG. 1 for one Hall element. The average of 10 samples is 84.9 μV and the standard deviation is shown. In this case, an offset of 15.5 μV occurs.
FIG. 4B shows a result when the spinning current method is used in two orthogonal directions with respect to the Hall element pairs in the arrangement and connection relation described above with reference to FIG. In this case, the average of 10 samples is −0.9 μV and the standard deviation is 10.7 μV, and it can be confirmed that the effect of reducing the offset voltage is remarkable in the embodiment of the present invention.

Although one embodiment of the present invention has been described in detail with reference to FIGS. 1 to 4, the technical idea of the present invention is not limited to such an embodiment.
That is, in the embodiment of FIGS. 1 to 4, the magnetic converging plate is applied as described above, and the mutual arrangement of the pair of Hall elements in the planar projection is related to the imaginary line VL between the opposing edges. One requirement is to arrange them in mirror image relations (mirror symmetry) so that they are in symmetrical positions. And when the corresponding electrodes of each Hall element are connected (short-circuited) and a magnetic field in the opposite direction is input to each Hall element, the requirement that the mirror-symmetric arrangement is adopted is also satisfied. Therefore, the Hall voltage can be detected. Therefore, as long as the above requirements are equally satisfied, it is possible to adopt a configuration in which the number of Hall elements is four or eight. In this case, a highly reliable detection output can be obtained based on the outputs of a plurality of pairs of Hall elements.

  Furthermore, the Hall elements are arranged and connected so as to exhibit a Hall voltage detection characteristic equivalent to that when they are arranged in an effective mirror image relationship (mirror symmetry) with respect to the drive current supply direction and the Hall voltage detection direction. Just do it. For this reason, arrangements other than those already described with reference to FIGS. 1 to 4 can be adopted.

FIG. 5 is a diagram showing a Hall voltage detector as another embodiment of the present invention in which the Hall element is arranged differently from the arrangement described with reference to FIGS. 1 to 4. is there.
In the embodiment of FIG. 5, with respect to the arrangement of the Hall elements as described above with reference to FIGS. 1 to 4, the arrangement is such that one Hall element is rotated by an angle such as 45 degrees or 90 degrees. .
In FIG. 5, the corresponding parts to FIG. 2 described above are shown with the same reference numerals.

  In the Hall voltage detection device in the embodiment of FIG. 5, the switching of the outputs of the first Hall element 100 and the second Hall element 200 a is performed based on the two-phase clock signal supplied from the control circuit 210. The circuit 220 is configured to switch the connection relationship between the drive current source 230 and the operational amplifier 240 that amplifies the Hall voltage. Then, the output of the operational amplifier 240 is demodulated by the demodulation circuit 250, and further, a detection output is obtained via the integrator 260 at the subsequent stage.

  In the embodiment of FIG. 5, the arrangement relationship of the second Hall element 200a with respect to the first Hall element 100 is particularly described in the above configuration with reference to FIGS. 1 (a) and 1 (b). The second Hall element 200 is different from the arrangement of the second Hall element 200 in that the arrangement is rotated by an angle of more than 0 degree and 180 degrees or less, for example, 45 degrees or 90 degrees. When the rotation angle is 0 degree, the arrangement is the same as described above with reference to FIGS.

100, 200, 200a, 600, 800, 1001, 1002 ... Hall elements 210, 610, 810, 1010 ........... Control circuit 220, 620, 820, 1020 ......... Switching circuit 230, 630, 830, 1030 ................................................................................. Drive current source 240, 640, 840, 1040 ............ …………………… Operational amplifiers 250, 650, 850, 1050 …………………………………… Demodulator circuits 260, 660, 860, 1060 ……………… ……………………… Integrator

Claims (3)

A first Hall element having both electrode pairs of one electrode pair of the two pairs of electrodes and another electrode pair facing each other in a direction crossing the facing direction of the one electrode pair; A magnetic flux direction for changing the direction of a magnetic flux parallel to each of the magnetic sensitive surfaces of the paired first Hall element and the second Hall element so as to interlink with the magnetic sensitive surface. A switching element, a switching circuit unit that alternately switches the one electrode pair and the other electrode pair of each Hall element as a drive current supply electrode pair and a Hall voltage detection electrode pair over time, and each of the pairs A detection circuit unit that processes and outputs each Hall voltage by the Hall element so as to cancel out the offset voltage included therein, and a Hall voltage detection device comprising:
The arrangement of the two Hall electrode pairs on the planar projection of the pair of first Hall elements in the pair of the two Hall electrode pairs is between the hall elements of the pair. A Hall voltage detection device, wherein the Hall voltage detection device is arranged in a mirror image relationship so as to be in a symmetrical position with respect to a passing virtual line.   The magnetic flux direction changing element is a magnetic converging plate made of a magnetic material arranged such that each corresponding end portion of the magnetic flux direction changing element is passed to each magnetosensitive surface of the pair of Hall elements. Item 2. The Hall voltage detection device according to Item 1.   3. The Hall voltage detection device according to claim 1, wherein the pair of Hall elements is a plurality of pairs of Hall elements.

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