JP5487880B2 - Regulator, integrated circuit device and electronic device - Google Patents

Description

  The present invention relates to a regulator, an integrated circuit device, an electronic device, and the like.

  Conventionally, a regulator (constant voltage generation circuit) that adjusts the voltage of an external power supply voltage and supplies the adjusted voltage to an internal circuit is known. As a conventional technique of such a regulator, techniques disclosed in Patent Documents 1 and 2 are known.

  For example, in the regulator disclosed in Patent Document 1, the reference voltage generated by the reference voltage generation circuit is input to the inverting input terminal of the amplifier circuit (operational amplifier). Further, first and second resistors are provided between the output node of the regulator and VSS, and a divided voltage by these first and second resistors is input to the non-inverting input terminal of the amplifier circuit. A drive transistor is provided between the input node of the external power supply voltage and the output node of the regulator, and the constant voltage is output from the output node of the regulator by controlling the gate electrode of the drive transistor by the amplifier circuit.

  However, this regulator has a problem in that the power consumption increases when the circuit is designed for stable operation, and the circuit operation stability deteriorates when the circuit is designed for low power consumption. .

JP 2001-92544 A JP-A-60-252926

  According to some embodiments of the present invention, it is possible to provide a regulator, an integrated circuit device, an electronic device, and the like that can achieve both stable operation of the circuit and low power consumption.

  One embodiment of the present invention is provided in series between a differential amplifier circuit having an offset voltage between a non-inverting input terminal and an inverting input terminal, and an output node of the amplifier circuit and a first power supply node. And a phase compensation capacitor having one end connected to a connection node between the first resistor and the second resistor, the first resistor and the second resistor. The connection node signal is fed back to the non-inverting input terminal of the amplifier circuit, and the output node signal of the amplifier circuit is fed back to the inverting input terminal of the amplifier circuit.

  According to one aspect of the present invention, a constant voltage determined by the offset voltage between the non-inverting input terminal and the inverting input terminal of the amplifier circuit and the resistance ratio of the first and second resistors is generated. In one aspect of the present invention, a phase compensation capacitor is provided at the connection node of the first and second resistors, and a signal at the connection node is fed back to the non-inverting input terminal of the amplifier circuit. The signal at the output node is fed back to the inverting input terminal. This makes it possible to realize a regulator that can generate a constant voltage with stable circuit operation.

  In one embodiment of the present invention, the amplifier circuit is connected to a differential section having a first differential transistor, a second differential transistor, and a current mirror circuit, and an output node of the differential section. And an output unit.

  In this way, the signal at the connection node of the first and second resistors is fed back to the non-inverting input terminal of the differential unit having the first and second differential transistors and the current mirror circuit, and the differential unit The voltage adjustment can be performed by feeding back the signal at the output node of the amplifier circuit to the inverting input terminal of the amplifier circuit.

  In one embodiment of the present invention, the conductivity of the gate electrode of the first differential transistor is different from the conductivity of the gate electrode of the second differential transistor, so that the offset voltage is set. Good.

  In this way, the offset voltage can be set by the work function difference voltage obtained by making the conductivity of the gate electrodes of the first and second differential transistors different.

  In one embodiment of the present invention, the W / L ratio of the first differential transistor is different from the W / L ratio of the second differential transistor, or the first current constituting the current mirror circuit is made different. The offset voltage may be set by making the W / L ratio of the mirror transistor different from the W / L ratio of the second current mirror transistor constituting the current mirror circuit.

  In this way, the offset voltage can be set by changing the W / L ratio of the first and second differential transistors or by changing the W / L ratio of the first and second current mirror transistors. become able to.

  In one embodiment of the present invention, the differential section includes a first current source, and the first current source includes a first current source resistor whose one end is connected to the first power supply node. A depletion type first current source transistor having a source connected to the other end of the first current source resistor and a gate connected to the first power supply node. The threshold voltage of the transistor may have a negative temperature characteristic, and the resistance value of the first current source resistor may have a positive temperature characteristic.

  In this way, a circuit for generating a reference voltage for generating a tail current of the first current source can be eliminated, and the number of current paths can be reduced. Further, the temperature dependency and variation of the tail current flowing through the first current source can be reduced.

  In the aspect of the invention, the first current source resistor may be an N well resistor formed by an N well.

  In this way, the resistance value of the first current source resistor can have a positive temperature characteristic.

  In one embodiment of the present invention, the first resistor and the second resistor are poly resistors formed by a polysilicon layer, and the first current source resistor forming region is the N well resistor. On top of this, the poly resistors which are the first resistor or the second resistor may be laid out.

  In this way, the layout efficiency can be improved because the first current source resistor and the first resistor or the second resistor can be laid out using one region.

  In the aspect of the invention, the output unit includes a drive transistor controlled by an output node of the differential unit, and a second current source provided in series with the drive transistor, and the second current source Has one end connected to the first power source node, the other end of the second current source resistor connected to the source, and the gate connected to the first power source node. A depletion-type second current source transistor, the threshold voltage of the second current source transistor has a negative temperature characteristic, and the resistance value of the second current source resistor is positive. It may have the following temperature characteristics.

  In this way, a circuit for generating a reference voltage for generating the tail current of the second current source can be eliminated, and the number of current paths can be reduced. In addition, the temperature dependence and variation of the tail current flowing through the second current source can be reduced.

  In the aspect of the invention, the second current source resistor may be an N well resistor formed by an N well.

  In this way, the resistance value of the second current source resistor can have a positive temperature characteristic.

  In the aspect of the invention, the first resistor and the second resistor are poly resistors formed by a polysilicon layer, and the second current source resistor forming region which is the N well resistor. On top of this, the poly resistors which are the first resistor or the second resistor may be laid out.

  In this case, the layout efficiency can be improved because the second current source resistor and the first resistor or the second resistor can be laid out using one region.

  In one embodiment of the present invention, when the resistance value of the first resistor is R1 and the resistance value of the second resistor is R2, the resistance ratio R2 / R1 cancels the temperature characteristic of the offset voltage. It may have temperature characteristics.

  In this way, the temperature dependence of the constant voltage generated by the regulator can be reduced.

  Another aspect of the invention relates to an integrated circuit device including any of the regulators described above.

  In another aspect of the present invention, a constant voltage generated by the regulator is supplied as a power supply voltage, and a constant voltage generated by the regulator is supplied as a power supply voltage to reset the logic circuit. A power-on reset circuit that outputs a signal may be included.

  In this way, it is possible to reduce the power consumption of the integrated circuit device by reducing the current path in the regulator.

  In another aspect of the present invention, the power-on reset circuit is configured such that a voltage from a voltage dividing tap set to the first resistor or the second resistor is input to an inverting input terminal, and the first power supply A node may be connected to a non-inverting input terminal, and a comparator having an offset voltage between the non-inverting input terminal and the inverting input terminal may be included.

  This makes it possible to set the determination voltage level of the power-on reset circuit and generate the reset signal by effectively using the first and second resistors of the regulator.

  In another aspect of the present invention, the differential unit included in the comparator includes a third current source, and the third current source includes a third current whose one end is connected to the first power supply node. And a depletion-type third current source transistor having a source resistor and a source connected to the other end of the third current source resistor and a gate connected to the first power supply node. The threshold voltage of the current source transistor may have a negative temperature characteristic, and the resistance value of the third current source resistor may have a positive temperature characteristic.

  In this way, a circuit for generating a reference voltage for generating a tail current of the third current source can be eliminated, and the number of current paths can be reduced. In addition, the temperature dependence and variation of the tail current flowing through the third current source can be reduced.

  In another aspect of the present invention, the output section of the comparator includes a fourth current source, and the fourth current source has a fourth current source having one end connected to the first power supply node. And a depletion type fourth current source transistor having a source connected to the other end of the fourth current source resistor and a gate connected to the first power supply node. The threshold voltage of the current source transistor may have a negative temperature characteristic, and the resistance value of the fourth current source resistor may have a positive temperature characteristic.

  In this way, a circuit for generating a reference voltage for generating a tail current of the fourth current source can be eliminated, and the number of current paths can be reduced. In addition, the temperature dependence and variation of the tail current flowing through the fourth current source can be reduced.

  Another aspect of the invention relates to an electronic device including any one of the integrated circuit devices described above.

The structural example of the regulator of this embodiment. The detailed structural example of the regulator of this embodiment. The figure which shows the structural example of the current source used for the regulator of this embodiment. Explanatory drawing of a work function difference voltage. FIG. 5A and FIG. 5B are circuit diagrams used for circuit operation comparison between this embodiment and a comparative example. 6A and 6B are explanatory diagrams of poles and zeros obtained by solving a transfer function. 7A and 7B are explanatory diagrams of a method for realizing stable operation of the circuit. The example of the feedback method of the comparative example of this embodiment. The structural example of the comparative example of a regulator. FIG. 10A and FIG. 10B are diagrams comparing the temperature dependence of the tail current. FIG. 11A and FIG. 11B are diagrams comparing variations in tail current values. 12A and 12B show examples of the layout of resistors. Explanatory drawing of the method of reducing the temperature dependence of a constant voltage. 14A and 14B are also explanatory diagrams of a technique for reducing the temperature dependence of the constant voltage. 1 is a configuration example of an integrated circuit device including a regulator, a power-on reset circuit, and a logic circuit. Example of regulator and power-on reset circuit. The example of a structure of the comparator which a power-on reset circuit contains. 2 shows a configuration example of an integrated circuit device for wireless communication. Configuration example of an electronic device.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Configuration FIG. 1 shows a configuration example of a regulator (constant voltage generation circuit) of this embodiment. As shown in FIG. 1, the regulator according to the present embodiment includes an amplifier circuit AM and first and second resistors RB1 and RB2. Further, a phase compensation capacitor C0 is included.

  The amplifier circuit AM is a differential amplifier having an offset voltage VOFF between a non-inverting input terminal (first differential input terminal in a broad sense) and an inverting input terminal (second differential input terminal in a broad sense). A circuit (op-amp). That is, in a general differential amplifier circuit, the voltage difference between the non-inverting input terminal and the inverting input terminal is approximately 0 V in the case of virtual grounding. However, in the amplifier circuit AM of FIG. Between the inverting input terminals, an offset voltage VOFF due to a work function difference voltage described later is set.

  The resistors RB1 and RB2 are provided in series between the output node NQ1 of the amplifier circuit AM and the VSS node (first power supply node in a broad sense). The voltage of output node NQ1 is voltage-divided by resistors RB1 and RB2, and a divided voltage is generated at connection node NQ2.

  Here, each resistance of RB1 and RB2 may include a plurality of resistance units connected in series. Each resistance unit of the plurality of resistance units has a resistance element and a switch element connected in parallel, and the resistance values of RB1 and RB2 are variably set by turning on and off the switch elements of each resistance unit. The For example, based on a signal from an initial value setting circuit such as a fuse circuit or a nonvolatile memory, the switch element of each resistance unit is set to ON or OFF. In this way, it is possible to adjust the variation in resistance value (constant voltage value) due to manufacturing process fluctuations.

  The phase compensation capacitor C0 is a capacitor having one end connected to a connection node NQ2 between the resistors RB1 and RB2. In FIG. 1, the other end of the phase compensation capacitor C0 is connected to the VSS node. Note that the other end of the capacitor C0 may be connected to a VDD node (second power supply node in a broad sense) or the like. The capacitor C0 can be realized by, for example, a capacitor having a structure composed of a first layer of polysilicon and a second layer of polysilicon, a capacitor having an MIM (Metal-Insulator-Metal) structure, a gate capacitor, or the like.

  As shown in FIG. 1, in the regulator of this embodiment, the signal (voltage) at the connection node NQ2 of the resistors RB1 and RB2 is fed back (positive feedback) to the non-inverting input terminal (positive side terminal) of the amplifier circuit AM. . The signal (voltage) at the output node NQ1 of the amplifier circuit AM is fed back (negative feedback) to the inverting input terminal (negative terminal) of the amplifier circuit AM. Specifically, the connection node NQ2 is connected to the non-inverting input terminal of the amplifier circuit AM, and the output node NQ1 is connected to the inverting input terminal of the amplifier circuit AM.

  For example, in a general differential amplifier circuit, a connection for feeding back a signal to both the non-inverting input terminal and the inverting input terminal is not performed. In this regard, since the amplifier circuit AM of FIG. 1 is an amplifier circuit having an offset voltage VOFF between the non-inverting input terminal and the inverting input terminal, such feedback connection is possible. By adopting such a feedback connection, the negative feedback becomes a voltage follower, and the positive feedback can determine the output voltage by adjusting the feedback amount by resistance division.

  Specifically, the resistance values of the resistors RB1 and RB2 are R1 and R2. Then, the regulator of the present embodiment generates a constant voltage of Q1 = VREG = VOFF × {(R1 + R2) / R1}.

  For example, a conventional regulator requires a circuit for generating a reference voltage for generating a constant voltage. Accordingly, since there is a current path in the reference voltage generation circuit, power is wasted for the current path.

  On the other hand, in the regulator according to the present embodiment, Q1 = VREG = VOFF × {(R1 + R2) / R1} using the offset voltage VOFF of the amplifier circuit AM as a reference voltage without providing such a reference voltage generation circuit. A constant voltage is generated. Accordingly, the number of current paths is reduced by the number of current paths of the reference voltage generation circuit, so that low power consumption can be realized.

  In the present embodiment, as shown in FIG. 1, the signal at the output node NQ1 of the amplifier circuit AM is fed back (negative feedback) to the inverting input terminal of the amplifier circuit AM, and the signal at the connection node NQ2 between the resistors RB1 and RB2 is returned. Feedback (positive feedback) is made to the non-inverting input terminal. A phase compensation capacitor C0 is provided for this connection node NQ2. By doing so, as will be described in detail later, it is possible to prevent oscillation of the circuit and realize stable operation of the circuit. Therefore, according to the regulator of this embodiment, both stable operation of the circuit and low power consumption can be achieved.

  Moreover, in a general regulator design method, an operational amplification circuit for voltage generation performs operational amplification (for example, 1.5 times operational amplification) based on some reference voltage (for example, 1V), A voltage (for example, 1.5V) is generated. A buffering amplifier circuit (for example, a voltage follower-connected amplifier circuit) performs buffering of the voltage after the operational amplification, thereby ensuring the current supply capability of the regulator.

  According to this method, design can be performed in two stages such as an operational amplification part and a buffering part, so that the design can be facilitated. That is, the circuit configuration of performing buffering while performing operational amplification is very difficult to design from the viewpoint of circuit stabilization. When performing operational amplification, negative feedback via a feedback resistor is required, but the design should be made while ensuring both stability against phase lag caused by the feedback resistor and feedback capacitance and current supply capability. This is because it is extremely difficult.

  In this regard, the configuration of the present embodiment in FIG. 1 is configured to realize operational amplification and buffering with a single amplifier circuit. That is, the viewpoint of design for operational amplification is brought to the positive feedback side, and the viewpoint of design for buffering is brought to the negative feedback side, which is different from the conventional general regulator design method. Yes.

  FIG. 2 shows a detailed configuration example of the regulator of this embodiment. As shown in FIG. 2, the amplifier circuit AM includes a differential unit DF and an output unit QB connected to the output node NB1 of the differential unit DF. Furthermore, a capacitor CC and a resistor RC for phase compensation can be included. The differential unit DF includes a current mirror circuit including first and second differential transistors TB1 and TB2 and transistors TB4 and TB5.

  Specifically, the differential section DF includes differential transistors TB1 and TB2, current mirror transistors TB4 and TB5, and a first current source ISB1. The gate electrode of the differential transistor TB1 is connected to a connection node NQ2 between the resistors RB1 and RB2. The gate electrode of the differential transistor TB2 is connected to the output node NQ1 of the output unit QB. The differential transistors TB1 and TB2 have different gate electrode conductivities, and the difference between the threshold voltages of these TB1 and TB2 becomes the work function difference voltage VWD.

  The P-type transistors TB4 and TB5 are provided between the N-type differential transistors TB1 and TB2 and the VDD node (second power supply node in a broad sense). Transistors TB4 and TB5 have their gate electrodes connected to node NB2, thereby forming a current mirror circuit. The first current source ISB1 is provided between the differential transistors TB1 and TB2 and the VSS node (first power supply node in a broad sense).

  The output part QB includes a drive transistor TDR and a second current source ISB2 provided in series. Then, the signal of the connection node NQ1 between the driving transistor TDR and the second current source ISB2 is input to the inverting input terminal (second differential input terminal) which is the gate electrode of the transistor TB2 of the differential section DF and fed back. Is done. The signal at the connection node NQ2 between the resistors RB1 and RB2 is input to the non-inverting input terminal (first differential input terminal) that is the gate electrode of the transistor TB1 of the differential section DF and fed back. The phase compensation capacitor CC and resistor RC are provided between the output node NB1 of the differential section DF and the output node NQ1 of the output section QB.

  The resistors RB1 and RB2 are provided between the output node NQ1 and the VSS node of the output unit QB. The phase compensation capacitor C0 is provided between the connection node NQ2 of the resistors RB1 and RB2 and the VSS node.

  In FIG. 2, the work function difference voltage VWD which is the offset voltage VOFF is set by making the conductivity of the gate electrode of the differential transistor TB1 different from the conductivity of the gate electrode of the differential transistor TB2.

  For example, when the gate electrode of the differential transistor TB1 is N-type, the gate electrode of the differential transistor TB2 is P-type. TB1 is, for example, a depletion type N-type transistor (NMOS transistor), and TB2 is, for example, an enhancement type N-type transistor. For example, the differential transistors TB1 and TB2 have the same substrate impurity concentration and channel impurity concentration, but have different gate electrode conductivity and different gate electrode impurity concentrations.

Specifically, the threshold voltage of the MOS transistor can be expressed as Vth = φ _MS −Q _SS / C _OX + 2φ _F + Q _D / C _OX . Here, φ _MS is a work function difference between the gate electrode and the substrate (P well), Q _SS is a fixed charge in the oxide film, C _OX is a capacity per unit area of the gate oxide film, and φ _F Is the Fermi level, and Q _D is the charge in the depletion layer. Depending on the setting of the impurity concentration of the N-type gate electrode of the differential transistor TB1 and the impurity concentration of the P-type gate electrode of the differential transistor TB2, the threshold voltage of the differential transistor TB1 is about -0.2V to -0.5V, for example. The threshold voltage of the differential transistor TB2 can be set to about 0.5V to 0.8V, for example.

  The voltage difference between the node NQ1 and the node NQ2 is set to the threshold voltage difference (work function difference voltage) between the differential transistors TB2 and TB1 by the virtual ground of the amplifier circuit AM, thereby generating and outputting a constant voltage. The Therefore, according to the regulator of FIG. 2, it is not necessary to separately provide a circuit for generating a reference voltage, and the number of current paths can be reduced correspondingly, so that power consumption can be reduced.

  FIG. 3 is a diagram showing a specific configuration example of the first and second current sources ISB1 and ISB2 of FIG. In FIG. 3, the first current source ISB1 includes a first current source resistor RB3 and a first current source transistor TB3. One end of the current source resistor RB3 is connected to the VSS node (first power supply node). The current source transistor TB3 is a depletion type transistor (NMOS transistor) having a source connected to the other end of the current source resistor RB3 and a gate connected to the VSS node.

  Similarly, the second current source ISB2 includes a second current source resistor RB4 and a second current source transistor TB6. One end of the current source resistor RB4 is connected to the VSS node (first power supply node). The current source transistor TB6 is a depletion type transistor (NMOS transistor) having a source connected to the other end of the current source resistor RB4 and a gate connected to the VSS node.

  For example, when the tail currents ITL1 and ITL2 flowing in TB3 and TB6 become small due to an increase in the threshold voltage of the transistors TB3 and TB6, the voltages of the source nodes of TB3 and TB6 become low. When the voltage at the source node of TB3 and TB6 decreases, the voltage between the gate and source of TB3 and TB6 increases, so that the current flowing through TB3 and TB6 increases, thereby causing the tail current ITL1 flowing through TB3 and TB6. , ITL2 is kept constant.

  On the other hand, when tail currents ITL1 and ITL2 flowing through TB3 and TB6 increase due to a decrease in the threshold voltage of transistors TB3 and TB6, the voltage at the source node of TB3 and TB6 increases. When the source node voltage of TB3 and TB6 increases, the voltage between the gate and source of TB3 and TB6 decreases, so that the tail currents ITL1 and ITL2 flowing in TB3 and TB6 are reduced, thereby causing TB3 and TB6 to be reduced. The flowing tail currents ITL1 and ITL2 are kept constant. In this way, it is possible to realize the current sources ISB1 and ISB2 through which the constant tail currents ITL1 and ITL2 flow.

  As described above, the current sources ISB1 and ISB2 having the configuration shown in FIG. 3 have a configuration in which current is generated in a self-contained manner and voltage is generated, and negative feedback is applied by the source resistors RB3 and RB4 provided at the sources. It has become. Therefore, even when the transistors TB3 and TB6 and the resistors RB3 and RB4 are varied, the generated tail currents ITL1 and ITL2 are smaller than the variations of TB3, TB6, RB3, and RB4. Can be generated.

  The current source transistors TB3 and TB6 are depletion type N-type transistors, and the voltage of VSS (the voltage of the first power supply node, the ground voltage) is set to the gate electrode. That is, since the transistors TB3 and TB6 are depletion type N-type transistors, a current flows even when VSS is set to the gate electrode. Therefore, it is only necessary to set the gate electrodes of the transistors TB3 and TB6 to VSS, and it is not necessary to separately prepare a reference voltage generation circuit set for the gate electrodes, so that the number of current paths can be reduced. That is, since the number of current paths can be reduced by the number of current paths of the reference voltage generation circuit, power consumption can be reduced.

  The threshold voltages of the transistors TB3 and TB6 have negative temperature characteristics, and the resistance values of the resistors RB3 and RB4 have positive temperature characteristics. For example, the resistors RB3 and RB4 are N well resistors formed by N wells, and the N well resistors have positive temperature characteristics. Therefore, as the temperature rises, the threshold voltages of the transistors TB4 and TB6 decrease, while the resistance values of the resistors RB3 and RB4 increase. Therefore, the tail currents ITL1 and ITL2 flowing through the current sources ISB1 and ISB2 are almost constant. Kept. When the temperature decreases, the threshold voltages of the transistors TB3 and TB6 increase while the resistance values of the resistors RB3 and RB4 decrease. Therefore, the tail currents ITL1 and ITL2 flowing through the current sources ISB1 and ISB2 are kept almost constant. Be drunk. Therefore, the temperature characteristics of the tail currents ITL1 and ITL2 can be made closer to flat characteristics.

  That is, only the configuration in which negative feedback is applied by the resistors RB3 and RB4 cannot reduce the temperature variation, but the transistors TB3 and TB6 have negative temperature characteristics, while the resistors RB3 and RB4 have positive temperature characteristics. Thus, the temperature variation can be reduced.

  FIG. 4 is a band diagram for explaining the work function difference voltage. As shown in FIG. 4, the work function of the N-type gate electrode and the P-well of the differential transistor TB1 on the non-inverting input terminal side and the P-type gate electrode and the P-well of the differential transistor TB2 on the inverting input terminal side The work function difference becomes the work function difference voltage VWD.

  Note that the offset voltage between the non-inverting input terminal and the inverting input terminal of the differential section DF (the offset voltage between the first and second differential input terminals) is set by other than the work function difference voltage as shown in FIG. May be. For example, the offset voltage may be set by changing the W / L ratio (current supply capability) of the differential transistor TB1 and the W / L ratio of the differential transistor TB2. Alternatively, by changing the W / L ratio of the first current mirror transistor TB4 constituting the current mirror circuit and the W / L ratio of the second current mirror transistor TB5 constituting the current mirror circuit, the offset voltage is changed. May be set.

  In addition to setting the work function difference voltage VWD in this way, the W / L ratio (current supply capability) of the differential transistor and current mirror transistor can also be set to enable fine adjustment of the constant voltage generated by the regulator. become. For example, when the work function difference voltage VWD is about 0.9V and a constant voltage is to be generated by applying a voltage of 1V across the resistor RB1, the difference between 1.0V and 0.9V is 0.1V. Is adjusted by adjusting the W / L ratio of the differential transistor and the current mirror transistor. In this way, it is possible to adjust the voltage applied to both ends of the resistor RB1 and adjust the generated constant voltage.

2. Phase Compensation Next, the phase compensation method of this embodiment will be described. In the present embodiment, as shown in FIG. 1 and the like, the regulator output Q1 (the signal at the node NQ1) is fed back to the inverting input terminal of the amplifier circuit AM, and the regulator output Q2 (the signal at the node NQ2) is fed back to the amplifier circuit AM. Is fed back to the non-inverting input terminal.

  For example, in negative feedback, which is feedback to the inverting input terminal, if the phase delay is about 120 degrees or less, the phase margin is 60 degrees or more, so that stable circuit operation can be ensured. Therefore, in FIG. 1, if the phase delay from the input is 90 degrees with respect to the output Q1, the oscillation operation of the circuit is prevented and the stable operation of the circuit can be ensured. Further, for the output Q2 on the positive feedback side, if the phase delay from the input is 180 degrees, stable operation of the circuit can be ensured. At this time, if the resistance values of the resistors RB1 and RB2 can be made sufficiently high, the current flowing from the output node NQ1 to VSS can be reduced, so that low power consumption can be realized.

  Therefore, in the present embodiment, the phase compensation capacitor C0 is provided at the node NQ2, and the resistance value of the resistor RB1 is increased to achieve both stable operation of the circuit and low power consumption.

  Next, the phase compensation method of this embodiment will be described with reference to the circuits of FIGS. 5 (A) and 5 (B). In the circuit of FIG. 5A, the phase compensation capacitor C0 is provided at the node NQ2, and in the circuit of FIG. 5B, the phase compensation capacitor C0 is not provided at the node NQ2.

Here, differential signals AC1 and AC2 are input to the non-inverting input terminal INP and the inverting input terminal INN, respectively. Then, the transfer function H1 (S) from the input to the Q1 in the circuit of FIG. 5A and the transfer function H2 (S) from the input to the Q2, and from the input in the circuit of FIG. 5B to the Q1. The transfer function H1 (S) _NC and the transfer function H2 (S) _NC from the input to Q2 are solved, and the frequency characteristics are examined by paying attention to the difference between the pole and the zero point.

When solving the transfer function, each transistor is modeled for small signal analysis, and basically a gm element model is used. However, for the transistors TB4 and TB5 in FIGS. 5A and 5B, a model having rds and gate / source capacitance in addition to the gm element is used. In addition, regarding the solution of the pole, if the mathematical expression is solved as it is, it becomes too complicated. That is, a simplified operation is performed by extracting the main term from the numerator / denominator and rewriting the description. 5A and 5B, it is assumed that the differential transistors TB1 and TB2 have the same size, and the transistors TB4 and TB5 constituting the current mirror circuit have the same size. Therefore, in the mathematical formulas described below, an operation of replacing one of these with the other is appropriately performed. For example, an operation of replacing gm _TB1 with gm _TB2 and an operation of replacing rds _TB5 with rds _TB4 are performed.

  In the case where the capacitor C0 is provided as shown in FIG. 5A, when the transfer function H1 (S) from the input to the output Q1 is solved, the DC gain is obtained as in the following equation (1). R1 and R2 are resistance values of the resistors RB1 and RB2.

  Further, the pole is obtained as in the following formulas (2), (3), and (4). In the following formulas (2) and (3), the above-described simplification operation is performed.

  Also, the zero point is obtained as in the following formulas (5), (6), and (7).

  Further, in the case where the capacitor C0 is provided as shown in FIG. 5A, when the transfer function H2 (S) from the input to the output Q2 is solved, the DC gain, the pole, and the zero point are expressed by the following equations (8) to (13). It is determined as follows. In the following formulas (9) and (10), the above-described simplification operation is performed.

Further, when the capacitor C0 is not provided as shown in FIG. 5B, when the transfer function H1 (S) _NC from the input to the output Q1 is solved, the DC gain, pole, and zero are expressed by the following equations (14) to (18). It is obtained like this.

Further, when the capacitor C0 is not provided as shown in FIG. 5B, when the transfer function H2 (S) _NC from the input to the output Q2 is solved, the DC gain, pole, and zero are expressed by the following equations (19) to (23). It is obtained like this.

As can be understood from the DC gain, poles, and zeros obtained by solving the above four transfer functions H1 (S), H2 (S), H1 (S) _NC , and H2 (S) _NC , the four transfer functions The difference between the two DC gains DC1 and DC2 shown in the following expressions (24) and (25) and the presence or absence of the poles P1, P2, and P3 and the zeros Z1, Z2, and Z3 shown in the following expressions (26) to (31) Can be discussed.

  For example, as shown in FIG. 6A, when the capacitor C0 is provided, all the poles P1 to P3 and all the zeros Z1 to Z3 exist in the transfer function of Q1, but in the transfer function of Q2, There is no zero point Z2. On the other hand, when the capacitor C0 is not provided, the pole P2 and the zero point Z2 do not exist in both the transfer functions of Q1 and Q2.

  Next, the poles P1 to P3 and the zeros Z1 to Z3 will be described with reference to FIG. As indicated by A1 in FIG. 6B, P1 is a pole determined by phase compensation (CC, RC) inside the amplifier circuit. As indicated by A2, P2 is a pole determined by the capacitance C0 outside the amplifier circuit.

As shown in A3, P3 is a pole determined by the parasitic capacitance (cgs) inside the amplifier circuit, and as shown by A4, Z1 is a zero point determined by the parasitic capacitance (cgs) inside the amplifier circuit. P3 and Z1 are common to all the transfer functions H1 (S), H2 (S), H1 (S) _NC , and H2 (S) _NC described above, and the frequencies are also close. Since the negative pole and the negative zero cancel each other in both the gain and phase frequency characteristics, the pole P3 and the zero Z1 can be ignored.

As indicated by A5, Z2 is a zero point determined by a capacitor C0 outside the amplifier circuit. Further, as indicated by A6, Z3 can be skipped to a high frequency by setting the resistance value of the resistor RC so that gm _TDR · RC = 1.

  From the above, the pole P3 and the zeros Z1 and Z3 shown in A3, A4, and A6 can be excluded from the analysis target. Therefore, as shown in FIG. 7A, only the poles P1, P2 and the zero point Z2 need to be analyzed.

Then, as indicated by B1 in FIG. 7A, in the transfer function to Q1 when C0 is provided, the phase is delayed by 90 degrees due to the pole P1. The phase is also delayed by 90 degrees due to the pole P2, and this can be offset by the zero point Z2 by adjusting the gm _TDR and selecting the resistance value of the RB1. Specifically, it can be adjusted by sufficiently increasing the resistance value R1 of RB1 and increasing gm _TDR (increasing current, increasing W / L ratio). As a result, the phase is only 90 degrees delayed by the pole P1.

  As shown in B2, in the transfer function to Q2 when C0 is provided, the phase is delayed by 90 degrees due to the pole P1. The phase is also delayed by 90 degrees due to the pole P2, but unlike the case of B1, since the zero point Z2 does not exist, the phase is delayed by 180 degrees.

  As shown in B3, in the transfer function to Q1 when C0 is not provided, the phase is delayed by 90 degrees due to the pole P1. Further, since the external capacitor C0 does not exist, the pole P2 does not exist, and the phase delay due to P2 does not occur. As a result, the phase is delayed by 90 degrees.

  As shown in B4, in the transfer function to Q2 when C0 is not provided, the phase is delayed by 90 degrees due to the pole P1. Further, since the external capacitor C0 does not exist, the pole P2 does not exist, and the phase delay due to P2 does not occur. As a result, the phase is delayed by 90 degrees, and the difference from the transfer function to Q1 shown in B3 is only the DC gain.

  The above analysis is summarized as shown in FIG. That is, by providing the capacitor C0 and canceling out the phase delay due to the pole P2 at the zero point Z2, the transfer function to Q1 has a phase delay of 90 degrees due to the pole P1. Therefore, by returning Q1 to the inverting input terminal as shown in FIG. 1, oscillation is prevented and the circuit operation becomes stable.

  Also, by providing the capacitor C0, the transfer function to Q2 is 180 degrees behind the phase due to the poles P1 and P2. Therefore, by returning Q2 to the non-inverting input terminal as shown in FIG. 1, oscillation is prevented and the circuit operation is stabilized.

  For example, FIG. 8 shows a feedback method of a comparative example of this embodiment. In FIG. 8, the non-inverting input terminal of the amplifier circuit AM is set to VSS, and the signal at the connection node NQ2 of the resistors RB1 and RB2 is negatively fed back to the inverting input terminal of the amplifier circuit AM. Even in the configuration of FIG. 8, a constant voltage can be generated based on the offset voltage VOFF. However, in the configuration of FIG. 8, there is a problem that if the resistance values of the resistors RB1 and RB2 are increased in order to reduce power consumption, the stability of the circuit is extremely lowered.

  That is, if only the resistance value of the resistor RB1 is increased, the feedback amount is simply reduced, and the circuit is in a stable operation direction. However, if the resistance value of the resistor RB2 is not increased but only the resistance value of the resistor RB1 is increased, the regulator output voltage (VREG) increases. Since the power supply voltage is limited and the desired voltage level to be output is limited within a certain range, when the resistance value of the resistor RB1 is increased, it is necessary to increase the resistance value of the resistor RB2 as well. is there. Then, a phase lag is caused by the resistor RB2 and the gate capacitance of the negative feedback destination, and this becomes close to the internal pole of the amplifier circuit AM, so that the circuit operation becomes unstable. For example, if the output Q2 having a phase delay of 180 degrees is negatively fed back to the inverting input terminal of the amplifier circuit AM as shown in FIG. 8, the circuit operation becomes unstable as indicated by B5 in FIG. .

On the other hand, in this embodiment, since the feedback method as shown in B6 and B7 in FIG. 7B is adopted, both stable operation of the circuit and low power consumption can be achieved.
That is, in this embodiment, by increasing the resistance value of RB1 (inevitably increasing the resistance value of RB2), as a result, the current consumption flowing from the node NQ1 to VSS is reduced, and the gm _TDR is increased. Realizes stable operation of the circuit.

  For example, the current path in the regulator of FIG. 3 is the path of the current source ISB1, the path of the current source ISB2, and the paths of the resistors RB1 and RB2. Among these, for the paths of the resistors RB1 and RB2, by forming the RB1 and RB2 with, for example, a high-resistance polysilicon resistor and setting the resistance value to, for example, 50 M ohms or more, the current flowing through the current path is reduced as much as possible. it can. Further, by increasing the resistance value R1 of RB1, the phase delay due to the pole P2 can be canceled at the zero point Z2 as described above to return the phase, and the circuit operation can be stabilized.

Further, in order to cancel the phase delay due to the pole P2 at the zero point Z2, it is necessary to increase the gm _{TDR of the} driving transistor TDR. Therefore, the current consumption of the regulator in FIG. 3 is the tail current flowing in the current source ISB2. ITL2 becomes dominant. That is, since the tail current ITL1 and the current flowing through RB1 and RB2 can be sufficiently reduced, the tail current ITL2 becomes dominant in the overall consumption current.

  On the other hand, in FIG. 3, the current source ISB2 includes a depletion type transistor TB6 having a negative temperature characteristic and a P-well resistor RB4 having a positive temperature characteristic. Thereby, as shown in FIGS. 10A to 11B, which will be described later, variations in the tail current ITL2 due to temperature fluctuations, power supply voltage fluctuations, and process fluctuations can be reduced. Therefore, it is not necessary to take a wide design margin, so that the value of the tail current ITL2 that is dominant in the entire current consumption can be made sufficiently close to the low current consumption side. As a result, the current consumption of the regulator can be further reduced.

3. FIG. 9 shows a configuration example of a regulator that is a comparative example of the regulator of FIG. In this comparative example, the configurations of the current sources ISB1 and ISB2 are different from those in FIG. The regulator of the present invention may be configured as shown in FIG.

  In the comparative example of FIG. 9, the reference voltage VR is generated by the reference voltage generation circuit REFG configured by the transistors TG1 and TG2. The reference voltage VR is input to the gate electrodes of the transistors TG3 and TG4, thereby generating tail currents ITL1 and ITL2 in the current sources ISB1 and ISB2.

  In the comparative example of FIG. 9, the number of current paths is increased compared to FIG. 3 by the amount of the current path of the current IRG in the reference voltage generation circuit REFG. Therefore, current consumption increases. On the other hand, the regulator of FIG. 3 can reduce the number of current paths as compared with FIG.

  10A and 10B are diagrams comparing the temperature dependence and power supply voltage dependence of the tail current generated by the regulator of FIG. 3 and the tail current generated by the comparative example of FIG. .

  In FIGS. 10A and 10B, the resistances RB3 and RB4 of the current sources ISB1 and ISB2 in FIG. 3 are N-well resistors having positive temperature characteristics and those having flat temperature characteristics. The case of resistance is shown in comparison.

  As shown in FIG. 10A, in the regulator of FIG. 3 in which the current sources ISB1 and ISB2 are configured by the depletion type transistors TB3 and TB6 and the N-well resistors RB3 and RB4, the temperature of the tail current ITL (ITL1, ITL2) The characteristic can be made almost flat. Therefore, fluctuations in the tail current ITL due to temperature fluctuations can be suppressed.

  On the other hand, when a current source is configured as in the comparative example of FIG. 9, the temperature characteristics of the tail current ITL (ITL1, ITL2) are not flat, and the tail current ITL also varies due to temperature variation. The same applies when the resistors RB3 and RB4 are made of poly resistors.

  Further, as shown in FIG. 10B, the regulator of FIG. 3 in which the current sources ISB1 and ISB2 are configured by the depletion type transistors TB3 and TB6 and the resistors RB3 and RB4, the tail current ITL is changed even when the power supply voltage is changed. It can be kept almost constant. Therefore, the fluctuation of the tail current ITL due to the fluctuation of the power supply voltage can be suppressed. This is the same when the resistors RB3 and RB4 are made of poly resistors.

  On the other hand, when the current source is configured as in the comparative example of FIG. 9, when the power supply voltage changes, the tail current ITL also changes. Therefore, fluctuations in the tail current ITL due to fluctuations in the power supply voltage cannot be suppressed, and the configuration in FIG. 3 is more advantageous in this respect.

  FIG. 11A is a histogram that compares the variation of the tail current generated by the regulator of FIG. 3 and the tail current generated by the comparative example of FIG. In FIG. 11A, a histogram is created using the Monte Carlo method. FIG. 11B shows the average value, maximum value, minimum value, and variance of the tail current.

  As shown in FIG. 11 (A), according to the regulator of FIG. 3, because of resistance feedback, the tail current varies due to variations in the manufacturing process, such as variations in the threshold voltage of the transistor and variations in the gate length. Can be suppressed. Therefore, it is possible to generate a tail current with high accuracy.

4). Layout Arrangement FIGS. 12A and 12B show examples of resistor layout arrangement. 12A is a plan view and FIG. 12B is a cross-sectional view.

  In FIG. 3, the resistors RB1 and RB2 are formed by poly resistors, while the resistors RB3 and RB4 for the current source of the differential unit DF and the output unit QB are formed by N-well resistors having positive temperature characteristics. To do. By forming RB3 and RB4 with N-well resistors to have a positive temperature characteristic, it becomes possible to cancel out the negative temperature characteristic of the threshold voltage of the depletion type transistors TB3 and TB6, and the current source The temperature characteristics of the tail currents ITL1 and ITL2 of ISB1 and ISB2 can be made flat.

  On the other hand, in order to reduce the power consumption of the regulator, it is necessary to reduce the current values of the currents RB1 and RB2 and the tail currents ITL1 and ITL2 flowing in the current sources ISB1 and ISB2, and these current values are reduced. For this purpose, it is necessary to increase the resistance values of the resistors RB1, RB2, RB3, and RB4.

  However, if the resistance values of the resistors RB1 to RB4 are to be increased, the layout area of the resistors RB1 to RB4 is increased, leading to an increase in the scale of the integrated circuit device.

  Therefore, in this embodiment, the layout method shown in FIGS. 12A and 12B is adopted.

  That is, in FIG. 12A, the resistors RB1 and RB2 in FIG. 3 are poly resistors formed by a polysilicon layer, and the resistors RB3 and RB4 are N well resistors formed by an N well. . Then, as shown in FIG. 12A, the resistors RB1 and RB2 which are poly resistors are laid out on the formation region of the resistors RB3 and RB4 which are N well resistors. In other words, the resistors RB3 and RB4 that are N-well resistors and the resistors RB1 and RB2 that are poly resistors are laid out so as to overlap in plan view.

  Specifically, in FIG. 12A, the resistors RB1 and RB2 are formed of a plurality of poly resistor units. That is, a plurality of poly resistance units are arranged in a snake shape, and adjacent poly resistance units are connected via metal wiring and contacts. One end of the resistors RB1 and RB2 becomes the tap TPP1, and the other end becomes the tap TPP2. Taking FIG. 3 as an example, in the resistor RB1, the node NQ1 is connected to the tap TPP1, and the node NQ2 is connected to the tap TPP2. In the resistor RB2, the node NQ2 is connected to the tap TPP1, and VSS is connected to the tap TPP2.

  The resistors RB3 and RB4 are constituted by a plurality of N-well resistor units. That is, a plurality of N-well resistance units are arranged in a snake shape, and adjacent N-well resistance units are connected via metal wiring and contacts. One end of the resistors RB3 and RB4 is a tap TPN1, and the other end is a tap TPN2. Taking FIG. 3 as an example, in the resistor RB3, the source of the transistor TB3 is connected to the tap TPN1, and VSS is connected to the tap TPN2. In the resistor RB4, the source of the transistor TB6 is connected to the tap TPN1, and VSS is connected to the tap TPN2. The layout of the poly resistors and the N well resistors is not limited to that shown in FIG. 12A, and various modifications can be made.

  In FIG. 12A, the poly resistance units are arranged so that the longitudinal direction thereof is in the lateral direction (first direction) with respect to the paper surface, and the N well resistance units are arranged with the longitudinal direction perpendicular to the paper surface. It arrange | positions so that it may become a direction (2nd direction orthogonal to a 1st direction). In this way, the tap TPP1 and TPP2 take-out location and the taps TPN1 and TPN2 take-out location can be made different, so that the signal wiring layout can be simplified and made more efficient.

  12A and 12B, the resistors RB1 and RB3 and RB2 and RB4 can be laid out using one region of the integrated circuit device. Therefore, the layout efficiency can be improved and the area of the integrated circuit device can be reduced.

  12A and 12B, since two resistors (poly resistor and N well resistor) can be arranged in one region, the layout area of each resistor is increased in order to increase the resistance value of each resistor. Even if the size is increased, the increase in the overall layout area can be minimized. Therefore, it is easy to reduce the power consumption of the circuit by increasing the resistance value of each resistor.

  In particular, in the present embodiment, attention is paid to the fact that if the resistors RB3 and RB4 are formed of N-well resistors, another circuit element can be laid out thereon. Therefore, the resistors RB3 and RB4 having positive temperature characteristics are realized by N-well resistors, the resistors RB1 and RB2 are realized by poly resistors, and a poly resistor is formed on the N well resistors, thereby reducing the layout area. Plan

  In this case, if the N-well resistor and the poly resistor are laid out in the same place, the resistance value of the other resistor may be changed by the voltage from one resistor. However, the accuracy of the N-well resistor is not emphasized, and it is sufficient that the resistance value is high. Therefore, the resistance value fluctuation due to the voltage from the poly resistor is not a problem. On the other hand, when the resistance value of the poly resistor is increased, the resistance of the resistance value due to the voltage from the upper and lower elements becomes more susceptible. However, since the voltages applied to the N-well resistors RB3 and RB4 in FIG. 3 are close to 0V, there is an advantage that the adverse effect on the poly-resistance is not so problematic.

5. As described above, the regulator of this embodiment shown in FIG. 1 has a constant voltage of Q1 = VREG = VOFF × {(R1 + R2) / R1} = VOFF × {1+ (R2 / R1)}. Generate. The offset voltage VOFF set by the work function difference voltage has a negative temperature characteristic. For this reason, if the resistors RB1 and RB2 are formed of resistance elements having the same temperature characteristics, the term of the resistance ratio R2 / R1 has no temperature dependence, and the constant voltage VREG has a negative temperature characteristic. That is, the constant voltage VREG becomes low at a high temperature and becomes high at a low temperature, and has temperature dependence.

  Therefore, in the present embodiment, it is desirable to employ a method of canceling the temperature dependence of the offset voltage VOFF with the resistance ratio R2 / R1. That is, when the resistance value of the resistor RB1 is R1, and the resistance value of the resistor RB2 is R2, the resistance ratio R2 / R1 has a temperature characteristic that cancels the temperature characteristic of the offset voltage VOFF. For example, when the offset voltage VOFF has a negative temperature characteristic, the resistance ratio R2 / R1 has a positive temperature characteristic. In this way, the temperature dependence of the constant voltage VREG can be reduced by offsetting the temperature characteristic of the offset voltage VOFF and the temperature characteristic of the resistance ratio R2 / R2, and for example, the constant voltage VREG having a temperature characteristic close to flat can be generated. Is possible.

  FIG. 13 shows an example of a configuration for realizing such a temperature compensation method. In FIG. 13, the resistor RB1 is formed by a resistor element RE1, and the resistor RB2 is formed by resistor elements RE21 and RE22. RE21 is the same type of resistance element as RE1. On the other hand, RE22 is a different type of resistance element from RE1 and RE21, and has a positive temperature characteristic coefficient (smaller negative slope) than RE1 and RE21. Thus, in FIG. 13, the resistor RB2 is formed by mixing a plurality of resistance elements RE21 and RE22 having different temperature characteristics. In this way, the resistance ratio R2 / R1 of the resistors RB1 and RB2 can be made temperature dependent, and the temperature characteristic of the offset voltage VOFF can be offset by the temperature characteristic of the resistance ratio R2 / R1. It becomes possible.

  FIG. 14A shows the temperature dependence of the constant voltage VREG when the temperature compensation of FIG. 13 is performed and when it is not performed. As shown in FIG. 14A, by performing the temperature compensation of FIG. 13, a constant voltage VREG having a flatter temperature characteristic can be obtained.

  FIG. 14B shows the temperature variation rate (temperature dependence) of the resistance values of the resistance element RE21 and the resistance element RE22. If the resistor RB2 is formed by such resistor elements RE21 and RE22, the resistance ratio R2 / R1 can be made temperature dependent. Then, by canceling out the temperature characteristic of the offset voltage VOFF, a constant voltage VREG having a flat temperature characteristic as shown in FIG. 14A can be generated.

6). Integrated Circuit Device FIG. 15 shows an example of an integrated circuit device including the regulator of this embodiment. The integrated circuit device of FIG. 15 includes a regulator 100, a power-on reset circuit 110, and a logic circuit 120 of this embodiment.

  The regulator 100 is a circuit having the configuration described with reference to FIGS. 1 to 3 and the like, and performs voltage adjustment of an external power supply voltage VDDE (for example, 2.4 V to 3.6 V) supplied from the outside of the integrated circuit device. The adjusted constant voltage is output as the power supply voltage VDDA (for example, 1.8 V).

  The logic circuit (control circuit) 120 operates by being supplied with the constant voltage generated by the regulator 100 as the power supply voltage VDDA, and performs various logical operation processes. The logic circuit 120 includes logic elements such as NAND, NOR, and inverter.

  The power-on reset circuit 110 operates by being supplied with the constant voltage generated by the regulator 100 as the power supply voltage VDDA, and outputs a reset signal XRST to the logic circuit 120. For example, when the external power supply voltage VDDE is applied and the voltage level of the power supply voltage VDDA increases, the reset signal XRST changes from the L level (active level) to the H level (inactive level). Therefore, after the logic circuit 120 is reset by the reset signal XRST, the reset state is released. This reset release enables the circuit operation of the logic circuit 120. The regulator 100 may supply the power supply voltage VDDA to a voltage generation circuit (band gap reference circuit) or a constant current generation circuit (not shown).

  In FIG. 15, the logic circuit 120 shifts to a standby mode (sleep mode) when the supply of a clock or the like is stopped. As a result, power consumption in the logic circuit 120 is only leakage current. In addition, since the current flows only in the regulator 100 and the power-on reset circuit 110 in the standby mode, the power consumption of the integrated circuit device can be minimized.

  Specifically, the current consumption in the regulator 100 of FIG. 3 is only the current flowing through the tail currents ITL1 and ITL2 and the resistors RB1 and RB2. That is, in the comparative example of FIG. 9, there is a current path in the reference voltage generation circuit REFG, but in FIG. 3, since the reference voltage generation circuit REFG is not necessary, the number of current paths can be reduced by that amount, and low power consumption is achieved. Electricity can be achieved.

  Further, by sufficiently increasing the resistance values of RB1 and RB2, the circuit operation can be stabilized and the power consumption can be reduced as described above. Also, the tail current at the current source can be reduced in power consumption by sufficiently increasing the resistance value. Therefore, it is possible to significantly reduce the power consumption of the integrated circuit device during standby (sleep), and it is possible to prevent a situation where power is wasted during standby. In particular, when the integrated circuit device is a wireless communication IC as described later, there is an advantage that power consumption can be saved in a standby mode (sleep mode) in which wireless transmission and reception are not performed.

  Further, according to the configuration of FIG. 15, the regulator 100 performs voltage adjustment so that the power supply voltage VDDA becomes smaller than the external power supply voltage VDDE, so that the operation power supply voltage of the logic circuit 120 can be lowered. Therefore, the power consumption of the integrated circuit device during normal operation can be saved.

  FIG. 16 shows a configuration example of the regulator 100 and the power-on reset circuit 110. As shown in FIG. 16, the power-on reset circuit 110 includes a comparator CP. An inverter IV1 that buffers the output signal CPQ of the comparator CP may be included.

  The comparator CP has an offset voltage VOFF between its non-inverting input terminal and the inverting input terminal. Specifically, for example, the offset voltage VOFF by the work function difference voltage VDW described in FIG. 4 is set. Alternatively, as described above, the offset voltage VOFF may be set by changing the W / L ratio of the differential transistor or the current mirror transistor.

  The voltage VD from the voltage dividing tap TPV set in the resistor RB2 (or resistor RB1) of the regulator 100 is input to the inverting input terminal of the comparator CP. A VSS node (first power supply node) is connected to the non-inverting input terminal of the comparator CP. Therefore, when the external power supply VDDE is turned on, the power supply voltage VDDA rises, and the voltage VD input to the inverting input terminal of the comparator CP becomes larger than the offset voltage VOFF, the output signal CPQ of the comparator CPQ becomes L level. Become. As a result, the reset signal XRST changes from the L level to the H level, and the reset state is released after the logic circuit 120 is reset.

  As described above, in FIG. 16, the voltage dividing tap TPV of the resistors RB1 and RB2 included in the regulator 100 is effectively used to set the determination voltage level of the power-on reset circuit 110 and realize the generation of the power-on reset signal XRST. Yes.

  FIG. 17 shows a specific configuration example of the comparator CP. The comparator CP includes a differential unit DFC and an output unit QBC connected to the output node NC1 of the differential unit DFC.

  The differential unit DFC includes first and second differential transistors TC1 and TC2, a current mirror circuit including transistors TC4 and TC5, and a third current source ISC3. The output unit QBC includes a drive transistor TDRC and a fourth current source ISC4 provided in series.

  In FIG. 17, the work function difference voltage VWD that is the offset voltage VOFF is set by making the conductivity of the gate electrode of the differential transistor TC1 different from the conductivity of the gate electrode of the differential transistor TC2. Specifically, the differential transistor TC1 is a depletion type transistor with an N-type gate electrode, and the differential transistor TC2 is an enhancement type transistor with a P-type gate electrode.

  The third current source ISC3 includes a third current source resistor RC3 having one end connected to the VSS node (first power supply node) and a third current source transistor TC3. The transistor TC3 is a depletion type transistor (NMOS transistor) in which the other end of the resistor RC3 is connected to the source and the VSS node is connected to the gate.

  The fourth current source ISC4 includes a fourth current source resistor RC4 having one end connected to the VSS node, and a fourth current source transistor TC6. The transistor TC6 is a depletion type transistor (NMOS transistor) in which the other end of the resistor RC4 is connected to the source and the VSS node is connected to the gate.

  The threshold voltages of the transistors TC3 and TC6 have negative temperature characteristics, and the resistance values of the resistors RC3 and RC4 have positive temperature characteristics. These resistors RC3 and RC4 are formed by N-well resistors. This makes it possible to bring the temperature characteristics of the tail currents ITL3 and ITL4 of the current sources ISC3 and ISC4 closer to flat characteristics.

  According to the comparator CP having the configuration shown in FIG. 17, a circuit for generating a reference voltage for generating the tail currents ITL3 and ITL4 of the current sources ISC3 and ISC4 becomes unnecessary, and the number of current paths can be reduced correspondingly. For example, in a state other than the reset state (a state where CPQ is at L level and XRST is at H level), the tail current ITL4 does not flow, so that only a current path of the tail current ITL3 exists in the comparator CP.

  Accordingly, the paths through which current flows in the integrated circuit device of FIG. 15 in the standby mode are three current paths (ISB1 path, ISB2 path, RB1 and RB2 paths) in the regulator 100, and the power-on reset circuit 110. One current path (ISC3 path) in the comparator CP is a total of only four current paths. Therefore, the current consumption of the integrated circuit device in the standby mode can be minimized.

  FIG. 18 shows a configuration example in the case where the integrated circuit device including the regulator of this embodiment is an RF wireless communication IC. The integrated circuit device includes a reception circuit 30, a demodulation circuit 36, a transmission circuit 40, a modulation circuit 46, a clock generation circuit 48, a control circuit 50, a regulator 100, and a power-on reset circuit 110.

  The receiving circuit 30 includes a low noise amplifier LNA, a mixer 32, and a filter unit 34. The low noise amplifier LNA performs processing for amplifying an RF reception signal input from the antenna ANT with low noise. The mixer 32 performs a down conversion by performing a mixing process of the amplified received signal and the local signal (local frequency signal) from the clock generation circuit 48. The filter unit 34 performs a filtering process on the received signal after the down conversion. Specifically, the filter unit 34 performs bandpass filter processing realized by a complex filter or the like, and extracts a baseband signal while performing image removal.

  The demodulation circuit 36 performs demodulation processing based on the signal from the reception circuit 30. For example, demodulation processing of a signal modulated by FSK (frequency shift keying) is performed on the transmission side, and the demodulated reception signal is output to the control circuit 50.

  The modulation circuit 46 performs modulation processing on the transmission signal from the control circuit 50. For example, the transmission signal is modulated by FSK, and the modulated transmission signal is output to the transmission circuit 40. Then, the transmission circuit 40 outputs the transmission signal amplified by the power amplifier PA to the antenna ANT.

  The clock generation circuit 48 includes a PLL circuit configured by a VCO (voltage controlled oscillator) or the like, and generates various clock signals, local signals to the mixer 32, and the like.

  The control circuit 50 (logic circuit) performs overall control of the integrated circuit device, digital processing in the baseband, and the like. The control circuit 50 includes, for example, a link layer circuit 52 and a host I / F (interface) 54, and executes link layer protocol processing, interface processing with an external host, and the like.

  The regulator 100 is the regulator of the present embodiment described with reference to FIGS. 1 to 3, etc., and receives the external power supply voltage VDDE and supplies the power supply voltage VDDA after voltage adjustment to the power-on reset circuit 110 and the control circuit 50. . The power-on reset circuit 110 outputs a power-on reset signal XRST to the control circuit 50 when the external power supply voltage VDDE is turned on.

  According to the present embodiment, the standby mode (sleep mode) is realized by stopping the clock supply to the control circuit 50 and the like and setting the operations of the reception circuit 30 and the transmission circuit 40 to the disabled state. . In this standby mode, power consumption in the regulator 100 and the power-on reset circuit 110 is dominant in power consumption of the integrated circuit device.

  In this regard, according to the present embodiment, the number of current paths in the regulator 100 and the power-on reset circuit 110 can be minimized. Therefore, power consumption in the regulator 100 and the power-on reset circuit 110 can be minimized, and power consumption in the standby mode of the integrated circuit device can be reduced.

  The integrated circuit device to which the regulator of this embodiment is applied is not limited to the wireless communication IC as shown in FIG. 18, and can be applied to various types of integrated circuit devices. For example, the present invention can be applied to a detection device that detects a desired signal from a sensor signal from a sensor. Examples of such a detection device include a device that detects a physical quantity such as angular velocity information and acceleration information using a vibrator.

7). Electronic Device FIG. 19 shows a configuration example of an electronic device including the integrated circuit device 310 of this embodiment. The electronic device includes an antenna ANT, an integrated circuit device 310, a host 320, a detection device 330, a sensor 340, and a power supply unit 350. Note that the electronic apparatus according to the present embodiment is not limited to the configuration shown in FIG. Various modifications such as addition of) are possible.

  The integrated circuit device 310 is a wireless circuit device realized with a circuit configuration as shown in FIG. 18, and performs a signal reception process from the antenna ANT and a signal transmission process to the antenna ANT. The host 320 controls the entire electronic device, and controls the integrated circuit device 310 and the detection device 330. The detection device 330 performs various detection processes (physical quantity detection processes) based on sensor signals from the sensor 340 (physical quantity transducer). For example, processing for detecting a desired signal from the sensor signal is performed, and the digital data after A / D conversion is output to the host 320. The sensor 340 is, for example, a smoke sensor, an optical sensor, a human sensor, a pressure sensor, a biological sensor, a gyro sensor, or the like. The power supply unit 350 supplies power to the integrated circuit device 310, the host 320, the detection device 330, and the like.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, in the specification or the drawings, it is described at least once together with different terms having a broader meaning or the same meaning (first differential input terminal, second differential input terminal, first power supply node, second power supply node, etc.). The terminology used (non-inverting input terminal, inverting input terminal, VSS node, VDD node, etc.) can be replaced with the different terminology anywhere in the specification or the drawings. Further, the configurations and operations of the regulator, the integrated circuit device, and the electronic device are not limited to those described in this embodiment, and various modifications can be made.

AM amplifier circuit, RB1, RB2 first and second resistors, C0 phase compensation capacitor,
DF differential section, QB output section, TB1, TB2 first and second differential transistors,
TDR drive transistor, ISB1, ISB2 current source,
CC phase compensation capacitor, RC phase compensation resistor,
30 receiving circuit, 32 mixer, 34 filter section,
36 demodulation circuit, 40 transmission circuit, 46 modulation circuit, 48 clock generation circuit,
50 control circuit, 52 link layer circuit, 54 host I / F,
100 regulator, 110 power-on reset circuit, 120 logic circuit,
310 integrated circuit device, 320 host, 330 detection device,
340 sensor, 350 power supply

Claims (18)

A differential amplifier circuit having an offset voltage between the non-inverting input terminal and the inverting input terminal;
A first resistor and a second resistor provided in series between an output node of the amplifier circuit and a first power supply node;
A phase compensation capacitor having one end connected to a connection node of the first resistor and the second resistor;
The amplifier circuit is
A differential section having a first differential transistor, a second differential transistor, a current mirror circuit, and a first current source;
An output unit connected to an output node of the differential unit;
Including
The output unit is
A driving transistor controlled by an output node of the differential section;
A second current source provided in series with the drive transistor and provided in parallel with the first resistor and the second resistor;
Including
A signal at the connection node of the first resistor and the second resistor is fed back to the non-inverting input terminal of the amplifier circuit;
A regulator characterized in that a signal at the output node of the amplifier circuit is fed back to the inverting input terminal of the amplifier circuit to generate a constant voltage at the output node . In claim 1,
  When the offset voltage of the differential circuit is VOFF, the resistance value of the first resistor is R1, and the resistance value of the second resistor is R2, VREG = VOFF × {(R1 + R2) / R1} A regulator characterized by generating a constant voltage VREG. In claim 1 or 2,
  The other end of the phase compensation capacitor is connected to the first power supply node or the second power supply node to which the source of the driving transistor is connected. In any one of Claims 1 thru | or 3 ,
Wherein a conductive gate electrode of the first differential transistor, by varying the conductivity of the gate electrode of the second differential transistors, regulators, characterized in that the offset voltage is set. In any one of Claims 1 thru | or 4 ,
The W / L ratio of the first differential transistor is different from the W / L ratio of the second differential transistor, or the W / L ratio of the first current mirror transistor constituting the current mirror circuit. wherein by varying the W / L ratio of the transistor for the second current mirror constituting the current mirror circuit, regulator, characterized in that the offset voltage is set to. In any one of Claims 1 thru | or 5 ,
The first current source of the differential portion,
A first current source resistor having one end connected to the first power supply node;
A depletion-type first current source transistor having a source connected to the other end of the first current source resistor and a gate connected to the first power supply node;
The threshold voltage of the first current source transistor has a negative temperature characteristic;
The regulator characterized in that a resistance value of the first current source resistor has a positive temperature characteristic. In claim 6 ,
The regulator according to claim 1, wherein the first current source resistor is an N-well resistor formed by an N-well. In claim 7 ,
The first resistor and the second resistor are poly resistors formed by a polysilicon layer,
The regulator is characterized in that the first resistor or the poly resistor as the second resistor is laid out on the formation region of the first current source resistor as the N well resistor. In any of claims 6 to 8 ,
The second current source of the output unit,
A second current source resistor having one end connected to the first power supply node;
A depletion type second current source transistor having a source connected to the other end of the second current source resistor and a gate connected to the first power supply node;
The threshold voltage of the second current source transistor has a negative temperature characteristic;
A regulator characterized in that a resistance value of the second current source resistor has a positive temperature characteristic. In claim 9 ,
The second current source resistor is an N well resistor formed by an N well. In claim 10 ,
The first resistor and the second resistor are poly resistors formed by a polysilicon layer,
The regulator is characterized in that the first resistor or the poly resistor as the second resistor is laid out on a formation region of the second current source resistor as the N well resistor. In any one of Claims 1 thru | or 11 ,
When the resistance value of the first resistor is R1 and the resistance value of the second resistor is R2, the resistance ratio R2 / R1 has a temperature characteristic that cancels the temperature characteristic of the offset voltage. And regulator. Integrated circuit device which comprises a regulator according to any one of claims 1 to 12. In claim 13 ,
A logic circuit to which a constant voltage generated by the regulator is supplied as a power supply voltage;
An integrated circuit device comprising: a power-on reset circuit that supplies a constant voltage generated by the regulator as a power supply voltage and outputs a reset signal to the logic circuit. In claim 14 ,
The power-on reset circuit is
A voltage from a voltage dividing tap set to the first resistor or the second resistor is input to an inverting input terminal, the first power supply node is connected to a non-inverting input terminal, and the non-inverting input terminal An integrated circuit device comprising a comparator having an offset voltage between the inverting input terminals. In claim 15 ,
The differential unit included in the comparator includes a third current source,
The third current source is
A third current source resistor having one end connected to the first power supply node;
A depletion type third current source transistor having a source connected to the other end of the third current source resistor and a gate connected to the first power supply node;
The threshold voltage of the third current source transistor has a negative temperature characteristic;
The integrated circuit device, wherein the resistance value of the third current source resistor has a positive temperature characteristic. In claim 16 ,
The output part of the comparator includes a fourth current source,
The fourth current source is:
A fourth current source resistor having one end connected to the first power supply node;
A depletion type fourth current source transistor having a source connected to the other end of the fourth current source resistor and a gate connected to the first power supply node;
The threshold voltage of the fourth current source transistor has a negative temperature characteristic;
The integrated circuit device according to claim 4, wherein a resistance value of the fourth current source resistor has a positive temperature characteristic. An electronic device comprising the integrated circuit device according to claim 13 .

Images