JP5485910B2 - Non-volatile status indicator switch - Google Patents

Description

  The present invention relates generally to the use of relays in aircraft electrical systems, and more particularly to systems and methods for storing and displaying fault conditions detected in relays.

  An important function in an aircraft electrical system is to generate, regulate and distribute power throughout the aircraft. There are several different power sources in the aircraft, which are used to power the aircraft electrical system. These power sources may include engine driven AC generators, auxiliary power units, external power sources and ram air turbines. Aircraft electrical components operate at many different voltage levels using both alternating current and direct current. However, most aircraft systems use 400Hz, 115V AC or 28V DC. In addition, some aircraft use 26V AC for lighting purposes. The DC power supply is typically provided by a “self-exciting” generator that includes an electromagnet, where the power is generated by a rectifier, so that the output voltage is regulated to 28V DC. Typically, AC power with a phase voltage of 115V is generated by an alternator, typically in a three-phase system and at a frequency of 400 Hz.

  In aircraft electrical systems, relays are commonly used to control the supply of power to various loads. A typical relay includes a contact for connecting to a power source and a contact for connecting to a load. The electromechanical contact is closed by the magnetic field generated by the coil. The coil is excited by a control current provided to the relay via a control input. Closing the contact allows a load current to flow.

  Failures in aircraft electrical systems can be dangerous. In particular, a failure in an electrical load such as a fuel pump may result in an explosion. Examples of possible faults in aircraft electrical systems include ground faults (short to ground) and arc faults (short between power lines). A ground fault results in a net current imbalance, and an arc fault does not result in a net current imbalance.

  Various safety devices are used for aircraft electrical systems. These safe delivery devices include universal safety devices (UFI), arc fault circuit safety devices (AFCI), and thermally sensed circuit breakers (CBs) commonly installed in the current cockpit. Can be included.

  The present invention relates to a non-volatile status indicator switch. In one embodiment, the present invention relates to an aircraft electrical system comprising a fault detection circuit connected to a relay and a fault indicator circuit connected to the fault detection circuit and a control input of the relay, wherein the fault indicator The circuit includes a non-volatile memory element, the failure detection circuit is configured to detect a failure and provide a signal indicating the failure to the failure indicator circuit, and the failure indicator circuit supplies a predetermined control signal to the relay And storing information indicating the detection of the failure in the nonvolatile memory element so as to respond to a signal indicating the failure.

  In another embodiment, the invention relates to a method for controlling a relay in an aircraft electrical system, the method detecting at least one fault, using the solid-state non-volatile memory to at least one fault. Storing at least one fault, maintaining the at least one fault record in the absence of power, clearing the at least one fault when a reset signal is received, and at least one fault stored. Open the relay to stop the flow of power to the load in the aircraft electrical system.

  In yet another embodiment, the present invention is connected to an input logic circuit configured to receive a fault signal indicating detection of a fault and a reset signal indicating a request for fault reset, and to an output of the input logic circuit. A fault indicator circuit including an electromechanical switch, wherein the output of the input logic circuit is generated from the fault signal and the reset signal, and the electromechanical switch controls the relay in response to the output of the input logic circuit The electromechanical switch is surrounded by a shielding material that reduces the influence of an external magnetic field during its operation.

1 is a schematic diagram of an aircraft electrical system according to an embodiment of the present invention. It is the schematic of the failure protected relay which concerns on one Embodiment of this invention. 1 is a schematic diagram of a fault indicator circuit according to an embodiment of the present invention. FIG. FIG. 2 is a schematic diagram of a power supply that may be used to power a fault indicator circuit according to one embodiment of the present invention. 6 is a flowchart illustrating a method for controlling the operation of a relay in response to failure detection in accordance with one embodiment of the present invention. 2 is a schematic diagram of input logic and non-volatile memory that may be used in a fault indicator circuit in accordance with one embodiment of the present invention. FIG. FIG. 7 is a timing diagram showing an operation for storing a failure of the input logic circuit and the nonvolatile memory element of FIG. 6. FIG. 7 is a timing diagram illustrating an operation for clearing a stored failure of the input logic circuit and the non-volatile memory element of FIG. 6. FIG. 4 is a schematic diagram of a drive circuit used in a fault indicator circuit according to an embodiment of the present invention. FIG. 3 is a schematic diagram of a relay control switch used in a fault indicator circuit according to an embodiment of the present invention. FIG. 3 is a schematic diagram of a visual indicator used in a fault indicator circuit according to an embodiment of the present invention. It is a circuit diagram of a failure indicator circuit according to an embodiment of the present invention. FIG. 4 is a circuit diagram of a power supply assembly for use with a fault indicator circuit according to an embodiment of the present invention. 1 is a schematic block diagram of a fault indicator circuit including an electromechanical switch having an electromagnetic shield in accordance with one embodiment of the present invention. FIG. FIG. 4 is a schematic block diagram of a fault indicator circuit including a visual indicator that indicates a non-fault condition in accordance with an embodiment of the present invention. 2 is a schematic block diagram of a fault indicator circuit including a visual indicator that indicates a fault condition in accordance with an embodiment of the present invention. FIG.

  Referring to the drawings, there is shown an embodiment of a fault indicator circuit according to the present invention that may include a relay for use in an aircraft electrical system. The fault indicator circuit can be used to interrupt a control signal provided to the relay when a fault condition is detected. The interruption of the control signal allows the relay to disconnect power from the load. In some embodiments of the present invention, the fault indicator circuit includes a non-volatile memory for storing information indicating the presence of a fault. When power is removed from the fault indicator, the non-volatile memory stores fault status information. When power is restored to the relay, the fault indicator circuit can prevent the relay from being activated until the fault is cleared and the monitoring device is manually reset.

  In many embodiments, the fault indicator circuit is implemented using solid state circuit components. For example, various solid state non-volatile memory elements can be used to store fault conditions. In other embodiments, the fault indicator circuit can be implemented using an electromechanical switch. An electromagnetic shielding material can be used to shield the electromechanical switch from magnetic field interference.

  The solid and electromechanical fault indicator circuits are each typically provided with a signal indicating fault detection from a fault detection circuit that monitors the relay with which the fault indicator switch is associated. The fault indicator then stores the fault in non-volatile memory and interrupts control of the relay in response to the fault. The fault indicator circuit according to embodiments of the present invention further includes a reset mechanism that can be used to clear the non-volatile memory. For a solid state fault indicator circuit, the reset mechanism can include a reset signal that prompts to clear a fault stored in non-volatile memory. For an electromechanical fault indicator switch, the reset mechanism includes changing the physical position of the electromechanical switch, for example, by pressing a button.

  Many embodiments of the fault indicator circuit include a sensor indicator to alert an operator or maintenance personnel of the presence of a fault. The sensor indicator can include a visual or audio (audio) indicator. Solid fault indicator circuit embodiments can include light emitting diodes (LEDs) as visual indicators. An embodiment of a fault indicator circuit that uses an electromechanical switch may include a pop-up button that indicates the presence of a fault.

  FIG. 1 is a schematic diagram of an aircraft electrical system 100 according to one embodiment of the present invention. The aircraft electrical system 100 includes a power supply 101 that is connected to a load 103 via a fault protected relay 105. The fault protected relay includes a fault detection circuit 110 connected to a fault indicator circuit 120 and a relay 140. A fault indicator circuit 120 is also connected to the relay 140. The fault protected relay 105 includes an external control input 152, a ground input 154 and a reset input 155.

  The relay 140 controls the flow of power from the power source to the load. This relay is typically controlled by an external control signal supplied to the control input 152. During normal operation, the fault indicator circuit 120 sends an external control signal to the relay control input 142. If the fault detection circuit detects a fault, the fault indicator circuit 120 can interrupt the operation of the relay by providing a relay control input that ignores the external control signal and instead opens the relay circuit.

  In the illustrated embodiment, fault detection circuit 110 monitors a relay for indication of faults in the aircraft electrical system. The fault detection circuit according to the present invention can detect one or more various different faults. If the failure detection circuit 110 detects a failure, the failure detection circuit provides a failure signal to the failure indicator circuit 120. The fault signal includes information indicating the presence or absence of a fault that is currently occurring.

  If a failure is detected by the failure detection circuit 110, the failure indicator circuit 120 blocks the signal that controls the relay 140 and stores the failure in a non-volatile memory. Non-volatile memory preserves the presence of a fault when power is lost. In some embodiments, a reset signal is used to clear a fault from the non-volatile memory. The reset signal may be provided by an aircraft mechanic after confirming that the relay circuit is ready for safe operation.

  Relay 140 can be implemented using all commercially available relays or relays specifically designed for a particular aircraft electrical system 100. The fault indicator circuit 120 can be implemented using a logic circuit or a microprocessor connected to a display. In many embodiments, the indicator is any type of visual indicator such as a light emitting diode (LED) or a pop-up switch. The fault detection circuit 110 can be implemented using a current imbalance detection circuit such as a ground fault detection and / or arc fault detection circuit. Other suitable circuits include overcurrent detection circuits and more sophisticated circuits such as circuits that detect faults using current and / or power profiles. In many cases, the fault detection circuit can be implemented using any circuit capable of detecting abnormal operation within the aircraft electrical system 100.

  FIG. 2 is a schematic diagram of the failure protected relay 200. The failure protected relay 200 includes a failure detection circuit 210, a failure indicator circuit 220, a power source 230 and a relay 240. The control line 252 is connected to the fault protected relay 200 and carries the control signal to the fault protected relay. The output 256 of the fault protected relay 200 is connected to a load (not shown). The failure detection circuit 210 is connected to the failure indicator circuit 220 and the relay 240. Relay 240 is also connected to fault indicator circuit 220. The power supply 230 is connected to a control line 252 that carries control signals, a ground 255, and a fault indicator circuit 220.

  The fault protected relay 200 operates in the same manner as the relay 105 of FIG. 1 and controls the flow of power from the power source to the load using the relay 240. Relay 240 receives an external control signal via fault indicator circuit 220. The current through the relay is monitored by a fault detection circuit 210 that provides a signal indicating the fault condition to the fault indicator circuit 220 via output 253. If a failure is detected, the failure indicator circuit 220 generates a control signal that inhibits the relay 240 from supplying power to the load.

  In many embodiments, fault indicator circuit 220 controls the operation of relay 240 by opening or closing the current loop that excites the relay coil. The fault indicator circuit is configured to receive a signal indicating a fault from the fault detection circuit. Depending on whether a fault exists, the fault indicator circuit completes the current loop or breaks the current loop. In some embodiments, the fault indicator circuit completes the current loop when no fault exists. External control signal 252 also controls the operation of the relay. The external control signal can be generated in response to a pilot attempting to turn on an aircraft electrical component controlled by a relay. Upon detection of a fault, the fault indicator circuit breaks the current loop. In some embodiments, the fault indicator circuit provides a predetermined control signal as an alternative to the external control signal. The fault indicator circuit continues to provide a predetermined control output signal until a reset command is received. Reset signal 254 is supplied by maintenance personnel who have confirmed that the relay circuit is ready for safe operation. In one embodiment, the reset signal is provided by another circuit.

  A power supply 230 provides power to the components used in the fault indicator circuit 220. The power supply receives a relatively small amount of current from the external control signal 252 and provides power to the fault indicator circuit.

  The relay 240 and fault detection circuit 210 can be implemented according to known principles using any type of circuit that is commercially available or specifically designed. The circuit used to implement the fault indicator circuit according to an embodiment of the present invention is shown below.

  FIG. 3 is a schematic diagram of a failure indicator circuit 320 according to one embodiment of the present invention. Fault indicator circuit 320 includes an input logic circuit 322, a non-volatile memory element 324, and a drive circuit 326 that are connected together in series. The fault indicator circuit further includes a switch 328 and a visual indicator 329 connected together to the drive circuit 326. The fault 350 and reset 354 inputs to the fault indicator circuit are provided to the input logic circuit 322. The fault indicator switch control input 352 and control output 356 are connected to the switch 328.

  The fault indicator circuit 320 is configured to receive a fault signal from the fault input 350, a reset signal from the reset input 354, and a control in signal from the control input 352. Based on the value of the input signal, fault indicator circuit 320 can determine that a fault exists, visually indicate the presence of such fault, and / or open the relay. In the following, further details of these operations will be described.

  In the illustrated embodiment, the input logic circuit 322 is connected to a line that provides reset and fault signals. The fault signal indicates the presence of a current fault. The reset input 354 provides a reset signal that instructs the memory of the fault indicator circuit 320 to clear all records indicating a previous fault. Input logic 322 uses these signals to determine whether a current fault is reported and whether past faults should remain in memory or be cleared. The output of the input logic circuit 322 is provided to a non-volatile memory element 324 that is configured to provide a signal indicative of a system fault condition.

  Non-volatile memory element 324 stores system fault conditions and responds to signals received from input logic circuit 322. The non-volatile nature of the non-volatile memory element makes it possible to maintain a faulty state even when there is no power. As a result, once the fault is stored in the non-volatile memory, the non-volatile memory element 324 continues to indicate the presence of the fault to the elements downstream of the fault indicator circuit 320. The fault condition stored in the non-volatile memory element is determined by the signal received by the input logic circuit 322. When the input logic circuit instructs the non-volatile memory element to reset the fault stored in the memory, the non-volatile memory element clears all stored faults. Until the input logic circuit 322 indicates that a fault has been detected thereafter, a fault-free state is maintained and communicated to downstream elements of the fault indicator circuit 320.

  The drive circuit 326 receives a signal indicating the presence or absence of a failure from the nonvolatile memory element 324. This signal may indicate a current fault or a past open fault. Drive circuit 326 provides an input to switch 328 in response to the presence of a fault to prevent a control input signal from being applied to the control output line. In addition, the drive circuit indicates the presence of a fault by activating the visual indicator 329. In some embodiments, as a result of receiving the reset input by fault indicator circuit 320, drive circuit 326 stops the visual indicator and closes switch 328 to pass the signal on the control input line to the control output line. . In other embodiments, the visual indicator is manually reset. In some embodiments, a reset input is provided to the fault indicator circuit 320 when the visual indicator is manually reset.

  The switch 328 is turned on / off based on a signal received from the drive circuit 326. The switch 328 is connected to a control line for carrying a control-in signal to this switch and a control-out signal from this switch. Switch 328 is configured to open or close a circuit between control input 352 and control output 356. In summary, the switch can block the control signal. When the control output is connected to the control input of the relay, the absence of the control signal opens the relay and prevents current from flowing from the power source to the load.

  As discussed above, visual indicator 329 is activated and deactivated by a signal received from drive circuit 326. The non-volatile memory element stores the fault, and the output of the drive circuit 326 activates a visual indicator to indicate the presence of the fault to the operator. In the illustrated embodiment, drive circuit 326 activates both switch 328 and visual indicator 329 simultaneously. Thus, when the drive circuit 326 receives a failure indication from the non-volatile memory, the drive circuit drives the switch to open and simultaneously drives the visual indicator to indicate the presence of the failure to a human operator. In embodiments using an electronic circuit indicator, the drive circuit stops the visual indicator when a reset signal is received by the input logic circuit. In embodiments that use an electromechanical visual indicator, the visual indicator must be manually reset by the operator.

  The input logic circuit 322 can be implemented using a combination device such as a logic gate. Filter elements and switches can be included in the logic circuit 322 as well. The nonvolatile memory element 324 can be realized using various 1-bit nonvolatile memory elements. One embodiment of the present invention uses a potentiometer as the nonvolatile memory element 324. This potentiometer is a digital potentiometer. The drive circuit 326 can be implemented using devices such as transistors and logic gates. Switch 328 can be implemented using devices such as transistors and filters. The visual indicator 329 can be implemented using a transistor or LED or other type of switch connected to an electromechanical pop-up indicator. The element of the fault indicator circuit may include a filter component for removing noise such as high frequency current. In some embodiments, the fault indicator component is implemented using a suitably configured microprocessor, gate array or ASIC.

  FIG. 4 is a schematic diagram of a power source 430 that can be used to power a fault indicator circuit, in accordance with one embodiment of the present invention. In the illustrated embodiment, the power source 430 is connected between the control line and ground. The control line and ground connected to the power supply are further connected to other elements such as a fault indicator circuit. In many embodiments, the voltage signal can be provided using at least one delivery line from a power source. In many embodiments, the power supply uses a portion of the current flowing through the control line and converts this current into a stable voltage signal. The voltage signal generated by the power supply can be used to drive various components of the fault indicator circuit. In the illustrated embodiment, supply voltage Vcc is generated by power supply 430 and used by devices in the fault indicator circuit. In many embodiments, the value of Vcc is 5V. In other embodiments, other output voltages are provided. The power supply 430 according to embodiments of the present invention can be implemented using all commercially available power supply types or known power supply circuit structures.

  FIG. 5 is a flowchart illustrating a method for controlling the operation of a relay in response to detection of a failure in accordance with one embodiment of the present invention.

  Method 500 includes determining whether a fault is currently detected (510). If a fault is currently detected, the presence of the fault is stored in memory (520) and the relay is opened (530). If it is determined that no fault is currently detected (510), a determination is made as to whether a previous fault exists (540). If no current failure is detected and no past failures exist, the memory is reset (or cleared) (550) and the relay is allowed to perform normal operation (560).

  If it is determined that a previous fault exists (540), then a further determination is made as to whether the previous fault has been repaired (570). If the fault has not been repaired (570), the memory of the presence of the fault is maintained (520) and the relay is opened (530). On the other hand, if it is determined that the fault has already been repaired (570), the memory is reset (550) and the relay is allowed to operate normally (560). After opening the relay (530) or allowing normal operation (560), in order to continuously check for faults or resets, the method determines whether a fault is currently detected ( 510).

A decision table can be used to describe the method for controlling the operation of the relay according to the embodiment of FIG. Table 1 below shows the inputs and outputs to the fault indicator circuit according to one embodiment of the present invention. Input variables include fault status, current memory status, and reset signal. The output variables include the value of the next state of the memory and the open or closed state of the switch that supplies power to the relay. In Table 1, failure = 0 indicates that there is currently no failure, and failure = 1 indicates a failure. Memory = 0 indicates that no fault is stored, memory = 1 indicates that a fault is stored, reset = 0 indicates that there is no current reset signal, reset = 1 indicates a request to reset past faults, and switches = 0 indicates an open switch, and switch = 1 indicates a closed switch.

  In the first two rows, there is no memory of the current failure or the previous failure. Therefore, the next state of the memory does not change regardless of the reset value. In the illustrated table, the output of the switch is an inverted version of the memory output. Thus, while the memory is cleared, the switch is closed and the relay is allowed to carry power to the load. In line 3, there is currently no failure but there is a stored failure that has not been reset. Thus, the stored fault is maintained and the switch is open. In line 4, there is no current failure and there are stored failures and reset requests. Accordingly, the memory is cleared and the switch is closed to indicate a failure-free state. In the last four rows, a fault is currently detected. Thus, regardless of the previous state of memory or reset, it indicates the presence of a fault and the switch is opened.

  The operations summarized in Table 1 can be achieved by using logic circuits and non-volatile memory elements in accordance with embodiments of the present invention. Here, the logic circuit is used to combine signals indicating failure and reset and to provide the proper input to the memory element to maintain the failure state.

  As discussed above, the fault detection circuit can be used to detect the presence of a fault in the relay device, and the fault indicator circuit can be used to store the fault. Non-volatile memory elements can be used to maintain memory of faults in the absence of power. One possible choice for a non-volatile memory element is a potentiometer that includes a non-volatile memory. The potentiometer can be a digital potentiometer. The resistance of the potentiometer changes in response to the control signal and is stored in a non-volatile memory in the potentiometer. The presence of a fault is set corresponding to one resistance value, and the absence of a fault is set corresponding to another resistance value. In other embodiments, other types of non-volatile memory elements are used. In one embodiment, an EEPROM is used as the non-volatile memory element.

  The logic circuit can be used to provide an appropriate input to the non-volatile memory element in response to a failure and reset input to the logic circuit. The nature of the logic circuit depends on the nature of the nonvolatile memory element. For example, when a potentiometer is used as a non-volatile memory element, the logic circuit generates an output due to the presence of a fault, and the potentiometer is pushed to a high resistance value by this output. Upon receipt of the reset signal, the logic circuit generates an output and sets the potentiometer to a low resistance value.

  FIG. 6 is a schematic diagram of an input logic circuit 622 and a non-volatile memory element 624 used in a fault indicator circuit according to one embodiment of the present invention. As discussed above, the nature of the input logic circuit 622 depends on the nature of the nonvolatile memory element 624. In the illustrated embodiment, the non-volatile memory element 624 is a digital potentiometer having a memory and a counter. This potentiometer has three inputs including the following signals. That is, these signals indicate whether a potentiometer is selected, whether the counter should be counted up (high) or counted down (low) (active low chip selection), and whether the counter should be increased. (Active low increment). The counter increment signal often appears as a “pulse train”. The potentiometer can only change when a device is selected. Further, for each pulse in the pulse train, the counter counts up or down depending on the state of the up / down signal. The memory maintains the counter value at the end of the pulse train. This value is stored until the device is selected again and another pulse train is received. In some embodiments, a high (large) count is used to indicate a failure and a low (small) count is used to indicate that there is no failure.

  In an embodiment using a potentiometer as the non-volatile memory element 624, the logic circuit 622 responds to a fault and resets the input signal by generating an input for storing the proper information in the potentiometer. It is configured. In the illustrated embodiment, the input logic circuit uses the fault and reset inputs to generate device selection signals, count up / down signals, and pulse trains. In other embodiments, the non-volatile memory has different inputs and the input logic circuit generates the appropriate signals to supply to these inputs.

  In the embodiment shown in FIG. 6, the non-volatile memory element 624 can be implemented using an Intersil (TM) X9315 digitally controlled potentiometer manufactured by Intersil Americas, Inc. of Milpitas, California. The specification and operating principle of this potentiometer are described in the data sheet FN8179.1 dated 15 September 2005, which is incorporated into the present application by reference. The Intersil (TM) potentiometer further includes a counter and a non-volatile memory. Further, the Intersil (TM) potentiometer includes first, second and third input terminals 1, 2, 7 and an output terminal 5. Although not shown, the non-volatile memory device 624 further includes terminals connected to the Vcc and Vss operating voltages.

  Intersil (TM) potentiometers typically operate in the manner described above. An increment signal is supplied to the input terminal 1, an up / down signal is supplied to the input terminal 2, and a device selection signal is supplied to the input terminal 7. The increment signal controls the increase or decrease of the digital potentiometer. The up / down signal indicates whether the resistance of the non-volatile memory element should be increased to indicate a failure or decreased to indicate no failure. The device selection signal enables the potentiometer operation. The counter value is stored in non-volatile memory when no device is selected.

  In the embodiment shown in FIG. 6, input logic circuit 622 generates the necessary inputs to store and clear information using an Intesil ™ digitally controlled potentiometer. The input logic circuit 622 has two inputs (602, 603), three outputs (631, 632, 633), a NOR gate 601, a NAND gate (611, 612, 613, 614), an inverter 605, and a delay element (604, 606). , 607). Inputs 602 and 603 are connected to the input of NOR gate 601 and to reset and fault input signals, respectively. Input 602 is further connected to output 632, which is connected to pin 2 of digital potentiometer 624 (up / down input that counts down when low).

  The output of the NOR gate 601 is connected to both inputs of the NAND 611 (actually operating as an inverter). The output of the NAND 611 (node A) is connected to one input of the NAND 612. The output of the NAND 612 is connected to the second input (ie, feedback) of the NAND 612 via the delay element 604 and is connected to the first input of the NAND 613. The output of the NAND 613 is connected to the output 631, and the output 631 is connected to pin 1 (active low increment input) of the digital potentiometer 624. The node A is further connected to a delay element 606 connected to the inverter 605. The output of the inverter 605 is connected to the second input of the NAND 613 and the delay element 607. The output of the delay element 607 is connected to the first input of the NAND 614. Node A is further connected to the second input of NAND 614. The output of the NAND 614 is connected to the output 633, and this output 633 is connected to pin 7 active low (chip or device selection) of the digital potentiometer 624.

  In operation, node A is a logical combination of reset signal (R) and fault signal (F) inputs and is equivalent to “R + F” (ie, R · OR · F). As with the reset input, the fault input is not high, so assuming a typical steady state operation indicating no fault and no reset request, "R + F" or node A is low. When node A is low, the output of NAND 612 is high in the steady state and the output of inverter 605 is also high in the steady state. Thus, during steady state operation defined by no failure or reset (ie, node A is low), the output of NAND 613 is low along with output 631 and pin 1 of the digital potentiometer 624 (active low increment input). It becomes. Further, during steady state operation when node A is low, the output of NAND 614 goes high with output 631 and pin 7 (active low chip select input) of digital potentiometer 624. Thus, during steady state operation when node A is low, the digital potentiometer device is not selected and does not respond to changes in the increment input (pin 1) and up / down input (pin 2).

  When the fault input transitions from low to high indicating a current fault, node A transitions from low to high. Since the output of NAND 612 was previously high for steady state operation, the output of delay element 604 goes high. Next, the output of NAND 612 goes low because both inputs are high. After a delay, the output of delay element 604 goes low and, as a result, the output of NAND 612 goes high again. Thus, after node A transitions from low to high, the output of NAND 612 oscillates at a frequency that depends on the delay period provided by delay element 604. In one embodiment, the frequency of the oscillating output of NAND 612 (similar to a clock) is twice the delay period of delay element 604. As node A transitions from low to high, the output of inverter 605 goes low after a delay caused by delay element 606. Until the output of the inverter 605 becomes low (that is, during the delay caused by the delay element 606), the output (increment signal) of the NAND 613 is an inversion of the oscillation output (clock) of the NAND 612. When the delay period of the delay element 606 has passed, the output of the inverter 605 goes low, and as a result, the output of the NAND 613 (increment signal) remains high.

  Before node A transitions from low to high from steady state, the output of delay element 607 is high and the output of NAND 614 is high. Therefore, as soon as node A transitions from low to high, the output of NAND 614 goes low and remains low during the delays from both delay elements 606 and 607. At this time, the output of the delay element 607 goes low, so the output of the NAND 614 returns to high again. Thus, when node A transitions from low to high, an active low pulse is provided by the output of NAND 614 as a chip or device selection. The period of the active row chip selection pulse is determined by adding the delays generated by the delay elements 606 and 607.

  FIG. 7 shows a timing diagram illustrating the operation of the input logic circuit and non-volatile memory element of FIG. 6 during a failure. This figure shows the reset (602) and fault (603) input signals, node A (R + F), the outputs of NAND gates 612, 613, and 614, and the output of digital potentiometer 624 at pin 5 from top to bottom. Represents. As discussed above, for steady state operation with reset and fault low, node A is low, NAND 612 output is high, NAND 13 output is low, and NAND 14 output. Is high. The digital potentiometer output (pin 5) indicates no failure, in which case the potentiometer's internal resistance and steady state corresponding output voltage are high enough to be supplied to the drive circuit 326 (see FIG. 3). .

  When the fault signal transitions from low to high to indicate a current fault, node A goes high, NAND 612 oscillates at a period determined by delay element 604, and NAND 13 (to the active low increment input of digital potentiometer 624). ) Outputs an inverted type of NAND 612 during which the hair is constant by the delay element 606, and NAND 614 (input to the active low chip selection input of the digital potentiometer 624) is a period determined by the delay elements 606 and 607. , Become low. In response, the digital potentiometer 624 decreases the internal resistance and the corresponding output voltage at pin 5 at each falling edge of the increment signal while the chip select signal is low. The signal trace for pin 5 shown in FIG. 7 illustrates these four transitions that result from reducing the output voltage.

  The digital potentiometer 624 actually stores the set resistance of the potentiometer at the rising edge of the chip select signal while the increment signal is high so that the value is not lost if the digital potentiometer loses power. The value of the output voltage at pin 5 is stored. If a reset occurs after the occurrence of the fault but before the fault is cleared, this reset has no effect on the output of the digital potentiometer, as shown in FIG. In some embodiments, the operation of the input logic circuit and the non-volatile memory is consistent with Table 1 above.

  FIG. 8 is a timing diagram showing an operation for clearing a failure in response to a reset of the input logic circuit and the nonvolatile memory element shown in FIG. From top to bottom, this figure shows the reset (602) and fault (603) input signals, node A (R + F), the outputs of NAND gates 612, 613, 614, and the digital potentiometer 624 at pin 5. Output is shown. As discussed above, for steady state operation with reset and fault low, node A is low, NAND 612 output is high, NAND 13 output is low, and NAND 14 output is High. The output of the digital potentiometer (pin 5) indicates a previous failure, where the internal resistance of the potentiometer and the corresponding output voltage in steady state are low compared to the internal default position (see FIG. 7).

  Except when the reset signal transitions from low to high to indicate a request to clear the fault, the up / down signal (reset) instructs the digital potentiometer to increment the output at pin 5 as shown. Thus, the input logic functions as described above with respect to FIG. 7 to indicate a failure. Digital potentiometer 624 again stores the output voltage value at pin 5 at the rising edge of the chip select signal while the increment signal is high, by actually storing the resistance setting value of the potentiometer. Here, the digital potentiometer stores a high value indicating that there is no failure and that an actual failure has been cleared.

  In some embodiments, the duration of delay element 606 is set such that a predetermined integer number of oscillations are delivered to the active low increment input of digital potentiometer 624. In one embodiment, the predetermined integer value of oscillation is equal to or greater than the maximum count value of the digital potentiometer. In one embodiment, the oscillation generated by delay element 604 occurs at a frequency of 71 KHz, the delay period for delay element 606 is 10 ms, and the delay period for delay element 607 is 0.1 ms.

  The various logic gates used in the input logic circuit 622 can be implemented by commercially available NOR, NAND and NOT gates. The NOR gate can be realized by using a low power configurable multifunction gate (Philips Semiconductor (TM) 74LVC1G57) manufactured by Philips Semiconductor of Washington, DC. The NAND gate can be realized by using a dual 2-input NAND gate with a Schmitt-Trigger input (TexasInstrument (TM) Sn74LVC2G132) manufactured by Texas Instruments of Dallas, Texas. The NOT gate can be implemented using a triple inverting Schmitt trigger (Philips Semiconductor (TM) 74LVC3G14) with a 5V tolerant input. The delay period for the delay element 604 can be generated using an RC circuit having a resistance of 20 KΩ and a capacitance of 500 pF. The delay with respect to the delay element 606 can be realized by using an RC circuit having a resistance of 49.9 KΩ and a capacitance of 10 μV and 0.1 μF. The delay with respect to the delay element 607 can be realized by using an RC circuit including a resistance of 100 KΩ and a capacitance of 0.01 μF at 10V.

  In the embodiment shown in FIG. 6, an input logic circuit having a reset and fault input signal operates to store and clear fault conditions with a digital potentiometer. In other embodiments, other non-digital potentiometers with other digital potentiometers or memories can be used. In one embodiment, the input logic can be used with an EEPROM or other non-volatile memory device. In one embodiment, a flip-flop type component can be used as a non-volatile memory element with suitable input logic. In one embodiment, the flip-flop type or 1-bit non-volatile memory component can be implemented as an ASIC. In other embodiments, the flip-flop type components can be implemented as programmable logic devices. In another embodiment, the input logic and flip-flop type components can be implemented using programmable logic devices (ie, PLD, CPLD, FPGA) and / or ASIC.

  FIG. 9 is a schematic diagram of a drive circuit 726 used in a fault indicator circuit, according to one embodiment of the present invention. The drive circuit 726 includes two inverters connected in series with each other. The drive circuit 726 includes one input and two outputs. The input supplies a low or high signal to the drive circuit 726. A low signal can be used to communicate that there is no fault, and a high signal can be used to communicate the presence of a fault, and vice versa. In the illustrated embodiment, the input signal and the inverted version of the input signal are provided as output signals to both switch 328 and visual indicator 329. In one embodiment, these inverters are triple inverting Schmitt trigger inverters (Philips Semiconductor (TM) 74LVC3G14) with 5V tolerant inputs. In other embodiments, a NAND gate configured as an inverter can be used. In other embodiments, other suitable inverters can be used.

  FIG. 10 is a schematic diagram of a relay control switch 828 for use in a fault indicator, according to one embodiment of the present invention. The relay control switch 828 includes an NMOS transistor 830 and a PMOS transistor 831 whose drains and gates are connected. The resistor R8 connects the drain of the NMOS transistor 830 to the source of the PMOS transistor 831. For example, other components such as additional resistors and filter components can be included in this embodiment. The relay control switch 828 has one input terminal and one output terminal. The first input signal corresponds to an on / off signal supplied by the drive circuit. The first input signal is supplied to the gate of transistor 830, which can turn transistor 830 off or on. When transistor 830 is on, the drain current of transistor 830 supplies the appropriate switch voltage to the gate of second transistor 831 to turn on or off the second transistor.

  The second input signal can be an external control signal that can be used to control the relay. When transistor 831 is on, an external control signal is received at the source of transistor 831. When the second transistor 831 is on, the circuit that carries the current corresponding to the external control signal from the control input to the control output of the relay control switch 828 is closed. The control input signal further provides a drain voltage to transistor 830.

  The relay control switch can be implemented using different arrangements of NMOS or PMOS transistors. In other embodiments, electromagnetic switches can be used instead of transistors. In some embodiments, the first transistor can be implemented using a Fairchild Semiconductor (TM) 2N7002 N-channel enhanced mode FET DMOS transistor manufactured by Fairchild Semiconductor, Inc. of Portland, Maine. The transistor is a Philips Semiconductor (TM) BSH202P-channel enhanced mode MOS transistor.

  FIG. 11 is a schematic diagram of a visual indicator circuit 929 that includes an electrical visual indicator for use in a fault indicator circuit, in accordance with one embodiment of the present invention. The visual indicator circuit 929 includes an NMOS transistor connected to a light emitting diode (LED). The drain of the NMOS transistor is connected to the cathode of this LED. The source of the NMOS is grounded. The anode of the LED is connected to a power source. The resistor R9 is connected between the power source and the anode of the LED. In other embodiments, PMOS transistors can be used in place of NMOS transistors. In other embodiments, the visual indicator circuit includes other components such as resistors or filters.

  The input signal from the drive circuit is supplied to the visual indicator at the gate of the transistor. In the illustrated embodiment, a high input signal turns on the NMOS transistor. When the transistor is turned on, current from the power source will flow through the LED and the LED will emit light. The LED provides a visual indication of the failure.

  The switch used in the visual indicator can be realized using an NMOS transistor, a PMOS transistor or an electromechanical switch. For example, this transistor can be implemented as a Fairchild Semiconductor (TM) 2N7002 N-channel enhanced mode FET DMOS transistor, or as a Philips Semiconductor (TM) BSH202P-channel enhanced mode MOS transistor. In other embodiments, other types of switches suitable for driving the LEDs can be used.

  12A and 12B are circuit diagrams of a failure indicator circuit 1000 according to one embodiment of the present invention. The fault indicator circuit 1000 includes sub-circuits corresponding to the input logic circuit and nonvolatile memory element of FIG. 6, the drive circuit of FIG. 7, the relay control switch of FIG. 8, and the visual indicator of FIG. These sub-circuits can operate as described above for each sub-circuit.

  A number of parallel RC filters are included to filter the high frequency portion of the input signal and prevent this input signal from interlacing with the rest of the fault indicator circuit 1000. Many series RC components are used as delay elements.

  The reset switch 1002 supplies a reset signal to the failure indicator circuit 100 when the switch is closed. The reset signal is supplied by a high voltage level from the power supply 1001. In the illustrated embodiment, when the reset switch 1002 is closed, the power supply provides 5V to the input of the fault indicator circuit 1000. Input 1005 provides a fault signal to fault indicator circuit 1000. The fault signal may be generated anywhere in the aircraft electrical system and is provided to fault indicator circuit 1000 via input 1005.

  FIG. 13 is a circuit diagram of a power supply assembly 1400 used to power a fault indicator circuit, according to one embodiment of the invention.

  The power supply assembly 1400 includes a control line 1401 connected to a power supply 1430 through a resistor 1431. The power supply 1430 is grounded via a first bypass capacitor 1432 connected to its input 1402 and via a second bypass capacitor 1432 connected to the output 1403 of the power supply 1430. The power source 1430 has two other terminals that are grounded together. A diode 1435 is connected across the input 1402 and output 1403 of the power supply 1435. Power supply assembly 1400 generally receives one input from control line 1401 and is further grounded. The power supply assembly 1400 has one output 1403.

  The power supply 1430 receives a small amount of current from the control line 1401 and provides stable power to the various elements of the fault indicator circuit 1000 via its output 1403. The diode 1435 prevents current from flowing directly from the control line 1401 to the output 1403 of the power supply, but allows current to flow in the opposite direction. The first and second bypass capacitors 1432 and 1434 filter high frequency components of current and voltage to prevent damage to the power supply 1430. In one embodiment, control line 1401 carries 15V and power supply assembly 1430 uses sufficient current to generate a stable 5V supply voltage at output 1403. The power supply voltage is supplied as a Vcc signal to various transistors and other components of the fault indicator circuit 1000. In another embodiment, the control line can supply an AC voltage and the power source is configured as such.

  In one embodiment, a low power consumption and small transistor (SOT) can be used to implement the power supply 1430. One embodiment uses a Linear Technology (TM) LT1790 micropower SOT-23 low dropout reference power supply manufactured by Linear Technology, Inc. of Milpitas, California. The diode can be implemented using a high conductance high speed diode such as, for example, 1N4148 Fairchild Semiconductor (TM). The first bypass capacitor 1432 at the input can be implemented using a 0.1 μF capacitor (25V). The second bypass capacitor 1432 at the output can be implemented using a 1 μF capacitor (10V). The resistor may be a 2.43 KΩ resistor.

  FIG. 14 is a schematic diagram of a fault indicator circuit including an electromagnetic seal according to an embodiment of the present invention. Fault indicator circuit 1100 is connected to the coil of relay 1110, which is then connected to load 1120. Fault indicator circuit 1100 includes an input logic circuit 1103, an electromechanical switch 1105 and an electromagnetic shield 1140.

  The failure indicator circuit 1100 receives the failure signal and the control-in signal and generates a control-out signal. The input logic circuit 1103 receives the failure signal and the reset signal and controls the electromechanical switch 1105 in the failure indicator circuit 1100. The input logic circuit turns off the electromechanical switch 1105 when the fault signal indicates the presence of a fault. In response, electromechanical switch 105 opens a current loop that supplies current to relay 1110. The electromechanical switch operates as a non-volatile memory and maintains a fault memory by maintaining the state of the circuit until the fault indicator circuit is reset. A reset signal or stimulus is similarly provided to the fault indicator circuit 1100. The electromechanical switch controls the relay by interrupting (ie, disconnecting) an external control signal that controls the relay, where appropriate. Reset of fault indicator circuit 1100 clears the fault and instructs electromechanical switch 1105 to pass the control signal. The reset signal clears past faults and the fault signal indicates the current fault. In many embodiments, the reset signal is provided by a switch. In many embodiments, this switch is part of a pop-up indicator. In other embodiments, the switch is isolated from the circuit that indicates all faults.

  An electromechanical switch may be unintentionally disconnected due to the effects of an electromagnetic field such as that generated by a relay coil. The electromagnetic shield 1140 reduces the likelihood that the electromagnetic field will interfere with the operation of the electromechanical switch within the fault indicator circuit 1100, in accordance with embodiments of the present invention.

  Fault indicator circuit 1100 and relay 1110 can be implemented using a variety of commercially available products. The electromagnetic shield 1140 can be implemented using any type of material that interacts with, absorbs, or interferes with the electromagnetic field. In one embodiment, a metallic material is used for electromagnetic shielding.

  In some embodiments, an iron alloy having a high permeability is used to form the magnetic shield. Some examples of such materials include cold rolled steel, low carbon steel, electric iron, mild steel, silicon steel (SiFe), HyMu alloy meaning a general class of alloys with high levels of magnetic permeability (mu). Contains. Some examples of materials that can be used to implement a magnetic shield include Supermalloy, Hymu 800, Siltron Z, Supermendur, Permalloy, Hy-Ra 80, Orthonol, Deltamax, Hypernik and Mu-metal.

  The electromechanical switch 1105 can be implemented using a reed switch or a reed relay. A reed switch is an electrical switch that operates by applying a magnetic field. The magnetic field can be applied using a permanent magnet or by an electromagnet. One type of reed switch includes a pair of contacts formed from magnetic material sealed in a glass container. This contact is normally open and closes when a magnetic field is present, or opens when a magnetic field is applied normally closed. A reed relay typically includes one or more reed switches, which are controlled by an electromagnet.

  Reed switches and reed relays are formed such that they are disconnected using a magnetic field and do not require actual mechanical or electrical disconnection. The reed switch is intended to be operated by a corresponding electromagnet. However, reed switches are vulnerable to parasitic magnetic fields that can exist in the atmosphere around the switch. Depending on the sensitivity of the reed switch, various ambient magnetic fields can interfere with the reed switch and disconnect the switch if it is not intended to be disconnected by the operating logic.

  One important quality of an electromechanical switch is its sensitivity, which indicates the amount of magnetic energy required to excite the switch. For example, when an electromechanical switch is activated using a coil electromagnet, the sensitivity is measured in units of ampere turns, which corresponds to the current in the coil multiplied by the number of turns. The electromagnetic shield used to protect the electromechanical switch from unexpected disconnection is selected to match the sensitivity of the electromechanical switch. For example, a low sensitivity reed switch requires a high magnetic field to activate and can be protected by a thin sheet of iron material. For the same purpose, a sensitive reed switch that is easily disconnected requires a thick shield that does not allow even a small part of the parasitic electromagnetic field to pass.

  Once the fault is cleared, a reset stimulus is provided to the fault indicator circuit. FIG. 15A shows a visual indicator and manual reset mechanism to be used with a fault indicator circuit 1100 '. Fault indicator circuit 1100 'includes a pop-up indicator 1210, such as a pop-up button. The failure signal disconnects the electromechanical switch 1105 'in the failure indicator circuit 1100'. The electromechanical switch opens the current loop and pushes the pop-up indicator 1210 from position 1220 to position 1230 (see FIG. 15B). The electromechanical switch pop-up indicator 1210 effectively maintains a memory of this fault in the up position (1230). Once the fault is cleared, the fault indicator circuit 1100 ′ can be reset by depressing the pop-up indicator from the up position 1230 to the down position 1220, allowing the electromechanical switch 1105 ′ to pass the control signal to the relay. Become.

  In the embodiment of FIGS. 15A and 15B, the pop-up indicator pops up in response to a failure and provides a visual indicator of the failure while acting as a non-volatile memory of the failure until reset. In the illustrated embodiment, the fault indicator circuit is manually reset when the pop-up indicator is depressed. In other embodiments, the electromechanical switch is manually reset using a different manual reset mechanism.

  Although the invention has been described with reference to certain exemplary embodiments, various modifications may be made to the invention without departing from the spirit and scope of the invention as defined by the appended claims and their equivalents. It should be understood that modifications and changes are possible.

Claims (16)

A fault detection circuit connected to a relay, and a fault indicator circuit connected to the control input of the fault detection circuit and the relay,
The fault indicator circuit includes a non-volatile memory element including a potentiometer having a non-volatile memory;
The fault detection circuit is configured to detect a fault and provide a signal indicating the fault to the fault indicator circuit;
The failure indicator circuit provides a signal indicating the failure by supplying a predetermined control signal to the relay and storing information indicating a failure detection in a non-volatile memory of the potentiometer. An aircraft electrical system that is configured to respond.   The aircraft electrical system of claim 1, wherein the fault indicator circuit is configured to receive a reset signal and clear the non-volatile memory element based on the reset signal. The aircraft electrical system of claim 1, wherein the fault indicator circuit is
Receive external control signal,
If the non-volatile memory element does not contain information indicating a failure detection, the external control signal is passed through the failure indicator circuit to the control input of the relay;
An aircraft electrical system that prevents the external control signal from passing to a control input of the relay when the non-volatile memory element contains information indicating a failure detection. The aircraft electrical system of claim 1, wherein the fault indicator circuit is
An input logic circuit configured to receive a signal indicating a failure and receive a signal indicating a request to reset the non-volatile memory element; and a switch connected to an output of the input logic circuit An aircraft electrical system comprising: a switch configured to prevent the control signal from flowing to the relay when the non-volatile memory element includes information indicating detection of a fault.   The aircraft electrical system of claim 4, wherein the switch includes at least one transistor.   The aircraft electrical system according to claim 4, wherein the switch is an electromechanical switch.   5. The fault indicator circuit according to claim 4, wherein the input logic circuit is configured to generate a first output signal indicating the presence of a fault, wherein the first output signal is derived from the reset signal and the fault signal. The resulting fault indicator circuit.   5. The fault indicator circuit of claim 4, wherein the input logic circuit and the non-volatile memory element are implemented by at least one programmable logic device and an ASIC.   The aircraft electrical system of claim 1, wherein the fault indicator circuit further includes a visual indicator for visual indication of stored faults.   The aircraft electrical system of claim 9, wherein the visual indicator comprises at least one LED.   The aircraft electrical system of claim 9, wherein the visual indicator is a pop-up button. 12. The aircraft electrical system of claim 11, wherein the fault indicator circuit further includes a manual reset mechanism configured to receive a reset stimulus and generate a reset request signal in response to the reset stimulus. In addition,
An aircraft electrical system that provides the reset stimulus when the pop-up button is pressed.   The aircraft electrical system of claim 1, wherein the relay controls the flow of current from a power source to a load.   2. The fault indicator circuit of claim 1, wherein the potentiometer is a digital potentiometer having at least one high resistance location and at least one low resistance location, and the fault indicator circuit is the at least one high resistance location. And a fault indicator circuit configured to store a fault as one of the at least one low resistance location.   The fault indicator circuit of claim 1, wherein the non-volatile memory element includes a 1-bit memory element. In a method for controlling a relay of an aircraft electrical system, the method comprises:
Detecting at least one fault;
Storing a record of said at least one fault using a potentiometer comprising a solid state non-volatile memory;
Maintaining the record of the at least one failure in the absence of power;
If a reset signal is received, clearing the record of the at least one fault; and
Opening the relay to stop current flow to the aircraft electrical system if the at least one fault is stored.

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