JP5422341B2 - Semiconductor light emitting device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor light emitting device, and more particularly to a method for manufacturing a semiconductor light emitting device.

  In recent years, semiconductor light-emitting elements have been used not only for display device light sources such as backlights for liquid crystal displays but also for lighting devices such as general lighting and vehicular lamps due to higher efficiency. For example, when a semiconductor light emitting device is used as a light source of a liquid crystal backlight for a cellular phone so far, it was driven with a current of about 20 mA. However, in the illumination field, it is driven with a higher output of 1 A and 50 times the driving current. Need. As the driving current increases, the amount of heat generated from the semiconductor light emitting element also increases. For this reason, the research and development of adopting Cu (copper) as a support for heat dissipation in semiconductor light-emitting elements that require high output and optical semiconductor devices using the same have been conducted. Various methods of forming the support made of Cu are conceivable. For example, a method of forming using a plating method is known. There is a method of simply bonding a Cu metal plate to a wafer. However, if a plating method is used, it is not necessary to apply pressure to the wafer at the time of bonding, and an improvement in yield is expected.

On the other hand, a group III represented by Al _x In _y Ga _z N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1), which is a main material of a semiconductor light emitting device that emits blue light. Nitride semiconductors are generally formed on a different substrate such as sapphire having a different lattice constant as a growth substrate (wafer), and stress is inherent in the process of crystal growth. There was a problem that the nitride semiconductor wafer was warped. As one method for solving this problem, there is a method of dividing and subdividing a semiconductor film wafer after crystal growth into a semiconductor light emitting element region. That is, a part of the semiconductor film of the wafer is removed by dry etching or the like to release the inherent stress, and the growth substrate (sapphire) is laser lifted off after the above-described support is formed on the flattened wafer. This is the method of peeling and removing by this method. However, when part of the semiconductor film is removed and partitioned, side surfaces of the stacked structure of the semiconductor film for each partition (n-type layer, active layer serving as a light-emitting layer, p-type layer) are exposed. If deposits or the like adhere to the side surface during this step, defects such as leakage increase and yield decreases. Further, when the plating method as described above is simply used, plating enters a groove (street, referred to as a divided groove) for a partition formed by removing the semiconductor film, and a short circuit occurs on the side surface of the semiconductor light emitting element. In addition, since the plating also enters the side surface of the semiconductor light emitting device, there is a problem such as a decrease in light extraction efficiency due to the light emitted from the light extraction from the side surface being absorbed by the Cu plating.

  In order to avoid the above problems, the resist is filled in the dividing grooves formed in the semiconductor film in a lattice shape, and then a plating film is formed so as to cover the semiconductor film and the filling resist, and then the sapphire substrate is removed. Then, a method of manufacturing a semiconductor light emitting element is proposed in which an n-type electrode is formed on the exposed semiconductor layer, and the resist is removed before dicing (see, for example, Patent Document 1).

  FIG. 1 is a flowchart of a manufacturing method for explaining the conventional manufacturing method steps of a semiconductor light emitting device, for example, a manufacturing method of a semiconductor light emitting device in which a metal plate is formed using a plating method. In this manufacturing method, a semiconductor film is formed on a growth substrate using MOCVD (metal organic chemical vapor deposition) or the like (FIG. 1A), and the semiconductor film of the wafer is divided into chip regions (FIG. 1B). )), A p-type electrode is formed on the divided semiconductor film (FIG. 1 (c)), and the dividing groove is filled with a resist material (FIG. 1 (d)). A metal film for plating, which becomes a conductive film for plating, is formed over the groove (FIG. 1E), a plating support is formed on the metal film by plating (FIG. 1F), and a growth substrate is formed. The semiconductor film is removed and exposed (FIG. 1 (g)), an n-type electrode is formed on the exposed semiconductor film (FIG. 1 (h)), and finally the semiconductor film and the metal plate are divided into individual parts. The semiconductor light emitting device is formed into a chip (FIG. 1 (i)) and includes respective steps.

JP2007-83112

  In the figure of Patent Document 1, the resist material filled in the dividing grooves is drawn so that the surface is flat, and it is described that a normal photolithography technique is used. It has been found that in the conventional method for manufacturing a nitride-based semiconductor light-emitting element, the yield of the semiconductor light-emitting element is reduced and the generation of a plating-unformed region (metal film disconnection) occurs.

  Such inconvenience will be described with reference to the drawings.

  FIG. 2 is a schematic plan view of a wafer after a resist is filled in the dividing grooves 4 in a lattice shape that divides the semiconductor light emitting element region 3, and a plating metal film is formed on the entire surface so as to cover the semiconductor film and the filling resist. Indicates. FIG. 3 is a partially enlarged cross-sectional view of the wafer after a metal film for plating showing the structure in the vicinity of the dividing groove 4 is formed on the entire surface. In FIG. 3, 10 is a growth substrate, 20 is a semiconductor film, 30 is a p-type electrode, 40 is a metal film, and 50 is a resist layer.

  It is necessary to form a metal film 40 for starting plating such as Au on the entire surface of the wafer in advance by using an electron beam evaporation method. In the electrolytic plating used in the subsequent plating support formation, the metal film 40 serves as an electrode for attracting Cu ions in the plating bath, and all the regions where plating is to be formed must be electrically connected to each other. is there.

  In Patent Document 1, it is described that the height of the resist layer 50 is equal to the depth of the dividing groove 4, but in an actual photolithography experiment, the shape is fixed after exposure or development after the entire resist material is applied. Since a plurality of processes such as a baking process are performed, the photoresist material actually undergoes thermal shrinkage due to the baking process, and the resist layer 50 filled in the dividing grooves 4 becomes a concave shape (so-called “shrink”) due to a decrease in volume. It has been found that a sharp corner (spike S) is formed at the edge of the edge. When the metal film 40 is formed on the resist material having such a shape by, for example, electron beam evaporation, the metal film is not formed on the spike S, and the metal film 40 on the semiconductor film 20 and the dividing groove 4 ( The electrical connection of the metal film 40 on the resist material is interrupted. Therefore, the metal film 40 on the semiconductor film 20 is electrically isolated, and the plating is not started well even after the plating support is formed by the plating method (FIG. 1 (f)), and as shown in FIG. In some cases, plating (support) was not formed or peeled off (spike SEM image) at the spike S), resulting in a decrease in manufacturing yield.

  Further, even in a region where the metal film 40 is not disconnected (electrically connected region) as described above, the plating film is greatly swelled along the dividing groove 4 as shown in FIG. 5 (SEM image). was there. As shown in FIG. 3, the embedded portion of the resist layer 50 in the dividing groove 4 produced by the technique shown in the prior art is formed in a state of being “drawn (concave)” toward the growth substrate 10 side. As shown in FIG. 6, the plating film 60 on the metal film 40 (also referred to as a plating support, metal support, or Cu support) grows in the normal direction of the metal film 40. Then, it grows toward the center of the recess (FIG. 6A). As shown in FIG. 6B, the Cu plating film 60 plated on the metal film 40 comes into contact with each other at the center of the “shrinkage” portion from the vicinity where the thickness exceeds 10 μm, and is pressed near the center of the resist material embedded portion. The plating will continue in a matching manner. As a result of this plating contact, stress is accumulated in the continuously formed Cu plating film, and when the thickness of the support 60 reaches a practical thickness of 60 μm or more, the embedded portion near the center of the dividing groove or formed plating is formed. The entire film 60 is lifted up, and in the worst case, as shown in FIG. 6C, the entire plated film 60 may be peeled off from the metal film 40, thereby reducing the manufacturing yield.

  Further, when the resist material is filled in the dividing grooves 4 using a photomask and photolithography, the embedded portion of the resist layer 50 produced by the technique shown in the prior art is a growth substrate as shown in FIG. The metal film for plating 40 is formed on the entire surface as shown in FIG. 7B, and the plating method is used as shown in FIG. 7C. Then, a plating support 60 is formed on the metal film 40, the growth substrate 10 is removed by the laser lift-off method as shown in FIG. 8A, and the semiconductor film 20 is exposed. As shown in FIG. The layer 50 is removed and an n-type electrode is formed on the exposed semiconductor film (FIG. 1 (h)), and finally the semiconductor film section is divided as shown in FIG. The chip is made into an element, but “shrinking (concave Since the plating metal film 40 and the support 60 have a convex shape corresponding to Jo) "is manufactured, the semiconductor light emitting element of each of the semiconductor film 20 will have a cross sectional shape as shown in FIG. As can be seen from the figure, the convex portion of the support portion 60 around the semiconductor film 20 obstructs the optical path of the emitted light (arrow) from the end side surface of the semiconductor film 20. Even if the light is reflected, there is a problem that since the reflectance of the support portion is low, the light is greatly attenuated, and the light extraction efficiency is adversely affected.

  In view of these problems, an object of the present invention is to provide a semiconductor light emitting device and a method for manufacturing the same capable of preventing the generation of an unplated region and improving the yield and light extraction efficiency in manufacturing the semiconductor light emitting device. .

  In order to solve the above-described problems, a method of manufacturing a semiconductor light emitting device according to the present invention includes a step of forming a semiconductor film including an active layer on a substrate, and a dividing groove that partitions the semiconductor film into a semiconductor light emitting device region. A step of filling the dividing groove with a resist material to form a buried protection portion, a step of forming a metal film for initiating plating covering the surface of the semiconductor film and the buried protection portion, and a step on the metal film Forming a metal support made of metal plating, and the step of forming the embedding protection portion includes a convex curved surface in which the surface of the embedding protection portion is raised toward the metal support. It includes a step of forming a filled resist material. As a result, it is possible to prevent generation of an unplated region, which has been difficult in the prior art, and to improve the yield of semiconductor light emitting device manufacturing, and the embedded protection portion has a curved surface shape that settles on the outer peripheral side of the divided semiconductor light emitting device. Since it functions as a mold that defines the skirt portion, it can contribute to the improvement of the light extraction efficiency of the semiconductor light emitting device.

  In the method of manufacturing a semiconductor light emitting device, the step of forming the filled resist material includes a step of applying the resist material on the semiconductor film and the dividing groove, and exposing the resist material through a photomask. A step of developing and forming a pattern of a resist material corresponding to the dividing groove, a step of heating until the resist material is liquefied, and a step of cooling the resist material can be included.

  In the above method for manufacturing a semiconductor light emitting device, the angle formed by the tangent line of the curved surface of the embedded protection portion and the surface of the substrate may be 60 degrees or less.

  In the above method for manufacturing a semiconductor light emitting device, the viscosity of the resist material filling the dividing grooves may be 90 cP or more.

In the method of manufacturing a semiconductor light emitting device, the step of forming the semiconductor film includes a step of forming a semiconductor film made of an n-type semiconductor layer, an active layer, and a p-type semiconductor layer on the substrate, before the step of forming a includes the step of laminating a p-type electrode on the p-type semiconductor layer, after the step of forming the metal support, is peeled off the substrate from the n-type semiconductor layer, Exposing the light extraction surface of the n-type semiconductor layer, forming an n-type electrode on the light extraction surface, and dividing the metal support along the bottom surface of the dividing groove. It can be.

  The semiconductor light-emitting device of the present invention is a semiconductor light-emitting device manufactured by the above-described method for manufacturing a semiconductor light-emitting device, wherein the metal support is bonded to the semiconductor film via the metal film, and around the semiconductor film It has a curved surface that sinks outward.

  In the semiconductor light emitting device, an angle formed between a tangent line of the settling curved surface and an interface between the semiconductor film and the metal film may be 60 degrees or less.

  ADVANTAGE OF THE INVENTION According to this invention, a manufacturing yield can be improved, the manufacturing method of the semiconductor light-emitting device which was excellent in heat dissipation and improved light extraction efficiency can be provided.

It is a flowchart which shows the manufacturing process of the manufacturing method of the conventional semiconductor light-emitting device. After the resist is filled in the dividing grooves 4 in a lattice shape for partitioning the semiconductor light emitting element region 3 in the manufacturing process of the semiconductor light emitting element manufacturing method, and a metal film for plating is formed on the entire surface so as to cover the semiconductor film and the filled resist It is a schematic plan view of the wafer. FIG. 3 is a partial enlarged cross-sectional view along line AA in FIG. 2. It is the SEM image of the wafer which shows the state of the non-formation of the plating (support body) after the plating support body formation in the manufacturing process of the manufacturing method of a semiconductor light emitting element, or peeling. It is a SEM image of the wafer which shows a mode that the plating film after the plating support formation in the manufacturing process of the manufacturing method of a semiconductor light-emitting device is greatly raised. It is the partial expanded sectional view of a wafer which shows the mode after forming the metal film for plating which shows the structure of the division groove vicinity in the manufacturing process of the manufacturing method of a semiconductor light-emitting device on the whole surface. It is the partial expanded sectional view of a wafer which shows the mode after forming the metal film for plating which shows the structure of the division groove vicinity in the manufacturing process of the manufacturing method of a semiconductor light-emitting device on the whole surface. It is the partial expanded sectional view of a wafer which shows the mode after forming the metal film for plating which shows the structure of the division groove vicinity in the manufacturing process of the manufacturing method of a semiconductor light-emitting device on the whole surface. It is a schematic sectional drawing of the conventional semiconductor light-emitting device. It is a schematic sectional drawing of the semiconductor light-emitting device which is embodiment of this invention. It is a flowchart which shows the manufacturing process of the manufacturing method of the semiconductor light-emitting device which is embodiment of this invention. It is the partial expanded sectional view of the wafer explaining the manufacturing process of the manufacturing method of the semiconductor light-emitting device which is embodiment of this invention. It is the partial expanded sectional view of the wafer explaining the manufacturing process of the manufacturing method of the semiconductor light-emitting device which is embodiment of this invention. It is the partial expanded sectional view of the wafer explaining the manufacturing process of the manufacturing method of the semiconductor light-emitting device which is embodiment of this invention. It is a SEM image of the wafer which shows the surface after plating in the manufacturing process of the manufacturing method of the semiconductor light-emitting device by this example of the present invention.

  Hereinafter, an embodiment according to the present invention, a semiconductor light emitting device for growing a GaN-based semiconductor on a sapphire substrate, will be described with reference to the drawings. The growth apparatus of the embodiment described below is an apparatus for growing an epitaxial film of a mixed crystal of GaN-based semiconductor such as GaN, AlN, InN, etc. by MOCVD, but is one example that embodies the present invention. Thus, the present invention is not limited to the following embodiment.

  FIG. 10 is a schematic configuration diagram of the semiconductor light emitting device of this embodiment.

  As shown in FIG. 10, the semiconductor light emitting device includes an n-type electrode 70, a semiconductor film 20, a p-type electrode 30, a plating metal film 40, and a plating film 60 (metal support). The semiconductor film 20 includes an n-type semiconductor layer 21, an active layer 22, and a p-type semiconductor layer 23 that are sequentially stacked from the n-type electrode 70 side.

  This semiconductor light emitting element has a curved bottom 41 that settles on the plating film 60 on the outer peripheral side of the semiconductor film 20. The curved surface where the skirt portion 41 sinks is a curved surface of 0 ° ≦ θ ≦ 60 ° in the range of an angle θ where the tangent line intersects the plane of the interface between the semiconductor film 20 and the p-type electrode 30. Within this range of angle θ, the optical path of the emitted light (arrow) from the end side surface of the semiconductor film 20 is not obstructed, and the light extraction efficiency is greatly improved.

  The upper surface 20a of the n-type semiconductor layer 21 is a light extraction surface for extracting light from the active layer 22 to the outside, and this is roughened by chemical or mechanical treatment to improve the light extraction efficiency of the semiconductor light emitting device. It can also be set as the structure which raises.

  The n-type electrode 70 forms an anode of the semiconductor film 20 by making ohmic contact with the n-type semiconductor layer 21 of the semiconductor film 20. The n-type electrode 70 shown in FIG. 10 may have a multilayer structure made of Cr, Ti, Au, Al, Ni, etc. in contact with the n-type semiconductor layer 21. The p-type electrode 30 is electrically connected to the plating film 60 through the metal film 40, and the plating film 60 serves as an extraction electrode for the p-type electrode 30. The p-type electrode 30 and the n-type electrode 70 are disposed opposite to each other on both sides in the thickness direction of the semiconductor film 20 so that the area of the n-type electrode 70 is smaller than that of the p-type electrode 30. Thereby, the semiconductor light emitting device of this embodiment improves light extraction.

  The p-type electrode 30 is also in ohmic contact with the p-type semiconductor layer 23, thereby forming the positive electrode of the semiconductor film 20. As a material of the p-type electrode 30, a single layer film, a laminated film, or an alloy containing any of Pt, Ru, Os, Rh, Ir, Pd, Ag, Ti, Au, and Ni can be used.

  Next, as shown in FIG. 10, the metal film 40 disposed on the plating film 60 side of the p-type electrode 30 is a layer serving as a base when the plating film 60 is formed by a plating method. It is preferable to use Au or Ni that does not dissolve in the plating bath at the time of forming the support on the surface, and it may be formed as an Au single layer film, but has a function of preventing diffusion of Cu into the alloy or p-type electrode 30. You may laminate | stack via Ti, Ta, etc. The total thickness of the metal film 40 is, for example, 1 to 5 μm.

The plating film 60 is a metal layer formed, for example, by electroplating using the metal film 40 as a base. Since Cu has high thermal conductivity, Cu is preferable as a material for the substrate of the semiconductor light emitting device. By providing the plating film 60 made of Cu having high thermal conductivity, the heat generated in the active layer 22 can be easily released to the outside, and the heat dissipation efficiency of the semiconductor light emitting device can be improved.
Furthermore, since Cu has a low electric resistance, it is preferable as a material for the substrate of the semiconductor light emitting device. Since the plated portion 70 made of Cu is joined to the p-type electrode 30 via the metal film 40, it can be used as a conductive terminal, and a wiring connected to the p-type terminal need not be used.

  The thickness of the plating film 60 is preferably 50 to 200 μm, and more preferably about 60 μm. When the thickness of the plating film 60 is less than 50 μm, the plating film 60 is too thin, so that the durability as a semiconductor light emitting element is not only inferior, but handling becomes difficult and production efficiency decreases. On the other hand, when it exceeds 200 μm, it becomes difficult to divide into semiconductor light emitting elements by laser scribing.

  As the semiconductor film 20 composed of the p-type semiconductor layer 23, the active layer 22, and the n-type semiconductor layer 21, in addition to a GaN-based single crystal, a GaP-based single crystal, a GaAs-based single crystal, a ZnO-based single crystal, etc. A known semiconductor light emitting material can be used. In particular, in the case of a GaN-based single crystal, a growth substrate made of a SiC single crystal can be used in addition to sapphire as a growth substrate.

As the semiconductor layer made of a GaN-based single crystal, for example, nitridation represented by the general formula Al _x In _y Ga _z N (where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1). A physical semiconductor is used.

  Although not shown, the n-type semiconductor layer 21 is configured by laminating a base layer, an n-contact layer doped with an n-type impurity, and an n-cladding layer in contact with the active layer 22. The n contact layer can also serve as an underlayer and / or an n clad layer. A small amount of n-type impurity may be doped within a predetermined range also in the underlayer, but good crystallinity can be maintained if it is undoped. Although it does not specifically limit as an n-type impurity, For example, Si, Ge, Sn, etc. are mentioned, Preferably it is Si and Ge, More preferably, Si is used. The n-contact layer is preferably doped with an n-type impurity, which is preferable in terms of maintaining good ohmic contact with the n-type electrode 70, suppressing crack generation, and maintaining good crystallinity.

  An n-cladding layer can be provided between the n-contact layer and the active layer 22. The n-clad layer can be formed of AlGaN, GaN, GaInN, or the like. Alternatively, a heterojunction of these structures or a superlattice structure in which a plurality of layers are stacked may be used. When the n-cladding layer is formed of GaInN, it is desirable to make it larger than the band gap of GaInN of the active layer 22. Moreover, it is preferable to comprise from a semiconductor material with a high refractive index.

  Next, the active layer 22 adjacent to the n-type semiconductor layer 21 may have any structure of double hetero, single quantum well (SQW), or multiple quantum well (MQW).

  The p-type semiconductor layer 23 can be formed by stacking a p-clad layer in contact with the active layer 22 and a p-contact layer. The p-cladding layer is not particularly limited as long as it has a composition larger than the band gap energy of the active layer 22 and can confine carriers in the active layer 22. Although it does not specifically limit as a p-type impurity of a p clad layer and a p contact layer, For example, Preferably Mg is mentioned.

  Next, a method for manufacturing the semiconductor light emitting device according to the present embodiment will be described with reference to the drawings. FIGS. 11A to 11I are flowcharts of a method for manufacturing a semiconductor light-emitting element for forming a plating support using an electric or electrolytic plating method, explaining the outline of the present embodiment. 12 to 14 are schematic cross-sectional views illustrating a method for manufacturing a semiconductor light emitting device according to an embodiment of the present invention.

--Semiconductor film formation process--
As shown in FIG. 12A, an n-type semiconductor layer 21, an active layer 22, and a p-type semiconductor layer 23 are sequentially stacked on the growth substrate 10 to form a semiconductor film 20 (FIG. 11A).

  As the growth substrate 10, it is preferable to use a substrate suitable for epitaxially growing a semiconductor film such as a sapphire substrate. In addition, a III-V compound semiconductor single crystal substrate such as GaAs, InP, or GaP, a silicon (Si) substrate, or the like can be used. Note that since the lattice constants of the substrate 10 and the n-type semiconductor layer 21 differ by 10% or more, a buffer layer can be formed on the substrate 10 in advance when the semiconductor film 20 is formed on the substrate 10. In this case, defects in the n-type semiconductor layer 21 can be reduced by using AlN, AlGaN, or the like having an intermediate lattice constant between the substrate 10 and the n-type semiconductor layer 21 as the buffer layer.

  The growth method of the semiconductor film 20 is not particularly limited, and a nitride semiconductor can be epitaxially grown by MOCVD (metal organic vapor phase epitaxy), HVPE (hydride vapor phase epitaxy), MBE (molecular beam epitaxy) or the like.

For example, in the MOCVD method, hydrogen (H ₂ ) or nitrogen (N ₂ ) as a carrier gas, trimethyl gallium (TMG) or triethyl gallium (TEG) as a Ga source which is a group III source, trimethyl aluminum (TMA) or Al as a source Triethylaluminum (TEA), trimethylindium (TMI) or triethylindium (TEI) as the In source, ammonia (NH ₃ ), hydrazine (N ₂ H ₄ ), or the like as the N source that is a group V raw material are used. As the dopant, monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ) can be used as the Si raw material for the n-type. For the p-type, for example, biscyclopentadienyl magnesium (Cp ₂ Mg) can be used as the Mg raw material.

--Division groove forming process--
As shown in FIG. 12B, a lattice-shaped dividing groove 4 that penetrates through the n-type semiconductor layer 21, the active layer 22, and the p-type semiconductor layer 23 on the growth substrate 10 and divides into a plurality of rectangular semiconductor light emitting element regions. Is formed on the semiconductor film 20 (FIG. 11B).

  By patterning using a normal photolithography technique, for example, reactive ion etching (RIE), the dividing grooves 4 are formed in a lattice shape in the semiconductor film 20 as shown in FIG. 20 is partitioned into semiconductor light emitting element regions. The dividing groove 4 determines the outer shape of the obtained semiconductor light emitting device, and the n-type semiconductor layer 21, the active layer 22 and the p-type semiconductor layer 23 are exposed in the dividing groove.

--P-type electrode formation process--
As shown in FIG. 12C, a p-type electrode 30 is formed on each p-type semiconductor layer 23 of the divided semiconductor film 20 by using a photolithography technique or an electron beam evaporation method (FIG. 11). (C)).

--- Divided groove convex embedding process ---
As shown in FIGS. 12 (d) and 13 (b) to 13 (c), a convex embedding protection portion 51 made of a resist material is formed in the dividing groove 4 (FIG. 11 (d)). The height of the embedding protection part 51 is formed so as to rise beyond the depth of the dividing groove 4.

  As shown in FIG. 12D, a resist material is applied and formed with a thickness larger than the depth of the dividing groove 4. First, using a spin coating method, a photoresist material having a predetermined viscosity is applied to the wafer so as to fill the dividing grooves 4. The applied resist material covers the dividing grooves 4, the p-type semiconductor layer 23, and the p-type electrode 30 formed in the previous step, and forms an uneven resist layer 50 while maintaining the uneven structure.

  As shown in FIG. 13A, the wafer is heat-treated while maintaining the shape of the resist layer 50 as the first baking step. Thereafter, as an exposure step, the resist layer 50 is applied with a power suitable for the resist material using a photomask MSK having a desired pattern corresponding to the grid-like division grooves (light shielding is applied to the concave portions of the resist layer 50, that is, the division grooves 4). To expose. Thereby, a latent image is formed in the non-exposed part.

  After removing the photomask MSK, the wafer is heat-treated and solidified while maintaining the shape of the resist layer 50 as a second baking step, and then degassed for 30 minutes. As a result of the baking of the second baking, the entire resist layer 50 is baked, and as a result, the resist material near the center of the dividing groove 4 is pulled and solidified.

  Next, as shown in FIG. 13B, the developing process is performed by immersing the wafer in a developing solution while maintaining the shape of the resist layer 50 as a developing process, and the resist material of the resist layer 50 in unnecessary portions is removed. To do. At this time, the resist material in the dividing groove 4 that is vertically exposed through the mask is patterned in the middle of the oblique side of the applied resist layer 50 (corresponding to the inner wall of the recess). A resist spike S is formed on the substrate. The resist material in the dividing groove 4 has a cross-sectional shape in which a substantially central portion is drawn and protrusions are formed at both ends.

  Next, as shown in FIG. 13C, the resist in the dividing groove 4 is liquefied again with spikes by performing heat treatment as the third baking, that is, re-baking, and the convex shape is formed by surface tension in the dividing groove. Aggregates the resist. In this state, the resist is solidified again through a temperature lowering process as a cooling process, and the embedded protection part 51 having a convex structure can be formed. Thus, the filling resist material in the dividing groove 4 is formed so that the surface of the embedding protection portion 51 has a raised convex curved surface in the third baking step.

  The embedding protection part 51 preferably has a continuous convex curved surface where a tangent line parallel to the substrate can be drawn at the apex of the embedding protection part, and the range of the angle θ at which the tangent line with the embedding protection part 51 intersects the growth substrate. It is preferable that 0 degree ≦ θ ≦ 60 degrees. As an experimental result, the film thickness of the metal film 40 after the film formation may be thinner than the plane portion on the surface (slope portion) inclined with respect to the wafer plane, for example, due to the film formation speed during electron beam evaporation. . The thickness of the slope portion is cos θ times that of the plane portion using the angle θ, and becomes 1/2 when θ = 60 degrees, for example. Since the metal film 40 is an underlayer for starting plating, it is preferable to be thin. However, when the film thickness is too thin, the metal film 40 is not sufficiently formed and is easily separated electrically and physically. Further, since the resist material is a photosensitive organic compound, the adhesion with the metal film 40 is not necessarily good. Therefore, when there is no film thickness of the metal film 40 to some extent, it is considered that a part of the thin metal film 40 is peeled off during the process. Therefore, when the angle θ is out of the range (θ> 60 degrees), the metal film 40 cannot secure a sufficient film thickness that can withstand the steps after the formation of the metal film 40 to be formed. In addition, by setting the angle θ to 10 degrees or more, the light incident on the support and absorbed is greatly reduced, and the light extraction efficiency is improved. Accordingly, the range of the angle θ is preferably 10 degrees ≦ θ ≦ 60 degrees.

  Furthermore, when the side surface of the semiconductor film is inclined at an angle smaller than 60 degrees with respect to the growth substrate, the angle θ is preferably larger than the angle of the side surface of the semiconductor film with respect to the growth substrate. In particular, when the semiconductor film is removed by dry etching, the side face of the semiconductor film has an inclination of about 45 degrees with respect to the growth substrate. Therefore, the angle θ is preferably set to 45 degrees or more. Since the light emitted from the semiconductor side surface is distributed around the direction perpendicular to the side surface, by setting the angle θ to 45 degrees or more, the angle formed between the semiconductor side surface and the tangent line becomes 90 degrees or more. Most of the light emitted from the light does not enter the support substrate, and light absorption by the support substrate can be reduced. Therefore, the range of the angle θ is more preferably 45 degrees ≦ θ ≦ 60 degrees.

  The resist material used must have a viscosity of 90 cP or more, more preferably 300 cP or more. However, 1 cP (centipoise) = 0.001 Pa · s (pascal second). This is because the resist layer 50 is applied to the wafer at a thickness approximately equal to the depth of the dividing grooves 4 (around 10 μm) or more. This is because a resist material 50 having a viscosity lower than the above value cannot form a sufficiently thick resist layer 50, and instead of realizing a convex shape, the dividing grooves 4 cannot be filled. When the resist material has a viscosity of less than 90 cP, the resist material only covers the side surface of the dividing groove 4.

  As described above, after the resist material is filled into the divided grooves 4, exposure development processing is performed, and then the heating is performed again to fluidize the resist material so that it rises from the divided grooves 4, that is, rises and solidifies. As a result, convex embedding protection portions 51 are formed in a lattice shape corresponding to the dividing grooves 4. The convex embedded protection part 51 prevents the metal film 40 formed in the next step from being formed on the n-type semiconductor layer 21, the active layer 22, and the p-type semiconductor layer 23 on the side surface of the dividing groove 4. In addition to functioning as a protective layer, the embedded protective portion 51 functions as a mold for defining a curved bottom portion 41 that settles on the outer peripheral side of the divided semiconductor light emitting element.

--Metal film formation process--
As shown in FIG. 13D, a metal film 40 is formed on the convex surface of the embedded protection part 51 and on the surface 30a of the p-type electrode 30 (FIG. 11E). As a method for forming the metal film 40, an evaporation method, a sputtering method, or the like can be used.

--Plating support forming process--
As shown in FIG. 14A, a plating film 60 is formed on the entire surface of the metal film 40 (FIG. 11F). The plating film 60 can be formed by an electrolytic plating method, an electroplating method while passing a current through the metal film 40, or the like. The thickness of the plating film 60 is preferably 50 to 200 μm, and can be 60 μm. In general, the plating process is a series of processes including degreasing, acid treatment, neutralization, water washing, plating, and water washing. Degreasing, acid treatment, neutralization, and water washing treatment are performed by appropriately selecting conditions according to need. Cu or the like can be used as a material for the plating film. The non-plated part is covered with a protective coating.

--Growth substrate peeling process--
As shown in FIG. 14B, the surface of the n-type semiconductor layer 21 is exposed using a laser lift-off method (FIG. 11G). Laser light is irradiated from the growth substrate 10 side to the vicinity of the interface between the substrate 10 and the semiconductor film 20 to thermally decompose a part of the buffer layer and the n-type semiconductor layer 21 at the interface portion. 20, The plating film 60 (support substrate) on which the p-type electrode and the metal film 40 are laminated is peeled off. In addition to the laser lift-off method, other known techniques such as a polishing method and an etching method can also be used for peeling the growth substrate.

  Next, as shown in FIG. 14C, the resist material embedding protection portion 51 formed in the dividing groove 4 is removed to expose the dividing groove 4. The removal of the buried protective part 51 can be performed with a normal resist removing solvent such as N-methyl-2-pyrrolidone (NMP).

--N-type electrode formation process--
As shown in FIG. 14C, after cleaning such as etching, a predetermined metal is laminated on the surface of the n-type semiconductor layer 21 to form an n-type electrode 70 (FIG. 11H). Note that the n-type electrode 70 may be sequentially stacked to have a multilayer structure. As a method of forming the n-type electrode 70, for example, a sputtering method or a vapor deposition method can be used.

--- Chip formation process--
As shown in FIG. 14 (d), laser scribing is performed by scanning the vertical line on the bottom surface of the dividing groove while irradiating laser light (arrow) from the side of the plating film 60 at a position approximately at the center of the dividing groove 4. Divide (FIG. 11 (i)). Here, it can be executed by fixing the surface side of the n-type semiconductor layer 21 to a heat-resistant substrate as a stage with an adhesive tape or the like, and the semiconductor light emitting element can be easily divided together with the plating film 60. A conventional laser scribing method can be applied when dividing the semiconductor light emitting device having the plating film 60.

  As shown in FIG. 10, the semiconductor light emitting device of this embodiment manufactured in this way has a curved skirt 41 that settles on the plating film 60 on the outer peripheral side of the semiconductor film 20, and thus the semiconductor film 20 The optical path of the radiated light (arrow) from the end side surface is not obstructed, and the light extraction efficiency is greatly improved. As shown in FIG. 10, the obtained metal support of the semiconductor light emitting device has a shape in which light emitted from the semiconductor film 20 is less likely to hit the plating film 60 as compared with the conventional case.

  Further, according to the method for manufacturing a semiconductor light emitting device, the convex embedded protection portion 51 made of a resist material functions as a mold for defining the skirt portion 41, so that the semiconductor light emitting device can be easily manufactured, The plating film 60 is not formed or peeled off, and the overall occurrence of lifting can be greatly reduced, and the manufacturing yield can be increased and the manufacturing cost can be reduced.

--Semiconductor film formation (FIG. 11A)-
A growth substrate (C-plane sapphire substrate) 10 capable of growing Al _x In _y Ga _z N (where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1) by MOCVD is prepared. Then, the semiconductor film 20 in which the n-type semiconductor layer 21 made of Al _x In _y Ga _z N, the active layer 22 (light emitting layer), and the p-type semiconductor layer 23 are stacked on the growth substrate 10 by MOCVD is crystal-grown. I let you.

Specifically, a sapphire substrate as a growth substrate was put into an MOCVD apparatus and heated at 1000 ° C. for 10 minutes in a hydrogen atmosphere (thermal cleaning). Next, about 500 ° C., trimethylgallium (TMG) 10.4 μmol / min and ammonia (NH ₃ ) 3.3LM were supplied for 3 minutes to form a low-temperature buffer layer (GaN layer). Next, the temperature was raised to 1000 ° C. and held for 30 seconds to crystallize the low-temperature buffer layer, and TMG 45 μmol / min and NH ₃ 4.4LM were supplied at the same temperature for 20 minutes to form an underlying GaN layer of about 1 μm. . At a temperature of 1000 ° C., TMG 45 μmol / min, NH ₃ 4.4LM, SiH ₄ 2.7 × 10 ⁻⁹ μmol / min are supplied for 120 minutes to grow the n-GaN layer (n-type semiconductor layer 21) to a thickness of about 7 μm. It was.

A multiple quantum well structure made of InGaN / GaN was applied to the active layer 22. Here, five periods of growth were performed with two layers of InGaN / GaN as one period. At a temperature of about 700 ° C., TMG 3.6 μmol / min, trimethylindium (TMI) 10 μmol / min, NH ₃ 4.4LM were supplied for 33 seconds, an InGaN well layer having a thickness of about 2.2 nm and TMG 3.6 μmol / min, NH ₃ 4.4LM was supplied for 320 seconds, and the growth of the GaN barrier layer having a thickness of about 15 nm was repeated for five cycles.

The temperature was raised to 870 ° C., TMG 8.1 μmol / min, trimethylaluminum (TMA) 7.5 μmol / min, NH ₃ 4.4LM, biscyclopentadienylmagnesium (Cp ₂ Mg) 2.9 × 10 ⁻⁷ μmol / For 5 minutes, about 40 nm of the p-AlGaN cladding layer was grown. Subsequently, TMG 18 μmol / min, NH ₃ 4.4LM, Cp ₂ Mg 2.9 × 10 ⁻⁷ μmol / min were supplied at the same temperature for 7 minutes to grow a p-GaN layer (p-type semiconductor layer 23) of about 150 nm.

--Division groove formation (FIG. 11 (b))-
Using a photolithography technique, a resist mask having an opening in a region for forming the dividing groove 4 was formed. Thereafter, the wafer was put into a reactive ion etching apparatus, and the division grooves 4 were formed by a two-step procedure by dry etching treatment using Cl ₂ plasma. Specifically, the treatment was performed at a process pressure of 0.2 Pa, a high frequency power of 100 W, a bias power of 50 W, and a Cl ₂ supply amount of 20 sccm for 1680 seconds. The conditions are in accordance with the film thickness of the GaN-based semiconductor film 20 under these conditions, and the dry etching conditions are not limited to the above.

--P-type electrode formation (FIG. 11 (c))-
Using photolithography and electron beam vapor deposition, Pt: 1 nm / Ag: 150 nm / Ti: 100 nm / Pt: 100 nm / Au: 200 nm is applied to a desired position on the surface of the p-type semiconductor layer 23 where the p-type electrode formation region is exposed. A p-type electrode 30 serving also as a reflective layer was formed. Here, the electrodes are formed after the dividing groove forming step, but the electrodes may be formed after the semiconductor film forming step, and it can be easily estimated that the order of the steps is not limited.

--Division groove convex embedding (FIG. 11 (d))-
After the dividing groove 4 was filled with a resist material, exposure and development were performed to fill the dividing groove. That is, the embedding protection part 51 of the dividing groove 4 was formed. A known resist material can be used, but a positive resist was selected as the optimum selection. Details are shown below.

--- Conditions for forming convex embedding protection with positive resist--
(Resist Material Application) A positive resist material (manufactured by Tokyo Ohka: LA300PM) was used, and spin coating conditions: about 7.5 μm was applied at 4000 rpm. The applied resist material traces the structure of the dividing groove and the p-type electrode formed in the previous step, and is formed while maintaining the concavo-convex structure, and the concavo-convex resist layer 50 is formed. When the thick resist layer 50 having a thickness of 6 μm or more is formed, the resist material viscosity needs to be 90 cP or more. This is because when the resist material viscosity is less than 90 cP, there is no resist material in an amount that maintains a sufficiently high convex shape in the dividing groove.

  (First Bake) Then, the first bake was performed at 90 ° C. for 120 seconds.

(Exposure) Thereafter, exposure was performed at 250 mJ / cm ² using a photomask having a desired pattern.

  (Second Bake) Then, the second bake was heat-treated at 110 ° C. for 120 seconds to solidify, and then degassed for 30 minutes. As a result of the baking of the second baking, the entire resist material was baked, and as a result, the resist material near the center of the dividing groove 4 was pulled and solidified.

  (Development) Thereafter, development was performed using a developer (Clearant Japan: AZ600MF) to remove the resist material of the resist layer 50 in unnecessary portions. At this time, since the resist layer exposed vertically through the mask is patterned in the middle of the oblique side of the resist layer (corresponding to the inner wall of the recess), spikes were formed on the periphery of the dividing groove 4.

  (Third baking) By performing 20 minutes at 150 ° C. as a re-baking treatment, the embedded protective portion precursor was liquefied again and aggregated into a convex shape by surface tension in the dividing groove. From this state, the embedded protective part 51 having a convex structure was formed by solidifying again during the temperature lowering process.

  Through the above steps, a good electrolytic plating state can be ensured in all regions in the wafer surface. In particular, the plating support body is formed on the dividing groove 4 without being lifted by the accumulated stress in the plating film 60 and causing peeling. It became possible. Further, the spike shape at the end of the embedded protection part is also integrated with the slope of the embedded protection part 51. As a result, it is possible to satisfactorily ensure electrical conductivity during electrolytic plating in all regions within the wafer surface, and the metal film 40 and the plating film 60 can be formed without disconnection.

--Metal film formation (FIG. 11 (e))-
A metal film 40 for starting plating was formed on the buried surface of the dividing groove 4 and the p-type electrode surface. Ti: 100 nm / Au: 400 nm was formed by an electron beam evaporation method, and then Au: 3000 nm was formed by a resistance heating method in which the film formation rate was significantly higher than that of a sputtering method or an electron beam evaporation method. As a specific method for forming the conductive film for plating, vapor deposition, sputtering, or the like can be used.

--Plating support formation (FIG. 11 (f))-
The wafer was immersed in a plating bath, and a copper plated support 60 was laminated to a thickness of about 150 μm using an electrolytic plating method. Specifically, the support 60 was formed by copper plating using a copper cyanide or copper sulfate-based bath. At that time, organic-based smoothing agents and brightening agents may be used as additives for adjusting mechanical properties such as plating rigidity and flatness. FIG. 15 shows an SEM image of the front surface (back surface of the support 60) after plating according to this example. As can be seen from the comparison with the prior art of FIG. 5, the back surface of the support 60 formed using this embodiment is flat and does not peel off.

--Growth substrate peeling (FIG. 11 (g))-
Next, the growth substrate 10 was removed by using an existing laser lift-off method to expose the surface of the semiconductor film 20 (n-GaN layer). Specifically, the growth substrate 10 is irradiated with laser from the growth substrate 10 (sapphire) side to decompose GaN at the interface between the growth substrate 10 and the semiconductor film 20 into gallium (Ga) and nitrogen (N ₂ ). Was peeled from the semiconductor film 20. Other methods such as grinding, polishing, and RIE can also be applied to the growth substrate 10 removal method. If the growth substrate 10 is dissolved in a specific solution such as Si or SiC, the growth substrate 10 can be removed by chemical treatment (wet etching).

--N-type electrode formation (FIG. 11 (h))-
An n-type electrode 70 made of Ti: 1 nm / Pt: 100 nm / Au: 1500 nm was formed at a desired position on the surface of the n-type semiconductor layer 21 exposed by removing the growth substrate 10 using photolithography and electron beam evaporation. .

--- Chip (FIG. 11 (i))-
The wafer was divided into individual semiconductor light emitting elements to form chips. Specifically, a chip was formed by removing a desired region of the metal support 60. Specifically, the metal support 60 was cut by irradiating the surface of the metal support 60 with a YAG laser and divided into individual semiconductor light emitting devices.

  By passing through the above process, the semiconductor light-emitting device excellent in heat dissipation and light extraction was able to be obtained.

  According to the above embodiment, since the shape of the embedding protection portion 51 filled in the dividing groove is formed so as not to have the spike portion, there is a region where the metal film for starting plating is electrically isolated throughout the wafer surface. The film can be formed without generation. As a result, the disconnection of the plating is suppressed, and the plating film (support) can be reliably formed on the semiconductor film by electrolytic plating, and the yield can be improved.

  In order to eliminate the spike shape of the embedding protection part 51 and make it a gentle convex shape, after patterning the resist layer 50 using a normal photolithography technique, the temperature is finally 15 to 120 ° C., more preferably 130 ° C. It is possible by performing a baking treatment for ˜25 minutes (more preferably 20 minutes). At this time, by using a resist material having a viscosity of 90 cP or more, more preferably 300 cP or more, a pattern of the resist layer 50 that fills the dividing grooves can be obtained.

  Since the embedding protection portion 51 filled in the dividing groove has a gently convex surface (having only a tangent line of 0 ° ≦ θ ≦ 60 °), the plating film is formed as shown in the prior art. The plating films do not press against each other on the dividing groove, and a flat plating surface that does not peel off can be achieved.

  The periphery of the divided semiconductor region is filled with a convex resist material, a plating film is formed, the substrate is peeled off, and then through an electrode formation step and a chip formation step, from the active layer end of the manufactured semiconductor light emitting device With respect to the traveling direction of the extracted light, the shielding object including the plating support surface can be eliminated, and the light extraction efficiency can be improved.

  INDUSTRIAL APPLICABILITY The present invention can improve the manufacturing yield, and can provide a semiconductor light emitting device with excellent heat dissipation and high light extraction efficiency. Therefore, the present invention can be used in the optical industry where the semiconductor light emitting device is used for various display lamps. There is.

4 Dividing groove 10 Growth substrate 20 Semiconductor film 20a Light extraction surface 21 n-type semiconductor layer 22 active layer 23 p-type semiconductor layer 30 p-type electrode 40 metal film 50 resist layer 51 buried protection part 60 metal support, support, plating film 70 n-type electrode S spike

Claims (6)

A method for manufacturing a semiconductor light emitting device, comprising:
Forming a semiconductor film including an active layer on a substrate;
Forming a dividing groove for partitioning the semiconductor film into a semiconductor light emitting element region;
Filling the dividing groove with a resist material to form a buried protection portion;
Forming a metal film for initiating plating covering the surface of the semiconductor film and the embedded protection part;
Forming a metal support made of metal plating on the metal film,
The step of forming the embedding protection part includes the step of molding the filled resist material so that the surface of the embedding protection part has a convex curved surface raised to the metal support side , and
The step of forming the filled resist material includes a step of applying the resist material on the semiconductor film and the dividing groove, and a resist corresponding to the dividing groove by exposing and developing the resist material through a photomask. A method for manufacturing a semiconductor light emitting device , comprising: a step of forming a pattern of a material; a step of heating until the resist material is liquefied; and a step of cooling the resist material . The method of manufacturing a semiconductor light emitting device according to claim 1 wherein there the angle between the buried protective portion of the curved surface of the tangent and the surface of the substrate is less than 60 degrees. The method of manufacturing a semiconductor light emitting device according to claim 1 or 2 viscosity of the resist material filling the dividing grooves is equal to or not less than 90 cP. Forming the semiconductor film includes forming a semiconductor film including an n-type semiconductor layer, an active layer, and a p-type semiconductor layer on the substrate;
Before the step of forming the dividing groove, wherein the step of laminating a p-type electrode on the p-type semiconductor layer,
After the step of forming the metal support, the step of peeling the substrate from the n-type semiconductor layer to expose the light extraction surface of the n-type semiconductor layer, and forming an n-type electrode on the light extraction surface process and method of manufacturing a semiconductor light-emitting device according to any one of claims 1-3, characterized in that it comprises the steps of dividing the metal support along the bottom surface of the dividing groove. A semiconductor light emitting device manufactured by the manufacturing method of the semiconductor light-emitting device according to any one of claims 1-4,
The semiconductor light-emitting element, wherein the metal support has a curved surface that is bonded to the semiconductor film through the metal film and settles outward around the semiconductor film. 6. The semiconductor light emitting device according to claim 5 , wherein an angle formed by a tangent of the sinking curved surface and an interface between the semiconductor film and the metal film is 60 degrees or less.