JP5395240B2 - Solid-state imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device that generates image data according to incident radiation.

  In X-ray imaging technology, in recent years, X-ray imaging systems using solid-state imaging devices have been widely used instead of X-ray photosensitive films. Such an X-ray imaging system does not need to be developed like an X-ray photosensitive film, and is highly convenient, such as being able to confirm an X-ray image in real time, and is superior in terms of data storage and ease of handling. It has a point. For example, in X-ray imaging for dental diagnosis, such an X-ray imaging system is becoming widespread in various imaging modes such as panorama, cephalo, and CT. As an example, the dental X-ray imaging apparatus disclosed in Patent Document 1 images X-rays output from an X-ray source and transmitted through a subject using an X-ray detection element having a CCD system.

  As a solid-state imaging device used in such an X-ray imaging system, a device using CMOS technology is known, and among them, a passive pixel sensor (PPS) type is known. The PPS solid-state imaging device includes a pixel array in which PPS pixels including a photodiode that generates an amount of electric charge according to incident light intensity are two-dimensionally arranged in M rows and N columns. In response, the charge generated in the photodiode is converted into a voltage value by an integration circuit, and the voltage value is further converted into a digital value for output.

  In general, the output ends of each of the M pixels in each column are connected to the input ends of the integration circuits provided corresponding to the columns via readout wirings provided corresponding to the columns. ing. Then, the charges generated in the photodiodes of each pixel are sequentially input from the first row to the M-th row for each row through the readout wiring corresponding to the corresponding column to the integration circuit. Are sequentially input to the analog / digital converter from the first column to the Nth column.

JP 2004-208754 A

  In the X-ray imaging system described above, the size required for the pixel array of the solid-state imaging device varies depending on the imaging application. For example, in X-ray imaging in dental diagnosis, the width in the longitudinal direction of the pixel array in cephalometric imaging Is required to be a long solid-state imaging device having a length of 22 cm or more. When such a long solid-state imaging device is required, it may be difficult to manufacture the solid-state imaging device on a single substrate depending on the diameter of the semiconductor wafer used for the production of the solid-state imaging device. is there. In such a case, two substrates that are shorter than the dimensions required for the solid-state imaging device are arranged in the longitudinal direction, and the respective pixel arrangements are combined and used as one solid-state imaging device (so-called tiling). The dimensions can be satisfied.

  However, since it is difficult to eliminate the gap between the end of the substrate and the end of the pixel array produced on this substrate, when two substrates are used side by side, A region (dead area) where an X-ray image is not captured is generated at the boundary portion (seam). Depending on the imaging application, the position of such a dead area may be limited. For example, in dental cephalometric imaging, imaging is performed while moving the solid-state imaging device in the horizontal direction (horizontal direction) with the longitudinal direction of the solid-state imaging device aligned with the vertical direction (vertical direction). Since the temporomandibular joint exists near the center of the image, if there is a dead area near the center of the entire tiled pixel array, there is a possibility that image data of a part important for diagnosis may be lost. Therefore, in such a case, it is necessary to remove the position of the dead area from the vicinity of the center by making the longitudinal widths of the pixel arrays on the two substrates different from each other.

  Here, when the two substrates constituting the PPS solid-state imaging device described above are juxtaposed in the row direction of each pixel array, if the widths of the pixel arrays in the longitudinal direction are different from each other, The number of columns in the pixel array is different from each other, causing the following problem. That is, in the solid-state imaging device of the PPS system, the electric charges generated in the photodiodes of each pixel are converted into voltage values for each column and further converted into digital values. The digital values are converted in parallel from two substrates. When output, the time required to finish outputting the digital values for all the columns differs for each board, and the board with the smaller number of columns waits until the digital values are output from the board with the larger number of columns. It must be in a state, and the time required for imaging one frame becomes long.

  The present invention has been made to solve the above problems, and in a solid-state imaging device having a configuration in which each pixel array formed on two substrates is tiled in the row direction, imaging of one frame is performed. The purpose is to shorten the time required for.

The solid-state imaging device according to the present invention is a solid-state imaging device that generates image data according to incident radiation, and M × NA pixels (M and NA are integers of 2 or more) each including a photodiode are M. A first substrate having a first pixel array that is two-dimensionally arranged in rows and NA columns, and M × NB pixels (NB is an integer of 2 or more smaller than NA) each including photodiodes are arranged in M rows and NB columns. A second substrate having a second pixel array, the first column of which is arranged along the NA column of the first pixel array, and the first and second pixel arrays. (NA + NB) readout wirings arranged for each column and connected to the photodiodes included in the pixels of the corresponding column via the readout switch, and the amount of charge input via the readout wiring Hold the corresponding signal and output the held signal And a signal output unit, the signal output unit, a first output port for outputting a signal corresponding to the respective columns from the first column of the first pixel array to the n-th column (2 ≦ n <NA) sequentially In parallel with the output from the first output port , each column from the (n + 1) th column of the first pixel array to the NB column through the NA column and the first column of the second pixel array And a second output port for sequentially outputting signals corresponding to.

  According to the solid-state imaging device of the present invention, the dead area can be removed from the vicinity of the center by tiling two substrates having different pixel array lengths in the column direction. It can be suitably used for applications where there is a restriction on the position of the. Also, when imposing a pixel array on a wafer during the manufacture of a solid-state imaging device, imposing a combination of a plurality of pixel arrays having a wide width in the longitudinal direction and a plurality of pixel arrays having a narrow width in the longitudinal direction Therefore, as compared with the case of imposing a plurality of pixel arrays having the same width in the longitudinal direction, wasteful portions on the wafer can be reduced and the pixel array can be extracted more efficiently.

  In the solid-state imaging device according to the present invention, the first substrate having the first pixel array and the second substrate having the second pixel array having a smaller number of columns than the first pixel array include The NA column of the one pixel array and the first column of the second pixel array are tiled so as to be along each other. That is, this solid-state imaging device has a pixel arrangement of a (NA + NB) column obtained by adding the NB (<NA) column from the first column of the second pixel arrangement to the NA column of the first pixel arrangement. Have.

  The signal output unit outputs a signal corresponding to each column before the n-th column (that is, from the first column to the n-th column) of the first pixel array when outputting the signal to a data bus or the like. ) And subsequent columns and the first column to the NB column of the second pixel array (ie, the (n + 1) th column of the first pixel array, the NA column and the first column of the second pixel array). And the signals corresponding to (up to the NB column) are output in parallel. In this way, by dividing the output operation at the column (nth column) between the first column and the NA column of the first pixel array having a large number of columns and outputting the signals in parallel, The number of columns in one divided region and the number of columns in the other region can be the same or close to each other. Therefore, according to the solid-state imaging device according to the present invention, for example, signals are output from the first column to the NA column of the first pixel array, and in parallel therewith, the first column to the NB of the second pixel array. Compared with the method of outputting a signal from the column, the waiting time in the output operation can be made close to zero, and the time required for imaging one frame can be effectively shortened.

  In the solid-state imaging device according to the present invention, one or a plurality of continuous columns including the first column of the first pixel array and one or a plurality of continuous columns including the NB column of the second pixel array are provided. The insensitive area may be shielded from incident radiation. In a solid-state imaging device that generates image data according to incident radiation, the periphery of the pixel array is covered with a radiation shielding member in order to protect circuit parts such as a shift register arranged beside the pixel array from radiation. There are many. When the radiation shielding member is applied to a part of the pixel array, the above insensitive area is generated in the pixel array. Of the signals output from the signal output unit, the signals corresponding to the pixels included in the insensitive area are invalid data not related to the radiation image.

  In such a case, if the output order of signals in one area divided by the nth column is the same as the output order of signals in the other area, the following inconvenience occurs. That is, a signal output from the signal output unit is sent to another electronic circuit (CPU or the like) via a data bus or the like. At this time, a signal corresponding to the insensitive area (invalid data) is first in one area. In the other area, invalid data is output last. Thus, if the position of invalid data in the signal output order is different in each region, it can be a barrier when performing real-time processing in other electronic circuits.

  In order to solve such problems together, in the solid-state imaging device described above, the output order of signals in one region divided by the nth column and the output order of signals in the other region are opposite to each other. It may be. That is, the signal output unit starts a signal corresponding to each column from the first column to the nth column of the first pixel array from the first column to the nth column or from the nth column. The signals corresponding to each column from the (n + 1) th column of the first pixel array to the NB column through the NA column and the first column of the second pixel array are sequentially output up to the first column. The first pixel array may be sequentially output in the reverse order to the first column to the n-th column. The signal output unit outputs signals to the data bus or the like in this order, so that the positions of invalid data in the signal output order can be matched with each other in each region, and real-time processing can be easily performed in other electronic circuits. Can be done.

  In the solid-state imaging device, the number of columns from the first column to the n-th column in the first pixel array is equal to the number of columns from the (n + 1) -th column to the NA-th column in the first pixel array. It may be equal to the sum of the number of columns in the first column to the NB column. That is, by setting the number of columns in one region divided by the nth column as the boundary and the number of columns in the other region equal to each other, the waiting time in the signal output operation becomes almost zero, and the time required for imaging one frame Can be shortened more effectively.

  ADVANTAGE OF THE INVENTION According to this invention, in the solid-state imaging device provided with the structure by which each pixel arrangement | sequence formed on two board | substrates was tiled in the row direction, the time required for the imaging of one frame can be shortened.

1 is a configuration diagram of an X-ray imaging system 100. FIG. It is a figure which shows a mode that the solid-state imaging device 1 and the X-ray generator 106 are linearly displaced with respect to the subject A seeing from the upper side of the subject A (subject's head). 1 is a plan view of a solid-state imaging device 1. FIG. (A) It is a sectional side view of the solid-state imaging device 1 along the IVa-IVa line of FIG. (B) It is side sectional drawing of the solid-state imaging device 1 along the IVb-IVb line | wire of FIG. FIG. 2 is a diagram showing an internal configuration of the solid-state imaging device 1, and representatively shows a portion (pixel block) of a pixel array 10 </ b> A (10 </ b> B) corresponding to one signal readout unit among a plurality of signal readout units 21 </ b> A to 21 </ b> L. Yes. 3 is a circuit diagram of each of a pixel P _{m, j} , an integration circuit S _j and a holding circuit H _j included in the pixel block of the solid-state imaging device 1. FIG. It is a timing chart explaining operation | movement of the pixel block contained in the 1st column-nth column of 10 A of pixel arrays, and operation | movement of the signal output part 20 corresponding to this pixel block. The operations of the pixel blocks included in the (n + 1) -th to NA-th columns of the pixel array 10A and the first to NB-th columns of the pixel array 10B and the operation of the signal output unit 20 corresponding to this pixel block will be described. It is a timing chart to do. It is a timing chart explaining the input / output operation of the FIFO data buffers 23A to 23F provided corresponding to the pixel blocks included in the first column to the n-th column of the pixel array 10A. The input / output operations of the FIFO data buffers 23G to 23L provided corresponding to the pixel blocks included in the (n + 1) th to NAth columns of the pixel array 10A and the first to NBth columns of the pixel array 10B will be described. It is a timing chart. (A) It is a figure which shows a mode that two pixel arrangement | sequences 110A and 110B are tiled up and down, and it image | photographs, moving in parallel with a horizontal direction. (B) It is a figure which shows a mode that two pixel arrangement | sequences 120A and 120B are tiled up and down, and it image | photographs, moving in parallel in a horizontal direction. (A) In silicon wafer W, it is a figure which shows a mode that imposition of several pixel arrangement | sequence 120A with a wide width | variety of a longitudinal direction and several pixel arrangement | sequence 120B with a narrow width | variety of a longitudinal direction was performed. (B) It is a figure which shows a mode that the imposition of several pixel arrangement | sequence 110 with the equal width | variety of the elongate direction in the silicon wafer W was performed. (A)-(h) It is a timing chart which shows an example of the timing when a digital value is output from eight FIFO data buffers (1)-(8) each corresponding to eight pixel blocks of one pixel arrangement. (I)-(l) It is a timing chart which shows an example of the timing at which a digital value is output from four FIFO data buffers (9)-(12) respectively corresponding to four pixel blocks of the other pixel arrangement. (A)-(h) It is a timing chart which shows an example of the timing when a digital value is output from eight FIFO data buffers (1)-(8) each corresponding to eight pixel blocks of one pixel arrangement. (I)-(l) It is a timing chart which shows an example of the timing at which a digital value is output from four FIFO data buffers (9)-(12) respectively corresponding to four pixel blocks of the other pixel arrangement. It is a timing chart which shows the output order of the digital value from each FIFO data buffer 23A-23L. (A) It is a figure which shows the system which arranges the semiconductor substrates 3A and 3B by which film-like scintillators 4A and 4B were vapor-deposited on the surface, respectively, adjoining on the same plane. (B) It is a figure which shows the system by which scintillator 4A, 4B is vapor-deposited collectively after semiconductor substrate 3A, 3B is arranged adjacently on the same plane and semiconductor substrate 3A, 3B is juxtaposed. (C) It is a figure which shows the system which arrange | positions semiconductor substrate 3A, 3B so that the edge part of semiconductor substrate 3B may overlap with the edge part of semiconductor substrate 3A.

  The best mode for carrying out the present invention will be described below in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted.

  FIG. 1 is a diagram illustrating a configuration of a medical X-ray imaging system 100 including a solid-state imaging device 1 according to an embodiment of the present invention. The X-ray imaging system 100 of this embodiment mainly includes imaging modes such as panoramic imaging, cephalometric imaging, and CT imaging in dental care, and images an X-ray image of a subject's jaw. The X-ray imaging system 100 includes the solid-state imaging device 1 and the X-ray generator 106, and the X-rays output from the X-ray generator 106 and transmitted through the subject A (that is, the subject's jaw) are solid. Imaging is performed by the imaging apparatus 1.

  The X-ray generator 106 generates X-rays toward the subject A. The irradiation field of X-rays generated from the X-ray generator 106 is controlled by the primary slit plate 106b. The X-ray generator 106 incorporates an X-ray tube, and the amount of X-ray irradiation to the subject A is controlled by adjusting conditions such as tube voltage, tube current, and energization time of the X-ray tube. The The X-ray generator 106 outputs an X-ray at a predetermined divergence angle in a certain imaging mode by controlling the opening range of the primary slit plate 106b, and this predetermined divergence in another imaging mode. X-rays can be output with a divergence angle narrower than the angle.

  The solid-state imaging device 1 is a CMOS solid-state imaging device having a plurality of pixels arranged two-dimensionally, and converts an X-ray image that has passed through the subject A into electrical image data D. A secondary slit plate 107 that restricts the X-ray incident area is provided in front of the solid-state imaging device 1.

  The X-ray imaging system 100 further includes a turning arm 104. The turning arm 104 holds the X-ray generator 106 and the solid-state imaging device 1 so as to face each other, and turns them around the subject A during CT imaging or panoramic imaging. Further, a slide mechanism 113 for linearly displacing the solid-state imaging device 1 and the X-ray generation device 106 with respect to the subject A is provided at the time of cephalometric imaging or linear tomographic imaging. The turning arm 104 is driven by an arm motor 109 constituting a rotary table, and the rotation angle is detected by an angle sensor 112. The arm motor 109 is mounted on the movable part of the XY table 114, and the center of rotation is arbitrarily adjusted in the horizontal plane.

  Image data D output from the solid-state imaging device 1 is once captured by a CPU (central processing unit) 121 and then stored in the frame memory 122. From the image data stored in the frame memory 122, a tomographic image, a panoramic image, a cephalo image, or the like along an arbitrary tomographic plane is reproduced by a predetermined calculation process. These reproduced images are output to the video memory 124, converted into analog signals by the DA converter 125, displayed on the image display unit 126 such as a CRT (cathode ray tube), and used for various diagnoses.

  A work memory 123 necessary for signal processing is connected to the CPU 121, and an operation panel 119 provided with a panel switch, an X-ray irradiation switch, and the like is further connected. The CPU 121 also controls the motor drive circuit 111 that drives the arm motor 109, slit control circuits 115 and 116 that control the opening ranges of the primary slit plate 106 b and the secondary slit plate 107, and the X-ray generator 106. Each is connected to the control circuit 118 and further outputs a clock signal for driving the solid-state imaging device 1. The X-ray control circuit 118 feedback-controls the amount of X-ray irradiation to the subject based on the signal imaged by the solid-state imaging device 1.

  FIG. 2 is a diagram illustrating a state in which the solid-state imaging device 1 and the X-ray generation device 106 are linearly displaced with respect to the subject A when viewed from above the subject A (the subject's head). At the time of cephalometric imaging, the solid-state imaging device 1 and the X-ray generation device 106 move linearly in the same direction (arrow B in the figure) while maintaining a state of being opposed to each other on both sides of the subject A by the slide mechanism 113. However, the subject A is irradiated with X-rays, and X-ray images passing through the subject A are continuously captured.

  3 and 4 are diagrams illustrating the configuration of the solid-state imaging device 1 according to the present embodiment. FIG. 3 is a plan view of the solid-state imaging device 1. 4A is a side sectional view of the solid-state imaging device 1 along the line IVa-IVa in FIG. 3, and FIG. 4B is a side sectional view of the solid-state imaging device 1 along the line IVb-IVb in FIG. FIG. 3 and 4 also show an XYZ orthogonal coordinate system for easy understanding.

  3 and 4A, the solid-state imaging device 1 includes a semiconductor substrate 3A (first substrate) and a semiconductor substrate 3B (second substrate), and the two semiconductor substrates 3A, 3A, One imaging area is configured by 3B. The size required for the imaging area of the solid-state imaging device 1 varies depending on the imaging application. However, in X-ray imaging for dental diagnosis, the length of the imaging area in the longitudinal direction is 22 cm or more in cephalometric imaging. Is required. Therefore, as in this embodiment, two semiconductor substrates 3A and 3B shorter than the dimensions required for the solid-state imaging device 1 are arranged in the longitudinal direction, and the pixel arrays 10A and 10B are combined to form one imaging region. By using (so-called tiling), the required dimensions can be satisfied. When two semiconductor substrates 3A and 3B are used side by side in this way, a region (dead area C) where an X-ray image is not captured occurs at the boundary portion (seam) of these pixel arrays. This is because it is difficult to manufacture a gap between the end portions of the semiconductor substrates 3A and 3B and the end portions of the pixel arrays 10A and 10B fabricated on the semiconductor substrates 3A and 3B. The

  The solid-state imaging device 1 includes a pixel array 10A (first pixel array) and a scan shift register 30A each formed on the main surface of the semiconductor substrate 3A, and a pixel array 10B formed on the main surface of the semiconductor substrate 3B. (Second pixel array) and a scan shift register 30B. The solid-state imaging device 1 further includes a signal output unit 20, which includes a plurality of signal readout units 21 </ b> A to 21 </ b> H formed on the main surface of the semiconductor substrate 3 </ b> A and the main substrate 3 </ b> B. A plurality of signal reading units 21I to 21L formed on the surface, a plurality of analog / digital (A / D) converters 22A to 22L corresponding to the signal reading units 21A to 21L, and each A / D converter 22A And a plurality of FIFO (First-In-First-Out) data buffers 23A to 23L corresponding to .about.22L.

  The solid-state imaging device 1 includes a flat substrate 2, scintillators 4 </ b> A and 4 </ b> B, and an X-ray shielding member 5. The semiconductor substrates 3A and 3B described above are attached to the base material 2, and the scintillators 4A and 4B are disposed on the semiconductor substrate 3A and the semiconductor substrate 3B, respectively. The scintillators 4A and 4B generate scintillation light according to the incident X-rays, convert the X-ray images into optical images, and output the optical images to the pixel arrays 10A and 10B, respectively. The scintillators 4A and 4B are installed so as to cover the pixel arrays 10A and 10B, respectively, or are provided on the pixel arrays 10A and 10B by vapor deposition. The X-ray shielding member 5 is made of a material such as lead that has an extremely low X-ray transmittance. The X-ray shielding member 5 covers the peripheral portions of the semiconductor substrates 3A and 3B, particularly the regions where the scanning shift registers 30A and 30B and the signal reading units 21A to 21L are arranged, and the scanning shift registers 30A and 30B and the signal reading unit. X-ray incidence to 21A to 21L is prevented.

  The pixel array 10A is configured by two-dimensionally arranging M × NA pixels P (see FIGS. 4A and 4B) in M rows and NA columns. Further, the pixel array 10B is configured by two-dimensionally arranging M × NB pixels P in M rows and NB columns. In FIG. 3, the column direction coincides with the X-axis direction, and the row direction coincides with the Y-axis direction. Each of M, NA, and NB is an integer of 2 or more and satisfies NA> NB. The number (NA + NB) of pixels P in the row direction in the pixel arrays 10A and 10B is preferably larger than the number M of pixels P in the column direction. In this case, the imaging region including the pixel arrays 10A and 10B has a rectangular shape in which the row direction (Y-axis direction) is a long direction and the column direction (X-axis direction) is a short direction. The pixels P are arranged at a pitch of 100 μm, for example, and are of the PPS system and have a common configuration.

  Here, in FIG. 3, among the NA columns included in the pixel array 10A, the column located at the left end (that is, the column with the smallest Y coordinate) is the first column, and the column located at the opposite right end is the NA column. And Also, in the figure, among the NB columns included in the pixel array 10B, the column located at the left end (the column with the smallest Y coordinate) is the first column, and the column located at the opposite right end is the NB column. . In this case, in the present embodiment, the pixel arrays 10A and 10B are arranged so that the first column of the pixel array 10B and the NA column of the pixel array 10A are along each other.

  In addition, one or a plurality of continuous rows including the first row of the pixel array 10A are covered with the X-ray shielding member 5 and are insensitive areas shielded from incident X-rays. That is, no light is incident on these columns and no charge is generated, which does not contribute to imaging. Similarly, one or a plurality of continuous columns including the NB column of the pixel array 10B are also covered with the X-ray shielding member 5 and are insensitive areas. Therefore, in the pixel arrays 10 </ b> A and 10 </ b> B, an effective region for imaging is configured by the other pixel columns except for these pixel columns covered by the X-ray shielding member 5. In other words, the effective imaging area in the solid-state imaging device 1 is defined by the opening 5 a of the X-ray shielding member 5.

  The signal output unit 20 holds a voltage value corresponding to the amount of charge output from each pixel P, converts the held voltage value into a digital value, and outputs the digital value to the data bus DB. The plurality of signal readout units 21A to 21H are provided corresponding to two or more pixel columns in the pixel array 10A per signal readout unit, and the amount of charge output from each pixel P of the corresponding pixel column is determined. The corresponding voltage value is held, and this voltage value is output to the corresponding A / D converters 22A to 22H. Similarly, the plurality of signal readout units 21I to 21L are provided corresponding to two or more pixel columns in the pixel array 10B per signal readout unit, and the charges output from the respective pixels P of the corresponding pixel column. The voltage value corresponding to the amount of the signal is held, and this voltage value is output to the corresponding A / D converters 22I to 22L. At this time, the scan shift registers 30A and 30B control each pixel P so that the charges accumulated in each pixel P are sequentially output to the signal reading units 21A to 21L for each row.

  The plurality of A / D converters 22A to 22L receive the voltage values output from the corresponding signal reading units 21A to 21L, perform A / D conversion processing on the input voltage values (analog values), A digital value corresponding to the input voltage value is generated. The plurality of A / D converters 22A to 22L output the generated digital values to the FIFO data buffers 23A to 23L corresponding to the A / D converters 22A to 22L.

  The plurality of FIFO data buffers 23A to 23L obtain all the digital values corresponding to the NA column included in the pixel array 10A and the NB column included in the pixel array 10B, and then transfer the digital values to the data bus DB. Output. At this time, the FIFO data buffers 23A to 23F are arranged on the left side of the digital values corresponding to the respective columns from the first column to the n-th column (2 ≦ n <NA) of the pixel array 10A (the boundary line E in FIG. 3). The digital values stored in the six FIFO data buffers 23A to 23F) are sequentially output to the data bus DB. In parallel with this output operation, the FIFO data buffers 23G to 23L are arranged in columns from the (n + 1) th column of the pixel array 10A through the NA column and the first column of the pixel array 10B to the NB column. Corresponding digital values (digital values stored in the six FIFO data buffers 23G to 23L arranged on the right side of the boundary line E in FIG. 3) are sequentially output to the data bus DB. That is, when viewed from a processing device such as a CPU that controls the data bus DB, the six FIFO data buffers 23A to 23F arranged on the left side of the boundary line E constitute one output port, and on the right side of the boundary line E. Six FIFO data buffers 23G to 23L arranged in (1) constitute another output port.

Subsequently, a detailed configuration of the solid-state imaging device 1 according to the present embodiment will be described. FIG. 5 is a diagram illustrating an internal configuration of the solid-state imaging device 1, and represents a portion (pixel block) of the pixel array 10A (10B) corresponding to one signal readout unit among the plurality of signal readout units 21A to 21L. As shown. The pixel block in the pixel array 10A (10B) is configured by two-dimensionally arranging pixels P1 _{, i to} PM _{, k} in M rows (k-i + 1) columns. The pixel P _{m, j} is located in the m-th row and the j-th column. Here, i and k are integers of 1 or more and satisfy 1 ≦ i <k ≦ NA (or NB). M is an integer from 1 to M, and j is an integer from i to k. Each of the (k−i + 1) pixels P _{m, i to} P _{m, k} in the m-th row is connected to the scan shift register 30A (or 30B) by the m-th row selection wiring LV _{, m} . In FIG. 5, the scan shift registers 30 </ b> A and 30 </ b> B are included in the control unit 6. The output ends of the _M pixels P _{1, j to} P _{M, j} in the j-th column are connected to the integration circuit S _j of the signal reading units 21A to 21L by the j-th column reading wiring L _{O, j.} Yes.

Each of the signal readout units 21A to 21L includes (k−i + 1) integration circuits S _{i to} S _k and (k−i + 1) holding circuits H _{i to} H _k . Each integrating circuit S _j has a common configuration. Each holding circuit H _j has a common configuration. Each integrating circuit S _j has an input terminal connected to the readout wiring L _{O, j} , accumulates electric charge input to this input terminal, and outputs a voltage value corresponding to the amount of accumulated electric charge from the output terminal. Output to the holding circuit _Hj . The (k-i + 1) pieces of the integrating circuit _S i to S _k, respectively, connected to the control unit 6 by a reset wiring _{L R,} and also connected to the control unit 6 by a gain setting wiring _{L G.} Each holding circuit H _j has an input terminal connected to the output terminal of the integrating circuit S _j , holds a voltage value input to the input terminal, and the held voltage value is connected to the voltage output wiring from the output terminal. Output to L _out . Each of the (k−i + 1) holding circuits H _{i to} H _k is connected to the control unit 6 by a holding wiring L _H. Moreover, each holding circuit _{H j} is the j-th column selecting wiring _{L H,} are connected to the read shift register 31A of the control unit 6 (or 31B) by _j.

Each of the A / D converters 22A to 22L receives a voltage value output from each of the (k−i + 1) holding circuits H _{i to} H _k to the voltage output wiring L _out and inputs the input voltage value (analog value). A / D conversion processing is performed on the data, and digital values corresponding to the input voltage values are output to the FIFO data buffers 23A to 23L, respectively.

The scan shift register 30A (30B) of the control unit 6 outputs the mth row selection control signal Vsel (m) to the mth row selection wiring LV _{, m} , and this mth row selection control signal Vsel (m). Are given to (k−i + 1) pixels P _{m, i to} P _{m, k in the m} -th row. The M row selection control signals Vsel (1) to Vsel (M) are sequentially set to significant values. The read shift register 31A (31B) of the control unit 6 outputs the j-th column selection control signal Hsel (j) to the j-th column selection wiring LH _{, j} , and this j-th column selection control signal Hsel ( j) is applied to the holding circuit H _j . The (k−i + 1) column selection control signals Hsel (i) to Hsel (k) are also sequentially set to significant values.

The control unit 6 outputs a reset control signal Reset to the reset wiring _{L R,} giving the reset control signal Reset to the (k-i + 1) pieces of the integrating circuit _S i to S _k, respectively. Control unit 6 outputs a gain setting signal Gain to the gain setting wiring _{L G,} giving the gain setting signal Gain to the (k-i + 1) pieces of the integrating circuit _S i to S _k, respectively. Control unit 6 outputs a holding control signal Hold to the holding wiring _{L H,} it gives the holding control signal Hold to the (k-i + 1) pieces of the holding circuit _H i to H _k, respectively. Furthermore, although not shown, the control unit 6 also controls A / D conversion processing in the A / D converters 22A to 22L.

FIG. 6 is a circuit diagram of each of the pixel P _{m, j} , the integration circuit S _j, and the holding circuit H _j included in the pixel block of the solid-state imaging device 1. Here, a circuit diagram of the pixel P _{m, j} is shown on behalf of the pixels P _{1, i to} PM _{, k} , and an integration circuit S _j on behalf of the (k−i + 1) number of integration circuits S _{i to} S _k. In addition, a circuit diagram of the holding circuit H _j is shown as a representative of (k−i + 1) holding circuits H _{i to} H _k . That is, a circuit portion related to the pixel P _{m, j} in the m-th row and the j-th column and the j-th column readout wiring L _{O, j} is shown.

Pixel _{P m, j} includes a photodiode PD and a readout switch SW _1. The anode terminal of the photodiode PD is grounded, is connected the cathode terminal of the photodiode PD is the j-th column readout wiring L _O via the readout switch SW _1, and _j. The photodiode PD generates an amount of charge corresponding to the incident light intensity, and accumulates the generated charge in the junction capacitor. Readout switch SW ₁ is the m row selecting wiring _{L V,} m-th row selection control signal Vsel passed through the _m (m) is given from the control unit 6. The m-th row selection control signal Vsel (m) includes the NA pixels P _{m, 1 to} P _{m, NA} in the m-th row in the pixel array 10A and the NB pixels P _m, m in the m-th row in the pixel array 10B _{. 1} to P _m, is an indication of the _NB each opening and closing operation of the readout switch SW _1.

The pixel P _m, the _j, the m-th row selection control signal Vsel (m) is read switch SW ₁ in the open when a low level, the j-th column readout wiring charges generated in the photodiode PD L _{O , J} without being output to the junction capacitor. On the other hand, the m-th row selection control signal Vsel (m) is the read switch SW ₁ in closed when a high level, the electric charge accumulated in the junction capacitance portion is generated in the photodiode PD until it is for reading The signal is output to the j-th column readout wiring L _{O, j} through the switch SW ₁ .

The j-th column readout wiring L _{O, j} is connected to the readout switch SW _{1 of} each of the _M pixels P _{1, j to} P _{M, j} in the j-th column in the pixel array 10A (or 10B). The j-th column readout wiring L _{O, j} uses the charge generated in the photodiode PD of any one of the _M pixels P _{1, j to} P _{M, j} as the readout switch SW _{1 of the} pixel. _Is transferred to the integrating circuit S _j .

The integrating circuit S _j includes an amplifier A ₂ , an integrating capacitive element C ₂₁ , an integrating capacitive element C ₂₂ , a discharging switch SW ₂₁ and a gain setting switch SW ₂₂ . Integrating capacitive element C ₂₁ and the discharge switch SW ₂₁ is connected in parallel to each other, and provided between an input terminal of the amplifier A ₂ and the output terminal. Moreover, the integrating capacitive element C ₂₂ and the gain setting switch SW ₂₂ is connected in series to each other, the input of the amplifier A ₂ so that the gain setting switch SW ₂₂ is connected to the input terminal side of the amplifier A ₂ It is provided between the terminal and the output terminal. The input terminal of the amplifier A _2, j-th column readout wiring L _O, and is connected to the _j.

The discharge switch _{SW 21,} the reset control signal Reset passing through the resetting wiring _{L R} given from the control unit 6. The reset control signal Reset is an opening / closing operation of the discharge switches SW ₂₁ of the _NA integration circuits S _{1 to} S _NA corresponding to the pixel array 10A and the NB integration circuits S _{1 to} S _NB corresponding to the pixel array 10B. Is instructed. Gain setting switch _{SW 22,} the gain setting signal Gain is provided passing through the gain setting wiring _{L G} from the controlling section 6. The gain setting signal Gain is used to open / close the gain setting switch SW ₂₂ of each of the _NA integration circuits S _{1 to} S _NA corresponding to the pixel array 10A and the NB integration circuits S _{1 to} S _NB corresponding to the pixel array 10B. The operation is instructed.

In the integration circuit S _j , the integrating capacitive elements C ₂₁ and C ₂₂ and the gain setting switch SW ₂₂ constitute a feedback capacitive unit having a variable capacitance value. That is, when the gain setting signal Gain is at low level the gain setting switch SW ₂₂ is open, the capacitance value of the feedback capacitance section is equal to the capacitance value of the integrating capacitive element C _21. On the other hand, when the gain setting signal Gain is at a high level and the gain setting switch SW ₂₂ is closed, the capacitance value of the feedback capacitance section is equal to the sum of the capacitance values of the integrating capacitive elements C ₂₁ and C ₂₂ . When the reset control signal Reset is at a high level, the discharging switch SW ₂₁ is closed, the feedback capacitor unit is discharged, and the voltage value output from the integrating circuit S _j is initialized. On the other hand, when the reset control signal Reset is at a low level, the discharge switch SW ₂₁ is opened, the charge input to the input terminal is accumulated in the feedback capacitor unit, and the voltage value corresponding to the accumulated charge amount is an integration circuit. S _{j is} output.

The holding circuit H _j includes an input switch SW ₃₁ , an output switch SW _32, and a holding capacitive element C ₃ . One end of the holding capacitive element C ₃ is grounded. The other end of the holding capacitive element C ₃ is connected via an input switch SW ₃₁ is connected to the output terminal of the integrating circuit S _j, and is connected to the voltage output wiring L _out via the output switch SW _32. The input switch _{SW 31,} is given holding control signal Hold passed through the holding wiring _{L H} from the controlling section 6. The holding control signal Hold is an opening / closing operation of the input switches SW ₃₁ of the _NA holding circuits H _{1 to} H _NA corresponding to the pixel array 10A and the NB holding circuits H _{1 to} H _NB corresponding to the pixel array 10B. Is a signal for instructing. The output switch SW ₃₂ is supplied with the j-th column selection control signal Hsel (j) from the control unit 6 through the j-th column selection wiring L _{H, j} . The j-th column selection control signal Hsel (j) is a signal for instructing the opening / closing operation of the output switch SW ₃₂ of the holding circuit H _j .

In the holding circuit H _j , when the holding control signal Hold changes from the high level to the low level, the input switch SW ₃₁ changes from the closed state to the open state, and the voltage value input to the input terminal at that time is held. It is held in the use capacitive element C _3. Further, when the j-th column selection control signal Hsel (j) is at a high level, the output switch SW ₃₂ is closed, and the voltage value held in the holding capacitive element C ₃ is supplied to the voltage output wiring L _out . Is output.

When the controller 6 outputs a voltage value corresponding to the received light intensity of each of the (k−i + 1) pixels P _{m, i to} P _{m, k} in the m-th row in the pixel array 10A (or 10B), the reset control is performed. After instructing the signal Reset to open the discharge switch SW ₂₁ of each of the (k−i + 1) integration circuits S _{i to} S _k once after being closed, the pixel arrangement is performed by the m-th row selection control signal Vsel (m). of the m-th row in the 10A (10B) (k-i + 1) pixels _{P m,} i _~P m, _k and instructs each of the readout switch SW ₁ in over a predetermined period close as. The control unit 6 instructs the input switch SW ₃₁ of each of the (k−i + 1) holding circuits H _{i to} H _k to change from the closed state to the open state by the holding control signal Hold during the predetermined period. Then, after the predetermined period, the control unit 6 sets the output switch SW ₃₂ of each of the (k−i + 1) holding circuits H _{i to} H _k by the column selection control signals Hsel (i) to Hsel (k). Instructs to close sequentially for a certain period of time. The control unit 6 sequentially performs the above control for each row.

Thus, the control unit 6 controls the pixels _{P 1,} i _{~P M, k} respectively opening and closing operations of the readout switches SW ₁ included in each pixel block of the pixel array 10A (10B), the signal readout section The voltage value holding operation and the output operation in 21A to 21L are controlled. As a result, the control unit 6 reads out the voltage value corresponding to the amount of charge generated in each photodiode PD of the M × (k−i + 1) pixels P _{1, i to} P _{M, k} for each frame. The output is repeated from the units 21A to 21L.

  Next, the operation of the solid-state imaging device 1 will be described in detail. In the solid-state imaging device 1, under the control of the control unit 6, M row selection control signals Vsel (1) to Vsel (M), (NA + NB) column selection control signals Hsel (1) to Hsel (NA). And Hsel (1) to Hsel (NB), the reset control signal Reset, and the holding control signal Hold each change in level at a predetermined timing, so that images of light incident on the pixel arrays 10A and 10B are captured and frame data is acquired. Can be obtained. In the following description, it is assumed that the gain setting switch SW22 is closed.

FIG. 7 shows the operation of the pixel blocks included in the first column to the n-th column (pixel array on the left side of the boundary line E shown in FIG. 3) of the pixel array 10A, and the signal output unit 20 corresponding to this pixel block. It is a timing chart explaining operation. In this figure, in order from the top, (a) a reset control signal Reset instructing the opening / closing operation of the discharge switch SW ₂₁ of each of the integration circuits S _{i to} S _k , (b) the pixel P in the first row in the pixel block. _{1, i to} P _{1, k} The first row selection control signal Vsel (1) for instructing the opening / closing operation of the readout switch SW ₁ , (c) the second row of pixels P _{2, i to} P in the pixel block. _{2, k} each of the second row selection control signal Vsel for instructing opening and closing operations of the readout switches SW ₁ (2), and, (d) is opening and closing operation of the holding circuit _H i to H _k respective input switch _{SW 31} A holding control signal Hold to be indicated is shown.

In this figure, (e) the i-th column selection control signal Hsel (i) instructing the opening / closing operation of the output switch SW ₃₂ of the holding circuit H _i and (f) the holding circuit H _j the j-th column selection control signal Hsel instructing opening and closing operations of the output switch _{SW 32} (j), the instructing opening and closing operations of the output switch _{SW 32} of the (g) the holding circuit _{H k-2 (k-2} ) column Selection control signal Hsel (k-2), (h) the (k-1) th column selection control signal Hsel (k-1) for instructing the opening / closing operation of the output switch SW ₃₂ of the holding circuit H _k-1 , and (I) The k-th column selection control signal Hsel (k) for instructing the opening / closing operation of the output switch SW ₃₂ of the holding circuit H _k is shown.

Reading of charges generated in the photodiode PD of each of the (k−i + 1) pixels P _{1, i to} P _{1, k in} the first row and accumulated in the junction capacitance portion is performed as follows. Before the time _{t 10,} M row selecting control signals Vsel (1) ~Vsel (M) , (k-i + 1) number of column selection control signal Hsel (i) ~Hsel (k) , the reset control signal Reset, and the Each of the holding control signals Hold is at a low level.

Period from the time _{t 10} to the time _{t 11,} the reset control signal Reset to be output to the reset wiring _{L R} from the controlling section 6 becomes the high level, thereby, (k-i + 1) pieces of the integrating circuit _S i to S _k In each case, the discharging switch SW ₂₁ is closed, and the integrating capacitive elements C ₂₁ and C ₂₂ are discharged. Further, during a period from the time _{t 12} after the time _{t 11} to time _{t 15,} the first row selecting control output from the control unit 6 to the first row selecting wiring _{L V, 1} signal Vsel (1) a high level next, thereby, the first row in the pixel block (k-i + 1) pixels _P 1, i _{to P 1, k} the readout switch SW ₁ in each of closed.

Within this period (t _{12 to} t ₁₅ ), during the period from time t ₁₃ to time t ₁₄ , the holding control signal Hold output from the control unit 6 to the holding wiring L _H becomes high level. -i + 1) pieces of the holding circuit _H i to H _k input switch _{SW 31} closes in each.

During the period (t _{12 to} t ₁₅ ), the readout switch SW ₁ of each pixel P _{1, j} in the first row is closed, and the discharge switch SW ₂₁ of each integration circuit S _j is open. Therefore, the charges generated so far in the photodiode PD of the pixel P _{1, j} and accumulated in the junction capacitance portion are the readout switch SW ₁ and the j-th column readout wiring L _{O of the} pixel P _{1, j. , J} and transferred to the integrating capacitive elements C ₂₁ and C ₂₂ of the integrating circuit S _j and stored. Then, a voltage value corresponding to the amount of charges accumulated in the integrating capacitive element C _21, C ₂₂ of each integrating circuit S _j is output from the output terminal of the integrating circuit S _j.

At time _{t 14} in the period _(t 12 _{~t 15)} inside, by holding control signal Hold switches from high level to low level, the (k-i + 1) pieces of the holding circuit _H i to H _k, respectively, for input The switch SW ₃₁ changes from the closed state to the open state, and at this time, the voltage value output from the output terminal of the integrating circuit S _j and input to the input terminal of the holding circuit H _j is held in the holding capacitive element C _3. The

After a period (t _{12 to} t ₁₅ ), column selection control signals Hsel (i) to Hsel (k) output from the control unit 6 to the column selection wirings L _{H, i to} L _{H, k} are Hsel. Starting from (k), in reverse order (that is, in the order in which the column numbers are in descending order), it is at a high level for a certain period, whereby output switches for each of the (k−i + 1) holding circuits H _{i to} H _k The SW ₃₂ is closed in reverse order for a certain period, and the voltage value held in the holding capacitive element C ₃ of each holding circuit H _j is output in reverse order to the voltage output wiring L _out via the output switch SW _32. The Voltage value _{V out} to be output to the voltage output wiring _{L out} is intended to represent the received light intensity in the first row of the (k-i + 1) pixels _P 1, i _{to P 1, k} respective photodiodes PD is there. The voltage value output in reverse order from each of the (k−i + 1) holding circuits H _{i to} H _k is input to one of the A / D converters 22A to 22L, and converted into a digital value corresponding to the input voltage value. Converted.

Subsequently, the charge generated in the photodiode PD of each of the (k−i + 1) pixels P _{2, i to} P _{2, k} in the second row is read as follows. .

From time t _{20 when the} column selection control signal Hsel (k) becomes high level in the above-described operation, to time t ₂₁ after the time when the column selection control signal Hsel (i) once becomes high level and then becomes low level. period, the reset control signal reset to be output to the reset wiring _{L R} from the controlling section 6 becomes the high level, thereby, (k-i + 1) in number of the integrating circuit _S i to S _k, respectively, the discharge switch _{SW 21} Is closed, and the integrating capacitive elements C ₂₁ and C ₂₂ are discharged. Further, the period from the time _{t 22} after the time _{t 21} to time _{t 25,} the second row selection control signal Vsel (2) a high level output from the control section 6 to the second row selecting wiring _{L V, 2} next, thereby, the second row in the pixel block (k-i + 1) pixels _P 2, i _{to P 2, k} the readout switch SW ₁ in each of closed.

Within this period (t _{22 to} t ₂₅ ), during the period from time t ₂₃ to time t ₂₄ , the holding control signal Hold output from the control unit 6 to the holding wiring L _H becomes high level. -i + 1) pieces of the holding circuit _H i to H _k input switch _{SW 31} closes in each.

After the period (t _{22 to} t ₂₅ ), the column selection control signals Hsel (i) to Hsel (k) output from the control unit 6 to the column selection wirings L _{H, i to} L _{H, k} are Hsel ( The output switch SW _{32 of} each of the (k−i + 1) holding circuits H _{i to} H _k is closed in a reverse order for a fixed period. As described above, in the second row (k-i + 1) pixels _P 2, i _{to P 2, k} voltage value _{V out} indicating the received light intensities in the photodiodes PD is output to the voltage output wiring _{L out} Is done. A voltage value output in reverse order from each of the (k−i + 1) holding circuits H _{i to} H _k is input to one of the A / D converters 22A to 22L, and a digital value corresponding to the input voltage value Is converted to

FIG. 8 shows pixel blocks included in the (n + 1) th to NAth columns of the pixel array 10A and the first to NBth columns (pixel array on the right side of the boundary line E shown in FIG. 3) of the pixel array 10B. 6 is a timing chart for explaining the operation of the signal output unit 20 corresponding to the pixel block. In this figure, in order from the top, (a) reset control signal Reset, (b) first row selection control signal Vsel (1), (c) second row selection control signal Vsel (2), and (d) held. A control signal Hold is shown. The operations of these signals are the same as those shown in FIGS. 7A to 7D, and the pixels P _{1, i to} P _{M, k} , the integration circuits S _{i to} S _k , and the holding circuit H _i. operation of to H _k are also the holding circuit H _i to H _k similar operation as the output order of except for the above, omitted these a detailed description.

Further, in this figure, in order further Subsequently, (e) the i-th column selection control signal Hsel for instructing opening and closing operations of the output switch _{SW 32} of the holding circuit _{H i} (i), of the holding circuit _{H i + 1} (f) the instructing opening and closing operations of the output switch _{SW 32} (i + 1) column selection controlling signal Hsel (i + 1), first for instructing opening and closing operations of the output switch _{SW 32} of the (g) holding circuits _{H i + 2 (i + 2} ) column selection control The signal Hsel (i + 2), (h) the j-th column selection control signal Hsel (j) for instructing the opening / closing operation of the output switch SW ₃₂ of the holding circuit H _j , and (i) the output switch SW of the holding circuit H _{k. A} k-th column selection control signal Hsel (k) instructing ₃₂ open / close operations is shown.

The charge generated in the photodiode PD of each of the (k−i + 1) pixels P _{1, i to} P _{1, k in} the first row and stored in the junction capacitor is read, and held in each holding circuit H _j . After the period (t _{10 to} t ₁₅ ) held in the capacitive element C ₃ , the column selection control signals Hsel (i) to output from the control unit 6 to the column selection wirings L _{H, i to} L _{H, k} Hsel (k) starts from Hsel (i) and becomes high level for a certain period in the normal order (that is, in the order in which the column numbers are in ascending order), whereby (k−i + 1) holding circuits H _i to The output switch SW _{32 of} each of the H _k is closed in a positive order for a certain period, and the voltage value held in the holding capacitive element C ₃ of each holding circuit H _j is passed through the output switch SW ₃₂ and the voltage output wiring L Output to _out in normal order. A voltage value output in the normal order from each of the (k−i + 1) holding circuits H _{i to} H _k is input to one of the A / D converters 22A to 22L, and a digital value corresponding to the input voltage value Is converted to

Subsequently, the charge generated in the photodiode PD of each of the (k−i + 1) pixels P _{2, i to} P _{2, k} in the second row is read out and accumulated in the junction capacitance portion, and each holding circuit H is read out. _After a period (t _{21 to} t ₂₅ ) held in the holding capacitance element C ₃ of _j, the column selection control signal Hsel (from the control unit 6 to the column selection wirings L _{H, i to} L _{H, k} i) to Hsel (k) start from Hsel (i) and become high level for a certain period in the forward order, whereby the output switch SW _{32 of} each of the (k−i + 1) holding circuits H _{i to} H _k Close in a regular order for a certain period. As described above, in the second row (k-i + 1) pixels _P 2, i _{to P 2, k} voltage value _{V out} indicating the received light intensities in the photodiodes PD is output to the voltage output wiring _{L out} Is done. The voltage value output in the normal order from each of the (k−i + 1) holding circuits H _{i to} H _k is input to any of the A / D converters 22A to 22L, and the digital value corresponding to the input voltage value is obtained. Converted to a value.

Subsequent to the operations for the first row and the second row shown in FIG. 7 and FIG. 8, the same operation is performed from the third row to the M-th row to represent an image obtained by one imaging. Frame data is obtained. When the operation for the Mth row is completed, the same operation is performed again in the range from the first row to the Mth row, and frame data representing the next image is obtained. As described above, by repeating the same operation at a constant cycle, the voltage value _Vout representing the two-dimensional intensity distribution of the light image received by the pixel block is output to the voltage output wiring _Lout , and the frame data is repeatedly generated. Is obtained.

  Next, the operation of the FIFO data buffers 23A to 23L will be described. FIG. 9 shows the input of FIFO data buffers 23A to 23F provided corresponding to the pixel blocks included in the first to nth columns (pixel array on the left side of the boundary line E shown in FIG. 3) of the pixel array 10A. It is a timing chart explaining output operation. In this figure, in order from the top, (a) timing at which digital values are written from the A / D converters 22A to 22F to the FIFO data buffers 23A to 23F, and (b) digital values stored in the FIFO data buffer 23A are read out. (C) timing when a digital value stored in the FIFO data buffer 23B is read, (d) timing when a digital value stored in the FIFO data buffer 23C is read, (e) stored in the FIFO data buffer 23D The timing at which the digital value is read out, (f) the timing at which the digital value stored in the FIFO data buffer 23E is read out, and (g) the timing at which the digital value stored in the FIFO data buffer 23F is read out are shown.

As shown in FIG. 9A, the digital value writing operation from the A / D converters 22A to 22F to the FIFO data buffers 23A to 23F is performed in parallel in each of the FIFO data buffers 23A to 23F. The timing at which the operation of writing the digital values corresponding to the m-th row among the first to M-th rows constituting the pixel arrays 10A and 10B to the FIFO data buffers 23A to 23F is started (time t _{30 in the} figure). The digital value corresponding to the previous (m−1) th row starts to be read out from the FIFO data buffers 23A to 23F via the data bus DB (see FIG. 3) at substantially the same timing as ().

  At this time, the digital values stored in the FIFO data buffers 23A to 23F are read in the reverse order of the column numbers of the pixel arrays 10A and 10B from the FIFO data buffer 23F to the FIFO data buffer 23A. Specifically, after the read operation from the FIFO data buffer 23F (FIG. 9 (g)) is completed, the read operation from the FIFO data buffer 23E is started (FIG. 9 (f)), and the read from the FIFO data buffer 23E is started. After the operation is completed, a read operation from the FIFO data buffer 23D is started (FIG. 9 (e)). Thereafter, until the reading of the FIFO data buffer 23A is completed (FIG. 9 (b)), a digital operation is performed from each FIFO data buffer. Values are read in this order.

  As described above, the voltage value for each column held in each of the signal reading units 21A to 21F is output to the corresponding A / D converters 22A to 22F in the reverse order of the column numbers. The digital values output from the A / D converters 22A to 22F are simultaneously written in the FIFO data buffers 23A to 23F in parallel and are read in this order when the digital values are read via the data bus DB. (Ie in reverse order of column number). Therefore, by starting reading from the FIFO data buffer 23F as described above, the signal output unit 20 outputs the digital values corresponding to the respective columns from the first column to the n-th column of the pixel array 10A from the n-th column. Starting from the first column to the first column, the column numbers are output in reverse order.

The FIFO data buffers 23A to 23F output the digital value corresponding to the (m-1) th row to the data bus DB in this way, and then correspond to the mth row inputted in parallel with the output operation of the digital value. The digital value to be processed is substantially the same as time t ₃₁ in the figure (timing for starting the operation of writing the digital value corresponding to the (m + 1) th row to the FIFO data buffers 23A to 23F) and the (m−1) th row. Are output to the data bus DB in the same order as when the digital values corresponding to are output. By performing such an operation from the first row to the Mth row, the frame data is output to the data bus DB. When the operation is completed for the Mth row, the same operation is performed again in the range from the first row to the Mth row, and frame data representing the next image is output.

  FIG. 10 shows pixel blocks included in the (n + 1) th to NAth columns of the pixel array 10A and the first to NBth columns (pixel array on the right side of the boundary line E shown in FIG. 3) of the pixel array 10B. It is a timing chart explaining the input / output operation | movement of FIFO data buffer 23G-23L provided correspondingly. In this figure, in order from the top, (a) timing at which digital values are written from the A / D converters 22G to 22L to the FIFO data buffers 23G to 23L, and (b) digital values stored in the FIFO data buffer 23G are read out. (C) timing when the digital value stored in the FIFO data buffer 23H is read, (d) timing when the digital value stored in the FIFO data buffer 23I is read, (e) stored in the FIFO data buffer 23J The timing at which the digital value is read, (f) the timing at which the digital value stored in the FIFO data buffer 23K is read, and (g) the timing at which the digital value stored in the FIFO data buffer 23L is read out are shown.

As shown in FIG. 10A, the digital value writing operation from the A / D converters 22G to 22L to the FIFO data buffers 23G to 23L is performed in parallel in each of the FIFO data buffers 23G to 23L. Of the first row to the M rows constituting the pixel array 10A, the 10B, timing (time _{t 30} in FIG operation for writing digital values corresponding to the m-th row into the FIFO data buffer 23G~23L starts The digital value corresponding to the previous (m−1) th row starts to be read out from the FIFO data buffers 23G to 23L via the data bus DB (see FIG. 3) at almost the same timing as ().

  At this time, the digital values stored in the FIFO data buffers 23G to 23L are read in the normal order with respect to the column numbers of the pixel arrays 10A and 10B from the FIFO data buffer 23G to the FIFO data buffer 23L. Specifically, after the read operation from the FIFO data buffer 23G (FIG. 10B) is completed, the read operation from the FIFO data buffer 23H is started (FIG. 10C), and the read from the FIFO data buffer 23H is performed. After the operation is completed, a read operation from the FIFO data buffer 23I is started (FIG. 10 (d)). Thereafter, until the reading of the FIFO data buffer 23L is completed (FIG. 10 (g)), the data is digitally read from each FIFO data buffer. Values are read in this order.

  As described above, the voltage value for each column held in each of the signal reading units 21G to 21L is output to the corresponding A / D converters 22G to 22L in the normal order with respect to the column numbers. The digital values output from the A / D converters 22G to 22L are simultaneously written into the FIFO data buffers 23G to 23L in parallel, and the digital values are read out via the data bus DB in this order. (Ie, in normal order with respect to column number). Therefore, by starting reading from the FIFO data buffer 23G as described above, the signal output unit 20 starts from the (n + 1) th column of the pixel array 10A through the NA column and the first column of the pixel array 10B to the NBth. The digital values corresponding to the columns up to the column are output in the normal order, that is, in the reverse order to the output order of the digital values corresponding to the first to nth columns of the pixel array 10A.

The FIFO data buffers 23G to 23L output the digital value corresponding to the (m-1) th row to the data bus DB in this way, and then correspond to the mth row inputted in parallel with the output operation of the digital value. The digital value to be processed is substantially the same as the time t ₃₁ in the figure (timing at which the operation of writing the digital value corresponding to the (m + 1) th row to the FIFO data buffers 23G to 23L) and the (m−1) th row. Are output to the data bus DB in the same order as when the digital values corresponding to are output. By performing such an operation from the first row to the Mth row, the frame data is output to the data bus DB. When the operation is completed for the Mth row, the same operation is performed again in the range from the first row to the Mth row, and frame data representing the next image is output.

  The effects obtained by the solid-state imaging device 1 of the present embodiment described above will be described together with the problems in the conventional solid-state imaging device. In general, the size required for the pixel array of the solid-state imaging device varies depending on the imaging application. For example, in cephalometric imaging in dental diagnosis, the pixel array of the solid-state imaging device is 22 cm or longer. Is required. In cephalometric imaging, the positional relationship between the patient's skull and the maxilla and mandible is grasped, and information such as which part is extracted or whether the patient's orthodontic treatment is easy or difficult is obtained. This is because the vertical width of the array needs to cover almost the entire head of an adult.

  However, when such a long pixel arrangement is required, it may be difficult to produce the pixel arrangement on a single substrate depending on the diameter of the semiconductor wafer used for the production of the solid-state imaging device. . In such a case, two substrates that are shorter than the dimensions required for the pixel arrangement are arranged in the longitudinal direction, and the respective pixel arrangements are combined and used as one solid-state imaging device (so-called tiling). Can be satisfied.

  However, when two substrates are used side by side, a dead area C occurs at the boundary portion (seam) between the pixel arrays as shown in FIG. And depending on the imaging application, there are cases where there is a restriction on the position of such a dead area C. In the case of X-ray imaging in dental diagnosis, as shown in FIG. 11A, the two pixel arrays 110A and 110B are tiled in the vertical direction and imaged while being translated in the horizontal direction. When the vertical widths of 110B are equal to each other, the boundary between the pixel array 110A and the pixel array 110B passes through the ear of the subject A as shown in FIG. Note that areas FA and FB shown in the figure indicate imaging ranges by the pixel arrays 110A and 110B, respectively. In cephalometric imaging, information regarding the region G from the jaw of the subject A to the vicinity including the ears shown in FIG. 11A is important, but the boundary between the pixel array 110A and the pixel array 110B is the interior of the region G. Passing through this leads to lack of information regarding the region G, and is not preferable. Therefore, in such a case, as shown in FIG. 11B, the widths of the two pixel arrays 120A and 120B in the longitudinal direction are made different from each other, so that the boundary portion between the pixel arrays, that is, the dead area The movement path can be removed from the region G.

  Further, making the widths of the two pixel arrays to be tiled different in the longitudinal direction also has the following advantages. FIG. 12A is a diagram illustrating a state in which a plurality of pixel arrays 120A having a wide width in the longitudinal direction and a plurality of pixel arrays 120B having a narrow width in the longitudinal direction are impositioned on the silicon wafer W. FIG. 12B is a diagram showing a state in which a plurality of pixel arrays 110 having the same width in the longitudinal direction are impositioned on the silicon wafer W. As is apparent from these drawings, a plurality of pixel arrays 120A having a longer width in the longitudinal direction and a plurality of narrower widths in the longitudinal direction than imposing a plurality of pixel arrays 110 having the same width in the longitudinal direction. The imposition in combination with the pixel array 120B reduces the useless portion of the silicon wafer W and allows the pixel array to be extracted more efficiently.

  Here, in order to realize the above-described tiling method, when two substrates constituting a PPS solid-state imaging device are juxtaposed in the row direction of each pixel array, the longitudinal direction of the pixel array of each substrate is When the widths are different from each other, the number of columns of the pixel array on each substrate is different from each other, resulting in the following problem.

It is assumed that one pixel array having a wide width in the longitudinal direction has eight pixel blocks having the same number of columns, and the other pixel array having a narrow width in the length direction has four pixels having the same number of columns. It shall have a block. FIGS. 13A to 13H are timings showing examples of timings at which digital values are output from the eight FIFO data buffers (1) to (8) respectively corresponding to the eight pixel blocks of one pixel array. FIGS. 13 (i) to (l) are timing charts at which digital values are output from the four FIFO data buffers (9) to (12) respectively corresponding to the four pixel blocks of the other pixel array. It is a timing chart which shows an example. Usually, one FIFO data buffer (1) to (8) corresponding to the pixel array formed on one substrate constitutes one output port Pa1, and the FIFO data corresponding to the pixel array formed on the other substrate. In general, another output port Pa2 is configured by the buffers (9) to (12). In such a configuration, digital values are output in parallel from the output ports Pa1 and Pa2. At this time, the time required to complete the output of all the digital values differs between the output ports Pa1 and Pa2. In the example shown in FIG. 13, but FIFO data buffer FIFO data buffer (1) and the output port Pa2 output port Pa1 at time _{t 40} (9) is starting the output operation, the output port towards the output port Pa1 Pa2 for the number of FIFO data buffer is greater than, the time _{t 42} in which the output operation of the output port Pa1 ends is slower than the time _{t 41} in which the output operation of the output port Pa2 is completed. Thus, between time t ₄₁ ~t _42, the output port Pa2 is inevitably a wait state, the time required for imaging of one frame becomes long.

Such a problem makes the number of columns of the pixel array (number of FIFO data buffers) included in one output port close to the number of columns of the pixel array (number of FIFO data buffers) included in the other output port. (Preferably equal). For example, as shown in FIG. 14, six FIFO data buffers (1) to (6) are allocated to one output port Pb1, and the same number of FIFO data buffers (7) to (12) are allocated to the other output port. By assigning to Pb2, the time required to finish outputting all digital values can be made equal for each of the output ports Pb1 and Pb2. In the example shown in FIG. 14, has begun FIFO data buffer (7) the output operation of the FIFO data buffer (1) and the output port Pb2 of the output port Pb1 at time _{t 50,} the output operation of the output port Pb1 ends time t ₅₁ is the same as the time the output operation of the output port Pb2 ends.

  In view of such a point, in the solid-state imaging device 1 of the present embodiment, the FIFO data buffers 23A to 23L of the signal output unit 20 send digital values corresponding to the amount of charges generated in each pixel P to the data bus DB. When outputting, digital values corresponding to the columns before the n-th column of the pixel array 10A (that is, from the first column to the n-th column) are read from the FIFO data buffers 23A to 23F and the columns after the (n + 1) -th column and The digital values corresponding to the first column to the NB column of the pixel array 10B (that is, from the (n + 1) th column of the pixel array 10A to the NA column and the first column of the pixel array 10B to the NB column) are used as FIFO data. The data is output in parallel from the buffers 23G to 23L. In this manner, the output operation is divided at the column (n-th column) between the first column and the NA-th column of the pixel array 10A having a large number of columns, and the digital value is output in parallel. The number of columns in one region (the region on the left side of the boundary line E in FIG. 3) and the number of columns in the other region (the region on the right side of the boundary line E in FIG. 3) are the same or close to each other It can be the number of columns.

  Therefore, according to the solid-state imaging device 1 according to the present embodiment, for example, digital values are output from the first column to the NA column of the pixel array 10A, and in parallel, the first column to the NB column of the pixel array 10B. Compared with the method of outputting a digital value from the output time, the waiting time in the output operation can be made close to zero, and the time required for imaging one frame can be effectively shortened.

  Such an effect is that the number of columns from the first column to the n-th column in the pixel array 10A is the number of columns from the (n + 1) -th column to the NA-th column in the pixel array 10A and the first to NB-th columns in the pixel array 10B. This is particularly noticeable when it is equal to the sum of the number of columns. That is, the number of columns in one region (region on the left side of the boundary line E in FIG. 3) divided by the nth column and the number of columns in the other region (region on the right side of the boundary line E in FIG. 3) Since the waiting time in the digital value output operation becomes substantially zero, the time required for imaging one frame can be more effectively shortened.

  In the solid-state imaging device 1 according to the present embodiment, one or a plurality of continuous columns including the first column of the pixel array 10A and one or a plurality of continuous columns including the NB column of the pixel array 10B are X The insensitive area is shielded from incident X-rays by the line shielding member 5 (see, for example, FIG. 4B). Of the digital values output from the signal output unit 20, the digital values corresponding to the pixels included in the insensitive area are invalid data not related to the X-ray image.

  In such a case, if the output order of the digital values in one region divided by the nth column is the same as the output order of the digital values in the other region, the following inconvenience occurs. In other words, in FIG. 14, invalid data resulting from the X-ray shielding member 5 exists at the locations indicated by reference numerals Q1 and Q2. However, as shown in FIG. ), Invalid data Q1 is output first from one port Pb1, and invalid data Q2 is output last from the other port Pb2. As described above, if the positions of the invalid data Q1 and Q2 in the output order of the digital values are different from each other at the output ports Pb1 and Pb2, it may become a barrier when performing real-time processing in another electronic circuit.

  For such a problem, in the solid-state imaging device 1 according to the present embodiment, the output order of the digital values in one region (region on the left side of the boundary line E in FIG. 3) divided by the nth column is The output order of the digital values in the other region (the region on the right side of the boundary line E in FIG. 3) is opposite to each other (FIGS. 7 (e) to (i) and FIGS. 8 (e) to (i)). FIG. 9 (b) to (g) and FIG. 10 (b) to (g)). That is, the signal output unit 20 sequentially outputs the digital values corresponding to the first to n-th columns of the pixel array 10A from the n-th column to the first column, and the pixel array 10A. The digital values corresponding to the columns from the (n + 1) th column to the NB column through the NA column and the first column of the pixel array 10B are reversed from the first column to the nth column of the pixel array 10A. Output sequentially in order.

FIG. 15 is a timing chart showing the output order of such digital values from the FIFO data buffers 23A to 23L. FIGS. 15A to 15F show output timings in the FIFO data buffers 23A to 23F, and correspond to FIGS. 9B to 9G. FIGS. 15G to 15L show output timings in the FIFO data buffers 23G to 23L, and correspond to FIGS. 10B to 10G. Referring to the figure, at time _{t 60} and the start of FIFO data buffer 23G is output operation of FIFO data buffers 23F and the output port Pc2 output ports Pc1, at time _{t 61,} the FIFO data buffers 23A and 23L read When completed, the output operation of the output ports Pc1 and Pc2 is completed. Since the signal output unit 20 outputs digital values in this order, the output timings of the invalid data Q1 and Q2 from the output ports Pc1 and Pc2 can be made to coincide with each other. Real-time processing can be easily performed.

  In the solid-state imaging device 1 according to the present embodiment, the pixel arrays 10A and 10B are tiled by juxtaposing the semiconductor substrates 3A and 3B. As a tiling method, for example, the following is possible. is there. For example, as shown in FIG. 16A, the semiconductor substrates 3A and 3B on which film-like scintillators 4A and 4B are respectively deposited are arranged adjacent to each other on the same plane. In this method, since the scintillators 4A and 4B slightly wrap around the side surfaces (edges) of the semiconductor substrates 3A and 3B, the width of the dead area C is changed from the pixel P located at the end of each of the pixel arrays 10A and 10B to the semiconductor substrates 3A and 3B. 3B is determined by the distances to the respective edges of the 3B, the thicknesses of the portions of the scintillators 4A and 4B that have wrapped around the edges of the semiconductor substrates 3A and 3B, and the clearance (clearance) secured between the semiconductor substrates 3A and 3B. Is done.

  FIG. 16B shows a system in which the semiconductor substrates 3A and 3B are arranged adjacent to each other on the same plane as in FIG. 16A, but the scintillator 4A is disposed after the semiconductor substrates 3A and 3B are juxtaposed. , 4B are different from the method shown in FIG. In the method shown in FIG. 16B, since the scintillators 4A and 4B are deposited after the semiconductor substrates 3A and 3B are arranged, compared with the method shown in FIG. 16A, the edge of the semiconductor substrates 3A and 3B is reached. The width of the dead area C can be reduced by the amount that the scintillators 4A and 4B do not wrap around.

  FIG. 16C shows a method in which the semiconductor substrates 3A and 3B are arranged so that the end of the semiconductor substrate 3B overlaps the end of the semiconductor substrate 3A. In this method, the semiconductor substrates 3A and 3B are preferably arranged so that the horizontal positions of one ends of the pixel arrays 10A and 10B of the semiconductor substrates 3A and 3B coincide with each other. Thereby, the dead area C can be made very narrow.

The solid-state imaging device according to the present invention is not limited to the above-described embodiment, and various other modifications are possible. For example, in the above embodiment, the signal output unit 20 sequentially outputs the digital values corresponding to the first to nth columns of the pixel array 10A in reverse order, and the (n + 1) th column of the pixel array 10A. To the NB column of the pixel array 10B, digital values corresponding to each column are sequentially output in the normal order. The output order of the digital values corresponding to each column of the pixel arrays 10A and 10B is not limited to this, and the digital values corresponding to the respective columns from the first column to the nth column of the pixel array 10A are sequentially output in the normal order. In addition, digital values corresponding to the respective columns from the (n + 1) th column of the pixel array 10A to the NB column of the pixel array 10B may be sequentially output in reverse order. In this case, although the head of the data of the invalid data Q1, Q2 each row together the output timing shown in FIG. 15 (immediately after time _{t 60),} the invalid data Q1, Q2 outputs of from the output ports Pc1, Pc2 Since the timings coincide with each other, the effect of the solid-state imaging device of the present invention can be suitably obtained. In addition, the data from each output port is described to flow simultaneously on one data bus. However, a separate data bus may be provided for each output port, and each data port is connected to each output port. Two data buses may be provided in parallel.

DESCRIPTION OF SYMBOLS 1 ... Solid-state imaging device, 2 ... Base material, 3A, 3B ... Semiconductor substrate, 4A, 4B ... Scintillator, 5 ... X-ray shielding member, 6 ... Control part, 10A, 10B ... Pixel arrangement, 20 ... Signal output part, 21A ˜21L... Signal readout unit, 22A to 22L... A / D converter, 23A to 23L... FIFO data buffer, 30A and 30B... Scan shift register, 31A and 31B. pivot arm, 106 ... X-ray generator, 113 ... slide mechanism, A ... subject, A 2 _... amplifier, B ... moving direction, C ... dead _{area, C} 21, C _{22 ...} integrating capacitive element, C 3 _... holding Capacitance element, DB ... data bus, H _{1 to} H _NA , H _{1 to} H _NB ... holding circuit, L _G ... gain setting wiring, L _H ... holding wiring, L _{H, j} ... jth column selection wiring, L _{O, j} ... j-th column readout wiring, L _out ... voltage output wiring, L _R ... reset wiring, L _{V, m} ... m-th row selection wiring, P, P _{m, j} ... pixel, Pa1, Pa2 , Pb1, Pb2, Pc1, Pc2 ... output port, PD ... photodiode, Q1, Q2 ... invalid data, reset ... reset control _{signal, S 1 ~S NA, S 1} ~S NB ... integrating circuit, SW 1 _... for reading Switch, SW ₂₁ ... Discharge switch, SW ₂₂ ... Gain setting switch, SW ₃₁ ... Input switch, SW ₃₂ ... Output switch, W ... Silicon wafer.

Claims (2)

A solid-state imaging device that generates image data according to incident radiation,
A first substrate having a first pixel arrangement in which M × NA pixels each including a photodiode (M and NA are integers of 2 or more) are two-dimensionally arranged in M rows and NA columns;
M × NB pixels (NB is an integer of 2 or more smaller than NA) each including photodiodes are two-dimensionally arranged in M rows and NB columns, and the first column is the NA column of the first pixel array. A second substrate having a second pixel array disposed along
(NA + NB) readout wirings arranged for each column of the first and second pixel arrays and connected to the photodiodes included in the pixels of the corresponding columns via readout switches;
A signal output unit that holds a signal corresponding to the amount of charge input through the readout wiring and outputs the held signal;
The signal output unit includes a first output port for outputting the signals corresponding to the respective columns from the first column of the first pixel array to the n-th column (2 ≦ n <NA) sequentially, the first In parallel with the output from one output port, each column from the (n + 1) th column of the first pixel array to the NB column through the NA column and the first column of the second pixel array And a second output port that sequentially outputs the corresponding signals.
The number of columns from the first column to the n-th column in the first pixel array is the number of columns from the (n + 1) -th column to the NA-th column in the first pixel array and the first column to the n-th column in the second pixel array. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is equal to a sum of the number of columns of the NB column.

Images