JP5392963B2 - Electro-optical device and electronic apparatus - Google Patents

Description

The present invention relates to a technique for controlling the behavior of a light emitting element such as an organic light emitting diode (hereinafter simply abbreviated as “OLED”) element.

In recent years, as a next-generation light-emitting device that replaces liquid crystal elements, organic EL (Electronic Lumines)
cence) devices and light-emitting polymer devices are attracting attention. This O
LED elements are self-luminous and have little viewing angle dependency. Also, they do not require a backlight or reflected light, making them suitable for low power consumption and thinning. have.

The OLED element is a current-driven light emitting element that cannot maintain light emission when the current flowing through it is interrupted. For this reason, when driving an OLED element by an active matrix method,
In the writing period, a voltage (hereinafter referred to as “data voltage”) applied to the gate electrode of the driving transistor according to the gradation of the pixel is held by the capacitor element, and a current corresponding to this voltage is supplied to the OLED element The structure which keeps flowing is common (for example, Non-Patent Document 1). Such a driving method is called a voltage program method.
“51.4: Invited Paper: Modeling and Design of Polysilicon Drive Circuits for OLED Displays”, Simon W.-B. Tam, Tatsuya Shimoda, SID 04 Digest, p1406-p1409

By the way, under the configuration described above, when a current flows through the driving transistor as the data voltage is supplied in the writing period, the voltage of the power supply line drops due to the resistance associated with the power supply line. In the configuration in which one electrode of the capacitive element and the source electrode of the driving transistor are connected to the power supply line, the voltage at both ends of the capacitive element fluctuates with the fluctuation of the voltage of the power supply line in the writing period. As a result, there is a problem that the OLED element cannot emit light with an accurate luminance during the driving period. The present invention has been made in view of such circumstances, and an object of the present invention is to solve the problem of causing a light-emitting element to emit light at a desired luminance with high accuracy.

In order to solve this problem, an electronic circuit according to a first feature of the present invention includes a first terminal, a second terminal, and a gate terminal, and controls electrical connection between a power supply line and the driven element. A drive transistor (for example, drive transistor Qdr in FIG. 2) in which a current level of a drive current flowing between the first terminal and the second terminal changes according to a voltage of the gate terminal is connected to the gate terminal. The first electrode (for example, the first electrode L0a in FIG. 2) and the second electrode (
For example, a capacitance element (capacitance element C0 in FIG. 2) having a second electrode L0b in FIG. 2 and a first switching element for controlling the electrical connection between the first terminal of the drive transistor and the power supply line ( For example, the first transistor Qa1 in FIG. 2 and a second switching element (for example, the first transistor Qa1 in FIG. 2) that controls electrical connection between the first terminal or the second terminal of the driving transistor and the gate terminal of the driving transistor. 2 transistors Qa2) and a third switching element (for example, the third transistor Qa3 in FIG. 2) for controlling the electrical connection between the data line to which the data voltage is supplied and the second terminal of the driving transistor. A specific example of this configuration will be described later as a first embodiment (see particularly FIG. 2).

According to this configuration, the data voltage is written to the capacitor element by turning on the second switching element and the third switching element in the writing period. When a drive current flows from the drive transistor to the light emitting element during this writing period, the power supply voltage of the power supply line drops. According to the electronic circuit of the present invention, since the electrical connection between the drive transistor and the power supply line is switched by the first switching element, the first switching element is turned off (non-conducting state) during the writing period. The current path can be interrupted. Therefore, according to the present invention, the expected voltage can be written to the capacitive element with high accuracy by preventing the power supply voltage from dropping.

In this electronic circuit, a fourth switching element (for example, the fourth transistor Qa4 in FIG. 2) for controlling the electrical connection between the wiring to which a predetermined voltage is applied and the gate terminal of the driving transistor is further arranged. May be. In this configuration, if the fourth switching element is turned on before the data voltage is applied from the data line to the second terminal of the driving transistor via the third switching element, Since the voltage of the gate terminal of the driving transistor can be set to a predetermined voltage prior to the voltage writing, the data voltage can be written quickly and efficiently.

According to a second aspect of the present invention, an electronic circuit includes a first terminal, a second terminal, and a gate terminal, and controls electrical connection between a power line and the driven element. A drive transistor (for example, the drive transistor Qdr in FIG. 7) in which the current level of the drive current flowing between the second terminal changes according to the voltage of the gate terminal, the first electrode (L1a), and the second electrode (L1b) ), And the first electrode is connected to the gate terminal (for example, the first capacitor C1 in FIG. 7), the third electrode (L2a), and the fourth electrode (L2b). The fourth electrode controls the electrical connection between the second capacitor element (for example, the second capacitor element C2 in FIG. 7) connected to the power supply line and the first terminal of the drive transistor and the power supply line. A first switching element (for example, the first transistor Qb1 in FIG. 7); A second switching element (for example, the second transistor Qb2 in FIG. 7) that controls electrical connection between the first terminal or the second terminal of the driving transistor and the gate terminal of the driving transistor is supplied with a data voltage. A third switching element (for example, the third switching element Qb3 in FIG. 7) for controlling the electrical connection between the data line and the second electrode of the first capacitor element is provided. A specific example of this aspect is the second embodiment. Also in this configuration, in the writing period in which the data line and the second electrode of the second capacitor element are conducted by the third switching element, the drive current from the power supply line to the light emitting element via the drive transistor Therefore, the first switching element can be used to cut off the path of the power supply voltage, thereby preventing a drop in the power supply voltage and preventing the capacitor element from having the desired voltage with high accuracy. In this configuration, the voltage of the gate terminal is affected by the change in the voltage of the fourth electrode due to the capacitive coupling through the second capacitive element, as illustrated in FIG. As described above, the first electrode and the third electrode are connected to the gate terminal.

The first switching element is turned off during a writing period in which the data voltage is supplied to the second electrode of the first capacitive element via the third switching element, and the driving current is supplied to the driven element. It is turned on during the driving period. According to this aspect, since the first switching element is turned off during the writing period, it is possible to reliably prevent a power supply voltage drop during the writing period.

In a desirable aspect of the electronic circuit according to the first and second features, a fifth switching element (for example, in FIGS. 2 and 7) that controls electrical connection between the second terminal of the driving transistor and the driven element. A light emission control transistor Qel), and the fifth switching element is turned off in a writing period in which the data voltage is supplied to the second electrode of the first capacitor element, and the driving current is supplied to the driven element. It is turned on in the drive period for supply. According to this aspect, the cutoff and formation of the path of the drive current can be reliably controlled by the light emission control switching element in addition to the first switching element.

A first feature of the driving method according to the present invention includes a first terminal, a second terminal, and a gate terminal, and a current level of a driving current flowing between the first terminal and the second terminal is the gate terminal. A driving transistor that changes in accordance with the voltage of the driving transistor, and a capacitor element having a first electrode connected to the gate terminal of the driving transistor and a second electrode connected to a power supply line, and drives the driven element. A method for driving an electronic circuit, wherein the first terminal or the second terminal of the driving transistor and the gate terminal of the driving transistor are electrically connected and the second terminal of the driving transistor in the writing period. Setting the conduction state of the drive transistor by supplying a data voltage to the terminal;
In the drive period after the write period, the drive current having a current level corresponding to the conduction state of the drive transistor set in the write period is supplied to the driven element, and in the write period Is to electrically disconnect the driven element from the power line. In other words, in the driving period after the writing period, the driving current having a current level corresponding to the conduction state of the driving transistor set in the writing period is supplied from the power supply line to the driven element. The driven element is electrically disconnected from the power supply line at least at the end of the writing period. Specific examples of these aspects will be described later as the first embodiment. According to the present invention, since the supply of the drive current is stopped during the writing period, the potential of the power supply line does not vary. Therefore, the data voltage can be accurately written.

In addition, a second feature of the driving method according to the present invention includes a first terminal, a second terminal, and a gate terminal, controls electrical connection between a power supply line and a driven element, and the first terminal and the A driving transistor in which a current level of a driving current flowing between the second terminal and the second terminal changes according to a voltage of the gate terminal, a first electrode, and a second electrode, the first electrode being connected to the gate terminal An electronic circuit driving method comprising: a first capacitive element; and a second capacitive element that includes a third electrode and a fourth electrode, and the fourth electrode is connected to a power line. Electrically connecting the first terminal or the second terminal of the driving transistor to the gate terminal of the driving transistor and supplying a data voltage to the second electrode of the first capacitor; In the subsequent drive period, the writing A drive current having a current level corresponding to the conduction state of the drive transistor set in between is supplied from the power supply line to the driven element, and the driven element is supplied to at least a part of the writing period. It is to electrically disconnect from the power line. A specific example of this aspect will be described later as a second embodiment (FIG. 7) and a third embodiment (FIG. 13). According to the present invention as well, the data voltage can be accurately written in the electronic circuit as in the driving method according to the first feature.

In the driving method of the present invention, in the writing period, the path may be interrupted by turning off the switching element interposed between the driving transistor and the power supply line, or between the driving transistor and the light emitting element. Alternatively, the path may be blocked by turning off the switching element interposed between the two. According to these aspects, it is possible to easily and reliably switch the blocking and formation of the drive current path by controlling the switching element.

In a desirable mode of the driving method according to the present invention, a pause period between the writing period and the driving period is set (see, for example, FIGS. 12 and 14). In this idle period, the second electrode of the first capacitor element and the data line are made non-conductive, and the path for supplying the drive current from the power supply line to the light emitting element is blocked. That is, neither the writing of the data voltage nor the supply of the driving current to the light emitting element is executed in the idle period. According to this aspect, it is possible to reliably prevent the situation where the writing of the data voltage and the supply of the driving current to the light emitting element are performed in an overlapping manner. Therefore, it is possible to reliably prevent the fluctuation of the power supply voltage during the writing period and write the data voltage to the electronic circuit more reliably. Further, the second electrode of the first capacitor element may be in a floating state in a rest period between the writing period and the driving period.

The first feature of the electro-optical device according to the present invention is that a plurality of scanning lines, a plurality of data lines, and a plurality of electrons arranged corresponding to intersections of the plurality of scanning lines and the plurality of data lines. A circuit, a plurality of power supply lines, a scanning line driving circuit that drives the plurality of scanning lines, and a data line driving circuit that drives the plurality of data lines. Each electronic circuit belonging to one group of electronic circuits is connected, and each of the plurality of electronic circuits includes an electro-optic element, a first terminal, a second terminal, and a gate terminal, and the power line and the covered circuit. A driving transistor that controls electrical connection with the driving element, a current level of a driving current flowing between the first terminal and the second terminal changes according to a voltage of the gate terminal; a first electrode; Two electrodes, wherein the first electrode is the gate. A capacitive element connected to a first terminal, a first switching element that controls electrical connection between the first terminal of the driving transistor and the power supply line, and the first terminal or the second terminal of the driving transistor, A second switching element for controlling electrical connection between the driving transistor and the gate terminal; and a third switching element for controlling electrical connection between a data line to which a data voltage is supplied and the second terminal of the driving transistor. It is in providing. According to the present invention, the same effect as the electronic circuit according to the first feature can be obtained. A specific example of this configuration will be described later as the first embodiment (FIG. 2).

A second feature of the electro-optical device according to the invention is that a plurality of scanning lines, a plurality of data lines, and a plurality of electrons arranged corresponding to intersections of the plurality of scanning lines and the plurality of data lines. A circuit, a plurality of power lines, a scanning line driving circuit for driving the plurality of scanning lines, and a data line driving circuit for driving a plurality of data lines, and the plurality of power lines include the plurality of electrons Each electronic circuit belonging to one group of the circuits is connected, and each of the plurality of electronic circuits includes an electro-optic element, a first terminal, a second terminal, and a gate terminal, and the power line and the driven A drive transistor that controls electrical connection with an element, a current level of the drive current flowing between the first terminal and the second terminal changes according to a voltage of the gate terminal; a first electrode; Two electrodes, wherein the first electrode is the gate. A second capacitive element having a first capacitive element connected to the first terminal, a third electrode and a fourth electrode, wherein the fourth electrode is connected to the power supply line, the second terminal, and the plurality of power supplies A first switching element that controls electrical connection of one line to one power supply line, and a first switching element that controls electrical connection between the first terminal or the second terminal of the driving transistor and the gate terminal of the driving transistor. And a third switching element that controls electrical connection between the data line to which the data voltage is supplied and the second electrode of the first capacitor element. A specific example of this aspect will be described later as a second embodiment (FIG. 7). Also according to the present invention, for the same reason as the electronic circuit according to the second feature, the data voltage can be accurately written in each electronic circuit while suppressing the fluctuation of the power supply voltage of each power supply line.

In the electro-optical device according to each aspect described above, it is preferable that the plurality of power supply lines intersect the plurality of data lines. According to this aspect, since the plurality of electronic circuits arranged along the scanning line (that is, the electronic circuit that simultaneously performs writing of the data voltage) are connected to the common power supply line, the electronic circuit in the writing period is connected. Thus, it is possible to reliably prevent fluctuations in the power supply voltage in the power supply line. Therefore, the data voltage can be accurately written to each electronic circuit.

Further, from another viewpoint, the electro-optical device according to the second feature is arranged corresponding to a plurality of scanning lines, a plurality of data lines, and intersections of the plurality of scanning lines and the plurality of data lines. A plurality of electronic circuits, a plurality of power supply lines intersecting with the plurality of data lines, a scanning line driving circuit for driving the plurality of scanning lines, and a data line driving circuit for driving the plurality of data lines. Each of the plurality of electronic circuits belonging to one group among the plurality of electronic circuits is connected to the plurality of power lines, and each of the plurality of electronic circuits includes an electro-optic element, a first terminal, and a second terminal And a gate terminal, a drive transistor in which a current level of a drive current flowing between the first terminal and the second terminal changes according to a voltage of the gate terminal, and a first electrode and a second electrode The first electrode is connected to the driving track. A first capacitor connected to the gate terminal of the transistor, a third electrode and a fourth electrode, the second capacitor having the fourth electrode connected to the power supply line, and the first capacitor of the drive transistor. Controls electrical connection between the first switching element for controlling electrical connection between one terminal or the second terminal and the gate terminal of the driving transistor, and the data line and the second electrode of the first capacitor element. And the data voltage is applied to the second switching element during at least a part of a period in which the second switching element is in the on state after the first switching element is in the on state. Is supplied to the second electrode via the first electrode, and the conduction state of the drive transistor is set. The electric current level of the drive current supplied to the element is set, and after the period when the data voltage is supplied to the second electrode, the supply of the drive current to the electro-optic element is started. The optical element may be configured to be electrically disconnected from the power supply line.

The electro-optical device according to the invention is used in various electronic apparatuses. A typical example of this electronic device is
This is an apparatus using an electro-optical device as a display device. Examples of this type of electronic device include a personal computer and a mobile phone. However, the use of the electro-optical device according to the present invention is not limited to image display. For example, the electro-optical device of the present invention can also be applied as an exposure device for forming a latent image on an image carrier such as a photosensitive drum by irradiation of light.

<A: First Embodiment>
FIG. 1 is a block diagram showing the configuration of the electro-optical device according to the first embodiment of the invention. As shown in the figure, the electro-optical device 1 includes a pixel region A, a scanning line driving circuit 100, a data line driving circuit 200, a control circuit 300, and a power supply circuit 500. Among these, in the pixel region A, m scanning lines 10 extending in the X direction, m power lines 31 extending in the X direction in pairs with each scanning line 10, and orthogonal to the X direction. N data lines 103 extending in the Y direction are formed. A pixel circuit 400 is disposed at a position corresponding to each intersection of the scanning line 10 and the data line 103. Therefore, these pixel circuits 400 are arranged in a matrix of m rows × n columns.

The scanning line driving circuit 100 is a circuit for selecting and operating the pixel circuits 400 arranged in the pixel region A in units of rows for each horizontal scanning period. On the other hand, the data line driving circuit 200 includes one row (n) of pixel circuits 40 selected by the scanning line driving circuit 100 in each horizontal scanning period.
A data voltage Vdata corresponding to each of 0 is generated and output to each data line 103. This data voltage Vdata is a voltage corresponding to the gradation (luminance) designated for each pixel circuit 400.

The control circuit 300 controls each circuit by supplying various control signals such as a clock signal to the scanning line driving circuit 100 and the data line driving circuit 200, and each pixel circuit 4.
Image data designating the gradation of 00 is supplied to the data line driving circuit 200. On the other hand, the power supply circuit 500 includes a higher voltage (hereinafter referred to as “power supply voltage”) Vdd and a lower voltage (hereinafter referred to as “power supply voltage”).
Vss) (referred to as “ground voltage”). The power supply voltage Vdd is supplied to each pixel circuit 4 via the power supply line 31.
Power is supplied to 00. Further, the ground voltage Vss is supplied to all the pixel circuits 400 via a predetermined wiring (the ground line 32 shown in FIG. 2). The ground voltage Vss is a potential serving as a voltage reference.

Next, the configuration of each pixel circuit 400 will be described with reference to FIG. In the drawing, only one pixel circuit 400 in the j-th column (j is an integer satisfying 1 ≦ j ≦ n) belonging to the i-th row (i is an integer satisfying 1 ≦ i ≦ m) is illustrated. However, the other pixel circuits 400 have the same configuration. Note that the conductivity type of each transistor included in the pixel circuit 400 is not limited to that illustrated in FIG. A typical example of each transistor shown in FIG. 2 (and FIG. 7 described later) is a thin film transistor using low-temperature polysilicon as a semiconductor layer, but the form and material of each transistor are not limited at all.

As shown in FIG. 2, the pixel circuit 400 includes an OLED element 420 and a p-channel each inserted between a power supply line 31 to which a power supply voltage Vdd is supplied and a ground line 32 to which a ground voltage Vss is supplied. Type transistor (hereinafter referred to as “driving transistor”) Qdr. OLED
The element 420 is an element that emits light with luminance according to a forward current (hereinafter referred to as “driving current”), and has a structure in which a light emitting layer made of an organic EL material is interposed between an anode and a cathode. ing. The light emitting layer is formed, for example, by discharging a droplet of an organic EL material from an inkjet (droplet discharge) head and drying it. OLED element 4
The 20 cathodes are connected to the ground line 32. On the other hand, the driving transistor Qdr is an OLED element 4.
This is a transistor for controlling the drive current flowing through the transistor 20.

In addition, as a material of the OLED element 420, an organic light emitting material such as a low molecule / polymer or a dendrimer is used. However, the OLED element 420 is only an example of a light emitting element. That is, instead of the OLED element 420, an inorganic EL element, a field emission (FE) element, a surface-conduction electron emission (SE)
) Element, ballistic electron surface emitting (BS) element, LED
Various light-emitting elements such as (Light Emitting Diode) elements, electrophoretic elements, electrochromic elements, and the like may be used. The present invention is also applied to an exposure apparatus such as a write head used in an optical writing type printer or an electronic copying machine, as in this embodiment. Furthermore, for example, the present invention is also applied to a sensing device such as a biochip.

Now, for convenience, the scanning line 10 shown as one wiring in FIG.
The first control line 11 and the second control line 12 are included as shown in FIG. A first control signal Sa1 for defining a period during which the data voltage Vdata is taken into the pixel circuit 400 is applied to the first control line 11 of each row.
[1] to Sa1 [m] are supplied from the scanning line driving circuit 100. On the other hand, the second control line 12 of each row
The second control signals Sa2 [1] to Sa2 [m] for defining the period for initializing the voltage held in the pixel circuit 400 are supplied from the scanning line driving circuit 100. A specific waveform of each signal and an operation of the pixel circuit 400 corresponding to the waveform will be described later.

The first transistor Qa1 shown in FIG. 2 is a p-channel transistor having its drain electrode connected to the source electrode of the drive transistor Qdr and its source electrode connected to the power supply line 31, and the source electrode of the drive transistor Qdr Functions as a switching element for switching between conduction and non-conduction between the power line 31 and the power line 31. On the other hand, the light emission control transistor Qel shown in FIG. 2 is a p-channel transistor whose drain electrode is connected to the anode of the OLED element 420 and whose source electrode is connected to the drain electrode of the drive transistor Qdr. It functions as a switching element for controlling whether or not a drive current can be supplied from Qdr to the OLED element 420. The gate electrodes of the first transistor Qa1 and the light emission control transistor Qel are connected to the first control line 11. Therefore, the first
Each of the transistor Qa1 and the light emission control transistor Qel is turned off when the first control signal Sa1 [i] is at a high level, and is turned on when the first control signal Sa1 [i] is at a low level.

The second transistor Qa2 shown in FIG. 2 is an n-channel transistor whose drain electrode is connected to the source electrode of the driving transistor Qdr and whose source electrode is connected to the gate electrode of the driving transistor Qdr. Further, the third transistor Qa3 shown in FIG.
Is an n-channel transistor whose drain electrode is connected to the drain electrode of the driving transistor Qdr and whose source electrode is connected to the data line 103. The conduction and non-conduction between the drain electrode of the driving transistor Qdr and the data line 103 are It functions as a switching element for switching conduction. The gate electrodes of the second transistor Qa2 and the third transistor Qa3 are connected to the first control line 11. Therefore, each of the second transistor Qa2 and the third transistor Qa3 is turned on when the first control signal Sa1 [i] is at a high level, and is turned off when the first control signal Sa1 [i] is at a low level. It becomes. Second transistor Q
When a2 transitions to the on state, the drive transistor Qdr functions as a diode with the gate electrode and the source electrode conducting.

Next, the capacitive element C0 shown in FIG. 2 is a capacitor that holds electric charges between the first electrode L0a and the second electrode L0b. The first electrode L0a is connected to the gate electrode of the driving transistor Qdr and the second electrode
The electrode L0b is connected to the power supply line 31. The first electrode L0a of the capacitive element C0 and the drive transistor Qd
The drain electrode of the fourth transistor Qa4 is connected to the connection point _NG with the gate electrode of r. The fourth transistor Qa4 is an n-channel transistor having a source electrode connected to the ground line 32, and controls the electrical connection between the connection point _NG and the ground line 32 (typically the conduction and the connection between both). It functions as a switching element that switches non-conduction. 4th transistor Qa4
Are connected to the second control line 12. Therefore, if the second control signal Sa2 [i] is at a high level, the fourth transistor Qa4 is turned on, and if the second control signal Sa2 [i] is at a low level, the fourth transistor Qa4 is turned off.

Next, referring to FIG. 3, the first control signal Sa1 [1] to Sa1 [m] and the second control signal Sa2 [1
] To Sa2 [m] will be described in detail. As shown in the figure, the first control signal Sa1 [1
] Through Sa1 [m] are signals that sequentially become a high level every horizontal scanning period (1H). That is, the first control signal Sa1 [i] maintains a high level in the i-th horizontal scanning period of the vertical scanning period (1V) and maintains a low level in other periods.
The transition of the first control signal Sa1 [i] to the high level means selection of each pixel circuit 400 in the i-th row. As shown in FIG. 3, in the horizontal scanning period in which the first control signal Sa1 [i] is at a high level, the data voltage Vdata corresponding to the gradation of each pixel circuit 400 in the i-th row is the data line 1.
03. This data voltage Vdata is taken into the pixel circuit 400 via the third transistor Qa3 which is turned on by the high-level first control signal Sa1 [i]. Hereinafter, a period during which each of the first control signals Sa1 [1] to Sa1 [m] is at a high level (that is, a horizontal scanning period) is referred to as a “writing period T _WRT ”. On the other hand, during the period other than the writing period _TWRT (that is, the period during which each of the first control signals Sa1 [1] to Sa1 [m] is at the low level), the OLED element 42 is used.
0 is a period during which light is actually emitted (hereinafter referred to as “driving period T _EL ”).

The writing period TWRT in which the first control signal Sa1 [i] is at a high level is _divided into a first period T ₁ and a second period T ₂ . The first period T ₁ is a period until a predetermined time length elapses from the starting point of the writing period T _WRT , and the second period T ₂ is a remaining period of the writing period T _WRT . Second control signal Sa2 [i
] Maintains a high level during the first period T _{1 and} other periods (ie, the second period
This is a signal that maintains a low level during the period T ₂ and the driving period T _EL ). When the second control signal Sa2 [i] becomes high level, the connection point _{NG of} FIG. 2 is conducted to the ground line 32 through the fourth transistor Qa4 that is turned on.

Next, a specific operation of the pixel circuit 400 will be described with reference to FIGS. Hereinafter, the operation of the pixel circuit 400 in the j-th column belonging to the first row will be described by dividing it into a first period T ₁ , a second period T _2, and a driving period _TEL .

(a) First period T ₁ (writing period T _WRT )
In the first period T _1, as shown in FIG. 3, both the first control signal Sa1 [i] and second control signal Sa2 [i] is maintained at the high level. Therefore, the second transistor Qa2, the third transistor
The transistor Qa3 and the fourth transistor Qa4 are turned on, and the first transistor Qa1
The light emission control transistor Qel is turned off. FIG. 4 shows the pixel circuit 400 at this time.
FIG. 6 is a circuit diagram equivalently showing the electrical configuration of As shown in FIG. 3, the connection point N _G (that is, the gate electrode of the drive transistor Qdr) is electrically connected to the ground line 32 via the fourth transistor Qa4 that is turned on. As shown in FIG. The voltage V _G at the connection point _NG drops to the ground voltage Vss in the first period T ₁ . In other words, the first period T ₁ shown in FIG. 3 is selected to have a sufficient length of time for the voltage V _{G at the} connection point _NG to reach the ground voltage Vss. In the first period T _1, between the data line 103 and the ground line 32, the fourth transistor Qa4, current flows through the second transistor Qa2 and the driving transistor Qdr. This current serves as a kind of precharge current.

(b) Second period T ₂ (writing period T _WRT )
In the second period T _2, as shown in FIG. 3, the first control signal Sa1 [i] is while maintaining the high level, the second control signal Sa2 [i] is maintained at the low level. Accordingly, the second transistor Qa2 and the third transistor Qa3 are turned on, while the first transistor Qa1 ·
The fourth transistor Qa4 and the light emission control transistor Qel are turned off. Figure 5 (a)
FIG. 5 is a circuit diagram equivalently showing an electrical configuration of the pixel circuit 400 at this time. As shown in the figure, the connection point _NG is connected to the ground line 3 by the transition of the fourth transistor Qa4 to the OFF state.
2 is electrically disconnected. Further, when the second transistor Qa2 is turned on, the driving transistor Qdr is diode-connected, and the drain electrode is connected to the data line 103 via the third transistor Qa3. Therefore, the pixel circuit 4 at this time
00, as shown in FIG. 5 (b), a capacitive element C0 and a diode (
The driving transistor Qdr) is equivalent to a circuit inserted between the power supply line 31 and the data line 103. Therefore, the voltage V _G at the connection point N _G between the drive transistor Qdr a capacitor C0
3, the voltage gradually increases until reaching a level (V _G = Vdata−Vth) obtained by subtracting the threshold voltage Vth of the drive transistor Qdr from the voltage Vdata of the data line 103. The second period T ₂ is selected to have a sufficient length of time for the voltage V _G at the connection point _NG to reach the voltage “Vdata−Vth” from the time when the second transistor Qa2 and the third transistor Qa3 are turned on. Is done.

As described above, in the writing period T _WRT (the first period T ₁ and the second period T ₂ ),
When the first control signal Sa1 [i] is maintained at a high level, both the first transistor Qa1 and the light emission control transistor Qel are turned off. Therefore, the power supply line 31 and the drive transistor Qdr are electrically insulated, and the current path from the power supply line 31 to the ground line 32 via the OLED element 420 is interrupted. The pixel circuit 400 in such a state
Since no current flows from the power line 31, no voltage drop occurs in the power line 31. Therefore, in the writing period _TWRT , the intended charge amount can be held with high accuracy in the capacitive element C0 interposed between the power supply line 31 and the connection point _NG .

(c) Driving period T _EL
In the drive period T _EL, both the first control signal Sa1 [i] and second control signal Sa2 [i] becomes the low level. Therefore, the second transistor Qa2, the third transistor Qa3, and the fourth transistor
While the transistor Qa4 is turned off, the first transistor Qa1 and the light emission control transistor Qel are turned on. FIG. 6 is a circuit diagram showing an equivalent configuration of the pixel circuit 400 at this time. As shown in the figure, when the first transistor Qa1 and the light emission control transistor Qel transition to the ON state, the drive transistors Qdr and OL are driven from the power supply line 31.
A path to the ground line 32 via the ED element 420 is formed. At this time, the voltage V _G of the gate electrode of the driving transistor Qdr is maintained at the voltage held in the capacitive element C0 in the writing period T _WRT (that is, the voltage corresponding to the data voltage Vdata) as shown in FIG. Therefore, the drive current Iel flowing from the power supply line 31 into the OLED element 420 has a current amount corresponding to the data voltage Vdata. Therefore, the OLED element 420 emits light with a luminance corresponding to the data voltage Vdata.

Here, the drive current Iel flowing from the source electrode to the drain electrode of the drive transistor Qdr is expressed by the following equation (1).
Iel = (1/2) β (Vgs−Vth) ² (1)
In the equation (1), “Vgs” is a gate-source voltage of the driving transistor Qdr, and “β” is a gain coefficient of the driving transistor Qdr. In the driving period T _EL , the voltage V _G (= Vdata−Vth) held in the capacitive element C0 in the immediately preceding writing period _TWRT is applied to the gate electrode, and the first transistor turned on. Since the power supply voltage Vdd is supplied to the source electrode of the driving transistor Qdr via Qa1, the voltage Vgs is expressed as “Vdd− (Vdata−V
th) ". When this is substituted into the equation (1) and transformed, the drive current Iel is expressed by the following equation (2).
Iel = (1/2) β (Vdd−Vdata) ² (2)
That is, the drive current Iel does not depend on the threshold voltage Vth of the drive transistor Qdr. Therefore, according to the present embodiment, it is possible to compensate for the variation in the threshold voltage Vth of the drive transistor Qdr in each pixel circuit 400 and cause the OLED element 420 to emit light with a desired brightness with high accuracy.

By the way, in the actual pixel circuit 400, when the drive current Iel flows, the power supply voltage Vdd decreases. If the voltage drop at this time is “ΔV”, the power supply voltage after the drop is “Vdd−ΔV”.
" Since the connection point _NG is in a floating state during the driving period T _EL , when the power supply voltage Vdd drops by ΔV, the voltage at the connection point _NG also drops by ΔV. Therefore, since “Vdd” in the equation (2) becomes “Vdd−ΔV”, while “Vdata” in the equation becomes “Vdata−ΔV”, the influence of the drop of the power supply voltage Vdd on the drive current Iel is a result. Canceled by That is, even if the power supply voltage Vdd drops during the driving period T _EL , the luminance of the OLED element 420 is not affected.

Further, in the present embodiment, each power supply line 31 is formed along the direction of the arrangement of the pixels selected at once by the scanning line driving circuit 100 (that is, the direction of the arrangement of the pixels that simultaneously execute the capturing of the data voltage). Therefore, there is an advantage that the drop of the power supply voltage Vdd can be surely prevented in the writing period _TWRT . This will be described in detail as follows.

As a comparison with the present embodiment, a configuration in which the power supply line 31 extends in the direction along the data line 103 is assumed. In this configuration, when the scanning line driving circuit 100 selects the i-th row by the first control signal Sa1 [i] transitioning to a high level, the data voltage Vdata is taken into the pixel circuits 400 of each column belonging to this row. It is. Also a first transistor Qa1 and emission control transistor Qel of the i-th row of pixel circuits 400 as blocked the path of the driving current Iel is turned off in the writing period T _WRT, the pixel circuits 400 belonging to the other row ( that power supply voltage Vdd of the power supply line 31 from the driving current Iel is supplied in each row to the OLED element 420 of the pixel circuit 400) in the drive period T _EL drops. That is, while the data voltage of each pixel circuit 400 belonging to the i-th row is being captured in the writing period T _WRT,
Since the power supply voltage Vdd supplied to the electrode L0b varies, the data voltage Vdat is applied to the capacitive element C0.
It becomes difficult to maintain the desired amount of charge according to a.

On the other hand, in the configuration in which the power supply line 31 is formed along the row direction as in the present embodiment, 1
When the scanning line driving circuit 100 selects each i-th pixel circuit 400 commonly connected to the power supply line 31, the n pixel circuits 400 simultaneously fetch the data voltage Vdata. . Therefore, the supply of the drive current Iel to the OLED element 420 can prevent the power supply voltage Vdd of the power supply line 31 from dropping, and the data voltage Vdata can be accurately taken into each pixel circuit 400.

Incidentally, the wiring for supplying the power supply voltage Vdd from the power supply circuit 500 to each pixel circuit 400 includes a main power supply line arranged around the pixel region A and an auxiliary power supply extending in the row direction inside the pixel circuit 400. Including lines. The auxiliary power line is the area (opening ratio) where each OLED element 420 emits light.
From the viewpoint of sufficiently ensuring the width, the line width is narrower than that of the main power supply line. Therefore, most of the voltage drop of the power supply voltage Vdd occurs in the auxiliary power supply line. In a period in which each pixel circuit 400 in the i-th row is selected, each pixel circuit 400 belonging to another row is driven in the driving period T.
_Since it is in _EL , the drive current Iel flows into each OLED element 420. However, since most of the resistance of the power supply line 31 exists in the auxiliary power supply line, if the auxiliary power supply line is formed in the row direction as in the present embodiment, the expected effect of improving the voltage drop of the power supply voltage Vdd is Certainly played.

<B: Second Embodiment>
Next, a second embodiment of the present invention will be described. In addition, the same code | symbol is attached | subjected about the element similar to 1st Embodiment among this embodiment, and the description is abbreviate | omitted suitably.

FIG. 7 is a circuit diagram showing a configuration of the pixel circuit according to the present embodiment. As shown in the figure, the pixel circuit 401 of this embodiment includes an OLED element 420 and a p-channel type each inserted between a power line 31 and a ground line 32, as in the first embodiment. A drive transistor Qdr is included. An n-channel light emission control transistor Qel is interposed between the drive transistor Qdr and the OLED element 420. The gate electrode of the light emission control transistor Qel is connected to the first control line 11 to which the first control signal Sb1 [i] is supplied. On the other hand, the source electrode of the driving transistor Qdr is connected to the source electrode of the first transistor Qb1. This first transistor Qb1
Is an n-channel transistor having a drain electrode connected to the power supply line 31, and functions as a switching element that switches between conduction and non-conduction between the source electrode of the drive transistor Qdr and the power supply line 31. The gate electrode of the first transistor Qb1 is connected to the second control line 12 to which the second control signal Sb2 [i] is supplied.

On the other hand, the second transistor Qb2 shown in FIG.
The p-channel transistor is connected to the drain electrode of dr and the drain electrode is connected to the gate electrode of the driving transistor Qdr. The gate electrode of the second transistor Qb2 is connected to the first control line 11. In addition, the first electrode L1a of the first capacitive element C1 and the first electrode L2a of the second capacitive element C2 are connected to the gate electrode of the drive transistor Qdr. The second electrode L2b of the second capacitive element C2 is connected to the power line 31. The second electrode L1b of the first capacitive element C1 is connected to the drain electrode of the third transistor Qb3. The third transistor Qb3 is a switching element for controlling the electrical connection between the data line 103 and the second electrode L1b of the first capacitive element C1 (typically switching between conduction and non-conduction between the two). The source electrode is connected to the data line 103 and the gate electrode is connected to the first control line 11. In addition,
In this embodiment, the potential supplied to the electrode of each transistor changes appropriately according to the state of operation. Generally, in a p-channel transistor, an electrode on the high potential side is defined as a source electrode. Strictly speaking, in each transistor of this embodiment, the source electrode and the drain electrode are at any time according to the state of operation. Will be replaced. However, in this specification, for convenience of understanding the invention, one electrode of each transistor is formally expressed as a source electrode and the other electrode is expressed as a drain electrode.

Next, FIG. 8 is a timing chart showing waveforms of the first control signals Sb1 [1] to Sb1 [m] and the second control signals Sb2 [1] to Sb2 [m] in the present embodiment. As shown in the figure, in the i-th horizontal scanning period (1H) in each vertical scanning period (1V), the compensation of the threshold voltage Vth of the driving transistor Qdr and the data voltage in each pixel circuit 401 in the i-th row are performed. Vdata
Is used as a writing period _{TWRT in} which the data acquisition is performed, and during the other periods, each pixel circuit 4
OLED device 420 of 01 is used as a driving period T _EL to emit light. First control signal Sb1
[1] to Sb1 [m] are signals that sequentially become low level for each writing period _{TWRT in which} each row is selected. That is, the first control signal Sb1 [i] is at a low level in the writing period T _WRT in which the i-th row is selected, and is at a high level in other periods (the driving period T _EL corresponding to the i-th row). . The writing period T _WRT is divided into a first period T ₁ for compensating for the threshold voltage Vth of the driving transistor Qdr and a second period T ₂ for capturing the data voltage Vdata in the pixel circuit 401. As shown in FIG. 8, the second control signal Sb2 [i], the first control signal Sb1 [i] is in the second period T ₂ of the writing time T _WRT to the low level to the low level, otherwise During this period (driving period T _EL and first period T ₁ ).

Next, the operation of the pixel circuit 401 in this embodiment will be described by dividing it into a first period T ₁ and a second period T ₂ of the writing period T _WRT and a driving period _TEL . In the following, the j-th belonging to the i-th row
The operation will be described with particular attention paid to the pixel circuit 401 in the column, but the operations of the other pixel circuits 401 are the same.

(a) First period T ₁ (writing period T _WRT )
In the first period T ₁ , the first control signal Sb1 [i] transitions to a low level and the second control signal Sb2 [i] maintains a high level. Therefore, as shown in FIG. 9, the first transistor Qb1, the second transistor Qb2, and the third transistor Qb3 are turned on,
The light emission control transistor Qel is turned off. Thus, in the first period T _1, the voltage V _G at the connection point N _G between the gate electrode and the first capacitor element C1 of the driving transistor Qdr difference value between the power supply voltage Vdd and the threshold voltage Vth of the driving transistor Qdr ( V _G = Vdd−Vth). On the other hand, a predetermined voltage (hereinafter referred to as “reference voltage”) Vref is applied to the data line 103 in the first period T ₁ . This reference voltage Vref is applied to the second electrode L1b of the first capacitive element C1 through the third transistor Qb3 in the on state. The reference voltage Vref is, for example, the ground voltage Vss.

(b) Second period T ₂ (writing period T _WRT )
In the second period T _2, because both the first control signal Sb1 [i] and second control signal Sb2 [i] is maintained at the low level, as shown in FIG. 10, the first transistor Qb1 and the emission control Both transistors Qel are turned off. Therefore, the power supply line 31 and the drive transistor Qdr are electrically insulated, and the current path from the power supply line 31 to the ground line 32 via the OLED element 420 is interrupted. Since no current flows from the power supply line 31 to the pixel circuit 401 in such a state, a voltage drop in the power supply line 31 does not occur.
Therefore, the second electrode L2b of the second capacitive element C2 interposed between the power supply line 31 and the connection point _NG.
However, it is possible to apply a desired voltage with high accuracy. That is, in this embodiment, the same operation and effect as the first embodiment are exhibited.

In the second period T ₂ in which the second control signal Sb2 [i] is at a low level, the data voltage Vdata corresponding to the gray level of the pixel circuit 401 in the i-th row is applied to the data line 103. As shown in FIG. 10, at this time, since the third transistor Qb3 is turned on by the low-level first control signal Sb1 [i], the data voltage Vdata is supplied to the first capacitive element via the third transistor Qb3. Applied to the second electrode L1b of C1. That is, the voltage of the second electrode L1b is changed to the data voltage Vdata from the reference voltage Vref set by the first period T _1. When the voltage of the second electrode L1b changes by ΔV (ΔV = Vref−Vdata) in this way, the voltage V _G of the gate electrode of the driving transistor Qdr is due to the capacitive coupling between the first capacitive element C1 and the second capacitive element C2. The voltage change ΔV at the second electrode L1b is divided by the level (Vdd−) just before the level divided according to the ratio between the capacitance Ca of the first capacitance element C1 and the capacitance Cb of the second capacitance element C2. Vth
). Since the change in the voltage VG at the connection point NG is expressed as “ΔV · Ca / (Ca + Cb)”, the voltage VG at the connection point NG is at a level expressed by the following expression (3) in the second period T ₂ . Stabilize.
V _G = Vdd−Vth−ΔV · Ca / (Ca + Cb) (3)
In the present embodiment as described above, since the voltage of the second electrode L1b prior to incorporation of the data voltage Vdata is set to a predetermined reference voltage Vref, the gate electrode of the driving transistor Qdr in the second period T ₂ it is possible to accurately set the voltage V _G to the level corresponding to the data voltage Vdata.

(b) Driving period T _EL
In the drive period T _EL, both the first control signal Sb1 [i] and second control signal Sb2 [i] becomes the high level. Therefore, as shown in FIG. 11, the second transistor Qb2 and the third transistor Qb3 are turned off. On the other hand, since the first transistor Qb1 and the light emission control transistor Qel are both turned on, a path from the power line 31 to the ground line 32 via the drive transistor Qdr and the OLED element 420 is formed. Since the voltage V _G at the connection point N _G in the writing period T _WRT is maintained even in the driving period T _EL of the second transistor Qb2 and third transistor Qb3 is turned off, the OLED element 420 is a driving transistor Qdr A drive current Iel corresponding to the voltage between the gate and the source is supplied.

Since the voltage of the gate electrode when the source electrode of the drive transistor Qdr is used as a reference in the drive period T _EL is “− (V _G −Vdd)”, the drive current Iel is expressed by the following equation (4).
Iel = (1/2) β (Vdd -V G -Vth) 2 ...... (4)
By substituting equation (3) into equation (4) and transforming, equation (5) below is derived.
Iel = (1/2) β (k · ΔV) ² …… (5)
However, k is “Ca / (Ca + Cb)”. As shown in this equation (5), the drive current Iel supplied to the OLED element 420 is a difference ΔV () between the data voltage Vdata and the power supply voltage Vdd.
= Vdd-Vdata), and does not depend on the threshold voltage Vth of the driving transistor Qdr. That is, also in the present embodiment, it is possible to compensate for the variation in the threshold voltage Vth of the drive transistor Qdr in each pixel circuit 401 and cause the OLED element 420 to emit light with a desired brightness with high accuracy.

Incidentally, in the above embodiments is a drive period T _EL and writing time T _WRT has exemplified a configuration in which continuous on the time axis, in order to reliably prevent the voltage drop of the power supply line 31 in the writing period T _WRT it may be inserted through the rest period T _OFF between a driving period T _EL and writing time T _WRT. During the pause period T _OFF , the data voltage Vdata is taken into the pixel circuit 401 and the OLED element 4
This is a period in which the supply of the drive current Iel to 20 is not performed. For example, as shown in FIG. 12, the second control signal Sb2 [i] in this aspect maintains a low level in both the second period T ₂ of the writing period T _WRT and the immediate rest period T _OFF. The high level is maintained in the period from the end point of the pause period T _{OFF to} the start point of the next second period T ₂ . Therefore, the rest period T _{O
In FF} , the second transistor Qb2 and the third transistor Qb3 are kept off by the high-level first control signal Sb1 [i] (that is, the second electrode L1b of the first capacitor C1).
Since the input of the data voltage Vdata to the pixel circuit 401 is stopped since the pixel circuit 401 is in a floating state, the first transistor Qb1 is maintained off by the low-level second control signal Sb2 [i] (that is, the power line 31). The voltage drop in the power line 31 does not occur. In the configuration the writing period T _WRT and drive period T _EL is continuous as shown in FIG. 8, such distortion of the first control signal Sb1 [i] and the second control signal Sb2 [i] of the delay and waveform Although due to the writing period T _WRT and drive period T _EL may overlap each other (when the supply of the driving current Iel on the uptake and OLED device 420 of the data relative to other words the pixel circuit 401 is performed at the same time) may also occur According to the embodiment shown in FIG. 12, it is possible to reliably prevent the drive current Iel from being supplied to the OLED element 420 while the data voltage Vdata is being taken into the pixel circuit 401.

<C: Third Embodiment>
Next, a third embodiment of the present invention will be described. In the present embodiment, the same elements as those in the first embodiment and the second embodiment are denoted by common reference numerals, and the description thereof is omitted as appropriate.

FIG. 13 is a circuit diagram showing the configuration of the pixel circuit in the present embodiment. As shown in the figure, the pixel circuit 402 has a configuration in which the first transistor Qb1 of the pixel circuit 401 shown in FIG. 7 is omitted. That is, the source electrode of the drive transistor Qdr is the power supply line 31.
Connected directly to. The gate electrode of the light emission control transistor Qel inserted between the drive transistor Qdr and the OLED element 420 is connected to the third control line 13. Accordingly, the light emission control transistor Qel is supplied with the third control signal Sc3 [i supplied to the third control line 13.
] Is on when it is high and off when it is low.

Further, the pixel circuit 402 of the present embodiment includes an n-channel second transistor Qc2 and a third transistor Qc3 instead of the second transistor Qb2 and the third transistor Qb3 of the pixel circuit 401 shown in FIG. The gate electrode of the second transistor Qc2 is connected to the second control line 12 supplied with the second control signal Sc2 [i], and the gate electrode of the third transistor Qc3 is supplied with the first control signal Sc1 [i]. 1 is connected to the control line 11.

FIG. 14 is a timing chart showing waveforms of signals supplied to the pixel circuit 402. As shown in the figure, the first control signals Sc1 [1] to Sc1 [m] are sequentially set to the high level every horizontal scanning period (1H). Write period T _{W in which} the first control signal Sc1 [i] is maintained at a high level
_RT (horizontal scanning period) is divided into a first period T ₁ and a subsequent second period T ₂ . The second control signal Sc2 [i] is transmitted from the time point a predetermined time before the start point of the writing period T _WRT to the first period T _1.
It is a signal that becomes high level during the period until the end point of, and becomes low level during other periods. The operations in the first period T ₁ and the second period T ₂ are the same as in the second embodiment. That is, in the first period T _1, the second electrode from the high level first control signal Sc1 [i] via the third transistor Qc3 which turned on by the data line 103 first capacitive element C1 Lb1
Is applied with the reference voltage Vref and the second control signal Sc2 [i] at the high level
When the transistor Qc2 is turned on, the voltage V _G of the gate electrode of the driving transistor Qdr converges to “Vdd−Vth”. Then, in the second period T _2, since the second transistor Qc2 is the data voltage Vdata after having been turned off is applied to the second electrode L1b of the first capacitive element C1, the voltage V _G of the driving transistor Qdr Depending on the data voltage Vdata
Descent to level 4).

On the other hand, to the third control signal Sc3 [1] no Sc3 [m], a pixel circuit in the writing period T _WRT 402
This is a signal that defines a drive period T _EL for actually causing the OLED element 420 to emit light in accordance with the data voltage Vdata taken in by. That is, when the third control signal Sc3 [i] transits to a high level, the light emission control transistor Qel is turned on and the power supply line 31 to the OLED element 420 is turned on.
Is formed, and the voltage V _G of the gate electrode of the driving transistor Qdr is formed through this path.
The drive current Iel according to the above is supplied to the OLED element 420. The amount of the drive current Iel is as described in the equation (6).

The third control signal Sc3 [i] in the present embodiment is the time when the pause period T _OFF has elapsed after the first control signal Sc1 [i] falls to the low level (that is, from the end point of the writing period _TWRT ). Stand up to a high level. That is, in this embodiment, as in the configuration shown in FIG. 12, pause period T _OFF between the driving period T _EL and writing time T _WRT is interposed. This suspension period T
_OFF is a period during which the data voltage Vdata is not taken into the pixel circuit 402 and the drive current Iel is not supplied to the OLED element 420. In other words, during the suspension period T _OFF , all of the first control signal Sc1 [i], the second control signal Sc2 [i], and the third control signal Sc3 [i] are at a low level. Therefore, in the idle period T _OFF , all of the light emission control transistor Qel, the second transistor Qc2, and the third transistor Qc3 are in the off state. According to the configuration in which inserted a pause period T _OFF between a driving period T _EL and writing time T _WRT, the drive current Iel to the OLED element 420 in the middle of capturing the data for the pixel circuits 402 Can be reliably prevented. Therefore, the voltage drop of the power supply line 31 in the writing period is suppressed, and the expected data voltage Vdata is obtained with high accuracy in the pixel circuit 4.
02 can be written.

<D: Application example>
Next, an electronic apparatus using the electro-optical device 1 according to the present invention will be described. FIG.
1 is a perspective view illustrating a configuration of a mobile personal computer that employs an electro-optical device 1 according to each embodiment as a display device. The personal computer 2000 includes the electro-optical device 1 as a display device and a main body 2010. The main body 2010 includes a power switch 2.
001 and a keyboard 2002 are provided. Since the electro-optical device 1 uses an organic EL material for the OLED element 420, it is possible to display an easy-to-see screen with a wide viewing angle.

FIG. 16 shows a configuration of a mobile phone to which the electro-optical device 1 according to the embodiment is applied. A cellular phone 3000 includes a plurality of operation buttons 3001, scroll buttons 3002, and the electro-optical device 1 as a display device. By operating the scroll button 3002, the screen displayed on the electro-optical device 1 is scrolled.

FIG. 17 shows a personal digital assistant (PDA: Personal) to which the electro-optical device 1 according to the embodiment is applied.
Digital Assistants). The information portable terminal 4000 includes a plurality of operation buttons 40.
01, a power switch 4002, and the electro-optical device 1 as a display device.
When the power switch 4002 is operated, various types of information such as an address book and a schedule book are displayed on the electro-optical device 1.

Note that examples of electronic apparatuses to which the electro-optical device 1 according to the invention is applied include FIGS. 15 to 17.
In addition to those shown above, digital still cameras, televisions, video cameras, car navigation devices, pagers, electronic notebooks, electronic papers, calculators, word processors, workstations, video phones, POS terminals, printers, scanners, copiers, video players, Examples include a device equipped with a touch panel. The use of the electro-optical device according to the invention is not limited to image display. For example, in an image forming apparatus such as an optical writing type printer or an electronic copying machine, a writing head that exposes a photosensitive member according to an image to be formed on a recording material such as paper is used. However, the electro-optical device of the present invention is used. The electronic circuit referred to in the present invention is a concept including not only a pixel circuit constituting a pixel of a display device as in each embodiment but also a circuit that is a unit of exposure in the image forming apparatus.

1 is a block diagram illustrating a configuration of an electro-optical device according to a first embodiment of the invention. FIG. It is a circuit diagram which shows the structure of each pixel circuit. It is a timing chart which shows the waveform of the signal supplied to a pixel circuit. It is a circuit diagram which shows the structure of the pixel circuit in a 1st period. It is a circuit diagram which shows the structure of the pixel circuit in a 2nd period. It is a circuit diagram showing a configuration of a pixel circuit in a driving period. It is a circuit diagram which shows the structure of the pixel circuit which concerns on 2nd Embodiment. It is a timing chart which shows the waveform of the signal supplied to a pixel circuit. It is a circuit diagram which shows the structure of the pixel circuit in a 1st period. It is a circuit diagram which shows the structure of the pixel circuit in a 2nd period. It is a circuit diagram showing a configuration of a pixel circuit in a driving period. It is a timing chart which shows the waveform of the signal concerning other modes. It is a circuit diagram which shows the structure of the pixel circuit which concerns on 3rd Embodiment. It is a timing chart which shows the waveform of the signal supplied to a pixel circuit. It is a perspective view which shows the specific form of the electronic device which concerns on this invention. It is a perspective view which shows the specific form of the electronic device which concerns on this invention. It is a perspective view which shows the specific form of the electronic device which concerns on this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Electro-optical device, A ... Pixel area | region, 100 ... Scan line drive circuit, 200 ... Data line drive circuit, 300 ... Control circuit, 400, 401, 402 ... Pixel circuit, 500 ... Power supply circuit , 31 ... power line, 32 ... ground line, 10 ... scan line, 11 ... first control line, 12 ...
... second control line, 13 ... third control line, 103 ... data line, 420 ... OLED element, Q
dr …… Drive transistor, Qel …… Light emission control transistor, Qa1, Qb1 …… First transistor, Qa2, Qb2, Qc2 …… Second transistor, Qa3, Qb3, Qc3 …… Third transistor, Qa4 …… Fourth transistor , TWRT ... writing period, TEL ... driving period, TOFF ... pause period, Sa1 [1] to Sa1 [m], Sb1 [1] to Sb1 [m], Sc1 [1] to Sc1 [m] ... ... First control signal, Sa2 [1
] To Sa2 [m], Sb2 [1] to Sb2 [m], Sc2 [1] to Sc2 [m] ... the second control signal, Sc3 [1] to Sc3 [m]
…… Third control signal, Iel …… Drive current.

Claims (2)

Scanning and data lines intersecting each other;
A power line intersecting the data line;
A pixel provided corresponding to the intersection of the scanning line and the data line,
The pixel is
A light emitting element that emits light according to a drive current;
A drive transistor for controlling the drive current connected between the power line and the light emitting element;
A first capacitor comprising a first electrode and a second electrode, wherein the first electrode is connected to a gate of the driving transistor;
A second capacitor having a third electrode and a fourth electrode, wherein the third electrode is connected to a gate of the driving transistor, and the fourth electrode is connected to the power supply line;
A first transistor connected between the drive transistor and the power line;
A second transistor connected between the gate of the driving transistor and a node between the driving transistor and the light emitting element;
A third transistor connected between the second electrode of the first capacitor and the data line;
A fourth transistor connected between the node and the light emitting element ,
In the first period, the first, second, and third transistors are turned on, the fourth transistor is turned off, and a reference voltage is supplied to the data line.
In the second period, the second transistor and the third transistor are turned on, the first transistor and the fourth transistor are turned off, and the data voltage corresponding to the gray level that the light emitting element should emit on the data line Is supplied,
In the third period, the light emitting element emits light when the second transistor and the third transistor are turned off and the first transistor and the fourth transistor are turned on.   An electronic apparatus having the electro-optical device according to claim 1.

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