JP5371651B2 - Vehicle power supply system and communication device - Google Patents

Description

  The present invention relates to a vehicle power supply system and a communication device.

  Currently, in many devices, serial communication is performed in which data is transmitted through only one signal line. Examples of such serial communication include communication by LIN (Local Interconnect Network). For example, a circuit for performing such serial communication is integrated in the form of SCI (Serial Communication Interface), UART (Universal Asynchronous Receiver Transmitter), and the like. Therefore, when it is desired to provide a specific device with a serial communication function, an integrated circuit as described above may be mounted.

  The above-mentioned SCI, UART and the like usually do not have a function of transmitting and receiving simultaneously in parallel. Therefore, when performing so-called full-duplex communication, it is necessary to prepare at least two integrated circuits for transmission and reception. For example, Patent Literature 1 describes a charge control device including a microcomputer that performs serial communication. The microcomputer described in Patent Document 1 has a UART TX function and a UART RX function, and is configured to be able to use these simultaneously. Therefore, transmission and reception can be performed simultaneously if wiring is performed appropriately.

JP 2007-142694 A

  In order to realize full-duplex serial communication according to the prior art, it is necessary to prepare two communication circuits such as UART for performing serial communication for transmission and reception, which increases the circuit scale. was there.

A vehicle power supply system according to the present invention includes a cell controller that manages the state of battery cells constituting an assembled battery, and a receiving unit that receives a serial communication signal transmitted from the cell controller via a first transmission path. If, with respect to the cell controller, the transmission as a transmission timer that outputs a serial communication signal via the second transmission path, a serial communication signal output from the transmission timer has a predetermined data A power supply system for a vehicle having a control means for controlling a timer , wherein the receiving means includes a reception timer and a serial communication interface for inputting serial communication signals transmitted through the first transmission path in parallel. In response to the reception timer detecting a predetermined number of continuous predetermined level signals or more, the serial communication input Face starts receiving serial communication signal, characterized in that.
Communication device according to the present invention includes a receiving unit that receives data by serial communication via the external device and the first transmission line, the output terminal is connected to the external device via the second transmission path, a predetermined a transmission timer for outputting a signal having a predetermined signal level at the timing of the control means a signal output from the transmission timer to control the transmission timer so that the signal transmitting predetermined data by the serial communication The receiving unit includes a receiving timer and a serial communication interface for inputting serial communication signals transmitted through the first transmission path in parallel, and the receiving timer is a predetermined number. In response to detecting several or more consecutive predetermined level signals, the serial communication interface starts receiving serial communication signals. It is characterized in.

  According to the present invention, a communication circuit for transmission is not required when performing full-duplex serial communication, and the circuit scale can be made smaller than before.

It is a block diagram of the direct-current power supply system used for the drive system of the rotary electric machine for vehicles. 2 is a block diagram showing an internal structure of a battery controller 20. FIG. 4 is a schematic diagram showing a flow of data transmitted and received between the battery controller 20 and the cell controller 80. FIG. FIG. 4 is a waveform diagram illustrating a request signal RQ and a response signal RS in FIG. 3. It is a figure which shows the signal output to each transmission line of a direct-current power supply system. It is a block diagram which shows the internal structure of the battery controller 120 by 2nd Embodiment.

(First embodiment)
A DC power supply system according to an embodiment of the present invention will be described. This DC power supply system is used in a drive system for a vehicular rotating electrical machine.

<Explanation of cell controller>
FIG. 1 is a block diagram of a DC power supply system used in a drive system for a vehicular rotating electrical machine. The DC power supply system shown in FIG. 1 supplies DC power to a load (for example, an inverter device) connected to relays RLP and RLN. The relay RLP is on the positive side of the DC power supplied, and the relay RLN is on the negative side.

  The DC power supply system shown in FIG. 1 includes a battery module 9, a cell controller (C / C) 80, a battery controller 20, an ammeter Si, and a voltmeter Vd in addition to the relays RLP and RLN. The ammeter Si and the voltmeter Vd detect the amount of DC current and the amount of DC voltage supplied from the battery module 9 to the loads connected to the relays RLP and RLN, respectively. The detection results are output to terminals CUR and VALL of the battery controller.

  The battery module 9 has a plurality of battery cell groups GB1, ..., GBM, ..., GBN. Each group has a plurality of battery cells BC1 to BC4 connected in series. That is, the battery module 9 has a large number of battery cells connected in series. In the present embodiment, there are several tens to several hundreds of battery cells, for example. Moreover, in this embodiment, each battery cell is a lithium ion battery.

  The terminal voltage of each battery cell changes depending on the state of charge of the battery cell. For example, a terminal voltage of about 3.3V is obtained in a charging state of about 30%, and a terminal voltage of about 3.8V is obtained in a charging state of about 70%. When the battery cell is in an overdischarged state, the terminal voltage may be, for example, 2.5 V or lower, and in an overcharged state, it may be 4.2 V or higher. That is, each of the battery cells BC1 to BC4 can grasp the state of charge (SOC) by measuring the terminal voltage.

  In this embodiment, one group is composed of four battery cells for the purpose of facilitating the measurement of the terminal voltage. That is, the groups BG1 to GBN are configured by four battery cells BC1 to BC4, respectively. In FIG. 1, there are a plurality of groups between the group BG1 and the group GBM and between the group GBM and the group GBN. However, these groups have the same configuration as the group BG1. The description is omitted to avoid complicated explanation.

  The cell controller 80 has a plurality of integrated circuits (ICs) corresponding to each group constituting the battery module 9. In FIG. 1, the integrated circuits corresponding to the groups GB1, ..., GBM, ..., GBN are shown as 3A, ..., 3M, ..., 3N, respectively. As in the case of the battery cell group described above, in FIG. 1, there are a plurality of integrated circuits between the integrated circuit 3A and the integrated circuit 3M and between the integrated circuit 3M and the integrated circuit 3N. However, since these integrated circuits have the same configuration as the integrated circuit 3A, they are omitted in order to avoid complicated description.

  The integrated circuits 3A to 3N include voltage detection terminals V1 to V4, B1 to B4, and GND in order to detect the terminal voltage of each battery cell. The terminals V1 to V4, B1 to B4, and GND are connected to the positive and negative electrodes of the battery cells BC1 to BC4 of the group corresponding to each integrated circuit, respectively. The integrated circuits 3A to 3N individually detect the voltages of the battery cells BC1 to BC4 of the corresponding groups GB1 to GBN and make the SOCs of the battery cells BC1 to BC4 individually to equalize the SOC of all the battery cells of all the groups. The charging state adjusting resistors R1 to R4 for adjusting to the battery cell are connected in parallel to each battery cell via the switch element. The switch element will be described later with reference to FIG.

  The integrated circuits 3A to 3N have transmission / reception terminals TR, TX, FFI, and FFO for signal transmission. The transmission terminal TX is connected to the reception terminal TR of the integrated circuit adjacent in the downward direction in FIG. 1, and constitutes a signal transmission path 52 that connects the integrated circuits 3A to 3N in series. Similarly, the transmission terminal FFO is connected to the reception terminal FFI of the integrated circuit adjacent in the downward direction in FIG. 1 to form a signal transmission path 54 that directly connects the integrated circuits 3A to 3N. In FIG. 1, the reception terminals TR and FFI of the integrated circuit 3A located at the top are connected to the transmission terminals TX and FFTEST of the battery controller 20, respectively. Similarly, the transmission terminals TX and FFO of the integrated circuit 3N located at the bottom in FIG. 1 are connected to the reception terminals RX and FF of the battery controller 20, respectively.

  The integrated circuits 3A to 3N further have a function of detecting abnormal states of the battery cells BC1 to BC4 of the corresponding groups GB1 to GBN. In the present embodiment, the abnormal state of the battery cell refers to overcharge or overdischarge of the battery cell, abnormal increase in temperature, and the like.

  Transmission / reception of signals between the integrated circuits 3 </ b> A to 3 </ b> N and the host battery controller 20 is performed via the communication harness 50. The battery controller 20 operates at a low voltage of 12V or less with the chassis potential of the vehicle as the ground (GND) potential. On the other hand, the integrated circuits 3A to 3N have different potentials of the battery cells in the corresponding group. Therefore, the integrated circuits 3A to 3N are held at different potentials and operate at different potentials. As described above, since the terminal voltage of the battery cell changes depending on the state of charge SOC, the potential of each group with respect to the lowest potential of the battery module 9 changes based on the state of charge SOC of each battery cell.

  Since the integrated circuits 3A to 3N detect the terminal voltages of the battery cells of the corresponding group or perform discharge control for adjusting the charge state SOC of the battery cells of the corresponding group, the integrated circuits 3A to 3N have the potential of the corresponding group. The voltage difference applied to the integrated circuits 3A to 3N becomes smaller when the reference potentials of the integrated circuits 3A to 3N are changed. The smaller the voltage difference applied to the integrated circuits 3A to 3N has the effect that the withstand voltage of the integrated circuits 3A to 3N can be further reduced or the safety and reliability are improved. The reference potentials of the integrated circuits 3A to 3N are changed based on the potential. Specifically, by connecting a GND terminal serving as a reference potential of the integrated circuits 3A to 3N to somewhere in the battery cell of the corresponding group, the reference potential of the integrated circuit is changed based on the corresponding group potential. It becomes possible. In this embodiment, the negative electrode of the battery cell that is the lowest potential of each group is connected to the GND terminal of the integrated circuit.

  Further, in order for the integrated circuits 3A to 3N to generate a reference voltage and a power supply voltage for operating the internal circuit of the integrated circuit therein, each integrated circuit has the positive electrode of the battery cell and the integrated circuit that are the highest potential of the corresponding group. Are connected to the Vcc terminal. With such a configuration, each integrated circuit operates by receiving a potential difference, that is, a voltage between the highest potential and the lowest potential of the corresponding group.

  Since the power supply system of the battery controller 20 and the power supply system of the cell controller 80 are different in potential relation and the voltage value is also greatly different, the communication harness 50 connected to the battery controller 20 is connected to each of the integrated circuits 3A to 3N. It is necessary that the transmission / reception terminals are electrically insulated from the transmission paths 52 and 54 connected in series. For this reason, insulation circuits for electrically insulating the communication harness 50 and the transmission paths 52 and 54 are respectively provided on the entrance side and the exit side of the transmission paths 52 and 54 formed of the integrated circuits 3A to 3N. Yes. In FIG. 1, the insulation circuit provided on the entrance side of the transmission lines 52 and 54 is indicated by the entrance side interface INT (E), and the insulation circuit provided on the exit side is indicated by the exit side interface INT (O).

  Each of these interfaces INT (E) and INT (O) has a circuit in which an electric signal is once converted into an optical signal and then converted into an electric signal again. Since transmission of information between the battery controller 20 and the cell controller 80 is performed via this circuit, electrical insulation between the electric circuit of the battery controller 20 and the electric circuit of the cell controller 80 is maintained. The interface INT (E) on the entrance side has photocouplers PH1 and PH2. The photocoupler PH1 is provided between the transmission terminal TX of the battery controller 20 and the reception terminal TR of the high potential side integrated circuit 3A. The photocoupler PH2 is provided between the transmission terminal FFTEST of the battery controller 20 and the reception terminal FFI of the integrated circuit 3A. The photocouplers PH1 and PH2 in the entrance-side interface INT (E) maintain electrical insulation between the transmission terminals TX and FFTEST of the battery controller 20 and the reception terminals TR and FFI of the integrated circuit 3A. .

  Similarly, photocouplers PH3 and PH4 of the exit side interface INT (O) are provided between the reception terminals RX and FF of the battery controller 20 and the low potential side integrated circuit 3N, respectively. And electrical insulation between the transmission terminals of the integrated circuit 3N are maintained. More specifically, a photocoupler PH3 is provided between the transmission terminal TX of the integrated circuit 3N and the reception terminal RX of the battery controller 20, and a photocoupler is provided between the transmission terminal FFO of the integrated circuit 3N and the reception terminal FF of the battery controller 20. A coupler PH4 is provided.

  As described above, the integrated circuits 3 </ b> A to 3 </ b> N are connected in series by the transmission / reception terminals TX and TR to constitute the signal transmission path 52. A signal transmitted from the transmission terminal TX of the battery controller 20 is received by the reception terminal RX of the integrated circuit 3A via the photocoupler PH1 in the entrance side interface INT (E). Thereafter, this signal is sequentially transmitted from the transmission terminals TX of the respective integrated circuits 3A to 3N, and is sequentially received by the reception terminals RX of the adjacent integrated circuits. This signal is finally transmitted from the transmission terminal TX of the integrated circuit 3N and received by the reception terminal RX of the battery controller 20 via the photocoupler PH3 of the exit side interface INT (O). A loop-shaped communication path as described above is provided between the battery controller 20 and the integrated circuits 3A to 3N, and serial communication is performed via the loop-shaped communication path. The battery controller 20 receives measurement values such as terminal voltages and temperatures of the battery cells BC1 to BC4 through the serial communication. The integrated circuits 3A to 3N are further configured to automatically enter an operating state when a command is received via this transmission line. Therefore, when a communication command is transmitted from the battery controller 20, each of the integrated circuits 3A to 3N changes from the sleep state to the operating state.

  The integrated circuits 3A to 3N further perform abnormality diagnosis of the battery cells BC1 to BC4, and transmit a 1-bit signal via the next transmission path when an abnormal state of the battery cell is detected. When the integrated circuits 3A to 3N themselves detect an abnormal state or receive a signal indicating an abnormal state (hereinafter referred to as an abnormal signal) from another integrated circuit at the receiving terminal FFI, Send an abnormal signal. On the other hand, when the abnormal signal already received at the reception terminal FFI disappears, or when the abnormality judgment of itself changes and the abnormal state disappears, the abnormal signal transmitted from the transmission terminal FFO disappears. In this embodiment, this abnormal signal is a 1-bit signal. In principle, the battery controller 20 does not transmit an abnormal signal to the integrated circuit 3A. However, since it is important that the abnormal signal transmission path operates correctly, the battery controller 20 transmits a test signal, which is a pseudo abnormal signal, from the terminal FFTEST of the battery controller 20 for diagnosis of the transmission path. The test signal transmission path will be described below.

  As described above, the integrated circuits 3 </ b> A to 3 </ b> N are connected in series by the transmission / reception terminals FFO and FFI to constitute the signal transmission path 54. A test signal that is a pseudo abnormality signal transmitted from the transmission terminal FFTEST of the battery controller 20 is received by the reception terminal FFI of the integrated circuit 3A via the photocoupler PH2 in the entrance-side interface INT (E). Thereafter, this signal is sequentially transmitted from the transmission terminal FFO of each of the integrated circuits 3A to 3N, and is sequentially received by the reception terminal FFI of the adjacent integrated circuit. This signal is finally transmitted from the transmission terminal FFO of the integrated circuit 3N and received by the reception terminal FF of the battery controller 20 via the photocoupler PH4 of the exit side interface INT (O). As described above, the battery controller 20 transmits and receives the test signal, so that the communication path for the abnormal signal can be diagnosed, and the reliability of the system is improved. Further, as described above, even if there is no transmission request from the battery controller 20, the integrated circuit that has detected the abnormal condition sends an abnormal signal to the next integrated circuit, so that the abnormal condition is promptly transmitted to the battery controller 20. Thereby, the countermeasure against the occurrence of the abnormal state can be promptly executed.

  In the above description, the signal transmission is performed from the integrated circuit 3A corresponding to the high potential group of the battery module 9 toward the integrated circuit 3N corresponding to the low potential group, but this is an example. is there. Conversely, for example, a signal is transmitted from the battery controller 20 to the integrated circuit 3N corresponding to the low potential group of the battery module 9, and the received signals are sequentially included in the integrated circuits (including the integrated circuit 3M) corresponding to the high potential group. The signal may be sent to the battery controller 20 from the integrated circuit 3A corresponding to the group of the highest potential.

  The DC power supply system shown in FIG. 1 supplies DC power to a load such as an inverter device via a positive-side relay RLP and a negative-side relay RLN. These relays RLP and RLN are configured to be able to control opening and closing from the battery controller 20 and the inverter device. Therefore, the battery controller 20 or the inverter device can control the opening and closing of the relays RLP and RLN in response to detection of an abnormality in the integrated circuit.

  Further, the battery controller 20 receives the output of the current sensor Si, detects the current supplied from the entire battery module 9 to the inverter device, and determines the DC voltage supplied from the battery module 9 to the inverter device by the output of the voltmeter Vd. Detect.

<Description of battery controller>
FIG. 2 is a block diagram showing the internal structure of the battery controller 20. FIG. 2 shows only the blocks according to the present invention, and other blocks are omitted for the sake of simplicity.

  Within the battery controller 20, there are three internal buses B1, B2, and B3. The internal bus B1 and the internal bus B2 are connected to each other via the bus controller 24. Similarly, the internal bus B2 and the internal bus B3 are connected to each other via the bus controller 26.

  The CPU 21, ROM 22, and RAM 23 are connected to the internal bus B1. The ROM 22 is a nonvolatile storage device and stores a predetermined control program. The CPU 21 performs predetermined control by reading and executing a control program stored in the ROM 22. The RAM 23 is a volatile storage device, and the CPU 21 uses the RAM 23 as a work area.

  A timer 27 and an SCI (Serial Communication Interface) 29 are connected to the internal bus B3. The timer 27 has one transmission terminal, and this transmission terminal is connected to the transmission terminal TX of the battery controller 20. That is, a signal transmitted from the transmission terminal of the timer 27 is received by the reception terminal TR of the integrated circuit 3A shown in FIG.

  The timer 27 has a function of switching the signal level of the transmission terminal when a certain time has elapsed. For example, if the CPU 21 instructs the timer 27 to switch the signal level to L (Low) when 10 milliseconds have elapsed from the present time, the timer 27 will switch the transmission terminal at the time when 10 milliseconds have elapsed since the instruction was issued. Set the signal level to L.

  The SCI 29 has one receiving terminal, and this receiving terminal is connected to the receiving terminal RX of the battery controller 20. That is, the output from the transmission terminal TX of the integrated circuit 3N shown in FIG. 1 is input to the reception terminal of the SCI 29. In addition to the SCI 29, a timer 28 is connected to the reception terminal RX of the battery controller 20. Therefore, the output from the transmission terminal TX of the integrated circuit 3N shown in FIG.

  When the signal level of the input signal continuously becomes L for a certain time or longer and the data for adjusting the communication speed is acquired, the timer 28 stores the acquired data in the RAM 23 and notifies the CPU 21 of the fact. In response to the notification from the timer 28, the CPU 21 adjusts the communication speed to operate the SCI 29, and receives data transmitted by the integrated circuit 3N through serial communication. Data received by the SCI 29 is stored in the RAM 23 from the SCI 29. The CPU 21 can extract received data stored in the RAM 23.

  A DMA (Direct Memory Access) controller 25 is connected to the internal bus B2. The DMA controller 25 has a function of reading data stored in the RAM 23 and transmitting it to the timer 27. Since this function is executed independently of the CPU 21, the CPU 21 can execute other processes while data is being read and transmitted by the DMA controller 25. The bus controllers 24 and 26 perform internal bus arbitration and data transfer between the internal buses.

(Description of serial communication)
FIG. 3 is a schematic diagram illustrating a flow of data transmitted and received between the battery controller 20 and the cell controller 80. In each transmission path shown in FIG. 3, data is transmitted and received by serial communication of a protocol described later. FIG. 3 schematically shows a state in which the battery controller 20 requests the terminal voltage of the battery cell corresponding to the integrated circuit 3M as an example of data transmission / reception. In FIG. 3, the communication harness 50 and the interfaces INT (E) and INT (O) are omitted.

  When the battery controller 20 requests a terminal voltage of a specific battery cell such as a battery cell corresponding to the integrated circuit 3M, the battery controller 20 first transmits a request signal RQ from the transmission terminal TX. The request signal RQ includes data indicating a request for a terminal voltage and an integrated circuit that is a target for requesting the terminal voltage, that is, the integrated circuit 3M. The request signal RQ transmitted from the battery controller 20 is input to the reception terminal RX of the integrated circuit 3A in the cell controller 80.

  The integrated circuit 3A analyzes the content of the signal received from the reception terminal RX. Then, it is determined whether the received signal is a request for some operation from the integrated circuit 3A. If an affirmative determination is made, the integrated circuit 3A transmits a necessary signal in addition to the received signal from the transmission terminal TX. On the other hand, when the received signal does not require any operation from the integrated circuit 3A, the integrated circuit 3A transmits the received signal as it is from the transmission terminal TX. In FIG. 3, since the request signal RQ is a signal for requesting the terminal voltage of the battery cell from the integrated circuit 3M, the integrated circuit 3A transmits the request signal RQ as it is from the transmission terminal TX.

  The integrated circuit 3B and each subsequent integrated circuit operate in the same manner as the integrated circuit 3A. As a result, the request signal RQ is successively propagated between the integrated circuits from the integrated circuit 3A to the integrated circuit 3N. When the integrated circuit 3M receives the request signal RQ, since the request signal RQ is a signal for requesting the terminal voltage of the battery cell from the integrated circuit 3M as described above, the integrated circuit 3M sets the terminal voltage in addition to the received request signal RQ. A response signal RS is transmitted from the transmission terminal TX. An integrated circuit after the integrated circuit 3M (for example, the integrated circuit 3N) receives the request signal RQ and the response signal RS from the receiving terminal and transmits these signals as they are from the transmitting terminal.

  Finally, the integrated circuit 3N transmits the request signal RQ and the response signal RS from the transmission terminal TX. These signals are input to the reception terminal RX of the battery controller 20. The battery controller 20 acquires the terminal voltage of the battery cell corresponding to the integrated circuit 3M by referring to the received response signal RS. As described above, the battery controller 20 communicates with the cell controller 80.

  FIG. 4 is a waveform diagram showing the request signal RQ and the response signal RS in FIG. 4A shows only the request signal RQ, and FIG. 4B shows the request signal RQ and the response signal RS. In each waveform diagram shown in FIG. 4, time t0 is the time when transmission of each signal is started. While communication is not being performed, the signal level of the transmission line is H (High). In this serial communication, the start bit is 0 and the stop bit is 1.

  The request signal RQ includes a break field F1, a sync field F2, and an ID field F3. The break field F1 is a field indicating the start of communication, and is composed of continuous 0 (T1) of 13 bits or more and a stop bit (T2). The receiving side of the request signal RQ recognizes the start of serial communication when detecting consecutive 0s of 13 bits or more.

  The sync field F2 is a field for adjusting the communication speed, and includes a start bit (T3), an 8-bit fixed value (T4), and a stop bit (T5). The 8-bit value transmitted in the period T4 is 55 in hexadecimal. This value is “0101010101” in binary. That is, 0 and 1 appear alternately. The receiving side can obtain the serial communication speed from the sync field F2. That is, the time required for 1-bit transmission can be acquired from the sync field F2. In this serial communication, a value composed of a plurality of bits is transmitted in order from the lower bits.

  Since the transfer rate can be obtained from the sync field F2, the transmission rate of the signal transmitted from any of the integrated circuits from the transmission terminal TX does not necessarily match the reception terminal RX.

  The ID field F3 is a field representing the type of serial communication and the target integrated circuit. The ID field F3 includes a start bit (T6), an 8-bit identification value (T7), and a stop bit (T8). This identification value is a value corresponding to the type of request signal RQ, information specifying the integrated circuit that is the target of the request signal RQ, and the like.

  When each integrated circuit starts receiving the request signal RQ shown in FIG. 4A from the receiving terminal RX, it immediately starts transmitting a signal to the transmitting terminal TX. When the 8-bit identification value included in the ID field F3 is received, the integrated circuit determines whether or not the request signal RQ requests an operation from itself based on the identification value. If an affirmative determination is made, the response signal RS is transmitted from the transmission terminal TX following the request signal RQ, as shown in FIG.

  As shown in FIG. 4B, the response signal RS includes a data field F4. In FIG. 4B, only one data field F4 is shown, but a plurality of data fields F4 may be included in the response signal RS. Each data field F4 includes a start bit (T9), 8-bit data (T10), and a stop bit (T11). For example, as shown in FIG. 3, when the terminal voltage of the battery cell corresponding to the integrated circuit 3M is acquired, the integrated circuit 3M transmits a response signal RS including data representing the terminal voltage of the battery cell.

  FIG. 5 is a diagram illustrating signals output to the transmission lines of the DC power supply system. In FIG. 5, there are twelve integrated circuits 3A to 3L. In FIG. 5, the battery controller 20 transmits a request signal related to the integrated circuit 3G. Although there is some delay in each integrated circuit, each integrated circuit immediately transmits the signal received at the reception terminal RX from the transmission terminal TX. Thereby, the transmission of the request signal RQ by the battery controller 20 and the reception of the request signal RQ and the response signal RS by the battery controller 20 are performed in parallel. Therefore, the battery controller 20 needs to include a transmission timer 27 in addition to the reception timer 28 and the SCI 29.

(Explanation of timer)
As shown in FIG. 2, the timer 28 and the SCI 29 are connected to the reception terminal RX of the battery controller 20. The SCI 29 is an interface for performing serial communication. Similar to a communication circuit for general serial communication, the SCI 29 has a function of receiving 8-bit data to which a start bit and a stop bit are added. In the serial communication in this embodiment, the start of communication is indicated by consecutive 0s of 13 bits or more. However, the SCI 29 does not have a function of recognizing a signal indicating the start of communication. A timer 28 exists to recognize the start of communication. The SCI 29 starts serial communication in response to the timer 28 recognizing the start of communication. As shown in FIG. 5, the serial communication according to the present embodiment has the above-described configuration because all fields except the break field F1 have a format of “8-bit data to which a start bit and a stop bit are added”. Thus, the battery controller 20 can receive data. On the other hand, the timer 27 connected to the transmission terminal TX of the battery controller 20 does not have a special function related to serial communication. The details of the function of the timer 27 and the procedure by which the CPU 21 (FIG. 2) transmits the request signal RQ using the timer 27 will be described below.

  The timer 27 counts up a built-in counter at predetermined intervals. It is possible to input a specific count value and signal level to the timer 27 from the outside of the timer 27. When the count value and the signal level are inputted, the timer 27 sets the signal level of the transmission signal to the inputted signal level when the count value of the counter is increased by the specific count value inputted. For example, when data “100, H” is input to the timer 27, the timer 27 sets the signal level of the transmission terminal to H when the data is counted up by 100 from the count value at the time when the above data is input. To do.

  In addition, a plurality of pairs of specific count values and signal levels can be transmitted to the timer 27 at a time using the DMA controller 25. For example, when data “100, H” and data “200, L” are transmitted to the timer 27 by the DMA controller 25, the timer 27 is first counted up by 100 counts. Is set to H, and then the signal level at the transmission terminal is set to L when the count is further increased by 100 counts.

  The CPU 21 first stores a plurality of pairs of count values and signal levels in the RAM 23 in order to transmit a request signal from the transmission terminal TX. Thereafter, the CPU 21 causes the DMA controller 25 to transmit these pairs to the timer 27. Thereby, for example, the request signal RQ shown in FIG. 4 can be transmitted from the transmission terminal TX.

  FIG. 5 is a diagram illustrating an example of a request signal transmitted by the timer 27. FIG. 5A shows the waveform of a signal to be transmitted from the transmission terminal TX of the battery controller 20 now. The time when transmission of this signal is started is assumed to be t0. Note that the timer counts up every 0.01 microseconds. Further, the battery controller 20 transmits the signal shown in FIG. 5A at a speed of 19.2 kbps. When a signal is transmitted at 19.2 kbps, the time for transmitting 1-bit data is 52.08 microseconds. Therefore, the counter of the timer 27 advances by 5208 counts during transmission of 1-bit data.

  When transmitting a request signal under the above conditions, the number of transmitted bits from time t0, the count value from time t0, and the output at that time for each time when the signal level of the request signal changes The signal level is as shown in FIG. In FIG. 5B, for example, the number of bits transmitted by time t1 is 13, and the counter advances by 67704 counts from time t0 to time t1, and the signal level changes to H at time t1. It shows that you do. The CPU 21 stores the data TD shown in FIG. 5B in the RAM 23 and causes the DMA controller 25 to transmit it to the timer 27. Thereby, the CPU 21 can transmit a signal for serial communication from the transmission terminal TX without using SCI dedicated to serial communication.

According to the DC power supply system according to the first embodiment described above, the following operational effects can be obtained.
(1) Whereas the SCI 29 that receives data is a circuit having a function of performing serial communication, the timer 27 that transmits data is a circuit that can switch the signal level at a predetermined cycle. As a result, the circuit scale can be reduced as compared with the conventional configuration in which a transmission circuit for performing serial communication needs to be provided separately.

(Second Embodiment)
A DC power supply system according to an embodiment of the present invention will be described. Unlike the first embodiment, this DC power supply system includes a plurality of battery modules 9 and cell controllers 80. The same blocks as those of the first embodiment are denoted by the same reference numerals as those of the first embodiment, and the description thereof is omitted.

  FIG. 6 is a block diagram showing an internal structure of the battery controller 120 according to the second embodiment. The battery controller 120 is connected to the two cell controllers 80a and 80b, and communicates with each cell controller. Unlike the first embodiment, the battery controller 120 includes a plurality of transmission circuits and reception circuits in order to communicate independently with each cell controller.

  A timer 27a, a timer 28a, and an SCI 29a for communicating with the cell controller 80a are connected to the internal bus B3 of the battery controller 120. Each of these units is used to communicate with the cell controller 80a. Since the communication itself is the same as that of the timer 27, the timer 28, and the SCI 29 in the first embodiment, the description thereof is omitted. Further, a timer 27b, a timer 28b, and an SCI 29b for communicating with the cell controller 80b are connected to the internal bus B3. Each of these units is used to communicate with the cell controller 80b.

  According to the DC power supply system according to the second embodiment described above, the same operational effects as those obtained with the DC power supply system according to the first embodiment can be obtained.

  The following modifications are also within the scope of the present invention, and one or a plurality of modifications can be combined with the above-described embodiment.

(Modification 1)
The serial communication protocol is not limited to that according to the above embodiment. For example, the present invention can be applied to communication using LIN. Further, the connection form between the apparatuses that perform communication is not limited to that according to the above embodiment. For example, a configuration in which a communication device to which the present invention is applied and an external device communicate with each other on a one-to-one basis may be used.

(Modification 2)
The DMA controller 25 may transmit data from the ROM 22 to the timer 27 instead of the RAM 23. For example, if the pattern of the request signal transmitted by the battery controller 20 is limited, data corresponding to each pattern can be stored in the ROM 22 in advance.

(Modification 3)
The CPU 21 may directly transmit data to the timer 27 without using the DMA controller 25.

(Modification 4)
The present invention can also be applied to devices other than the vehicle power supply system. For example, an SCI that receives data by serial communication with an external device via a transmission line, a timer that measures the time, the output of which is connected to the external device via a transmission line different from the transmission line, A CPU that controls the timer so that the signal output from the timer becomes a signal for transmitting predetermined data by serial communication, and performs full-duplex serial communication with an external device using the SCI and the timer It may be a device.

  The present invention can also be applied to vehicle power supply systems and communication devices other than the above-described embodiments. The present invention may be applied to a vehicle power supply system that includes only a cell controller, a receiving unit, a timer, and a control unit. In addition, the present invention is not limited to the above-described embodiment as long as the characteristics of the present invention are not impaired, and other forms conceivable within the scope of the technical idea of the present invention are also within the scope of the present invention. included.

B1, B2, B3 ... Internal bus, BC1 to BC4 ... Battery cells, 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, 3I, 3J, 3K, 3L, 3M, 3N ... Integrated circuit, Si ... Current Vd ... Voltmeter, 9 ... Battery module, 20 ... Battery controller, 21 ... CPU, 22 ... ROM, 23 ... RAM, 24,26 ... Bus controller, 25 ... DMA controller, 27,28 ... Timer, 29 ... SCI 50 ... Communication harness, 52 ... Transmission path (serial communication), 54 ... Transmission path (flag communication), 80 ... Cell controller

Claims (6)

A cell controller for managing the state of the battery cells constituting the assembled battery;
Receiving means for receiving the serial communication signal transmitted from the cell controller via the first transmission path;
A timer for transmission that outputs a signal for serial communication to the cell controller via the second transmission path;
A vehicle power supply system having control means for controlling the transmission timer so that a serial communication signal output from the transmission timer becomes predetermined data ,
The receiving means includes
A reception timer and a serial communication interface for inputting serial communication signals transmitted through the first transmission path in parallel;
In response to the reception timer detecting a predetermined level signal of a predetermined number or more, the serial communication interface starts receiving a serial communication signal.
A power supply system for a vehicle. In the vehicle power supply system according to claim 1,
From the transmission timer to the cell controller via the second transmission path, and to the loop communication path from the cell controller to the receiving means via the first transmission path,
A vehicle power supply system , wherein a request signal transmitted from the transmission timer and a response signal transmitted from the cell controller are transmitted in a superimposed manner. In the vehicle power supply system according to claim 1 or 2,
The vehicle further comprising a memory for preliminarily storing data defining an output timing and an output level of the transmission timer, and controlling an output signal of the transmission timer based on the stored contents of the memory Power system. In the vehicle power supply system according to claim 3 ,
The vehicle power supply system characterized in that the means for controlling the output signal of the transmission timer based on the stored contents of the memory is a DMA controller . In the vehicle power supply system according to any one of claims 1 to 4,
By transmitting a pseudo abnormal signal as a test signal from the transmission timer and sequentially transmitting the second transmission path , the cell controller and the first transmission path to the receiving means, for serial communication. A vehicle power supply system characterized by performing a communication path diagnosis . Receiving means for receiving data by serial communication with an external device via the first transmission path;
Output terminal is connected to the external device via the second transmission path, a transmission timer for outputting a signal having a predetermined signal level at a predetermined timing,
A communication device having control means for controlling the transmission timer so that a signal output from the transmission timer becomes a signal for transmitting predetermined data by the serial communication ,
The receiving means includes
A reception timer and a serial communication interface for inputting serial communication signals transmitted through the first transmission path in parallel;
In response to the reception timer detecting a predetermined level signal of a predetermined number or more, the serial communication interface starts receiving a serial communication signal.
A communication device.

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