JP5341801B2 - Method and apparatus for visual inspection of semiconductor wafer - Google Patents

Description

  The present invention relates to a comparative inspection at a predetermined position in an appearance inspection of a semiconductor wafer, and particularly to a method for generating a reference image that is effective when it is difficult to acquire a reference image used for the comparative inspection from a specific location. .

  High-resolution images captured with an electron microscope may be used to detect extremely fine defects in semiconductor appearance inspection. However, inspection using an electron microscope does not achieve both ultra-fine defect detection and high-speed inspection. Therefore, fixed point observation (fixed point inspection) is performed in which inspection points in the chip are determined in advance, and the same inspection point of all or selected chips in the wafer is inspected. If this fixed point inspection is executed by image comparison with a reference image, high sensitivity inspection can be realized. By using fixed point inspection using an electron microscope in the early stages of semiconductor process development, it is possible to obtain appearance information of defects that have occurred and information on the distribution of defect occurrences within the wafer surface. Can be performed efficiently.

  As a related document, Patent Document 1 discloses a comparative inspection method using a reference image as a fixed point observation method using an electron beam microscope. Non-Patent Document 1 discloses a case of defect quantification using an inspection image as a fixed point observation method using an electron microscope.

JP 2009-37939 A

V. Svidenko, et al., “Powerful Quantitative Monitoring Tool Improves Cu and W Plug Fill”, pp. 5-11, Issue Two 2004, Nanochip Technology Journal (2004).

  With semiconductor miniaturization and process complexity, process margins have decreased and it has become difficult to determine process conditions. For this reason, in the early stage of semiconductor development, there are cases where non-defective chips exist on the entire surface of the wafer, and there is a problem that a reference image for comparison inspection cannot be taken.

  Although Patent Literature 1 discloses a comparative inspection method using a reference image stored in advance as a fixed point observation method using an electron beam microscope, since it does not touch on the above problems, a method for acquiring a reference image is disclosed. It has not been. For this reason, the method described in Patent Document 1 has a problem in that when no non-defective chip exists on the entire wafer surface, a reference image cannot be acquired and comparative inspection cannot be performed.

  Non-Patent Document 1 discloses a method for quantifying a defect image captured by image processing as a fixed point observation method using an electron beam microscope. However, no comparative inspection using a reference image is disclosed. For this reason, the method described in Non-Patent Document 1 has a problem that a high-sensitivity inspection capable of extracting fine defects cannot be performed.

  In view of the above problems, the present invention provides a method for generating a reference image in a comparative inspection and a method for evaluating the generated reference image, thereby enabling the application of a comparative inspection in an inspection target in which no non-defective product exists, and performing a high-sensitivity inspection. It is an object of the present invention to provide an appearance inspection method and an appearance inspection apparatus that are realized.

An outline of typical inventions among inventions disclosed in the present application will be briefly described as follows.
(1) An appearance inspection method for inspecting the appearance of a semiconductor wafer on which a plurality of chips are formed, and images the observation positions of corresponding patterns formed to be the same for each of the plurality of chips. A step of generating an averaged image using the captured captured image, comparing the averaged image with information representing a circuit design corresponding to the captured image, and satisfying a predetermined condition as a reference image And a step of comparing and inspecting the reference image and the picked-up image.
(2) In the semiconductor wafer inspection method, the step of imaging the same chip coordinate position of a plurality of chips fabricated on the wafer, the step of comparing the captured image with a reference image, and the captured image And evaluating the reference image generated from the captured image using the corresponding circuit design information.
(3) Using the step of imaging different positions of a plurality of chips formed on the semiconductor wafer, the step of comparing the captured image with a reference image, and circuit design information corresponding to the captured image An inspection method including a step of evaluating the reference image generated from the captured image at each different position.
(4) Using the step of imaging different positions of a plurality of chips formed on a semiconductor wafer, the step of comparing the captured image with a reference image, and circuit design information corresponding to the captured image And a step of evaluating the reference image generated from the captured image for each position having the same circuit pattern.
(5) The means for imaging the observation position of the corresponding pattern formed to be the same for each of the plurality of chips formed on the semiconductor wafer, and the captured image and the reference image are compared. Visual inspection apparatus comprising: means; input means for inputting information representing a circuit design corresponding to the captured image; and data conversion means for converting data so as to compare the information representing the circuit design with the captured image The means for generating an averaged image using the picked-up captured image is compared with information representing a circuit design corresponding to the averaged image and the captured image, and satisfying a predetermined condition And a means for selecting as the reference image.

  According to the present invention, it is possible to generate a reference image for executing a comparative inspection even in a state where a non-defective chip at the initial stage of semiconductor development cannot be obtained. As a result, it is possible to grasp the occurrence state of defects by performing a highly sensitive comparative inspection, and it is possible to speed up the process condition determination.

It is a block diagram of the 1st Example of this application. It is a figure which shows the arrangement | sequence of the chip | tip on a wafer. It is a figure explaining a chip | tip and a chip coordinate. It is a figure which shows the example of the captured image in an observation position. It is a figure which shows the flow which produces | generates a defect area | region image. It is a flowchart of fixed point observation. It is an example of the fixed point observation image used in order to produce | generate a reference | standard image. It is a flowchart which produces | generates a reference | standard image. It is an example of a circuit design image. It is a 2nd flowchart of fixed point observation. It is a 1st screen block diagram for a reference | standard image production | generation. It is a standard image generation flow figure in the 1st screen composition. FIG. 10 is a second screen configuration diagram for generating a reference image. It is a standard image generation flow figure in the 2nd screen composition.

  FIG. 1 shows the overall configuration of the inspection apparatus used in the first embodiment. The SEM device body 10 includes the following electron optical system and detection system. Reference numeral 101 denotes an electron source that emits an electron beam 100. The emitted electron beam 100 passes through the electron lenses 102 and 103, and astigmatism and misalignment are corrected by the electron beam axis adjuster 104. Reference numerals 105 and 106 denote two-stage deflectors which deflect the electron beam 100 and control the position where the electron beam 100 is irradiated. The deflected electron beam 100 is converged by the objective lens 107 and irradiated onto the imaging target area 109 of the wafer 108. From the imaging target region 109, secondary electrons and reflected electrons are emitted by the irradiated electron beam 100, and the secondary electrons and the reflected electrons collide with the reflecting plate 110 having the primary electron beam passage hole 110 ′, and are generated there. Secondary electrons are detected by the electron detector 111.

  Secondary electrons and reflected electrons detected by the detector 111 are converted into digital signals by the A / D converter 112 of the image signal processing system indicated by 127 and stored in the memory 114. An adder circuit 113 may be arranged between the A / D converter and the memory. When the electron beam 100 is raster-scanned on the imaging target area 109, the adder circuit 113 reduces shot noise by calculating an addition average (frame addition) of detection signals obtained at the same beam irradiation position. And an image with a high S / N can be obtained. Reference numeral 115 denotes an image processing unit that performs extraction of an abnormal part, measurement of the size of the extracted abnormal part, calculation of appearance characteristics of the abnormal part, and the like using an image stored in the memory 114. In order to enable generation of a reference image using data representing a circuit design, which will be described later, data representing a circuit design or data obtained by converting the data can be input to the image processing unit 115. The image processing unit 115 has a function of obtaining an imaging position shift correction at the time of SEM imaging by matching an SEM image with data representing a circuit design or data obtained by converting the SEM image. Specifically, as this method, a method of calculating the position where the maximum normalized correlation value is obtained as a position where the design data and the data representing the circuit design are matched can be used. You may use.

Reference numeral 116 denotes an XY stage, which moves the wafer 108 placed on the XY stage so that an image can be taken at an arbitrary position on the wafer 108.
Reference numeral 117 denotes a secondary storage device that can store an image stored in the memory 114. In addition, the abnormal portion of the inspection target area 109 obtained by image processing and the appearance characteristics of the abnormal portion can be stored in the memory 114. A computer terminal 118 can display an image stored in the secondary storage device 117 or the memory 114. Further, the user can control and set various operations of the SEM apparatus main body 10, the image processing system 127, the overall control system 119 described later, and the like by inputting to the terminal 118.

  119 is an overall control system, 120 is a current amount control unit for the electron source 101 of the electron beam 100, 121 is a deflection control unit for controlling the deflectors 105 and 106, and 122 is for controlling the electron lenses 102, 103, 104, and 107. An electronic lens control unit 123, a stage control unit 123 for controlling the field of view movement due to the movement of the XY stage 116, and a sequence control unit 124 for controlling the entire inspection sequence. A data input unit 126 receives the coordinates of the inspection target area 109 and data representing the circuit design to be compared with the SEM image. A data conversion unit 125 performs data conversion so that the data representing the circuit design can be easily compared with the SEM image. The terminal 118 may be used as the data input unit 126.

  FIG. 2 shows a top view of a wafer to be inspected. On the wafer, a large number of chips formed so as to have the same circuit pattern are arranged in a lattice pattern. Each chip can be designated by a row and column number as shown in FIG. A chip 30 shown in FIG. 3 is an enlargement of one of the many chips shown in FIG. The observation position 31 is specified by chip coordinates having an origin at the lower left of the chip, for example. Wafer coordinates, which are the positions of the observation position 31 on the wafer, are determined from the chip row and column numbers and the chip coordinates. The observation position in the chip 30 is not limited to one point, and a plurality of points formed to have the same pattern in the chip may be used. Also, points formed so as to have different patterns in the chip may be designated, and the designated points corresponding to each chip may be observed. FIG. 4 shows a captured image at the observation position 31 in FIG. 3, and represents a vertical line and space. FIG. 4 is an example of a captured image, and the pattern to be captured is not limited to this. Thereafter, the image of the same chip coordinate of different chips on the same wafer is taken and inspected, or the image of the same chip coordinate of a plurality of predetermined chips is taken across the plurality of wafers and inspected. Is called fixed point observation or fixed point inspection.

  FIG. 5 is a diagram showing an outline of defect area extraction processing required when performing inspection by image processing. A fixed-point observation image 50 obtained by fixed-point observation is a captured image at the fixed-point observation position shown in FIG. However, a defect 54 has occurred at the fixed point observation position in FIG. 5, and the fixed point observation image 50 shows a state in which the defect 54 is captured. Extraction of the defect area in the fixed point observation image 50 is performed by, for example, a difference process with respect to the reference image 51 not including the defect. A defect area image 52 is generated by binarizing the image subjected to the difference processing with an appropriate threshold value, and a defect area 53 is obtained. The defect is quantified using the image feature of the area on the fixed point observation image 50 corresponding to the defect area 53.

  Next, the fixed point observation flow will be described with reference to FIGS. First, the wafer 108 is loaded on the stage 116 of the SEM apparatus main body 10 and the wafer coordinate and the coordinate system of the stage 116 are associated with each other using the alignment mark on the wafer (S600). Next, in response to an input from the user terminal 118, the chip coordinates of the fixed point observation position and the chip for performing the fixed point observation are specified (S601). Thereafter, necessary input is performed via the user terminal 118. Note that the order of step S600 and step S601 may be reversed. Next, a reference image is designated (S602). The reference image is specified by further specifying a reference chip from the specified chips, positioning the stage 116 so that the fixed point observation position of the reference chip becomes the imaging target region 109, and It is executed by taking an image. The reference image is stored in the memory 114 or the secondary storage device 117, and is reused when the difference process for extracting the defective area shown in FIG. 5 is executed. When there are a plurality of fixed point observation positions in one chip, a reference image may be set for each point, or a reference image may be set by grouping for each shape of a circuit pattern to be imaged. Can be set as appropriate. Thereafter, S603 to S607 are performed for each chip designated in S601, and this is repeated until the last designated chip. First, the stage 116 is positioned so that the fixed point observation position of the designated chip becomes the imaging target area 109 (S603). Subsequently, the fixed point observation image 50 is captured and stored in the memory 114 (S604). In the defect area extraction processing (S605), the fixed point observation image 50 stored in the memory 114 and the reference image 51 stored in the memory 114 or the secondary storage device 117 are used to perform difference processing between both images in the image processing unit. 115. The defective area image 52 obtained as a result of the difference process is stored in the memory 114. Next, using the defect area 53 obtained from the defect area image 52, the image feature of the area on the fixed point observation image 50 corresponding to the defect area 53 is calculated by the image processing unit 115, and the defect is quantified (S606). ). Subsequently, if there is a chip for the next fixed point observation, the process returns to S603 (S607). If there is no chip for the next fixed point observation, the wafer is unloaded from the stage 116 of the SEM apparatus 10 (S608). Note that step S608 may be skipped and the subsequent processing may be performed while the wafer is held in the apparatus. Finally, the defect quantitative value calculated at each fixed point observation position is output to the user terminal 118 and the process ends (S609). Here, the output method is fixed point observation for the wafer and chip diagram shown in FIG. 2 for each fixed point observation position in the chip or for each group of fixed point observation positions having the same circuit pattern shape in the chip. It is conceivable to display a figure called a wafer map that displays the defect quantitative value of the chip that has been subjected to pseudo color according to the value, or to display a histogram for the defect quantitative value. The flow in FIG. 6 is based on the premise that an image of a predetermined chip coordinate of a different chip on the same wafer is captured and inspected, but in addition, a predetermined chip coordinate of a predetermined chip is determined. Images may be taken and inspected over a plurality of wafers. In this case, for each fixed point observation position in the chip, or for each group of fixed point observation positions having the same circuit pattern shape in the chip, a transition diagram of defect quantitative values over a plurality of wafers of the same chip is shown, or It is conceivable to show a transition diagram of defect quantitative values over a plurality of wafers of chips included in an arbitrary region of the wafer, or to simultaneously display the above-described wafer map over a plurality of wafers. The display content may be stored in the memory 114 or the secondary storage device 117 so that it can be reproduced later.

  By the way, there are cases in which it is difficult to obtain a good chip with no defects in a process condition setting state in the early stage of semiconductor development or the like. FIG. 7 is a diagram schematically showing a state in which images are taken at fixed point observation positions in N chips. The non-defective product does not exist in any place, the defect does not occur uniquely, and the appearance position and the appearance of the generated defect such as the black defect 70 and the white defect 71 change depending on the place. Since there is no non-defective chip, a reference image cannot be obtained from one place for one pattern.

As described above, when the reference image cannot be obtained by one imaging, the reference image is generated using images captured at a plurality of locations.
FIG. 8 shows a procedure for creating a reference image by capturing images at a plurality of fixed point observation positions for one circuit pattern shape.
First, a circuit design image is input (S800). FIG. 9 shows a circuit design image corresponding to the fixed point observation image shown in FIG. 7 as an example. The circuit design image is an image for identifying a layer such as a wiring or a ground, and the correspondence between the image coordinates on the circuit design image and the layer can be known. The circuit design image may be generated from the design data of the circuit design, may be generated from a line drawing representing the circuit design by manual input based on the fixed point observation image, or one or more fixed point observation images are added to the image Then, a line drawing representing a circuit design may be generated by image processing such as extracting a circuit pattern edge after binarization with an appropriate threshold value. As a method for inputting a line drawing representing a circuit design by manual input based on a fixed point observation image, the fixed point observation image is displayed on the display of the computer terminal 118 in FIG. 1, and the edge position of the circuit pattern on the image is displayed on the screen. There is a method of creating a line drawing by pointing with a pointer. In addition to tracing the edge position of the circuit pattern with the pointer, an efficient method is also conceivable in which the pointer is pointed and input if the edge of the circuit pattern is a straight line.

  Next, the stage 116 of FIG. 1 is positioned so that the fixed point observation position of the first chip (N = 1) becomes the imaging target region 109 of FIG. 1, and a fixed point observation image is captured (S801, S802). . Here, since there is no normal averaged image in the case of the first chip, the process proceeds to step S804 described later. If there is an already generated averaged image in the second and subsequent chips (N ≧ 2), the averaged image is updated after alignment with the fixed point observation image (S803). Here, the averaged image is an averaged image obtained by adding pixel values for each pixel in a simple case. In addition to this, for each identical pixel of a plurality of captured images, a method for obtaining the median value of the pixel values, and for each identical pixel of the plurality of captured images, a standard deviation of the pixel values is obtained and an average value is excluded except for an exceptional value. It is possible to create it using a method for obtaining the value as appropriate. In addition, when the average image which can be used with the wafer which passed through the same kind or the same process has already been produced | generated, you may progress to step S803 from the first chip | tip using the said averaged image.

  Subsequently, in step S804, the standard deviation value (variation) of the pixel value of the averaged image is calculated for each region indicated by each layer indicated in the circuit design image, and the threshold determined for each layer in step S805. The value is compared with the calculated standard deviation value. If the standard deviation value is within the threshold value in all the layers, the process is terminated (S807). Otherwise, the next chip image is further captured, and from step S802. Step S805 is repeated.

As described above, FIG. 8 shows a flow of sequentially capturing fixed point observation images for generating a reference image. However, first, all or a plurality of fixed point observation images are captured, and then an image for generating a reference image is selected. May be. The processing procedure will be described with reference to FIGS.
First, the chip coordinates of the fixed point observation position and the chip for performing the fixed point observation are specified (S1001). These designations are made from the user terminal 118. Next, the wafer 108 is loaded onto the stage 116 of the SEM apparatus main body 10, and the wafer coordinate and the coordinate system of the stage 116 are associated with each other using the alignment mark on the wafer (S1002). The order of step S1000 and step S1001 may be reversed. Thereafter, S1003 to S1005 are repeated for the chip specified in S1001.

  First, the stage 116 is positioned so that the fixed point observation position of the designated chip becomes the imaging target area 109 (S1003). Subsequently, the fixed point observation image 50 is captured and stored in the memory 114 (S1004). If there is still a chip for fixed point observation, the process returns to S1003 (S1005). If there is no chip for the next fixed point observation, the wafer is unloaded from the stage 116 of the SEM apparatus 10 (S1006). Step S1006 may be skipped and subsequent processing may be performed while the wafer is held in the apparatus.

  Next, in step 1007, one or a plurality of images for generating a reference image is selected from the plurality of captured fixed point observation images, and a reference image is generated and stored in the memory 114 in step S1008. A method for selecting a fixed point observation image and a method for generating a reference image using the selected fixed point observation image will be described later with reference to FIGS. After generating the reference image, the image processing unit 115 executes difference processing between both images using all the fixed point observation images stored in the memory 114 and the reference image stored in the memory 114. A defective area image obtained as a result of the difference processing is stored in the memory 114. Next, using the defect area obtained from the defect area image, the image feature of the area on the fixed point observation image corresponding to the defect area is calculated by the image processing unit 115, and the defect is quantified (S1009). Finally, the defect quantitative value calculated at each fixed point observation position is output to the user terminal 118 and the process ends (S1010). The output method is as described above.

  FIG. 11 is a diagram showing a first screen configuration for selecting from the fixed point observation images obtained by capturing all the fixed point observation images and then capturing the image for generating the reference image. Reference numeral 1100 denotes a screen. An area 1101 displays a captured fixed point observation image. When all the captured fixed point observation images cannot be displayed at once, all necessary fixed point observation images can be browsed by scrolling only within 1101 by means not shown or switching the screen. . Among a plurality of fixed point observation images displayed in 1101, an image surrounded by a thick line indicates a fixed point observation image that is instructed to be used for generating an averaged image, and is instructed when the operator clicks on the selected image. The A circuit design image 1102 corresponding to the fixed point observation image may be generated from the circuit design data, may be manually input by the operator based on the fixed point observation image, or may be an image based on the fixed point observation image. It may be generated by processing. Reference numeral 1102 can be used to confirm what layer region the fixed-point observation image is processed in order to generate a reference image. Reference numeral 1103 denotes an averaged image generated from one or more fixed-point observation images selected within 1101. Reference numeral 1104 denotes a numerical display area for displaying the standard deviation of the averaged image of each layer and the threshold value determined for each layer.

  FIG. 12 shows a flow for generating a reference image using the screen shown in FIG. First, a circuit design image is input (S1200), and a fixed point observation image is selected from a plurality of fixed point observation images stored in the memory 114 (S1202). Subsequently, if there is an already generated averaged image, the averaged image is updated after alignment with the captured image (S1203). If there is no already generated averaged image (N = 1), the process proceeds to step S1204 without passing through step S1203. In step S1204, the standard deviation value of the pixel value of the averaged image is calculated for each area indicated by each layer indicated in the circuit design image. In step S1205, the averaged image is displayed on 1103 in FIG. The standard deviation of the averaged image and the threshold value determined in each layer are displayed in 1104 of FIG. 11 (S1206). The operator uses the averaged image displayed in 1103 and the standardized image of the averaged image of each layer displayed in 1104 and the averaged image generated with reference to the threshold value defined in each layer as the reference image. Whether or not to end the process is determined (S1207). Further, when the fixed point observation image is additionally selected, the process returns to step S1202, and steps S1202 to S1207 are repeated. In step S1202, simultaneously with the selection of the fixed point observation image, the selected fixed point observation image can be excluded from the selection target so that the optimum fixed point observation image for generating an appropriate reference image can be selected. To do. If the operator determines in step S1207 that the average image or the standard deviation of the average image of each layer and the threshold value defined in each layer are appropriate, the process proceeds to step S1209 and is generated. The averaged image is used as a reference image, and the process ends (S1210).

  Next, a second screen configuration example for selecting all the fixed point observation images from the fixed point observation images obtained by capturing the images for generating the reference image will be described with reference to FIG. Reference numeral 1301 displayed on the screen 1300 is an area for displaying a captured fixed point observation image. When all the captured fixed point observation images cannot be displayed at once, all the fixed point observation images can be browsed by scrolling only within 1301 by means not shown. Of the fixed-point observation images displayed in 1301, the image indicated by the bold line is a fixed-point observation image that is instructed to be used for generating an averaged image, and is indicated by clicking on the selected image by the operator. Is done. A circuit design image 1303 corresponding to the fixed point observation image may be generated from the circuit design data, may be manually input by the operator based on the fixed point observation image, or may be an image based on the fixed point observation image. It may be generated by processing. 1303 can be used for confirming what layer region the fixed-point observation image is processed in order to generate an averaged image. Reference numeral 1304 denotes an averaged image generated from one or more fixed-point observation images selected from a plurality of fixed-point observation images in 1301. Reference numeral 1302 denotes an area for displaying an image indicating a result of extracting the defect area using the fixed point observation image displayed on the 1301 and the averaged image, and the images displayed at the same positions 1301 and 1302 correspond to each other. . The information described in step S609 in FIG. 6 is output to the wafer map indicated by 1305. Reference numeral 1306 denotes a numerical display area for displaying the standard deviation of the averaged image of each layer and the threshold value determined for each layer.

  FIG. 14 shows a flow for generating a reference image using the screen shown in FIG. First, a circuit design image is input (S1400), and a fixed point observation image is selected (S1402). Subsequently, if there is an already generated averaged image, the averaged image is updated after alignment with the captured image (S1403). If there is no already generated averaged image (N = 1), the process proceeds to step S1404 without passing through step S1403. In step S1404, the standard deviation value of the pixel value of the averaged image is calculated for each area indicated by each layer indicated in the circuit design image. In step S1405, the averaged image is displayed in 1304 of FIG. The standard deviation of the averaged image and the threshold value determined in each layer are displayed in 1306 of FIG. 13 (S1406). Further, a defect area image is generated from each fixed point observation image using the averaged image and displayed on 1302 (S1407). The operator displays the averaged image displayed in 1304, the relationship between the standard deviation of the averaged image of each layer displayed in 1306 and the threshold value determined in each layer, or the defective area image displayed in 1302. It is determined whether or not the averaged image generated for reference is used as a reference image (S1408). If a fixed point observation image is additionally selected, the process returns to step S1402, and steps S1402 to S1408 are repeated. In step S1402, the selected fixed point observation image can be excluded from the selection target simultaneously with the selection of the fixed point observation image, so that the optimum fixed point observation image for generating an appropriate reference image can be selected. To do. In step S1408, if the operator determines that the averaged image or the standard deviation of the averaged image of each layer and the threshold value defined in each layer, or the defect area image is appropriate, step S1408 Proceeding to S1410, the generated averaged image is set as a reference image, and the process is terminated (S1411). According to the reference image generation method based on the screen configuration shown in FIG. 13, since the defect area image based on the generated reference image can be sequentially confirmed, the processing in the fixed point observation image is further intuitively compared by comparing the defect and the defect area image. At the same time, the wafer map cannot be created unless the reference image is determined, and the wafer map is also updated sequentially, so that the outline of the defect occurrence status can be known quickly.

  Finally, the threshold value shown in S805 of FIG. 8 will be described. As for the threshold value, a fixed value may be set in advance for each layer, or a method of automatically determining from a captured image may be used. An example of a method for automatically determining the threshold value from the captured image will be described below. First, a grid for subdividing the image is set. The grid is not uniformly applied to the image, but is set for each layer, and the size of the grid is adjusted so that no grid crosses the layers. Here, it is assumed that there are N fixed-point observation images that have already been captured, and there are M lattices belonging to a certain layer, and the following description will focus on one layer. The standard deviation value of the pixel value in the lattice is calculated for each of N fixed-point observation images for M lattices. As a result, N × M standard deviation values are obtained. Here, the maximum value A (%) considered as the ratio of the normal part to the area of the layer of interest can be input and set from the computer terminal 118 of FIG. 1, for example, and the obtained N × M The standard deviation values are arranged in ascending order, and the ((N × M) × A / 100) standard deviation value (rounded down to the nearest decimal point) from the beginning is set as the threshold value in the equal layer. As a result, the threshold value TH for the standard deviation value for determination as the reference image can be obtained. According to this method, it is possible to generate an averaged image of each lattice by selecting one having N standard deviation values or less from the N lattice images in each lattice.

  According to the method described above, it is possible to generate a reference image for executing a comparative inspection even in a state where a non-defective chip at the initial stage of semiconductor development cannot be obtained. As a result, it is possible to grasp the occurrence state of defects by performing a highly sensitive comparative inspection, and it is possible to speed up the process condition determination.

DESCRIPTION OF SYMBOLS 10 ... SEM apparatus main body, 100 ... Electron beam, 101 ... Electron source, 102 ... Electron lens, 103 ... Electron lens, 104 ... Electron beam axis adjuster, 105 ... Deflector, 106 ... Deflector, 107 ... Objective lens, 108 DESCRIPTION OF SYMBOLS ... Wafer, 109 ... Imaging area, 110 ... Reflector, 110 '... Primary electron beam passage hole, 111 ... Electron detector, 112 ... A / D converter, 113 ... Adder circuit, 114 ... Memory, 115 ... Image processing unit 116 ... XY stage, 117 ... secondary storage device, 118 ... computer terminal, 119 ... overall control system, 120 ... current amount control unit, 121 ... deflection control unit, 122 ... electronic lens control unit, 123 ... stage control unit, 124: Sequence control unit, 125 ... Data conversion unit, 126 ... Data input unit, 127 ... Image signal Science, 30 ... chip, 31 ... observation position, 50 ... fixed point observation image, 51 ... reference image, 52 ... defect region image, 53 ... defect region, 1100 ... screen, 1101 ... fixed point observation image display region, 1102 ... circuit design image DESCRIPTION OF SYMBOLS 1103 ... Averaged image 1104 ... Numerical display area 1300 ... Screen, 1301 ... Fixed point observation image display area, 1302 ... Defect area image display area, 1303 ... Circuit design image, 1304 ... Averaged image, 1305 ... Wafer map, 1306 ... Numerical value display area

Claims (12)

An appearance inspection method for inspecting the appearance of a semiconductor wafer on which a plurality of chips are formed,
Imaging an observation position of a corresponding pattern formed to be the same for each of the plurality of chips;
Generating an averaged image using the imaged captured image;
Comparing the averaged image with information representing a circuit design corresponding to the captured image, and selecting a reference image that satisfies a predetermined condition;
Comparing and inspecting the reference image and the captured image;
Have
In the step of selecting the reference image, as the predetermined condition, in the averaged image
Variations in the values of the pixels belonging to each circuit pattern area of each layer
An appearance inspection method characterized by determining whether or not a threshold value is less than or equal to a threshold value provided in a road pattern . An appearance inspection method according to claim 1,
The visual inspection method, wherein in the step of imaging the observation position, a plurality of observation positions are imaged for each chip. An appearance inspection method according to claim 1 or 2,
In the step of selecting the reference image, an appearance inspection method using an image of the circuit design as information representing the circuit design is used. An appearance inspection method according to claim 1 or 2,
In the step of selecting the reference image, the circuit design information, the line pattern of the circuit pattern input based on the captured image, or the captured image is extracted as information representing the circuit design. One of the circuit pattern line drawings generated from the edge of the circuit pattern is used. An appearance inspection method according to claim 1 or 2,
A step of displaying the plurality of captured images on the screen;
Selecting a captured image used for generation of the averaged image from a plurality of captured images displayed on the screen;
A visual inspection method characterized by comprising: An appearance inspection method according to claim 5,
And displaying a defect area image generated by comparing the reference image and the captured image;
A visual inspection method characterized by comprising: An appearance inspection method according to claim 1,
In the step of imaging the observation position, it is necessary before the step of generating the averaged image.
Take all the images
Further, in the step of selecting the reference image, each ray is set to determine the threshold value.
A step of inputting a ratio of the normal portion to the area of the ya,
A visual inspection method characterized by comprising: The visual inspection method according to claim 7,
A step of displaying the plurality of captured images on the screen;
Select a captured image used to generate the averaged image from a plurality of captured images displayed on the screen
And steps to
A visual inspection method characterized by comprising: The visual inspection method according to claim 8,
Further, a defect area image generated by comparing the reference image and the captured image is displayed.
Tep,
A visual inspection method characterized by comprising: A plurality of chips formed on a semiconductor wafer are formed to be identical to each other.
Means for imaging the observed position of the corresponding pattern,
Means for comparing the captured image with a reference image;
Input means for inputting information representing a circuit design corresponding to the captured image;
A data transformation that converts data so that information representing the circuit design is compared with the captured image.
A visual inspection apparatus having a replacement means,
Means for generating an averaged image using the imaged captured image;
The averaged image is compared with information representing a circuit design corresponding to the captured image, and a predetermined condition is compared.
Means for selecting an image satisfying the condition as the reference image;
Have
  Appearance characterized in that, in the averaged image, it is determined whether or not variation in values of pixels belonging to each circuit pattern region of each layer is equal to or less than a threshold value provided for each circuit pattern of each layer Inspection device. The appearance inspection apparatus according to claim 10,
And a display means for displaying the plurality of captured images on the screen,
Select a captured image used to generate the averaged image from a plurality of captured images displayed on the screen
Means to
An appearance inspection apparatus characterized by comprising: An appearance inspection apparatus according to claim 11,
The display means further includes a defect area generated by comparing the reference image and the captured image.
A semiconductor wafer appearance inspection apparatus characterized by displaying a region image.

Images