JP5327883B2 - Gate circuit and laser drive circuit - Google Patents

Description

  The present invention relates to a gate circuit that controls passage / blocking of a burst data signal or the like used for optical communication according to the logic of a control signal, and a laser driving circuit including the gate circuit.

  When the transmission of burst data is turned ON / OFF by a control signal as in a burst transmitter, a so-called gate circuit that cuts off the transmission even when the burst data signal continues to be input is generally used. A gate logic circuit is a general term for circuits that output one logic for a plurality of input logics, but in the case of burst control, AND logic is often used. In other words, when the control signal is high, the gate circuit has the logic level of the data signal as it appears at the output terminal, but when the control signal is low, the data signal and the logic level of the data signal are the same regardless of whether the logic level of the data signal is high or low. The output logic level is fixed at the low level by the logical product of the control signal and the low level.

  Such a gate circuit is often used in, for example, a burst type laser driving circuit as shown in FIG. In this laser drive circuit, a laser element LD in which inductors L1 and L2 for high frequency cut are connected to an anode side terminal LDA and a cathode side terminal LDK, a differential burst data signal DATA is inputted, and the burst data is inputted to the laser element LD. A modulation circuit 10 that outputs a modulation signal corresponding to DATA, a bias circuit 20 that supplies a bias current to the laser element LD, an output light of the laser element LD is monitored, and a control voltage VCSM is supplied to the modulation circuit 10 and a bias circuit 20 includes an APC (Automatic Power Control) circuit 30 that supplies a control voltage VCSB to 20. The transmission enable signal TX_EN is input to the modulation circuit 10, the bias circuit 20, and the APC circuit 30 as the control signal. In the transmission enable signal TX_EN, High indicates enable (burst ON: laser emission), and Low indicates non-enable (burst OFF: laser extinction).

  The modulation circuit 10 gates the input burst data signal DATA according to the High / Low level of the transmission enable signal TX_EN, n-stage predrive circuits 121 to 12n for amplification, and an output that functions as a drive circuit. The buffer circuit 13 is configured. The gate circuit 11, the pre-drive circuits 121 to 12n, and the output buffer circuit 13 include current source circuits I11, I121 to 12n, and I13, respectively, and each of the current source circuits I121 to 12n and I13 is output from the APC circuit 30. The extinction ratio of the laser element LD is controlled to be constant by the control voltage VCSM. The current source circuit (not shown) of the bias circuit 20 is also controlled by the control voltage VCSB output from the APC circuit 30 so that the output optical power of the laser element LD becomes constant.

  The data signal is transmitted to the n-stage pre-drive circuits 121 to 12 n via the gate circuit 11. The gate circuit 11 is switched to one of the data signal passing mode and the low level fixed mode (data signal cutoff mode) by receiving the transmission enable signal TX_EN. When the burst is OFF, generally, when the transmission enable signal TX_EN is Low, the output level of the output buffer circuit 13 is fixed to Low level by fixing the output level of the gate circuit 11 itself to Low.

  FIG. 10 shows the configuration of the output buffer circuit 13. This output buffer circuit 13 comprises transistors Q1 to Q3 and resistors R1 to R5, and differential laser drive signals (signals corresponding to the burst data signal DATA) ISPB and ISPN are input to the bases of the transistors Q1 and Q2. The control voltage VCSM is input to the base of Q3.

  Thus, when the output buffer circuit 13 has a differential circuit configuration and the laser element LD is DC-connected, the laser drive signal ISPB is set to Low, the input terminal ISNB is set to High, and the potential of the cathode terminal LDK of the laser element LD is set to By fixing the potential of the anode terminal LDA so that VLDK> VLDA, the oscillation of the laser element LD is stopped, and a current flows from the VDDLD power source for the laser element LD to the laser driving circuit 10 via the laser element LD. To prevent this. In addition, the laser element LD can be extinguished together with controlling the bias circuit 20 so that no bias current flows to the laser element LD.

  It is considered that the gate circuit 11 providing such a function can be realized by application of a current adding circuit. FIG. 11 shows details of a typical current adding circuit 11A (see, for example, Patent Document 1). 111 and 112 are first and second buffer circuits (or amplifier circuits), and 113 is an emitter follower circuit. The first buffer circuit 111 includes transistors Q4 to Q6, resistors R6 to R8, and load resistors RL01 and RL02. The second buffer circuit 112 includes transistors Q7 to Q8, resistors R9 to R11, and load resistors RL01 and RL02. Composed. The emitter follower circuit 113 includes transistors Q10 to Q13 and resistors R12 and R13. The first and second buffer circuits 111 and 112 are connected in parallel by sharing the load resistors RL01 and RL02. Of these two buffer circuits 111 and 112, a DC level signal is input to the input side of the first buffer circuit 112 so that the output side of the second buffer circuit 112 is low. The operation current of the first buffer circuit 111 is turned off by turning on the operation current of the second buffer circuit 112, and the operation current of the first buffer circuit 111 is turned off in the low fixed mode. What is necessary is just to control so that an electric current may turn ON.

JP 2000-261257 A

  It is apparent from the operation principle that the conventional gate circuit using the current adding circuit 11A described in FIG. That is, since it is necessary to share the load resistance, the current flowing through the buffer circuit 111 and the current flowing through the buffer circuit 112 in FIG. 11 need to be the same. This is because the output amplitude of the differential buffer circuit is determined by the value of the load resistance and the amount of current flowing through the load resistance. Specifically, in FIG. 11, at least the current control resistors R8 and R11 have the same value, and the base voltages of the current control transistors Q6 and Q9 need to be the same. As a result, it is desirable that the first and second buffer circuits 111 and 112 are composed of elements of the same size.

  If there is no such restriction, it is desirable that the second buffer circuit 112 that only fixes the potential and does not require high-frequency operation can reduce the size, that is, the amount of current. The merit that the size of the second buffer circuit 112 can be reduced is that the output capacity load of the buffer circuit is reduced and the power consumption is reduced.

  Therefore, in the prior art, it has been desirable to arrange the gate circuit 11 at the input end of the modulation circuit 10 of the laser drive circuit. In the case of a first-stage buffer that may have a small driving capability, the above-described restrictions are not a problem. However, ideally, it is desirable that the gate circuit 11 be disposed immediately before the output buffer circuit 13. This is because in the conventional configuration as shown in FIG. 9, when the transmission enable signal TX_EN is in the OFF state, if the current of the pre-drive circuits 121 to 12n is cut off to save power, the output logic level of the gate circuit 11 is This is because, since the signal is not transmitted to the output buffer circuit 13, the extinction of the laser element LD cannot be ensured unless the current of the output buffer circuit 13 is completely cut off. If the gate circuit 11 can be disposed immediately before the output buffer circuit 13, not only can the currents of the predrive circuits 121 to 12n be interrupted during extinction, but the laser element LD can emit light even if the current of the output buffer circuit 13 is ambiguously interrupted. Can be prevented.

  However, disposing the gate circuit 11 immediately before the output buffer circuit 13 is nothing other than that the gate circuit 11 itself needs to have a corresponding driving capability. Since the drive capability of the buffer circuit 13 is basically determined by the amount of current, in the conventional technique, two large buffer circuits are arranged as shown in FIG. 11, which is extremely inefficient.

  The present invention has been made in view of the above points, and an object thereof is to realize a gate circuit capable of reducing power consumption when the output level is fixed and a laser driving circuit including the gate circuit while having high driving capability and high-speed operation capability. It is to be.

To achieve the above object, a gate circuit according to a first aspect of the present invention is connected to a first power supply terminal in a gate circuit that passes / cuts off a signal such as a burst data signal according to the logic of a control signal. A first buffer circuit having a first load resistor and a first current source circuit, for inputting an output signal of the preceding circuit, and a second load connected to the output side of the first buffer circuit; A second buffer circuit having a resistor and a second current source circuit, wherein a sum of the first load resistor and the second load resistor becomes a combined load resistor, and an output signal is extracted from the combined load resistor The first and second current source circuits are configured such that one of the first and second current source circuits is turned off when the operation is on, and the other is turned off when the first current source circuit is on. Outputs the output signal of the buffer circuit Characterized in that the second current source circuit outputs an output signal which is fixed to the logic level to a predetermined time of operation ON.
According to a second aspect of the present invention, in the gate circuit according to the first aspect, the value of the second load resistance is set larger than the value of the first load resistance, and the first current source circuit The current value is set larger than the current value of the second current source circuit.
According to a third aspect of the present invention, in the gate circuit according to the first or second aspect, a capacitor is connected in parallel with the second load resistor.
According to a fourth aspect of the present invention, in the gate circuit according to the first, second, or third aspect, a fixed voltage is applied as an input signal of the second buffer circuit.
According to a fifth aspect of the present invention, in the gate circuit according to the first, second, third, or fourth aspect, each of the first and second current source circuits is a first connected in series to a second power supply terminal. A transistor, a first resistor, a second transistor connected between a control terminal and a bias voltage terminal of the first transistor, a control terminal of the first transistor, and a second power supply terminal A third transistor having a polarity opposite to that of the second transistor connected in series and a second resistor, and control terminals of the second and third transistors of the first current source circuit; The control signal is applied to the control terminals of the second and third transistors of the second current source circuit in an inverted relationship with respect to each other.
According to a sixth aspect of the present invention, in the gate circuit according to the first, second, third, fourth, or fifth aspect, an emitter follower circuit is connected to an output side of the second buffer circuit.
According to a seventh aspect of the present invention, there is provided a laser driving circuit comprising: a pre-drive circuit that amplifies a burst data signal is connected to a front stage of the gate circuit according to the first, second, third, fourth, fifth, or sixth aspect; And a modulation circuit to which an output buffer circuit for driving is connected, and the control signal is a transmission enable signal.
According to an eighth aspect of the present invention, in the laser driving circuit according to the seventh aspect, when the transmission enable signal indicates burst data OFF, the first buffer circuit is turned off and the second buffer circuit is turned on. The output signal of the gate circuit is fixed at the low level, the output of the output buffer circuit is fixed at the low level, and the output buffer circuit is output regardless of whether or not the burst data signal is output from the pre-drive circuit. The output signal is fixed at a low level.

  According to the gate circuit of the present invention, the contribution to the realization of the power saving mode of the burst type laser driving circuit is remarkable. The power saving mode is a technique for suppressing power consumption of the laser driving circuit during a period in which the laser element is extinguished. The ultimate power saving mode technology in the PON system is a technology that can increase and decrease the power consumption at high speed in conjunction with the transmission enable signal. However, in the method of completely interrupting the circuit current of the laser driving circuit that requires a large amount of current and then recovering it, an extremely long transition time is required for recovery.

  Therefore, the burst response of the laser drive circuit by the transmission enable signal can be improved by cutting off the current of the pre-drive circuit group and the output buffer circuit in a mild but not perfect manner. However, in the prior art, if the circuit current is not cut off but reduced, the gate function does not act on the output buffer circuit, so that it is difficult to ensure laser quenching. The present invention is a technology that can fundamentally solve such a dilemma. It is possible to design the circuit current in the power saving mode with an emphasis on burst response, or to design with an emphasis on the power reduction amount in the power saving mode.

  If the technology of the present invention is used, circuit design necessary for such power saving for each burst communication can be facilitated, and safe and effective power saving can be realized. In addition, even when applied to a laser drive circuit with a conventional structure that does not have a power saving mode function, the predrive function and gate function can be compactly combined into a single gate circuit, reducing the circuit scale and reducing power consumption. Can contribute.

  The gate circuit of the present invention is not limited to a laser driving circuit. The present invention can be applied as a drive circuit that requires a gate function or an intermediate buffer circuit that requires a gate function.

It is a block diagram which shows the basic composition of the gate circuit in this invention. It is a circuit diagram of the gate circuit of the 1st example of the present invention. 1 is a block diagram of a burst type laser driving circuit to which a gate circuit according to a first embodiment of the present invention is applied. FIG. FIG. 4 is a characteristic diagram in which a transient analysis simulation is performed on the laser drive circuit of FIG. 3. FIG. 5 is a characteristic diagram comparing the conventional structure and the present invention regarding the laser current eye pattern from the transient analysis simulation result in FIG. 4. It is a circuit diagram of the gate circuit of the 2nd Example of this invention. It is the figure which compared the 1st Example of this invention with the 2nd Example about the eye pattern of the laser current by circuit simulation. It is a block diagram of the laser drive circuit which constructed | assembled the power saving structure further using the gate circuit of this invention. It is a block diagram of a typical burst type laser drive circuit. 1 is a circuit diagram of a typical output buffer circuit. It is a circuit diagram of the current addition circuit by a prior art.

  A basic configuration of the gate circuit 14 of the present invention that also functions as a pre-drive circuit will be described with reference to FIG. The gate circuit 14 includes a first buffer circuit 141, a second buffer 142, and an emitter follower circuit 123. A load resistor RL1 is connected between the output side of the first buffer circuit 141 and the power supply terminal VCC, and a load is connected between the output side of the first buffer circuit 141 and the output side of the second buffer 142. Resistor RL2 is inserted. The first and second buffer circuits 141 and 142 include independent current source circuits IS1 and IS2, respectively. When the current source circuit IS1 of the first buffer circuit 141 is turned on by the transmission enable signal TX_EN. Are controlled by the switches SW1 and SW2 so that the current source circuit IS2 of the second buffer circuit 142 is turned off. A bias data VL is inputted to the input side of the first buffer circuit 141 so that the burst data signal from the previous stage circuit is inputted and the output level of the second buffer circuit 142 is fixed to the input side of the second buffer 142. Is entered.

  When the switch SW1 is ON, that is, the current of the current source circuit IS1 flows and the switch SW2 is OFF, that is, the current of the current source circuit IS2 does not flow, the first buffer circuit 141 is in an operation ON state. The value of the load resistance of the first buffer circuit 141 is the value of the load resistance RL1. On the contrary, when the switch SW1 is OFF and the switch SW2 is ON, the second buffer circuit 142 is in an operation ON state, and the value of the load resistance of the second buffer circuit 142 is the sum of the load resistances RL1 and RL2. Become.

  Since the amplitudes of the outputs of the first and second buffer circuits 141 and 142 are determined by the product of the load resistance and the buffer circuit current, the current of the current source circuit IS2 of the second buffer circuit 142 that increases the load resistance is Even if the current is smaller than the current of the current source circuit IS1 of the first buffer circuit 141, the same amplitude level can be secured. Of course, the DC level is the same in the first buffer circuit 141 and the second buffer circuit 142.

  For example, if the values of the load resistors RL1 and RL2 are RL1 and RL2, the currents of the current source circuits IS1 and IS2 are IS1 and IS2, and RL2 / RL1 = 3, then IS2 / IS1 = 1/4. The circuit scale and current consumption of the second buffer circuit 142 can be greatly reduced. If the outputs of the first and second buffer circuits 141 and 142 are buffered by the emitter follower 143, the impedance of the first and second buffer circuits 141 and 142 can be increased, so that the value of the load resistance RL2 is relatively large. However, the output amplitude does not decrease (because the current flowing through RL2 is small).

  By replacing the pre-drive circuit 12n in the previous stage of the output buffer circuit 13 in the conventional laser driving circuit described with reference to FIG. 9 with the gate circuit 14 of the present invention, the conventional input stage gate circuit 11 becomes unnecessary. By reducing the overall circuit scale, it is possible to arrange the gate circuit in the previous stage of the ideal output buffer circuit 13.

<First embodiment>
A first embodiment of the gate circuit of the present invention will be described with reference to FIG. Since the gate circuit 14 of this embodiment is an improvement over the current adding circuit 11A described with reference to FIG. 11, the same elements as those in FIG. The gate circuit 14 includes a first buffer circuit 141, a second buffer circuit 142, and an emitter follower circuit 143. The first buffer circuit 141 includes transistors Q4 to Q6, CMOS transistors M1 and M2, resistors R6 to R8 and R14, and load resistors RL1 and RL3. The second buffer circuit 142 includes transistors Q7 to Q9, CMOS transistors M3 and M4, resistors R9 to R11, R15 to R19, and load resistors RL2 and RL4. The emitter follower circuit 143 includes transistors Q10 to Q13 and resistors R12 to R13. INV1 and INV2 are inverters.

  The basic configuration of the first and second buffer circuits 141 and 142 is a typical differential amplifier circuit, and load resistors RL1 and RL2 and RL3 and RL4 are connected in series. The input side of the second buffer circuit 142 is fixed by voltages V1 and V2 generated by a resistance dividing circuit including resistors 15 to R18. If the resistance dividing circuit is designed so that V2> V1, the potential of the differential output terminal OUTP is fixed to Low when the second buffer circuit 142 is turned on.

  The current source circuits of the first and second buffer circuits 141 and 142 are provided with switch circuits composed of CMOS transistors M1 and M2 and M3 and M4, respectively. An operation in the first buffer circuit 141 will be described as an example. The transmission enable TX_EN is set to High for the data passing mode and Low for the output level fixed mode. The transmission enable signal TX_EN at the CMOS logic level is inverted by the inverter INV1 and input to the gate terminals of the CMOS transistors M1 and M2 as GATAINP.

  When the transmission enable TX_EN is High, the transistor M1 is turned on and the transistor M2 is turned off. Therefore, the current source control voltage VCS is applied to the base voltage of the current source transistor Q6, and the first buffer circuit 141 is turned on. . Therefore, the data signals input to the differential input terminals IPB and INB are buffered by the first buffer circuit 141 and output to the output terminals OUTP and OUTN via the emitter follower circuit 143.

  At this time, in the current source circuit of the second buffer circuit 142, since the voltage level of the output GATEINN of the inverter INV2 becomes High, the transistor M3 is turned off, the transistor M4 is turned on, and the base terminal of the current source transistor Q9 is turned on. It is grounded, the current is cut off, and the operation is turned off.

  As described above, when the transmission enable signal TX_EN is High, the resistors RL1 and RL3 are load resistors of the first buffer circuit 141 of the present embodiment. The output terminals OPA1 and ONA2 of the first buffer circuit 141 are connected to the emitter follower 143 via the load resistors RL2 and RL4.

  On the other hand, when the transmission enable signal TX_EN is Low, the first buffer circuit 141 is turned off and the second buffer circuit 142 is turned on, contrary to the above state. At this time, it should be noted that the load resistance of the second buffer circuit 142 is “RL1 + RL2” or “RL3 + RL4”. As the load resistance increases, the second buffer circuit 142 can obtain the same output amplitude as that of the first buffer circuit 141 even when the current is smaller than that of the first buffer circuit 141.

  FIG. 3 is a block diagram when the gate circuit 14 according to the first embodiment is applied to the modulation circuit 10 of the laser driving circuit. The gate circuit 14 of the present invention is arranged in the preceding stage of the output buffer circuit 13 of the modulation circuit 10 and receives the output of the pre-drive circuit 121n-1 arranged in the preceding stage of the gate circuit 14. Here, the gate circuit 14 also functions as the conventional final stage pre-drive circuit 12n.

  FIG. 4 is an example of a circuit simulation result simulating the operation at a bit rate of 10 Gbps in the configuration of FIG. The conventional structure shown in (a) is an example in which the load resistances RL2 and RL4 are simulated as 0 (Ω). In this simulation, the current ratio of the first buffer circuit 141 and the second buffer circuit 142 is 4: 1. A section in which GATEINP is High and GATEINN is Low is a burst OFF section.

In the conventional structure shown in (a), since the potential fixing capability of the second buffer circuit 142 is insufficient, complete low level fixing is not realized, and the output terminal LDA of the output buffer circuit 13 of the modulation circuit 10 and LDK potential level becomes a forward direction (VLDK <VLDA) to the laser diode LD, as a result, current _{I LD} of the laser diode LD is continued 10mA about flow, it can be seen that not completely cut off.

On the other hand, in the first embodiment of the present invention shown in (b), the potential level of the output terminal OUTP of the gate circuit 14 can be sufficiently fixed at the low level during the burst OFF period. It can be seen that the level of the output terminal is maintained reversely connected (LDK> LDA) to the laser element LD. Therefore, it can be seen that the current I _LD is sufficiently cut off.

  FIG. 5 is an example in which the eye pattern waveform in the period of 10 ps to 150 ps in the simulation is compared between the conventional structure shown in FIG. 5A and the first embodiment of the present invention shown in FIG. In the present invention, since the output of the first buffer circuit 141 is connected to the emitter follower circuit 143 via the load resistors RL2 and RL4, these resistors and the output terminal capacitance of the second buffer circuit 142 are parasitic. A low-pass filter is formed. For this reason, the band is slightly reduced as compared with the conventional structure. As shown in FIG. 5, it can be seen that the rising and falling (Tr / Tf) of the eye pattern are slightly deteriorated in the present invention as compared with the conventional structure.

<Second embodiment>
The problems of the present invention as described above can be alleviated by the second embodiment shown in FIG. In this embodiment, speed-up capacitors CS1 and CS2 are connected in parallel with the load resistors RL2 and RL4, respectively. The purpose of the second buffer circuit 142 is to fix the potential level of the output terminal OUTP to Low. Therefore, it is sufficient that the load resistance of the second buffer circuit 142 has a DC value. On the other hand, for the first buffer circuit 141, the load resistors RL2 and RL4 cause waveform deterioration during high-frequency operation. Therefore, by connecting the capacitor CS1, the impedance Z (Ω) between the terminals OPA1 and OPA2 during high-frequency operation is such that the resistance value of the load resistor RL2 is R (Ω) and the capacitance value of the capacitor CS1 is C (F). Then
Z = R / (2πfCR + 1) (1)
It becomes. Here, f is an operating frequency (Hz). For example, assuming that the bit rate of 10 Gbps is 5 GHz, and R = 70Ω and C = 3pF, Z = about 9.2Ω. That is, this corresponds to the impedance being reduced to about 1/7 at high frequencies.

  This effect can be recognized remarkably even in the eye pattern waveform shown in FIG. In the transient characteristics in the second embodiment shown in FIG. 4 (a), there is almost no difference from the transient analysis simulation result in the first embodiment shown in FIG. However, when compared with the eye pattern waveform, it can be seen that Tr / Tf is improved (faster) in the waveform of the present embodiment than in the first embodiment. This indicates that the load on the first buffer circuit 141 is reduced by the action of the speed-up capacitors CS1 and CS2. By such a device, the gate circuit 14 having a gate function can be realized with low power consumption while maintaining a driving capability close to that of the conventional structure.

<Third embodiment>
A third embodiment of the present invention will be described with reference to FIG. In this embodiment, the gate circuit 14 described in the first and second embodiments is applied as a pre-drive circuit with a gate function of the modulation circuit 10 of the burst type laser drive circuit. For example, the output buffer circuit 13 may be a typical buffer circuit as shown in FIG. 10, but the APC circuit 30 includes single-pole double-throw switches SW3 and SW4 at the current control terminals (VCSM and VCSB) for transmission. The power consumption is reduced by ON / OFF controlling the currents of the current source circuits I121, I122, I12n-1, and I13 in conjunction with the enable signal TX_EN. The same applies to the current source circuit of the bias circuit 20. However, as described in FIG. 1, the current source I14 (IS1, IS2) of the gate circuit 14 as a pre-drive circuit with a gate function is linked to the transmission enable signal TX_EN, and one of the current source circuits IS1, IS2 The operation is turned on, and the other is turned off.

  In the configuration of FIG. 8, the current source control terminal is grounded via the pull-down resistors RPD1 and RPD2 in order to cut off the current of the current source circuit. However, in the present invention, the laser element is not required to be completely pulled down to the ground level. The LD can be quenched. In other words, it is possible to switch to a voltage that does not cut off the current but sufficiently reduces the current. This is because the stop of the modulation drive is governed not by the “stop” due to the current interruption of the pre-drive circuits 121 to 12n-1 and the output buffer circuit 13, but by the level fixing by the gate circuit 14. In other words, since the gate circuit 14 is arranged immediately before the output buffer circuit 13, the input terminal of the output buffer circuit 13 is always fixed at the low level when the burst is OFF, so that the output signals of the predrive circuits 121 to 12n-1 Is interrupted by the gate circuit 14, and the output terminal of the output buffer circuit 13 does not have a potential relationship in the forward direction with respect to the laser element LD.

<Other examples>
In the above embodiment, the description has been made on the assumption that the circuit is a BiCMOS device. However, it is needless to say that the present invention can be applied to a bipolar circuit or a circuit based on a CMOS process. In the above embodiment, a description has been given on the assumption that a positive voltage power supply is used, VCC is used as the first power supply terminal, and VEE is grounded as the second power supply terminal. It is sufficient that one power supply terminal has a higher potential. A negative voltage power supply can also be configured without detracting from the spirit of the present invention.

10: modulation circuit, 11: gate circuit, 11A: current addition circuit, 121 to 12n: pre-drive circuit, 13: output buffer circuit, 14: gate circuit 111: first buffer circuit, 112: second buffer circuit, 113: Emitter follower circuit 141: First buffer circuit 142: Second buffer circuit 143: Emitter follower circuit 20: Bias circuit 30: APC circuit

Claims (8)

In a gate circuit that passes / cuts off a signal such as a burst data signal according to the logic of the control signal,
A first buffer circuit having a first load resistor connected to the first power supply terminal and a first current source circuit, for inputting an output signal of the preceding circuit, and an output of the first buffer circuit A second load resistor connected to the side and a second current source circuit, and the sum of the first load resistor and the second load resistor becomes a combined load resistor, and output from the combined load resistor A second buffer circuit from which a signal is extracted, and the first and second current source circuits are turned off when one is turned on by the logic level of the control signal,
When the first current source circuit is in operation ON, the output signal of the first buffer circuit is output, and when the second current source circuit is in operation ON, an output signal fixed at a predetermined logic level is output. A gate circuit characterized by output. The gate circuit according to claim 1,
The value of the second load resistance is set larger than the value of the first load resistance, and the current value of the first current source circuit is set larger than the value of the current of the second current source circuit. A gate circuit characterized by setting. The gate circuit according to claim 1 or 2,
A gate circuit comprising a capacitor connected in parallel with the second load resistor. The gate circuit according to claim 1, 2 or 3,
A gate circuit, wherein a fixed voltage is applied as an input signal of the second buffer circuit. The gate circuit according to claim 1, 2, 3 or 4,
The first and second current source circuits respectively include a first transistor and a first resistor connected in series to a second power supply terminal, and a control terminal and a bias voltage terminal of the first transistor. A second transistor connected to the second transistor, a third transistor having a polarity opposite to that of the second transistor connected in series between the control terminal of the first transistor and the second power supply terminal, and a second transistor With resistance,
The control signal has a logic level at the control terminals of the second and third transistors of the first current source circuit and the control terminals of the second and third transistors of the second current source circuit. Are applied in an inverted relationship with each other. The gate circuit according to claim 1, 2, 3, 4 or 5,
An emitter follower circuit is connected to an output side of the second buffer circuit.   7. A modulation circuit in which a pre-drive circuit for amplifying a burst data signal is connected to the preceding stage of the gate circuit according to claim 1, and an output buffer circuit for driving a laser element is connected to the subsequent stage. And the control signal is a transmission enable signal. The laser drive circuit according to claim 7,
When the transmission enable signal indicates burst data OFF, the first buffer circuit is turned off, the second buffer circuit is turned on, and the output signal of the gate circuit is fixed at the low level, and the output buffer An output of the circuit is fixed at a low level, and an output signal of the output buffer circuit is fixed at a low level regardless of whether or not a burst data signal is output from the pre-drive circuit.

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