JP5321377B2 - Power semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for electric power which has a high-speed switching function, and can solve a problem that during switching, a displacement current flows and a high voltage is generated by resistance of a displacement current path, thereby a breakdown of a thin insulating film such as a gate insulating film and an insulation breakdown of the semiconductor device are occurred by the voltage. <P>SOLUTION: The semiconductor device can reduce a resistance between a first well region and a source pad in a part where a shape of a boundary of a first well region is concave and decrease a voltage generated resulting from displacement current during switching, because well contact hole per unit length for peripheral boundary of the first well region in a part where a shape of a boundary of a second conductive type first well region formed on a part of a surface of a first conductive type drift layer formed on a first main surface of a first conductive type semiconductor substrate is concave are arranged more than that in a part where a shape of boundary of the first well region is linear as viewed from above. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a power semiconductor device such as a silicon carbide semiconductor device.

  A power semiconductor device including a power vertical metal-oxide-semiconductor field-effect transistor (MOSFET) and a diode described in Patent Document 1 are shown in FIGS. 1 and 2 of the same document. As shown in FIG. 2, diodes are arranged in at least one row in the peripheral portion of the cell region of the MOSFET, that is, in the region adjacent to the gate pad portion. Each of these diodes is injected during forward bias into the N-type semiconductor layer on the drain side from the P well and P base shown in FIG. 2 when the MOSFET switches from the on state to the off state. Absorbs holes. For this reason, the above-mentioned structure of the same document can prevent the parasitic transistor shown in FIG. 3 of the same document from being turned on when the MOSFET is switched from the forward bias to the reverse bias.

  Here, in the structure of the same document, as shown in FIG. 2, the P base, which is the P well of the MOSFET, is electrically connected to the source electrode through the back gate.

JP-A-5-198816 (FIGS. 1 to 3)

  The problem to be solved by the present invention will be described below with reference to FIG.

When the MOSFET of the power semiconductor device described in Patent Document 1 is switched from the on state to the off state, the drain voltage of the MOSFET, that is, the voltage of the drain electrode rises rapidly, and in some cases reaches about several hundred volts. May reach. Due to the rise of the drain voltage, displacement currents are generated on the drain electrode side and the source electrode side via the depletion layer capacitance formed between the P well and the N ⁻ drain layer in the off state. This displacement current is generated not only in the P well of the MOSFET but also in the diode if the P-type region is provided in the N ⁻ drain layer like the P well or the P well.

The displacement current generated in this way flows to the drain electrode as it is generated on the drain electrode side, but the displacement current generated on the source electrode side flows to the source electrode via the P-well or P-type region. .
In the case of a power semiconductor device as shown in Patent Document 1, the source electrode and the field plate are electrically connected as described in the description of the conventional example. In the cross section shown, the displacement current that has flowed into the P well under the gate pad flows in the P well under the gate pad from the MOSFET cell direction toward the contact hole connected to the field plate, and passes through the field plate. Flows into the source electrode.

Here, the area of the P well under the gate pad is very large with respect to the area of the P well of the MOSFET cell and the P well of the diode cell. Since the well itself and the contact hole have a resistance with a certain large resistance value, a voltage of a value that cannot be ignored is generated in the P well. As a result, at a position in the P well where the distance in the plane direction is large from a place (contact hole) where the P well is electrically connected to the source electrode (usually connected to the ground potential) via the field plate. A large potential will be generated.
This potential increases as the displacement current increases, and increases as the fluctuation dV / dt of the drain voltage V with respect to time t increases.

  Here, it will be described again that the silicon carbide MOSFET is driven at high speed, that is, driven at high dV / dt.

  A conventional Si-MOSFET that is a unipolar element using Si (silicon) is operated at a relatively high speed of 20 V / nsec or more as an operation speed, but when operated at a high voltage of about 1 kV or higher. Since the conduction loss becomes very large, the operating voltage is limited to several tens to several hundreds volts. For this reason, an Si-IGBT (Insulated Gate Bipolar Transistor) has been used exclusively in a high voltage region of about 1 kV or higher. However, since the IGBT is a bipolar element, it is difficult to obtain high-speed switching characteristics like a unipolar element due to the influence of minority carriers. That is, since switching loss cannot be greatly reduced even if dV / dt is increased, it is not necessary to drive at high dV / dt, and it is used at an operating speed of about several V / nsec at most.

  On the other hand, a MOSFET using silicon carbide can obtain a low conduction loss even in a high voltage region of 1 kV or higher, and can operate at high speed because it is a unipolar element. Since it can reduce, the loss at the time of inverter operation | movement can be reduced further.

  In such an operating environment that is not possible with a conventional Si element, such as high-speed switching of 10 V / nsec or more in an operation of a high voltage region of 1 kV or higher, the displacement is generated in the P-well by the switching current as described above. The voltage becomes more prominent.

  Further, when such a MOSFET is formed using silicon carbide, an element having a sufficiently shallow p-type impurity level does not exist in the band gap of silicon carbide, so that p-type carbonization having a low resistivity near room temperature. Silicon cannot be obtained, and the contact resistance between the p-type silicon carbide and the metal also increases. Therefore, when a MOSFET power semiconductor device is configured using silicon carbide, the value of the contact resistance between the P-well composed of p-type silicon carbide and this metal is increased, and the voltage generated by the displacement current is also increased. Become.

  In a power semiconductor device including such a MOSFET, the voltage of the gate electrode is changed immediately after switching the MOSFET from the on state to the off state at a location where the gate insulating film of the MOSFET is sandwiched between the P well and the gate electrode. When the voltage is close to 0 V, a high voltage is generated in the P-well as described above, and the gate insulating film may be destroyed by a high electric field due to the high voltage. In order to obtain a highly reliable power semiconductor device, it is desirable that the electric field applied to the silicon dioxide film, which is a gate insulating film, be 3 MV / cm or less. The voltage had to be below a certain value.

  The present invention was made to solve such a problem, and in a power semiconductor device including a MOSFET that switches at high speed, the occurrence of dielectric breakdown between the gate electrode and the source electrode during switching can be suppressed. It is an object to provide a highly reliable power semiconductor device.

A power semiconductor device according to the present invention is formed on a part of a surface layer of a first conductivity type semiconductor substrate, a first conductivity type drift layer formed on a first main surface of the semiconductor substrate, and the drift layer. The second conductivity type first well region, the second conductivity type JTE region connected to the first well region, and a part of the surface layer of the drift layer are provided apart from the first well region. A second conductivity type second well region having a smaller area as viewed from above the first well region; a first conductivity type source region formed in a part of a surface layer of the second well region;
A gate insulating film formed on the surfaces of the first well region and the second well region;
A field oxide film having a thickness larger than that of the gate insulating film formed on a part of the surface of the first well region, and an upper portion on the opposite side of the drift layer in contact with the gate insulating film and the field oxide film A gate electrode having a portion sandwiching the gate insulating film between the first well region, a source contact hole provided on the second well region and the source region, and the first well region. A portion provided through the gate insulating film in the upper part of the peripheral portion of the well region, the boundary of the first well region being concave when viewed from above, and the boundary of which is linear when viewed from above more, the are many disposed per unit length of the boundary around the first well region, and the well contact hole having the same area, the source contact hole and the Werukonta A source pad electrically connecting the first well region and the second well region via a hole, a gate pad electrically connected to the gate electrode, and a second main surface of the semiconductor substrate; And a provided drain electrode.

  According to the power semiconductor device of the present invention, even when the power semiconductor device is driven at a high speed, it is possible to suppress the breakdown of the gate insulating film without applying a large strength electric field to the gate insulating film, thereby further improving reliability. A high power semiconductor device can be provided.

1 is a plan view schematically showing a power semiconductor device according to a first embodiment of the present invention. 1 is a plan view schematically showing a power semiconductor device according to a first embodiment of the present invention. 1 is a plan view schematically showing a part of a power semiconductor device according to a first embodiment of the present invention. 1 is a plan view schematically showing a part of a power semiconductor device according to a first embodiment of the present invention. 1 is a plan view schematically showing a part of a power semiconductor device according to a first embodiment of the present invention. It is sectional drawing which represents typically a part of power semiconductor device in Embodiment 1 of this invention. 1 is a plan view schematically showing a power semiconductor device according to a first embodiment of the present invention. It is sectional drawing which represents typically a part of power semiconductor device in Embodiment 1 of this invention. It is a top view which represents typically a part of power semiconductor device in Embodiment 2 of this invention. It is a top view which represents typically a part of power semiconductor device in Embodiment 2 of this invention. It is a top view which represents typically a part of power semiconductor device in Embodiment 3 of this invention. It is a top view which represents typically a part of power semiconductor device in Embodiment 3 of this invention. It is a top view which represents typically a part of power semiconductor device in Embodiment 3 of this invention. It is sectional drawing which represents typically a part of power semiconductor device in Embodiment 3 of this invention. It is a top view which represents typically a part of power semiconductor device in Embodiment 3 of this invention. It is sectional drawing which represents typically a part of power semiconductor device in Embodiment 3 of this invention. It is a top view which represents typically a part of power semiconductor device in Embodiment 3 of this invention. It is sectional drawing which represents typically a part of power semiconductor device in Embodiment 3 of this invention. It is a top view which represents typically a part of power semiconductor device in Embodiment 4 of this invention. It is a top view which represents typically a part of power semiconductor device in Embodiment 4 of this invention. It is a top view which represents typically a part of power semiconductor device in Embodiment 4 of this invention.

Embodiment 1 FIG.
In the first embodiment of the present invention, a description will be given using an example in which a vertical n-type channel silicon carbide MOSFET is mainly used as an example of the power semiconductor device 100. Also, the first conductivity type will be described as n-type, and the second conductivity type will be described as p-type.

  FIG. 1 is a plan view schematically showing the power semiconductor device 100 according to the first embodiment of the present invention from above. In FIG. 1, a source pad 10 is provided at the center of the upper surface of the power semiconductor device 100. A gate pad 11 is provided on one side viewed from the upper surface of the source pad 10. A gate wiring 12 is provided so as to extend from the gate pad 11 and surround the source pad 10. A gap is provided between the source pad 10 and the gate pad 11 and the gate wiring 12 so as not to short-circuit each other.

  A silicon carbide layer is provided below the source pad 10, the gate pad 11, and the gate wiring 12. A p-type first well region 41 is formed on the silicon carbide layer outside the gate pad 11 and the gate wiring 12. A p-type junction termination extension (JTE) region 40 is provided on the outer side.

  Here, the source pad 10 is electrically connected to the source electrode of a MOSFET unit cell provided in a large number under the source pad 10, and the gate pad 11 is electrically connected to the gate electrode of the unit cell. A gate voltage connected and supplied from an external control circuit is applied to the gate electrode.

  FIG. 2 is a plan view of a silicon carbide layer below layers such as source pad 10 and gate pad 11 of power semiconductor device 100 shown in FIG. 1 as viewed from above. In FIG. 2, a hole called a well contact hole 60 is formed in an interlayer insulating film (not shown) provided on the entire lower surface of the source pad 10 around the lower portion of the source pad 10 shown in FIG. A cell region 14 in which a large number of the unit cells are provided is provided on the inner side surrounded by the well contact hole 60 in a plan view. In FIG. 2, the arrangement of the well contact holes 60 is an example for illustrating the outline, and the detailed arrangement of the well contact holes 60 in the present embodiment is a convex shape when the cell region 14 is viewed from the top, as described later. In particular, a large number of well contact holes 60 are arranged in corner portions (such as C1 to C6 in FIG. 2) where the shape of the boundary of the first well region 41 is concave.

FIG. 3 is a plan view for explaining the vicinity of the connecting portion between the gate pad 11 and the gate wiring 12 in FIG. 1, and is an enlarged view of the vicinity of the corner portion C1 in FIGS. 4 and 5 are plan views schematically showing the configuration of the lower layer portion of the source pad 10 and the gate pad 11 in FIG. Furthermore, FIG. 6 shows a cross-sectional view schematically showing a cross section of the AA ′ portion shown in FIGS.
The power semiconductor device 100 according to the present embodiment will be described in detail with reference to FIGS.

  In FIG. 3, the source pad 10 is formed on the side of the gate wiring 12 extending from the gate pad 11 with an interval. In FIG. 4, gate electrodes 21 and 22 are provided on almost the entire surface with an interlayer insulating film (not shown) between the gate pad 11 and the gate wiring 12 shown in FIG. Gate contact holes 31 that are portions from which the insulating film has been removed are provided discretely.

  An interlayer insulating film (not shown) is formed on almost the entire surface in a portion corresponding to the lower portion of the source pad 10 in FIG. 4, and a well contact hole 60 which is a portion where the interlayer insulating film is removed is formed in a portion corresponding to the outer periphery of the source pad 10. Are provided discretely. Further, source contact holes 61 are provided discretely in the interlayer insulating film in the region described as the cell region 14 in FIG. 2 inside the region where the well contact holes 60 are provided discretely. A gate electrode 23 is formed in a lattice form below the interlayer insulating film in a portion where the well contact hole 60 and the source contact hole 61 corresponding to the lower portion of the source pad 10 are not provided. And connected to the gate electrodes 21 and 22 below the gate wiring 12. A field oxide film (not shown) is provided below the gate electrodes 21 and 22 in most of the regions below the gate pad 11 and the gate wiring 12, and interlayer insulation below the most regions of the source pad 10 is provided. A gate insulating film (not shown) having a thickness smaller than that of the field oxide film is provided below the film or the gate electrode 23. A boundary (gate insulating film field oxide film boundary 30) between the gate insulating film and the field oxide film is shown by a dotted line in FIG.

  FIG. 5 is a plan view for explaining a region mainly composed of a silicon carbide layer below the gate insulating film and the field oxide film, at a portion corresponding to FIGS. 3 and 4. As shown in FIG. 5, a p-type first well region 41 made of silicon carbide is provided from the region below the field oxide film below the gate pad 11 to the region beyond the well contact hole 60 in the planar direction. It has been. Further, the source contact hole 61 has a p-type second well region 42 at the center of each source contact hole 61 and n so as to surround the second well region 42 on a plane. A p-type second well region 42 is provided on the outer periphery of the source region 80 of the type. The center and outer peripheral second well regions 42 are connected at the bottom of the source region 80. In addition, between the second well regions 42 with respect to the adjacent source contact holes 61, an n-type drift layer made of silicon carbide is formed.

  Here, in a corner portion where the cell region 14 has a convex shape when viewed from the top, such as a connection portion between the gate pad 11 and the gate wiring 12, that is, when the first well region 41 has a concave shape when viewed from the top. Compared to other locations where the boundary between the cell region 14 and the first well region 41 is linear, the well per unit length of the outer periphery of the cell region 14, that is, the boundary around the first well region Many contact holes 60 are arranged. In FIG. 5, the well contact holes 60 are arranged in a single manner except for the corner portion, whereas the well contact holes 60 are arranged in a double manner in the corner portion.

Next, the structure demonstrated in FIGS. 3-5 is demonstrated from FIG. 6 from a cross-sectional direction.
In FIG. 6, drift layer 70 made of n-type silicon carbide is formed on the surface of substrate 20 made of n-type and low-resistance silicon carbide. A first well region 41 made of p-type silicon carbide is provided in the surface layer portion of the drift layer 70 in a region substantially corresponding to the region where the gate pad 11 (gate wiring 12) is provided.
Further, in the region centering on the surface layer portion of the drift layer 70 below the region where the source contact hole 61 is provided, the center portion of each region is made of silicon carbide at the center portion. A p-type second well region 42 is surrounded by a low-resistance n-type source region 80 made of silicon carbide so as to surround the second well region 42. The second well region 42 is provided.

A gate insulating film 32 made of silicon dioxide is formed on the upper portion of the silicon carbide layer substantially corresponding to the region where source pad 10 is provided. A field oxide film 33 made of silicon dioxide is formed on the silicon carbide layer in the region corresponding to the gate pad 11 and the gate wiring 12 other than the region where the gate insulating film 32 is formed. . A gate electrode 21 is provided on a part of the upper portion of the field oxide film 33.
A gate electrode 23 is provided on the gate insulating film 32 where the second well region 42 is in contact with the gate insulating film 32, and is electrically connected to the gate electrode 21 provided on the field oxide film 33. Has been.

An interlayer insulating film 35 made of silicon dioxide is formed over most of the gate insulating film 32, the field oxide film 33, and the gate electrodes 21, 22, and 23, and is provided through the interlayer insulating film 35. The second well region 42, the source region 80 and the source pad 10 are electrically connected through the ohmic electrode 63 by the source contact hole 61. Further, the first well region 41 and the source pad 10 are electrically connected via the ohmic electrode 64 by the well contact hole 60 provided through the interlayer insulating film 35 and the like. Further, the gate electrode 21 and the gate pad 11 are electrically connected by a gate contact hole 31 provided through the interlayer insulating film 35.
A drain electrode 13 is formed on the back side of the substrate 20 via a back side ohmic electrode 65.

  Here, the p-type first well region 41 connected to the source pad 10 through the ohmic electrode 63 in the well contact hole 60 and the drain electrode 13 through the substrate 20 and the back surface ohmic electrode 65 are connected. A diode is formed between the n-type drift layer 70 and the n-type drift layer 70. In the vertical MOSFET, the region (channel region) in contact with the gate insulating film 32 in the p-type second well region 42 between the n-type source region 80 and the n-type drift layer 70 is electrically connected. It can be controlled by the voltage of the gate electrode 23 on the gate insulating film 32. In the power semiconductor device of the present embodiment, a diode is connected in parallel between the source and drain of the MOSFET.

Next, a method for manufacturing the power semiconductor device 100 of the present embodiment will be described.
First, 1 × 10 ¹³ cm ⁻³ to 1 × 10 ¹⁸ is formed on the surface (first main surface) of the n-type low-resistance silicon carbide substrate 20 by a chemical vapor deposition (CVD) method. A drift layer 70 made of silicon carbide having an n-type impurity concentration of cm ⁻³ and a thickness of 4 to 200 μm is epitaxially grown. Subsequently, the p-type first well region 41, the p-type second well region 42, the p-type JTE region 40, and the n-type source region 80 are formed at predetermined positions on the surface of the drift layer 70 by ion implantation. Form. Al (aluminum) or B (boron) is suitable as the p-type impurity for ion implantation, and N (nitrogen) or P (phosphorus) is suitable as the n-type impurity for ion implantation. As the substrate 20 of silicon carbide semiconductor, a substrate whose first principal plane has a (0001) plane and has a 4H polytype and is tilted to 8 ° or less with respect to the c-axis direction is used. The plane orientation, polytype, and tilt angle may be used.

The depth of each of the first well region 41 and the second well region 42 needs to be set so as not to be deeper than the bottom surface of the drift layer 70 which is an epitaxial crystal growth layer. For example, the depth is in the range of 0.5 to 2 μm. Value. In addition, the p-type impurity concentration of each of the first well region 41 and the second well region 42 is higher than the impurity concentration of the drift layer 70 that is an epitaxial crystal growth layer, and is 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 6. It is set within the range of ¹⁹ cm ⁻³ .
The depth of the source region 80 is set so that its bottom surface does not exceed the bottom surface of the second well region 42, its n-type impurity concentration is higher than the p-type impurity concentration of the second well region 42, and 1 It is set within the range of × 10 ¹⁷ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ .
However, only in the vicinity of the outermost surface of drift layer 70, the p-type impurity concentration of each of first well region 41 and second well region 42 is different from drift layer 70 in order to increase the conductivity in the channel region of silicon carbide MOSFET. The n-type impurity concentration may be lower.

  Subsequently, annealing is performed in an inert gas atmosphere such as argon (Ar) gas or nitrogen gas, or in vacuum, in a temperature range of 1500 to 2200 ° C. and for a time in a range of 0.5 to 60 minutes, and ion implantation is performed. The activated impurities are electrically activated.

Next, a thermal oxide film is formed by sacrificing the surface of the drift layer 70 ion-implanted as described above, and the thermal oxide film is removed by hydrofluoric acid to thereby form the ion-implanted drift layer 70. The surface alteration layer is removed to expose a clean surface. Subsequently, an active region centered on the cell region 14 is opened by using a CVD method, a photolithography technique, or the like, and a film thickness called a field oxide film 33 is 0.5 to 2 μm in a region other than the cell region 14. A silicon dioxide film of a degree is formed. A gate insulating film 32 composed of a silicon dioxide film having a thickness of about 1/10 of that of the field oxide film 33 is formed in the active region centering on the cell region 14 by thermal oxidation or deposition.
The thickness of the gate insulating film 32 may be 30 nm or more and 300 nm or less, and more preferably 50 nm or more and 150 nm or less. This film thickness value depends on how much gate voltage and gate electric field drive (switching operation) the MOSFET, and preferably has a gate electric field of 3 MV / cm or less.

Subsequently, gate electrodes 21 to 23 made of a polycrystalline silicon material are formed on the gate insulating film 32 and the field oxide film 33 at predetermined positions using a CVD method, a photolithography technique, or the like. The polycrystalline silicon used for the gate electrodes 21 to 23 preferably contains P or B and has a low resistance. P and B may be introduced during the film formation of the polycrystalline silicon, or may be introduced by an ion implantation method after the film formation. The gate electrodes 21 to 23 may be a multilayer film of polycrystalline silicon and metal, or a multilayer film of polycrystalline silicon and metal silicide.
Note that the outermost end surfaces of the gate electrodes 21 to 23 may be disposed on the field oxide film 33. By doing so, it is possible to prevent the quality deterioration of the gate insulating film 32 exposed at the end face due to the over-etching of the end face by the dry etching process.

Next, an interlayer insulating film 35 made of a silicon dioxide film is formed on the gate electrodes 21 to 23 by a deposition method such as a CVD method. Subsequently, the interlayer insulating film 35 at the portions that become the well contact hole 60 and the source contact hole 61 is removed by using a photolithography technique and a dry etching technique.
Next, heat treatment at a temperature of 600 to 1100 ° C. is performed following the formation of the metal film mainly containing Ni by sputtering or the like, and the metal film mainly containing Ni reacts with the silicon carbide layer to carbonize. Silicide is formed between the silicon layer and the metal film. Subsequently, the metal film remaining on the interlayer insulating film 35 other than the silicide formed by the reaction is removed by wet etching using sulfuric acid, nitric acid, hydrochloric acid, or a mixed solution of these and hydrogen peroxide. .
The silicide formed in the well contact hole 60 and the source contact hole 61 in this way becomes ohmic electrodes 63 and 64 as shown in FIG. 6, and the n-type silicon carbide region such as the source region 80 and the first well. Ohmic connection is made to both p-type silicon carbide regions such as region 41.

Further, the interlayer insulating film 35 at a location that becomes the gate contact hole 31 is removed by using a photolithography technique and a dry etching technique. Subsequently, a back surface ohmic electrode 65 is formed on the back side of the substrate 20 by forming a metal mainly composed of Ni on the back surface (second main surface) of the substrate 20 and performing heat treatment.
Thereafter, a wiring metal such as Al is formed on the surface of the substrate by sputtering or vapor deposition, and processed into a predetermined shape by a photolithography technique, thereby forming the source pad 10, the gate pad 11, and the gate wiring 12. Furthermore, the drain electrode 13 is formed by forming a metal film on the surface of the back ohmic electrode 65 on the back surface of the substrate, and the power semiconductor device 100 whose sectional view is shown in FIG. 6 can be manufactured.

Next, the operation of the power semiconductor device 100 of the present embodiment will be described mainly with reference to FIG. FIG. 7 is a top view shown in FIG. 2 in which the flow of displacement current generated when the MOSFET is switched from the on state to the off state is schematically added with an arrow 15.
In the power semiconductor device 100 of the present invention, as shown in FIG. 7, a pn diode (position of the well contact hole 60 in FIG. 7) is formed around a cell region 14 in which a plurality of unit cells constituting a MOSFET are formed in parallel. Are provided in parallel. Here, the source of the MOSFET (n-type MOSFET in the present embodiment) is a second conductive type (p-type in the present embodiment) of a pn diode, and the MOSFET (n-type MOSFET in the present embodiment). Are integrated with the first conductivity type (in this embodiment, n-type) electrode of the pn diode.

  Now, when the voltage applied to the gate of the MOSFET (the gate pad 11 in this embodiment) is changed so that the MOSFET switches from the on state to the off state, the drain of the MOSFET (the drain in this embodiment) The voltage of the electrode 13) rises rapidly and changes from approximately 0V to several hundred volts. Then, the displacement current is p-type and n-type via the parasitic capacitance generated between the p-type first well region 41, the second well region 42, the JTE region 40, and the n-type drift layer 70, respectively. Flowing in both areas. In the p-type region, a displacement current flows from the p-type first well region 41, the second well region 42, and the like toward the source pad 10.

  This displacement current generates a voltage determined by the resistance value and the displacement current value of the region through which the displacement current flows. However, since the area of the second well region 42 is not large, the resistance value of the region is not large, and the generated voltage Also stays at some value. On the other hand, since the p-type region including the first well region 41 and the JTE region 40 connected to the first well region 41 has a large area, a displacement current generated at a location where the distance from the well contact hole 60 connected to the source pad 10 is large. When the well contact hole 60 flows into the ohmic electrode 64, a large potential voltage is generated.

The displacement current generated when the MOSFET is switched from the on state to the off state is not uniformly generated around the cell region 14, but as shown by the arrow 15 in FIG. Displacement current concentrates at a convex shape, that is, at a portion where the boundary shape of the first well region 41 is a concave shape, that is, at the corner portions C1 to C6 surrounded by a dotted line in FIG.
In addition, since the first well region 41 having a large area exists at a position corresponding to the lower portion of the gate pad 11, the value of the generated displacement current also increases.

  In the power semiconductor device 100 according to the present embodiment, as described in FIG. 5, the upper portion of the boundary of the first well region 41 as shown in C <b> 1 to C <b> 6 in FIG. More well contact holes 60 are arranged per unit length of the boundary around the first well region 41 than where the boundary shape of the first well region 41 is linear as viewed from the first well region 41. The resistance between the source pad 10 and the first well region 41 at the portion where the boundary shape of the region 41 is concave can be reduced as a whole, and the voltage generated by the displacement current flowing during switching can be reduced. .

Therefore, even when the switching speed of the voltage of the gate pad 11 of the MOSFET is switched off at a speed of 10 V / nsec or more, the voltage generated by the displacement current can be reduced, and the electric field induced in the gate insulating film 32 can be reduced. The size can be 3 MV / cm or less. Then, it is possible to suppress the dielectric breakdown of the gate insulating film 32 that is in contact with the first well region 41 and has the gate electrode 21 provided thereon.
As described above, according to the power semiconductor device 100 of the present embodiment of the present invention, even when switching is performed at a high speed, the gate insulating film 32 does not cause an insulation failure, and a highly reliable semiconductor device can be obtained. it can.

In the power semiconductor device 100 of the present embodiment, the contact resistance between the ohmic electrode 64 and the first well region 41 and the contact resistance between the ohmic electrode 63 and the second well region 42 are reduced. Although no special configuration has been provided, another configuration for reducing the contact resistance may be provided. For example, as shown in FIG. 8, in order to reduce the contact resistance between the ohmic electrode 63 and the second well region 42, the p-type impurity concentration is increased in the surface layer of the second well region 42 below the source contact hole 61. A low-resistance well contact region 46 having a p-type impurity concentration of 1 × 10 ²⁰ cm ⁻³ or more, for example, higher than that of the 2-well region 42 may be provided. Further, the surface layer of the first well region 41 below the well contact hole 60 has a lower resistance well contact region having a p-type impurity concentration of 1 × 10 ²⁰ cm ⁻³ or more than that of the first well region 41. 47 may be provided.

  Thus, by providing the p-type well contact regions 46 and 47 with low resistance, the current path from the first well region 41 and the second p well region 42 to the source pad 10 via the ohmic electrodes 63 and 64 is improved. The resistance value can be lowered, and the voltage generated when the displacement current flows can be further reduced.

  In the description of the method for manufacturing power semiconductor device 100 of the present embodiment, the formation of well contact hole 60 and source contact hole 61 and the formation of gate contact hole 31 are performed separately. The source contact hole 61 and the gate contact hole 31 may be formed at the same time. By forming the well contact hole 60 and the source contact hole 61 and the gate contact hole 31 at the same time, the number of steps can be reduced and the manufacturing cost can be reduced.

  Furthermore, in the description of the method for manufacturing power semiconductor device 100 of the present embodiment, the heat treatment for forming ohmic electrodes 63 and 64 on the front surface side and the heat treatment for forming back ohmic electrode 65 on the back surface side are performed separately. However, the surface-side ohmic electrodes 63 and 64 and the back-side back-side ohmic electrode 65 may be formed simultaneously by forming a metal containing Ni as a main component on both the front-side and the back-side. . This also reduces the number of processes and makes it possible to reduce manufacturing costs.

  In the present embodiment, the well contact holes 60 are all arranged with the same area, and the source contact hole 61 and the well contact hole 60 have the same area. By doing in this way, the etching rate in each hole at the time of dry etching for forming the well contact hole 60 and the source contact hole 61 can be made uniform, and the occurrence of contact failure can be suppressed.

In the power semiconductor device 100, the temperature sensor electrode and the current sensor electrode may be formed in part of the power semiconductor device 100. These electrodes may be formed. The presence / absence of the temperature sensor electrode and the current sensor electrode does not affect the effect of the power semiconductor device 100 of the present embodiment.
Furthermore, there may be a wide variety of cases such as the position and number of the gate pads 11 and the shape of the source pad 10, and these are the same as the above-described presence or absence of the current sensor electrode, etc. The effect of the device 100 is not affected at all.

  Although not shown and described, the silicon nitride film is left with openings that allow the source pad 10, gate pad 11, and gate wiring 12 on the upper surface of the power semiconductor device 100 to be connected to an external control circuit. Or a protective film such as polyimide.

  Furthermore, in power semiconductor device 100 of the present embodiment, an example in which doped polycrystalline silicon is used as the material of gate electrodes 21 to 23 has been described. However, the resistance of doped polycrystalline silicon is not sufficiently low. In some cases, the potentials of the gate electrodes 21 to 23 located away from the connection position with the gate pad 11 may be temporally shifted from the potentials of the gate pad 11 and the gate wiring 12. This temporal shift is determined by a time constant determined by a resistance component such as the resistance of the gate electrodes 21 to 23 and a parasitic capacitance formed between the source electrode 10 and the like. In the present embodiment, the low-resistance gate line 12 is provided in parallel to the gate electrode 22 below the gate line 12 to suppress the occurrence of the time lag as described above.

Embodiment 2. FIG.
FIG. 9 is a plan view of a partial cross section in the depth direction of the power semiconductor device 100 according to the second embodiment of the present invention as viewed from above, mainly from the gate insulating film 32 and the field oxide film 33. It is the figure explaining the area | region comprised with a lower silicon carbide layer. In FIG. 9, the cell region 14 has a convex shape when viewed from the top, that is, the first well region 41 has a concave shape when viewed from the top. A feature of the power semiconductor device 100 according to the present embodiment is that a bridging boundary that is a simple side is provided, the angle that intersects the original side is small, and the angle is gentle. Since the other points are the same as those in the first embodiment, detailed description thereof is omitted.

In FIG. 9, the well contact holes 60 are arranged in a single layer except for the corner portion, whereas in the corner portions, the well contact holes 60 are arranged in triple and quadruple, and the cell region 14 and the first region are seen from above. Compared to other portions where the boundary with the first well region 41 is linear, more well contact holes 60 are arranged on the outer periphery of the cell region 14, that is, per unit length of the boundary around the first well region. ing. 9a represents the angle at which a new side (bridging boundary) provided at the corner portion intersects one side of the original two sides with respect to two orthogonal sides of the corner portion. Θa is tan ⁻¹ 1.0 or 45 °.

  According to power semiconductor device 100 of the present embodiment, the displacement current generated in a concentrated manner at the corner portion when switching off can be further dispersed than the power semiconductor device of the first embodiment, and the displacement current flows. Sometimes the generated voltage can be reduced. Therefore, the voltage applied to the gate insulating film 32 at the time of switching can be reduced, and the highly reliable power semiconductor device 100 can be obtained.

Note that the arrangement method of the unit cells in the cell region 14 does not have to be the one shown in FIG. 9 in which square unit cells are arranged in a grid pattern. For example, as shown in FIG. The cells may be arranged alternately. In this case, an angle θb at which a new side provided in the corner portion intersects one of the original two sides with respect to two orthogonal sides of the corner portion is approximately 26.6 ° (tan ⁻¹ 0.5). By arranging in such a way, it is possible to arrange more well contact holes 60 for the first well 41 protruding to the corner portion.
When the unit cell arrangement method is neither as shown in FIG. 9 nor as shown in FIG. 10, a new side provided in the corner portion intersects one side of the original two sides with respect to the two orthogonal sides of the corner portion. The angle θ may be tan ⁻¹ 0.5 or more and tan ⁻¹ 1.0 or less.
Further, when the unit cell is a rectangle, the length of the short side of the unit cell is a, the length of the long side of the unit cell is b, and θ is tan ⁻¹ (b / 2a) or more tan ⁻¹ 1 0.0 or less.

Embodiment 3 FIG.
FIG. 11 is a plan view schematically showing one cross-section in the depth direction of a part of the power semiconductor device 100 according to the third embodiment of the present invention. In FIG. 11, the number per unit length of the boundary around the first well region 41 of the well contact hole 60 arranged around the first well region 41 below the gate pad 11 is below the gate pad 10. The number of well contact holes 60 arranged around the first well region 41 is larger than the number of boundaries per unit length around the first well region 41, and other detailed matters are implemented. Therefore, detailed description thereof is omitted.

  As shown in FIG. 11, according to the power semiconductor device 100 of the present embodiment, the first well region 41 of the well contact hole 60 arranged around the first well region 41 below the gate pad 11. The number per unit length of the surrounding boundary per unit length of the boundary around the first well region 41 of the well contact hole 60 disposed around the first well region 41 other than below the gate pad 10. Therefore, the voltage generated at the time of switching around the first well region 41 below the gate pad 11 having a large area can be reduced.

  Note that, as shown in the plan view of FIG. 12, even if the well contact holes 60 around the first well region 41 below the gate pad 11 are partly arranged in one row and partly in two rows, Similar effects can be achieved.

  Further, as shown in the plan view of FIG. 13, the number of well contact holes 60 in the corner portion is effectively increased by spreading MOSFET unit cells and extending the first well region toward the 41 cell region 14. May be. FIG. 14 is a cross-sectional view of the top view of FIG. 13 viewed from the cross-sectional direction.

  As shown in the plan view of FIG. 15 and the cross-sectional view of FIG. 16, the well contact region 47 below the well contact hole 60 may have a larger area than the well contact region 46 of the unit cell. By doing so, the contact area between the well contact region 47 and the ohmic electrode 64 can be increased. As a result, the contact resistance is lowered and the sheet resistance of the first well region 41 is also reduced. Voltage to be reduced.

Further, as shown in the top view of FIG. 17 and the cross-sectional view of FIG. 18, all well contact regions 47 below the well contact holes 60 may be connected to have a large area. In this way, by increasing the area of the well contact region 47 below the well contact hole 60, the sheet resistance of the first well region 41 is further reduced, so that the ohmic electrode 64 passes from the well contact region 47 to the source pad 10. The resistance of the route to reach can be reduced, and the potential increase due to the displacement current can be reduced.
Further, in the example of FIGS. 17 to 18, the well contact region 47 is formed so that the distance from the edge of the field oxide film 33 (gate insulating film field oxide film boundary 30) is equal, thereby distributing the displacement current. Can be prevented.

Embodiment 4 FIG.
FIG. 19 is a plan view schematically showing one cross section in the depth direction of a part of the power semiconductor device 100 according to the third embodiment of the present invention from the upper surface. In FIG. 19, the area of the well contact hole 60 at the corner is larger than the area of the well contact hole 60 other than the corner and the area of the source contact hole 61. Other detailed matters are the same as those of the first embodiment. Since it is the same, detailed description is abbreviate | omitted.

  In FIG. 19, the first well region 41 is seen around the cell region 14 in which square unit cells are regularly arranged in a lattice shape, and the boundary of the first well region 41 has a concave shape as viewed from above. A well contact hole 60 having a larger area is formed than a portion where the shape of the boundary is linear.

  Also with the power semiconductor device 100 of the present embodiment, the voltage generated when the displacement current flows in the corner portion can be reduced, as in the power semiconductor device 100 of the first to third embodiments. Therefore, the voltage applied to the gate insulating film at the time of switching can be reduced, and the highly reliable power semiconductor device 100 can be obtained.

  If the area of the well contact hole 60 in the corner portion is larger than the area of the source contact hole 61, as shown in FIG. On the other hand, a new side provided in the corner portion may be provided. Further, as shown in FIG. 21, the well contact hole 60 in the corner may be increased several times.

  According to power semiconductor device 100 of the present embodiment, even when the layout is difficult to easily increase the number of well contact holes 60 having the same area, the voltage generated when displacement current flows easily. Can be reduced. Therefore, the voltage applied to the gate insulating film 32 at the time of switching can be reduced, and the highly reliable power semiconductor device 100 can be obtained.

  In the first to fourth embodiments described above, the example of power semiconductor device 100 using a silicon carbide semiconductor has been described. However, this is merely an example, and a power semiconductor composed of another material. Even the device 100 has the same effect.

  In the first to fourth embodiments, the case where the semiconductor element formed in the cell region 14 is a vertical MOSFET is disclosed. For example, the silicon carbide semiconductor substrate 20 shown in FIG. Even if the semiconductor element having the IGBT cell region 14 is configured by providing the collector layer of the second conductivity type between the electrode 65 and the electrode 65, the above-described effects of the present invention can be achieved with respect to the semiconductor element having the IGBT cell region. Is played in the same way. Therefore, the scope of the present invention is a semiconductor element as a switching element having a MOS structure such as MOSFET or IGBT. When the semiconductor element is an IGBT, the drain (electrode) of the MOSFET corresponds to the collector (electrode), and the source (electrode) of the MOSFET corresponds to the emitter (electrode).

  Furthermore, in the present invention, the semiconductor element itself having the MOSFET structure described in the first to fourth embodiments is defined as a “semiconductor device” in a narrow sense. For example, the semiconductor element having the MOSFET structure and the semiconductor Incorporate a semiconductor element such as a freewheel diode connected in antiparallel to the element and an inverter module that is mounted on a lead frame and sealed together with a control circuit that generates and applies the gate voltage of the semiconductor element. The power module itself is also defined as “semiconductor device” in a broad sense.

  10 source pad, 11 gate pad, 12 gate wiring, 13 drain electrode, 14 cell region, 20 substrate, 21, 22, 23 gate electrode, 30, gate insulating film field oxide film boundary, 31 gate contact hole, 32 gate insulating film 33 Field oxide film, 35 Interlayer insulating film, 40 JTE region, 41 First well region, 42 Second well region, 46, 47 Well contact region, 60 Well contact hole, 61 Source contact hole, 63, 64 Ohmic electrode, 65 Back surface ohmic electrode, 70 drift layer, 80 source region, 100 power semiconductor device.

Claims (9)

A first conductivity type semiconductor substrate;
A drift layer of a first conductivity type formed on the first main surface of the semiconductor substrate;
A first well region of a second conductivity type formed in a part of the surface layer of the drift layer;
A second conductivity type JTE region connected to the first well region;
A second well region of a second conductivity type having a smaller area as viewed from above the first well region provided in a part of a surface layer of the drift layer and spaced apart from the first well region;
A first conductivity type source region formed in a part of a surface layer of the second well region;
A gate insulating film formed on the surfaces of the first well region and the second well region;
A field oxide film formed on a part of the surface of the first well region and having a thickness larger than that of the gate insulating film;
A gate electrode formed on the opposite side of the drift layer in contact with the gate insulating film and the field oxide film, and having a portion sandwiching the gate insulating film between the first well region;
A source contact hole provided above the second well region and the source region;
The gate insulating film is provided above the peripheral portion of the first well region, and the boundary is linear when viewed from the top where the first well region has a concave boundary when viewed from the top. A larger number of well contact holes of the same area disposed per unit length of the boundary around the first well region than
A source pad for electrically connecting the first well region and the second well region via the source contact hole and the well contact hole;
A gate pad electrically connected to the gate electrode;
A power semiconductor device comprising: a drain electrode provided on a second main surface of the semiconductor substrate. 2. The power semiconductor device according to claim 1, wherein a portion where the boundary of the first well region is concave when viewed from above has a shape in which a bridging boundary is provided so that the concave shape becomes gentle. . The number of well contact holes per unit length at the boundary of the first well region under the gate pad is larger than the number of well contact holes per unit length at the boundary of the first well region other than the lower portion of the gate pad. The power semiconductor device according to claim 1 or 2.   When the gate pad voltage is switched off at a switching speed of 10 V / nsec or more, the electric field induced in the gate insulating film sandwiched between the first well region and the gate electrode is 3 MV / cm or less. The power semiconductor device according to claim 1, wherein the power semiconductor device is a power semiconductor device. 3. The power semiconductor device according to claim 1, wherein the semiconductor substrate is a silicon carbide semiconductor substrate, and the drift layer is made of a silicon carbide material. The power semiconductor device according to claim 2, wherein an angle formed by the bridge boundary and the boundary is tan ⁻¹ 0.5 or more and tan ⁻¹ 1.0 or less. 2. The power semiconductor device according to claim 1, wherein a well contact region having a lower resistivity than the first well region is provided in a surface layer of the first well region below the well contact hole. 8. The power semiconductor device according to claim 7, wherein an area of the well contact region viewed from the upper surface is larger than an area of the well contact hole viewed from the upper surface. A first conductivity type semiconductor substrate;
A drift layer of a first conductivity type formed on the first main surface of the semiconductor substrate;
A first well region of a second conductivity type formed in a part of the surface layer of the drift layer;
A second conductivity type JTE region connected to the first well region;
A second well region of a second conductivity type having a smaller area as viewed from above the first well region provided in a part of a surface layer of the drift layer and spaced apart from the first well region;
A first conductivity type source region formed in a part of a surface layer of the second well region;
A gate insulating film formed on the surfaces of the first well region and the second well region;
A field oxide film formed on a part of the surface of the first well region and having a thickness larger than that of the gate insulating film;
A gate electrode formed on the opposite side of the drift layer in contact with the gate insulating film and the field oxide film, and having a portion sandwiching the gate insulating film between the first well region;
A source contact hole provided above the second well region and the source region;
The gate insulating film is provided above the peripheral portion of the first well region, and the boundary is linear when viewed from the top where the first well region has a concave boundary when viewed from the top. A plurality of well contact holes arranged with a larger area per area than
A source pad for electrically connecting the first well region and the second well region via the source contact hole and the well contact hole;
A gate pad electrically connected to the gate electrode;
A power semiconductor device comprising: a drain electrode provided on a second main surface of the semiconductor substrate.

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