JP5317898B2 - Method for manufacturing light-emitting diode element - Google Patents

Method for manufacturing light-emitting diode element Download PDF

Info

Publication number
JP5317898B2
JP5317898B2 JP2009208868A JP2009208868A JP5317898B2 JP 5317898 B2 JP5317898 B2 JP 5317898B2 JP 2009208868 A JP2009208868 A JP 2009208868A JP 2009208868 A JP2009208868 A JP 2009208868A JP 5317898 B2 JP5317898 B2 JP 5317898B2
Authority
JP
Japan
Prior art keywords
light emitting
film
electrode film
ito
emitting layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2009208868A
Other languages
Japanese (ja)
Other versions
JP2011060986A (en
Inventor
倉内  利春
松崎  封徳
慶子 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ulvac Inc
Original Assignee
Ulvac Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ulvac Inc filed Critical Ulvac Inc
Priority to JP2009208868A priority Critical patent/JP5317898B2/en
Publication of JP2011060986A publication Critical patent/JP2011060986A/en
Application granted granted Critical
Publication of JP5317898B2 publication Critical patent/JP5317898B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Led Devices (AREA)

Description

本発明は、発光ダイオード素子及び発光ダイオード素子の製造方法に関する。   The present invention relates to a light emitting diode element and a method for manufacturing the light emitting diode element.

図3の符号110は従来の発光ダイオード素子の一例を示している。
発光ダイオード素子110は、発光層119と、透明電極膜116と、反射電極膜117とを有している。発光層119はn型クラッド層113と、活性層114と、p型クラッド層115とを有している。
透明基板111上にバッファ層112と、n型クラッド層113とがこの順に配置され、n型クラッド層113が一部露出するようにして、n型クラッド層113上に活性層114と、p型クラッド層115と、透明電極膜116と、反射電極膜117とがこの順で配置されている。
Reference numeral 110 in FIG. 3 shows an example of a conventional light emitting diode element.
The light emitting diode element 110 includes a light emitting layer 119, a transparent electrode film 116, and a reflective electrode film 117. The light emitting layer 119 includes an n-type cladding layer 113, an active layer 114, and a p-type cladding layer 115.
The buffer layer 112 and the n-type cladding layer 113 are arranged in this order on the transparent substrate 111, and the active layer 114 and the p-type are formed on the n-type cladding layer 113 so that the n-type cladding layer 113 is partially exposed. The clad layer 115, the transparent electrode film 116, and the reflective electrode film 117 are arranged in this order.

n型クラッド層113の一部露出した面上には活性層114と離間して負端子122が配置され、反射電極膜117上には正端子121が配置されている。
不図示の直流電源の正極を正端子121に、負極を負端子122にそれぞれ電気的に接続し、正端子121と負端子122との間に直流電圧を印加して、直流電流を流すと、活性層114は光を放出する。
On the partially exposed surface of the n-type cladding layer 113, a negative terminal 122 is disposed apart from the active layer 114, and a positive terminal 121 is disposed on the reflective electrode film 117.
When a positive electrode of a DC power source (not shown) is electrically connected to the positive terminal 121 and a negative electrode is electrically connected to the negative terminal 122, a DC voltage is applied between the positive terminal 121 and the negative terminal 122, and a DC current flows. The active layer 114 emits light.

活性層114からp型クラッド層115側に放出された光は、透明電極膜116を透過し、反射電極膜117で反射され、透明電極膜116と発光層119とバッファ層112と透明基板111とを順に透過し、外部に放出される。
透明電極膜116としてはITO膜が好んで用いられ、発光層119上に透明電極膜116を成膜する方法としては、発光層119に対するダメージを少なくするために、真空蒸着法が好んで採用されている。
The light emitted from the active layer 114 to the p-type cladding layer 115 side is transmitted through the transparent electrode film 116 and reflected by the reflective electrode film 117, and the transparent electrode film 116, the light emitting layer 119, the buffer layer 112, the transparent substrate 111, and the like. In order and released to the outside.
An ITO film is preferably used as the transparent electrode film 116, and as a method for forming the transparent electrode film 116 on the light emitting layer 119, a vacuum deposition method is preferably employed in order to reduce damage to the light emitting layer 119. ing.

従来、発光ダイオード素子に用いられるITO膜の真空蒸着では、基板を250℃以上の温度に加熱し、かつ0.2nm/s程度の成膜レートで成膜していた。
このような条件で成膜されたITO膜表面の算術平均粗さは約20nm以上であり、発光層から放出された光がITO膜表面と反射電極膜との界面で散乱及び吸収されることにより、発光ダイオード素子の輝度が低下するという問題があった。
この問題を解決するために、特許文献1では交番電磁界を形成してITO材料の蒸気をイオン化する方法が開示されているが、交番電磁界形成手段を備えた真空蒸着装置を新たに用意する必要があり、コスト面で好ましくなかった。
Conventionally, in the vacuum evaporation of an ITO film used for a light emitting diode element, the substrate is heated to a temperature of 250 ° C. or higher and is formed at a film formation rate of about 0.2 nm / s.
The arithmetic average roughness of the ITO film surface formed under such conditions is about 20 nm or more, and the light emitted from the light emitting layer is scattered and absorbed at the interface between the ITO film surface and the reflective electrode film. There is a problem that the luminance of the light emitting diode element is lowered.
In order to solve this problem, Patent Document 1 discloses a method of forming an alternating electromagnetic field and ionizing the vapor of the ITO material. However, a vacuum deposition apparatus having an alternating electromagnetic field forming means is newly prepared. It was necessary and was not preferable in terms of cost.

特開2008−182138号公報JP 2008-182138 A

本発明は上記従来技術の不都合を解決するために創作されたものであり、その目的は、従来の真空蒸着装置を用いて、光の取り出し効率の高い発光ダイオード素子とその製造方法を提供することである。   The present invention was created to solve the above-mentioned disadvantages of the prior art, and an object of the present invention is to provide a light-emitting diode element having a high light extraction efficiency using a conventional vacuum evaporation apparatus and a method for manufacturing the same. It is.

本発明者らがITO膜表面の算術平均粗さと、反射率との関係を調べたところ、算術平均粗さが小さいほど反射率が大きくなることが分かった。
発光ダイオード素子の発光光の波長は、例えば短波長(青系統)のもので460nmであり、図4のグラフは、その波長での光の反射率と、ITO膜表面の算術平均粗さとの関係を示している。
発光ダイオード素子として実用上必要な反射率は80%以上であり、反射率80%以上を得るために必要な算術平均粗さは2.7nm以下であることが図4のグラフから分かる。
When the present inventors investigated the relationship between the arithmetic average roughness of the ITO film surface and the reflectance, it was found that the smaller the arithmetic average roughness, the higher the reflectance.
The wavelength of light emitted from the light emitting diode element is, for example, 460 nm for a short wavelength (blue system), and the graph of FIG. 4 shows the relationship between the reflectance of light at that wavelength and the arithmetic average roughness of the ITO film surface. Is shown.
It can be seen from the graph of FIG. 4 that the reflectance necessary for practical use as a light-emitting diode element is 80% or more, and the arithmetic average roughness necessary for obtaining the reflectance of 80% or more is 2.7 nm or less.

係る知見に基づいて成された本発明は、発光層と、前記発光層上に配置されたITO膜と、前記ITO膜上に配置された反射電極膜とを有し、前記発光層から放出され、前記ITO膜を透過した光は、前記反射電極膜で反射され、前記ITO膜と前記発光層とを透過して外部に放出される発光ダイオード素子の製造方法であって、前記発光層が表面に露出する基板とITO材料とを真空槽内に配置し、前記真空槽内を真空排気しながら前記ITO材料を加熱融解して蒸気を発生させ、前記蒸気を前記基板の前記発光層上に到達させて、前記基板を100℃以下の温度に冷却しながら、前記発光層上に前記ITO膜を0.26nm/s以下の成膜レートで成膜する蒸着工程と、前記基板を酸素ガスを含有するガスと接触させながら、400℃以上850℃以下のアニール温度で高速高温アニール処理をするアニール工程と、を有する発光ダイオード素子の製造方法である。 The present invention made on the basis of this finding has a light emission layer, and the ITO film disposed on the light emitting layer, and a reflective electrode film disposed on the ITO film, emitted from the light emitting layer The light transmitted through the ITO film is reflected by the reflective electrode film, passes through the ITO film and the light emitting layer, and is emitted to the outside. A substrate exposed on the surface and the ITO material are disposed in a vacuum chamber, and the ITO material is heated and melted while evacuating the vacuum chamber to generate vapor, and the vapor is deposited on the light emitting layer of the substrate. An evaporation process for forming the ITO film on the light emitting layer at a film formation rate of 0.26 nm / s or less while cooling the substrate to a temperature of 100 ° C. or lower; and oxygen gas is applied to the substrate. 400 ° C or higher while in contact with the contained gas And annealing steps of the high-speed high-temperature annealing at 850 ° C. below the annealing temperature, a method of manufacturing a light emitting diode element having a.

なお、算術平均粗さ(Ra)はJIS B0601:2001に規定されている。
本発明は上記のように構成されており、透明電極膜表面の算術平均粗さが小さいと、その表面に反射電極膜を形成したときに、反射電極膜の透明電極膜と密着する面が平滑になるので、反射電極膜で光の散乱や吸収が起こらず、反射率が高くなる。
The arithmetic average roughness (Ra) is defined in JIS B0601: 2001.
The present invention is configured as described above. When the arithmetic average roughness of the transparent electrode film surface is small, the surface of the reflective electrode film that is in close contact with the transparent electrode film is smooth when the reflective electrode film is formed on the surface. Therefore, light is not scattered or absorbed by the reflective electrode film, and the reflectance is increased.

表面の算術平均粗さの小さいITO膜が作成できるため、光の取り出し効率の高い発光ダイオード素子が作成可能となる。
従来の真空蒸着装置を用いることができるので、新たに特別な真空蒸着装置を用意するためのコストがかからない。
スパッタ法に比べて透明電極膜の成膜中に発光層が受けるダメージが少ないので、発光量が減少しない。
Since an ITO film having a small arithmetic average roughness on the surface can be produced, a light-emitting diode element with high light extraction efficiency can be produced.
Since a conventional vacuum deposition apparatus can be used, there is no cost for newly preparing a special vacuum deposition apparatus.
Since the light emitting layer is less damaged during the formation of the transparent electrode film than the sputtering method, the light emission amount does not decrease.

(a)〜(e):本発明の発光ダイオード素子の製造方法を説明するための図(A)-(e): The figure for demonstrating the manufacturing method of the light emitting diode element of this invention. 透明電極膜の真空蒸着装置の構造を説明するための図The figure for explaining the structure of the vacuum evaporation system of the transparent electrode film 従来の発光ダイオード素子の構造を説明するための図The figure for demonstrating the structure of the conventional light emitting diode element ITO膜表面の算術平均粗さと反射率との関係を示すグラフGraph showing the relationship between the arithmetic mean roughness of the ITO film surface and the reflectance 基板加熱温度とITO膜表面の算術平均粗さとの関係を示すグラフGraph showing the relationship between the substrate heating temperature and the arithmetic average roughness of the ITO film surface ITO膜の成膜レートと表面の算術平均粗さとの関係を示すグラフGraph showing the relationship between the deposition rate of the ITO film and the arithmetic average roughness of the surface

本発明である発光ダイオード素子の構造について説明する。
図1(e)の符号10eは本発明である発光ダイオード素子を示している。
発光ダイオード素子10eは発光層19と透明電極膜16と反射電極膜17とを有している。発光層19は、n型クラッド層13と、活性層14と、p型クラッド層15とを有している。
The structure of the light-emitting diode element according to the present invention will be described.
Reference numeral 10e in FIG. 1 (e) denotes a light emitting diode element according to the present invention.
The light emitting diode element 10 e includes a light emitting layer 19, a transparent electrode film 16, and a reflective electrode film 17. The light emitting layer 19 includes an n-type cladding layer 13, an active layer 14, and a p-type cladding layer 15.

透明な透明基板11上にバッファ層12が配置され、バッファ層12上にn型クラッド層13が配置されている。
n型クラッド層13上には、n型クラッド層13が一部露出するようにして、活性層14と、p型クラッド層15と、透明電極膜16と、反射電極膜17とがこの順に配置されている。
透明電極膜16は透明な導電性物質からなり、ここではITO膜が用いられている。また反射電極膜17には、ここではAg膜が用いられている。
反射電極膜17上には正端子21が配置され、n型クラッド層13の露出した面上には活性層14と離間して負端子22が配置されている。
A buffer layer 12 is disposed on a transparent transparent substrate 11, and an n-type cladding layer 13 is disposed on the buffer layer 12.
On the n-type cladding layer 13, the active layer 14, the p-type cladding layer 15, the transparent electrode film 16, and the reflective electrode film 17 are arranged in this order so that the n-type cladding layer 13 is partially exposed. Has been.
The transparent electrode film 16 is made of a transparent conductive material, and an ITO film is used here. Here, an Ag film is used as the reflective electrode film 17.
A positive terminal 21 is disposed on the reflective electrode film 17, and a negative terminal 22 is disposed on the exposed surface of the n-type cladding layer 13 so as to be separated from the active layer 14.

不図示の直流電源の正極を正端子21に、負極を負端子22にそれぞれ電気的に接続し、正端子21と負端子22との間に直流電圧を印加して、直流電流を流すと、活性層14は光を放出する。
活性層14からp型クラッド層15側に放出された光は、透明電極膜16を透過し、反射電極膜17で反射され、透明電極膜16と発光層19とバッファ層12と透明基板11とを順に透過し、外部に放出される。
後述する製造方法により、透明電極膜16の反射電極膜17と密着する面の算術平均粗さは2.7nm以下にされ、透明電極膜16の抵抗率は1.0×10-3Ω・cm以下にされている。
When a positive electrode of a DC power source (not shown) is electrically connected to the positive terminal 21 and a negative electrode is connected to the negative terminal 22, respectively, and a DC voltage is applied between the positive terminal 21 and the negative terminal 22, The active layer 14 emits light.
The light emitted from the active layer 14 to the p-type cladding layer 15 side is transmitted through the transparent electrode film 16 and reflected by the reflective electrode film 17, and the transparent electrode film 16, the light emitting layer 19, the buffer layer 12, the transparent substrate 11, and the like. In order and released to the outside.
By the manufacturing method described later, the arithmetic average roughness of the surface of the transparent electrode film 16 that is in close contact with the reflective electrode film 17 is set to 2.7 nm or less, and the resistivity of the transparent electrode film 16 is 1.0 × 10 −3 Ω · cm. It is below.

透明電極膜16の反射電極膜17と密着する面の算術平均粗さが2.7nm以下であるために、活性層14が放出する光の波長が460nmである場合、反射電極膜17に入射する光の80%以上が散乱又は吸収されずに反射される。
また、透明電極膜16の抵抗率が1.0×10-3Ω・cm以下であるために、この発光ダイオード素子10eは発光ダイオードとしての用途に好ましく用いることができる。
Since the arithmetic average roughness of the surface of the transparent electrode film 16 that is in close contact with the reflective electrode film 17 is 2.7 nm or less, when the wavelength of light emitted from the active layer 14 is 460 nm, the light enters the reflective electrode film 17. More than 80% of the light is reflected without being scattered or absorbed.
Moreover, since the resistivity of the transparent electrode film 16 is 1.0 × 10 −3 Ω · cm or less, the light-emitting diode element 10 e can be preferably used for use as a light-emitting diode.

次に、発光ダイオード素子10eの製造装置について説明する。
図2の符号30は透明電極膜16の真空蒸着装置を示している。
真空蒸着装置30は、真空槽39と、ステージ32と、るつぼ31とを有している。
真空槽39には真空排気装置41が設けられ、真空槽39内は真空排気可能にされている。
Next, an apparatus for manufacturing the light emitting diode element 10e will be described.
Reference numeral 30 in FIG. 2 indicates a vacuum deposition apparatus for the transparent electrode film 16.
The vacuum evaporation apparatus 30 includes a vacuum chamber 39, a stage 32, and a crucible 31.
The vacuum chamber 39 is provided with a vacuum exhaust device 41, and the inside of the vacuum chamber 39 can be evacuated.

ステージ32とるつぼ31は真空槽39内に配置されている。
ステージ32のるつぼ31と対向する面には、基板保持面36が設けられている。基板保持面36は静電吸着等により基板を保持可能に構成されている。
またステージ32には不図示の冷却パイプが設けられ、冷却パイプに制御装置45から温度管理された冷却媒体を流すことにより、基板保持面36上の基板を所定の温度に冷却可能にされている。
The stage 32 and the crucible 31 are arranged in a vacuum chamber 39.
A substrate holding surface 36 is provided on the surface of the stage 32 facing the crucible 31. The substrate holding surface 36 is configured to be able to hold the substrate by electrostatic adsorption or the like.
The stage 32 is provided with a cooling pipe (not shown), and the substrate on the substrate holding surface 36 can be cooled to a predetermined temperature by flowing a cooling medium whose temperature is controlled from the control device 45 to the cooling pipe. .

るつぼ31のステージ32と対向する面には、凹形状の凹部34が設けられている。
るつぼ31の凹部34とは逆側には加熱装置として、ここでは電子ビーム発生装置35が配置されている。電子ビーム発生装置35には真空槽39の外側に配置された電源装置42が電気的に接続されている。電源装置42には制御装置45が接続されている。
A concave portion 34 having a concave shape is provided on the surface of the crucible 31 facing the stage 32.
On the opposite side of the crucible 31 from the recess 34, an electron beam generator 35 is disposed here as a heating device. A power supply device 42 disposed outside the vacuum chamber 39 is electrically connected to the electron beam generator 35. A control device 45 is connected to the power supply device 42.

真空槽39内を真空排気しながら、電源装置42から電子ビーム発生装置35に電力を供給すると、電子ビーム発生装置35は真空槽39内に電子を放出する。放出された電子は不図示のコイルによる磁場を通過して進路を曲げられて、凹部34内の蒸着材料に入射し、蒸着材料を加熱可能にされている。
るつぼ31とステージ32の間にはシャッター33が配置されている。シャッター33には制御装置45が接続され、所定のタイミングで開閉可能にされている。
When electric power is supplied from the power supply device 42 to the electron beam generator 35 while evacuating the vacuum chamber 39, the electron beam generator 35 emits electrons into the vacuum chamber 39. The emitted electrons pass through a magnetic field by a coil (not shown), are bent, and enter the vapor deposition material in the recess 34 so that the vapor deposition material can be heated.
A shutter 33 is disposed between the crucible 31 and the stage 32. A control device 45 is connected to the shutter 33 and can be opened and closed at a predetermined timing.

次に、発光ダイオード素子10eの製造方法について説明する。図1(a)〜(d)の符号10a〜10dは各製造工程における処理対象物を示している。
まず、図1(a)に示すように、透明基板11上に、バッファ層12と、n型クラッド層13と、活性層14と、p型クラッド層15とを配置する。符号10aはこの処理対象物を示している。
次いで、蒸着工程として、処理対象物10aを真空蒸着装置30の真空槽39内に搬入し、ステージ32の基板保持面36上に、透明基板11が基板保持面36と対向し、p型クラッド層15がるつぼ31側を向いて露出するように、保持する。
るつぼ31の凹部34内に、ITO材料等の透明電極材料を配置する。
Next, a method for manufacturing the light emitting diode element 10e will be described. The code | symbol 10a-10d of Fig.1 (a)-(d) has shown the process target object in each manufacturing process.
First, as shown in FIG. 1A, a buffer layer 12, an n-type cladding layer 13, an active layer 14, and a p-type cladding layer 15 are arranged on a transparent substrate 11. Reference numeral 10a indicates the object to be processed.
Next, as a vapor deposition step, the object to be processed 10a is carried into the vacuum chamber 39 of the vacuum vapor deposition apparatus 30, and the transparent substrate 11 is opposed to the substrate holding surface 36 on the substrate holding surface 36 of the stage 32, and the p-type cladding layer. Hold so that 15 is exposed facing the crucible 31 side.
A transparent electrode material such as ITO material is disposed in the recess 34 of the crucible 31.

真空排気装置41を起動して、真空槽39内を真空排気する。以後、蒸着処理を終えるまで真空槽39内の真空排気を継続する。
ステージ32に設けられた冷却パイプに冷却媒体を流して処理対象物10aを所定の温度に冷却する。透明電極材料としてITO材料を用いる場合には100℃以下の温度が好ましい。以後、蒸着処理を終えるまで処理対象物10aの冷却を継続する。
The vacuum exhaust device 41 is activated to evacuate the vacuum chamber 39. Thereafter, evacuation in the vacuum chamber 39 is continued until the vapor deposition process is completed.
A cooling medium is passed through a cooling pipe provided on the stage 32 to cool the processing target 10a to a predetermined temperature. When an ITO material is used as the transparent electrode material, a temperature of 100 ° C. or lower is preferable. Thereafter, the cooling of the processing object 10a is continued until the vapor deposition processing is completed.

シャッター33を閉じた状態で、真空槽39内を真空排気しながら、電源装置42から電子ビーム発生装置35に所定の電力を供給し、真空槽39内に電子ビームを放出させ、凹部34内の透明電極材料に照射させ、透明電極材料を加熱融解して蒸気を発生させる。
本発明における透明電極材料の加熱融解方法は電子ビーム照射法に限定されず、抵抗加熱法等の加熱方法により透明電極材料を加熱融解させて、蒸気を発生させてもよい。
While the shutter 33 is closed, the vacuum chamber 39 is evacuated and a predetermined power is supplied from the power supply device 42 to the electron beam generator 35 to emit the electron beam into the vacuum chamber 39. The transparent electrode material is irradiated, and the transparent electrode material is heated and melted to generate vapor.
The method for heating and melting the transparent electrode material in the present invention is not limited to the electron beam irradiation method, and vapor may be generated by heating and melting the transparent electrode material by a heating method such as a resistance heating method.

シャッター33を開けて、透明電極材料の蒸気を処理対象物10aのp型クラッド層15上に到達させ、図1(b)に示すように、p型クラッド層15上に透明電極膜16を成膜する。
透明電極膜16の成膜中は、電子ビームを所定の出力値に設定し、所定の成膜レートで成膜させる。透明電極膜16としてITO膜を成膜する場合には0.26nm/s以下の成膜レートが好ましい。
The shutter 33 is opened so that the vapor of the transparent electrode material reaches the p-type cladding layer 15 of the object to be processed 10a, and the transparent electrode film 16 is formed on the p-type cladding layer 15 as shown in FIG. Film.
During the formation of the transparent electrode film 16, the electron beam is set to a predetermined output value and is formed at a predetermined film formation rate. When an ITO film is formed as the transparent electrode film 16, a film formation rate of 0.26 nm / s or less is preferable.

透明電極膜16を所定の膜厚で成膜したのち、シャッター33を閉じ、電子ビーム発生装置35への電力供給を止めて、蒸着処理を終了する。図1(b)の符号10bは蒸着処理後の処理対象物を示している。
後述する実施例に示すように、透明電極膜16としてITO膜を成膜する場合には、処理対象物10aを100℃以下の温度に冷却しながら、0.26nm/s以下の成膜レートで蒸着することにより、ITO膜表面の算術平均粗さを2.7nm以下にすることができる。
また透明電極膜16を真空蒸着法により成膜することで、発光層19にダメージを与えずに成膜することができる。
After forming the transparent electrode film 16 with a predetermined film thickness, the shutter 33 is closed, the power supply to the electron beam generator 35 is stopped, and the vapor deposition process is completed. The code | symbol 10b of FIG.1 (b) has shown the process target object after a vapor deposition process.
As shown in the examples described later, when an ITO film is formed as the transparent electrode film 16, the processing object 10a is cooled to a temperature of 100 ° C. or lower and a film forming rate of 0.26 nm / s or lower. By vapor deposition, the arithmetic average roughness of the ITO film surface can be reduced to 2.7 nm or less.
Further, the transparent electrode film 16 can be formed without damaging the light emitting layer 19 by forming the transparent electrode film 16 by a vacuum deposition method.

次いでアニール工程として、蒸着処理後の処理対象物10bを真空槽39から搬出し、酸素ガスを含有するガス雰囲気中に配置する。
処理対象物10bを酸素ガスを含有するガスと接触させながら、透明電極膜16に対してハロゲンランプ等から加熱光照射等の加熱方法により、高速高温アニール処理(RTA)する。透明電極膜16がITO膜である場合には400℃以上850℃以下のアニール温度が好ましい。
Next, as the annealing step, the processing target 10b after the vapor deposition is carried out of the vacuum chamber 39 and placed in a gas atmosphere containing oxygen gas.
While the object to be treated 10b is in contact with a gas containing oxygen gas, the transparent electrode film 16 is subjected to high-temperature and high-temperature annealing (RTA) by a heating method such as irradiation with heating light from a halogen lamp or the like. When the transparent electrode film 16 is an ITO film, an annealing temperature of 400 ° C. or higher and 850 ° C. or lower is preferable.

後述する実施例に示すように、400℃以上850℃以下のアニール温度での高速高温アニール処理により、透明電極膜16がITO膜である場合には、ITO膜表面の算術平均粗さはアニール処理前と変わらずに、ITO膜の抵抗率を1.0×10-3Ω・cm以下にすることができる。 As shown in the examples described later, when the transparent electrode film 16 is an ITO film by high-speed high-temperature annealing at an annealing temperature of 400 ° C. or higher and 850 ° C. or lower, the arithmetic average roughness of the ITO film surface is annealed. As before, the resistivity of the ITO film can be reduced to 1.0 × 10 −3 Ω · cm or less.

次いで、アニール処理後の処理対象物10bを不図示の成膜装置に搬入して、真空蒸着法やスパッタ法等により、図1(c)に示すように、透明電極膜16上に反射電極膜17を成膜する。図1(c)の符号10cは反射電極膜17を成膜後の処理対象物を示している。   Next, the object to be processed 10b after the annealing treatment is carried into a film forming apparatus (not shown), and a reflective electrode film is formed on the transparent electrode film 16 by a vacuum vapor deposition method, a sputtering method or the like as shown in FIG. 17 is formed. Reference numeral 10 c in FIG. 1C indicates a processing target after the reflective electrode film 17 is formed.

次いで、反射電極膜17を成膜後の処理対象物10cを不図示のエッチング装置に搬入し、反射電極膜17と、透明電極膜16と、p型クラッド層15と、活性層14とを部分的にエッチングして除去し、n型クラッド層13を一部露出させる。図1(d)の符号10dは、エッチング処理後の処理対象物を示している。   Next, the processing object 10c after forming the reflective electrode film 17 is carried into an etching apparatus (not shown), and the reflective electrode film 17, the transparent electrode film 16, the p-type cladding layer 15, and the active layer 14 are partially formed. The n-type cladding layer 13 is partially exposed by etching. Reference numeral 10d in FIG. 1D indicates a processing object after the etching process.

次いで、エッチング処理後の処理対象物10dを不図示の成膜装置に搬入して、真空蒸着法やスパッタ法等により、図1(e)に示すように反射電極膜17上に正端子21を形成し、n型クラッド層13の露出した面上に、活性層14と離間して、負端子22を形成する。
上述した工程により発光ダイオード素子10eが製造される。
Next, the processed object 10d after the etching process is carried into a film forming apparatus (not shown), and the positive terminal 21 is formed on the reflective electrode film 17 as shown in FIG. A negative terminal 22 is formed on the exposed surface of the n-type cladding layer 13, spaced from the active layer 14.
The light emitting diode element 10e is manufactured by the above-described process.

上述の製造方法では、反射電極膜17を成膜後に、反射電極膜17と一緒に透明電極膜16とp型クラッド層15と活性層14とをエッチングして部分的に除去したが、本発明はこれに限定されず、透明電極膜16とp型クラッド層15と活性層14とをエッチングして部分的に除去した後、反射電極膜17を成膜してもよい。   In the above manufacturing method, after the reflective electrode film 17 is formed, the transparent electrode film 16, the p-type cladding layer 15 and the active layer 14 are partially removed together with the reflective electrode film 17 by etching. The reflective electrode film 17 may be formed after the transparent electrode film 16, the p-type cladding layer 15 and the active layer 14 are partially removed by etching.

<実施例1>
蒸着工程において、処理対象物とITO材料とを真空槽39内に搬入したのち、真空槽39内を1×10-4Paの圧力に真空排気した。次いで、真空槽39内を真空排気しながら、電子ビーム発生装置35から360Wの出力で電子ビームを発生させ、凹部34内のITO材料に照射し、ITO材料を加熱融解させて、蒸気を発生させた。
<Example 1>
In the vapor deposition step, the object to be treated and the ITO material were carried into the vacuum chamber 39, and then the vacuum chamber 39 was evacuated to a pressure of 1 × 10 −4 Pa. Next, while evacuating the inside of the vacuum chamber 39, an electron beam is generated with an output of 360 W from the electron beam generator 35, irradiated to the ITO material in the recess 34, and the ITO material is heated and melted to generate vapor. It was.

成膜中の真空槽39内が3.0×10-2Paの圧力になるように調圧しながら、シャッター33を開いて、ITO材料の蒸気を処理対象物に到達させ、ITO膜の成膜を開始した。
なお、成膜中は、成膜レートを0.05nm/sのレートに設定し、処理対象物を24℃の温度に冷却していた。
ITO膜を40nmの膜厚に成膜したのち、シャッター33を閉じ、電子ビーム発生装置35を停止して、蒸着処理を終了した。
次いで、処理対象物を真空槽39内から搬出し、AFM(原子間力顕微鏡)を用いてITO膜表面の算術平均粗さを測定した。
While adjusting the pressure so that the inside of the vacuum chamber 39 during film formation becomes a pressure of 3.0 × 10 −2 Pa, the shutter 33 is opened, the vapor of the ITO material reaches the object to be processed, and the ITO film is formed. Started.
During film formation, the film formation rate was set to 0.05 nm / s, and the object to be processed was cooled to a temperature of 24 ° C.
After the ITO film was formed to a thickness of 40 nm, the shutter 33 was closed, the electron beam generator 35 was stopped, and the vapor deposition process was completed.
Next, the object to be treated was taken out of the vacuum chamber 39, and the arithmetic average roughness of the ITO film surface was measured using an AFM (atomic force microscope).

上述の測定を、成膜中の処理対象物を24℃以上150℃以下の所定の温度に変更して繰り返した。
図5のグラフは成膜中の処理対象物の温度と、成膜後のITO膜表面の算術平均粗さとの関係を示している。
図5のグラフから、算術平均粗さを2.7nm以下にするには、成膜中は処理対象物を100℃以下の温度に冷却する必要があることがわかる。
The above measurement was repeated by changing the object to be processed during film formation to a predetermined temperature of 24 ° C. or higher and 150 ° C. or lower.
The graph of FIG. 5 shows the relationship between the temperature of the processing object during film formation and the arithmetic average roughness of the ITO film surface after film formation.
From the graph of FIG. 5, it can be seen that in order to reduce the arithmetic average roughness to 2.7 nm or less, it is necessary to cool the object to be processed to a temperature of 100 ° C. or less during film formation.

<実施例2>
実施例1と同様の測定を、成膜中の処理対象物を24℃の温度に冷却し、電子ビームを360W以上460W以下の出力に変更することにより、成膜レートを0.05nm/s以上0.4nm/s以下の所定のレートに変更して繰り返した。
図6のグラフはITO膜の成膜中の成膜レートと表面の算術平均粗さとの関係を示している。
図6のグラフから、算術平均粗さを2.7nm以下にするには、ITO膜成膜中は成膜レートを0.26nm/s以下のレートにする必要があることがわかる。
<Example 2>
In the same measurement as in Example 1, the film formation rate was set to 0.05 nm / s or more by cooling the processing target during film formation to a temperature of 24 ° C. and changing the electron beam to an output of 360 W or more and 460 W or less. It changed and changed to the predetermined | prescribed rate of 0.4 nm / s or less, and repeated.
The graph of FIG. 6 shows the relationship between the deposition rate during the deposition of the ITO film and the arithmetic average roughness of the surface.
From the graph of FIG. 6, it can be seen that in order to make the arithmetic average roughness 2.7 nm or less, the film formation rate must be 0.26 nm / s or less during the ITO film formation.

<実施例3>
アニール工程において、窒素80%、酸素20%のガス雰囲気中にITO膜蒸着後の処理対象物を配置した。このときアニール装置内の圧力は大気圧になるように調圧した。
ハロゲンランプを用いて、350℃のアニール温度で1分間の高速高温アニール処理(RTA)をした。
次いで、処理対象物をアニール装置から搬出し、ITO膜の抵抗率と算術平均粗さとを測定した。
<Example 3>
In the annealing step, the object to be treated after the ITO film deposition was placed in a gas atmosphere of 80% nitrogen and 20% oxygen. At this time, the pressure in the annealing apparatus was adjusted to atmospheric pressure.
High-speed high-temperature annealing (RTA) was performed for 1 minute at an annealing temperature of 350 ° C. using a halogen lamp.
Next, the object to be treated was taken out of the annealing apparatus, and the resistivity and arithmetic average roughness of the ITO film were measured.

上述の測定を、アニール温度を350℃以上850℃以下の所定の温度に変更して繰り返した。
表1はアニール温度とITO膜の抵抗率及び算術平均粗さとの関係を示している。
The above measurement was repeated by changing the annealing temperature to a predetermined temperature of 350 ° C. or higher and 850 ° C. or lower.
Table 1 shows the relationship between the annealing temperature, the resistivity of the ITO film, and the arithmetic average roughness.

Figure 0005317898
Figure 0005317898

表1から、アニール温度を変更しても算術平均粗さは変わらず、抵抗率を1.0×10-3Ω・cm以下にするには、アニール温度を400℃以上の温度にする必要があることがわかる。 From Table 1, even if the annealing temperature is changed, the arithmetic average roughness does not change, and in order to make the resistivity 1.0 × 10 −3 Ω · cm or less, the annealing temperature needs to be 400 ° C. or higher. I know that there is.

10e……発光ダイオード素子
16……透明電極膜
17……反射電極膜
19……発光層
10e: Light emitting diode element 16: Transparent electrode film 17: Reflective electrode film 19: Light emitting layer

Claims (1)

発光層と、前記発光層上に配置されたITO膜と、前記ITO膜上に配置された反射電極膜とを有し、
前記発光層から放出され、前記ITO膜を透過した光は、前記反射電極膜で反射され、前記ITO膜と前記発光層とを透過して外部に放出される発光ダイオード素子の製造方法であって、
前記発光層が表面に露出する基板とITO材料とを真空槽内に配置し、前記真空槽内を真空排気しながら前記ITO材料を加熱融解して蒸気を発生させ、前記蒸気を前記基板の前記発光層上に到達させて、前記基板を100℃以下の温度に冷却しながら、前記発光層上に前記ITO膜を0.26nm/s以下の成膜レートで成膜する蒸着工程と、
前記基板を酸素ガスを含有するガスと接触させながら、400℃以上850℃以下のアニール温度で高速高温アニール処理をするアニール工程と、
を有する発光ダイオード素子の製造方法。
A light emitting layer, an ITO film disposed on the light emitting layer, and a reflective electrode film disposed on the ITO film;
The light emitted from the light emitting layer and transmitted through the ITO film is reflected by the reflective electrode film, passes through the ITO film and the light emitting layer, and is emitted to the outside. ,
The substrate having the light emitting layer exposed on the surface and the ITO material are disposed in a vacuum chamber, and the ITO material is heated and melted while the vacuum chamber is evacuated to generate vapor, and the vapor is generated on the substrate. A vapor deposition step of depositing the ITO film on the light emitting layer at a film forming rate of 0.26 nm / s or less while reaching the light emitting layer and cooling the substrate to a temperature of 100 ° C. or less;
An annealing step of performing high-speed high-temperature annealing at an annealing temperature of 400 ° C. or higher and 850 ° C. or lower while contacting the substrate with a gas containing oxygen gas;
The manufacturing method of the light emitting diode element which has this.
JP2009208868A 2009-09-10 2009-09-10 Method for manufacturing light-emitting diode element Expired - Fee Related JP5317898B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009208868A JP5317898B2 (en) 2009-09-10 2009-09-10 Method for manufacturing light-emitting diode element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009208868A JP5317898B2 (en) 2009-09-10 2009-09-10 Method for manufacturing light-emitting diode element

Publications (2)

Publication Number Publication Date
JP2011060986A JP2011060986A (en) 2011-03-24
JP5317898B2 true JP5317898B2 (en) 2013-10-16

Family

ID=43948286

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009208868A Expired - Fee Related JP5317898B2 (en) 2009-09-10 2009-09-10 Method for manufacturing light-emitting diode element

Country Status (1)

Country Link
JP (1) JP5317898B2 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8545629B2 (en) 2001-12-24 2013-10-01 Crystal Is, Inc. Method and apparatus for producing large, single-crystals of aluminum nitride
US7641735B2 (en) 2005-12-02 2010-01-05 Crystal Is, Inc. Doped aluminum nitride crystals and methods of making them
US9034103B2 (en) 2006-03-30 2015-05-19 Crystal Is, Inc. Aluminum nitride bulk crystals having high transparency to ultraviolet light and methods of forming them
US9771666B2 (en) 2007-01-17 2017-09-26 Crystal Is, Inc. Defect reduction in seeded aluminum nitride crystal growth
CN107059116B (en) 2007-01-17 2019-12-31 晶体公司 Defect reduction in seeded aluminum nitride crystal growth
US8080833B2 (en) 2007-01-26 2011-12-20 Crystal Is, Inc. Thick pseudomorphic nitride epitaxial layers
EP2588651B1 (en) 2010-06-30 2020-01-08 Crystal Is, Inc. Growth of large aluminum nitride single crystals with thermal-gradient control
CN102832297B (en) * 2011-06-17 2015-09-30 比亚迪股份有限公司 The preparation method of a kind of light emitting semiconductor device and current-diffusion layer
US8962359B2 (en) 2011-07-19 2015-02-24 Crystal Is, Inc. Photon extraction from nitride ultraviolet light-emitting devices
JP6275817B2 (en) * 2013-03-15 2018-02-07 クリスタル アイエス, インコーポレーテッドCrystal Is, Inc. Planar contacts to pseudomorphic and optoelectronic devices

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5032138B2 (en) * 2007-01-26 2012-09-26 株式会社アルバック Method for manufacturing light-emitting diode element

Also Published As

Publication number Publication date
JP2011060986A (en) 2011-03-24

Similar Documents

Publication Publication Date Title
JP5317898B2 (en) Method for manufacturing light-emitting diode element
Yang et al. Improved optical sintering efficiency at the contacts of silver nanowires encapsulated by a graphene layer
US11139170B2 (en) Apparatus and method for bonding substrates
WO2021103453A1 (en) Coating method for a semiconductor laser, and semiconductor laser
US10085339B2 (en) Method of manufacturing electroconductive nanowire network using electron beam, transparent electrode and electronic device using the same
TW201742936A (en) Film forming method for semiconductor device, aluminum nitride film forming method and electronic device capable of preventing the substrate from particles falling on the substrate and improving the performance of the electronic device
JP2011061084A (en) Method for manufacturing laminated substrate
JP2013138090A (en) Method for manufacturing light-emitting diode
JP4002169B2 (en) Electrostatic chuck
JP5032138B2 (en) Method for manufacturing light-emitting diode element
JP2012227473A (en) Semiconductor device manufacturing method
CN108004506B (en) A kind of noble metal nano particles and preparation method thereof based on In alloy
JP3719797B2 (en) Method for forming conductive thin film on organic thin film surface
KR101224529B1 (en) Heat treatment apparatus
JP5497301B2 (en) Semiconductor light emitting device and manufacturing method thereof
JP2005097730A (en) Film-forming apparatus and manufacturing apparatus
JP5730326B2 (en) Method for forming In metal oxide film
JP2018104645A (en) Target for ultraviolet generation and method for producing the same, and electron beam excitation ultraviolet light source
US10886468B2 (en) Manufacturing method and manufacturing apparatus for organic EL display device
TW201027768A (en) Manufacturing method of solar battery, etching device and CVD device
JP2007137690A (en) Method for inhibiting buildup of carbon foil, carbon foil, and apparatus for inhibiting buildup of carbon foil
JP7110528B2 (en) Method for manufacturing upper electrode film of organic EL element by sputtering method
JP2012212820A (en) Method for forming transparent conductive film
JPH1117226A (en) Electrodestructure of compound semiconductor and method for forming the same
WO2012128051A1 (en) Method for producing transparent conductive film and method for manufacturing solar cell

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20120524

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130129

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130130

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20130311

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130311

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130625

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130709

R150 Certificate of patent or registration of utility model

Ref document number: 5317898

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees