JP5316115B2 - Jitter reduction circuit and semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a jitter reduction circuit capable of reducing jitters on clock signal, and to provide a semiconductor integrated circuit. <P>SOLUTION: A jitter reduction circuit includes: a first frequency measuring circuit 11 for measuring a first frequency of a first clock signal CLK1; a second frequency measuring circuit 12 for measuring the second frequency of a second clock signal CLK2; a frequency comparing and determining circuit 20 for comparing the measured first and second frequencies and determining whether the first and the second frequencies have a prescribed relation; and a first delay control circuit 41 for receiving a first control signal CNT1 from the frequency-comparing and determining circuit and controlling delay of the first clock signal to the reduce jitters caused by the second clock signal. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The embodiments mentioned in this application relate to a jitter reduction circuit and a semiconductor integrated circuit.

  2. Description of the Related Art In recent years, semiconductor integrated circuits (LSIs) have become highly integrated and highly functional with miniaturization. For example, a semiconductor integrated circuit (LSI) has a plurality of internal circuits that use clock signals with different frequencies, or a predetermined clock depending on an operation mode. Some of which change the frequency of the signal are provided.

  As described above, in an LSI having a plurality of clock systems and each clock system operating at a different frequency, when the power supply voltage fluctuates due to the operation of a digital circuit of a certain clock system, the power supply voltage fluctuation becomes a power supply noise. Jitter is added in the propagation process of other clock signals.

  Therefore, for example, a circuit using a clock signal with jitter is difficult to operate at high speed and with accurate timing.

  FIG. 1 is a block diagram showing an example of a conventional semiconductor integrated circuit, and shows an example of a semiconductor integrated circuit which is not affected by power supply noise.

  In FIG. 1, reference numeral 50 indicates a semiconductor integrated circuit (chip), and 500 indicates a semiconductor package. Reference numeral 51 is a clock buffer, 52 is a data block, 53 is a clock driver, and 54 is a data driver.

  In the conventional semiconductor integrated circuit shown in FIG. 1, a dedicated power line A and a ground line AG are connected to the clock buffer 51, and a dedicated power line B and a ground line BG are connected to the data block 52. The

  Further, a dedicated power line C and a ground line CG are connected to the clock driver 53, and a dedicated power line D and a ground line DG are connected to the data driver 54.

  That is, by separating each digital circuit such as the clock buffer 51, the data block 52, the clock driver 53, and the data driver 54 by using a dedicated power supply line, it is possible to suppress the power supply noise caused by other digital circuits from flowing around as jitter. ing.

JP 2007-019100 A

  Conventionally, in a semiconductor integrated circuit 50, power supply noise generated in a certain digital circuit by separating the power supply line of each digital circuit, for example, wraps around to another clock system circuit sharing the same power supply line. Some have been proposed to prevent and suppress clock jitter.

  However, as shown in FIG. 1, in order to provide a dedicated power line and ground line for the clock buffer 51, the data block 52, the clock driver 53, and the data driver 54, for example, a pin for the semiconductor package 500 is provided. Must be provided.

  By the way, as described above, in recent years, an LSI (semiconductor integrated circuit) having a plurality of clock systems and each clock system operating at a different frequency is increasing.

  In such an LSI, in order to suppress jitter, for example, in order to provide a dedicated power supply line and a ground line for a circuit that generates power supply noise and another clock system circuit, a power supply pin or a ground pin This is not realistic because it leads to a significant increase.

  Further, in recent LSIs, there is a technique for dynamically changing the frequency of the clock signal in order to reduce power consumption. In that case, it is necessary to take a countermeasure against jitter corresponding to the frequency of the changing clock signal.

  In view of the above-described problems, an object of the present application is to provide a jitter reduction circuit and a semiconductor integrated circuit capable of reducing jitter on a clock signal.

  According to the first embodiment, there is provided a jitter reduction circuit including a first frequency measurement circuit, a second frequency measurement circuit, a frequency comparison / determination circuit, and a first delay control circuit.

  The first frequency measurement circuit measures the first frequency of the first clock signal, and the second frequency measurement circuit measures the second frequency of the second clock signal.

  The frequency comparison / determination circuit compares the measured first and second frequencies, and determines whether the first and second frequencies have a predetermined relationship.

The first delay control circuit receives the first control signal from the frequency comparison / determination circuit and controls the delay of the first clock signal to reduce jitter caused by the second clock signal.
When the first frequency is f1 and the second frequency is f2, the comparison determination circuit does not delay the first clock signal in the first delay control circuit if 2 × f2 / f1 is a substantially natural number. If the 2 × f2 / f1 is not a substantially natural number, the first delay control circuit outputs the first control signal so as to give the first delay time to the first clock signal. .

  According to each embodiment, it is possible to provide a jitter reduction circuit and a semiconductor integrated circuit capable of reducing jitter on a clock signal.

It is a block diagram which shows an example of the conventional semiconductor integrated circuit. It is a block diagram which shows an example of the semiconductor integrated circuit which has the jitter reduction circuit of a present Example. FIG. 3 is a block diagram illustrating an example of a frequency measurement circuit in the jitter reduction circuit of FIG. 2. FIG. 4 is a timing diagram for explaining the operation of the frequency measurement circuit of FIG. 3. FIG. 3 is a block diagram illustrating an example of a frequency comparison determination circuit in the jitter reduction circuit of FIG. 2. It is a figure which shows an example of the determination circuit in the frequency comparison determination circuit of FIG. FIG. 3 is a block diagram illustrating an example of a delay control circuit in the jitter reduction circuit of FIG. 2. It is a figure for demonstrating the relationship between the ratio of the frequency of two signals, and a jitter. It is a figure for demonstrating the relationship between the delay time by the jitter reduction circuit of a present Example, and a jitter. FIG. 3 is a timing chart for explaining the operation of the jitter reduction circuit of FIG. 2. It is a figure for demonstrating the conditions with little jitter in the jitter reduction circuit of a present Example.

  Hereinafter, a jitter reduction circuit and a semiconductor integrated circuit according to the present embodiment will be described in detail with reference to the accompanying drawings.

  FIG. 2 is a block diagram showing an example of a semiconductor integrated circuit having the jitter reduction circuit of this embodiment. In FIG. 2, reference numeral 1 is a semiconductor integrated circuit, 10 is a jitter reduction circuit, 41 is a first internal circuit, and 42 is a second internal circuit.

  As shown in FIG. 2, the semiconductor integrated circuit 1 of this embodiment includes a jitter reduction circuit 10, a first internal circuit 41, and a second internal circuit 42.

  The first internal circuit 41 and the second internal circuit 42 are circuits that operate with different clock signals (first and second control clock signals CLK1 ′, CLK2 ′) output from the jitter reduction circuit 10, respectively. A logic circuit or a memory circuit for realizing various functions.

  The semiconductor integrated circuit 1 does not supply the control clock signals CLK1 ′ and CLK2 ′ output from the jitter reduction circuit 10 to the first internal circuit 41 and the second internal circuit 42, for example. May be configured to output directly.

  The jitter reduction circuit 10 includes a first frequency measurement circuit 11, a second frequency measurement circuit 12, a frequency comparison determination circuit 20, a first delay control circuit 31, and a second delay control circuit 32.

  The first frequency measurement circuit 11 measures the frequency of the input first clock signal CLK1 and outputs the first clock frequency data f1data, and the second frequency measurement circuit 12 measures the frequency of the input second clock signal CLK2. Then, the second clock frequency data f2data is output.

  The frequency comparison / determination circuit 20 receives and compares the first clock frequency data f1data and the second clock frequency data f2data, and outputs control signals CNT1 and CNT2 to the first delay control circuit 31 and the second delay control circuit 32. .

  The first delay control circuit 31 receives the first clock signal CLK1, the second clock frequency data f2data, and the first control signal CNT1, performs a delay process to be described later on the first clock signal CLK1, and performs the first control clock signal CLK1. 'Is output.

  The second delay control circuit 32 receives the second clock signal CLK2, the first clock frequency data f1data, and the second control signal CNT2, performs a delay process described later on the second clock signal CLK2, and performs the second control clock signal CLK2. 'Is output.

  That is, for example, the frequency comparison / determination circuit 20 determines the frequency of the clock signals (CLK1, CLK2) input to the two circuits (41, 42) from the data obtained by the frequency measurement circuit (11, 12). Compare and judge the relationship.

  If the conditions are such that jitter is added to the clock, the control signals (CNT1, CNT2) from the frequency comparison / determination circuit 20 are activated, and the clock signals (CLK1, CLK2) input to the delay control circuits (31, 32) are added. On the other hand, a predetermined delay is given to reduce the jitter on the clock signal.

  FIG. 2 shows the case where the two clock signals CLK1 and CLK2 affect each other and give jitter, but for example, only the jitter that the second clock signal CLK2 gives to the first clock signal CLK1 is reduced. In this case, the second delay control circuit 32 or the like is not necessary.

  FIG. 3 is a block diagram showing an example of the frequency measurement circuit 11 (12) in the jitter reduction circuit 10 of FIG. 2, and FIG. 4 is a timing diagram for explaining the operation of the frequency measurement circuit 11 (12) of FIG. is there.

  Here, the first and second frequency measurement circuits 11 and 12 have the same configuration, and hereinafter, the first frequency measurement circuit 11 will be described as an example.

  As shown in FIG. 3, the first frequency measurement circuit 11 includes a binary counter 111, a register 112, and inverters 113 and 114.

  The first clock signal CLK1 is supplied to the enable / reset terminal of the binary counter 111 via two stages of inverters 113 and 114 connected in series, and is inverted by the inverter 113 and supplied to the clock terminal of the register 112. .

  Here, the binary counter 111 is enabled during the period in which the first clock signal CLK1 input via the two-stage inverters 113 and 114 is at the high level “H”, and performs the count operation. Reset to period.

  The reference clock signal ref-clk is supplied to the clock terminal of the binary counter 111, and the first clock signal CLK1 supplied to the enable / reset terminal via the inverters 113 and 114 is the reference clock signal ref in the high level “H” period. -Count the number of clk.

  Here, in order to simplify the description, FIG. 4 shows an example when the frequency of the reference clock signal ref-clk is 800 [MHz] and the frequency of the first clock signal CLK1 is 100 [MHz]. ing.

  At this time, the number of reference clock signals ref-clk counted during the period in which the first clock signal CLK1 is at the high level “H” is 4 (4 cycles), and the count value count output from the binary counter 111 is “4”. It becomes.

  Then, the count value count from the binary counter 111 is supplied to the register 112, and as shown in FIG. 4, after the first clock signal CLK1 falls from the high level “H” to the low level “L”, the count value count is increased again. The value “4” is held until the level rises to “H”.

  That is, the register 112 holds and outputs the value “4” counted during the period when the first clock signal CLK1 is at the high level “H” as the first frequency measurement data f1data of the first clock signal CLK1.

  As described above, the first and second frequency measurement circuits 11 and 12 have the same configuration. In the second frequency measurement circuit 12, the first clock signal CLK1 becomes the second clock signal CLK2, and the first clock frequency The data f1data becomes the second clock frequency data f2data.

  Further, in the second frequency measurement circuit 12, the first frequency measurement data f1data of the first clock signal CLK1 becomes the second frequency measurement data f2data of the second clock signal CLK2.

  5 is a block diagram illustrating an example of the frequency comparison / determination circuit 20 in the jitter reduction circuit 10 of FIG. 2, and FIG. 6 is a diagram illustrating an example of the determination circuit 203 (204) in the frequency comparison / determination circuit 20 of FIG. .

  As shown in FIG. 5, the frequency comparison determination circuit 20 includes a first arithmetic unit 201, a second arithmetic unit 202, a first determination circuit 203, and a second determination circuit 204.

  The first calculator 201 receives the first frequency measurement data f1data and the second frequency measurement data f2data from the first and second frequency measurement circuits, and calculates (2 × f1data) / f2data.

  Similarly, the second calculator 202 receives the first frequency measurement data f1data and the second frequency measurement data f2data from the first and second frequency measurement circuits, and calculates (2 × f2data) / f1data.

  Here, f1data and f2data are values obtained by counting the first and second clock signals CLK1 and CLK2 with the reference clock signal ref-clk, and the frequencies of the first and second clock signals CLK1 and CLK2 are f1 and f2. Is expressed as follows.

  That is, the first computing unit 201 performs (2 × f2) / f1 computation, and the second computing unit 202 performs (2 × f1) / f2 computation.

  As shown in FIG. 6, the determination circuit 203 (204) is an OR gate having a plurality of inputs, and is a quotient of several bits (4 bits in FIG. 6) of a decimal value by the quotient obtained by the calculation of the calculator 201 (202). The logical sum is taken and the control signal CNT1 (CNT2) is output.

  FIG. 7 is a block diagram showing an example of the delay control circuit 31 (32) in the jitter reduction circuit 10 of FIG. The first and second delay control circuits 31 and 32 have the same configuration, and hereinafter, the first delay control circuit 31 will be described as an example.

  As shown in FIG. 7, the first delay control circuit 31 includes buffers 301, 302,..., 30 m and selection circuits 311 and 312. Here, the buffers 301 to 30m and the selection circuit 311 function as a delay circuit.

  That is, the selection circuit 311 receives each output signal of the buffers 301 to 30m, selects and outputs the output signal of any buffer having a predetermined delay time according to the second frequency measurement data f2data.

  The selection circuit 312 receives the output signal of the selection circuit 311 and the first clock signal CLK1, selects either one according to the first control signal CNT1, and outputs it as the first control clock signal CLK1 ′.

  Specifically, the selection circuit 312 selects the output signal of the selection circuit 311 (delay circuit) when the first control signal CNT1 is at the high level “H” (“1”), and the first control signal CNT1 When the signal is at the low level “L” (“0”), the first clock signal CLK1 is selected and output as it is.

  When the first control signal CNT1 is at the low level “L”, the first clock signal CLK1 has no jitter due to the frequency relationship between the first clock signal CLK1 and the second clock signal CLK2. At this time, the first clock signal CLK1 is output as it is.

  FIG. 8 is a diagram for explaining the relationship between the frequency ratio of two signals and jitter. The clock signal input to the circuit that generates power supply noise is CLK2, and jitter is affected by this power supply noise. An example in which the clock signal to be rided is assumed to be CLK1 is shown.

  In FIG. 8, the vertical axis represents the period between jitter peaks (Period Jitter peak to peak: [ps]) on the first clock signal CLK1, and the horizontal axis represents the operating frequency (second frequency) of the circuit that generates noise. The frequency [MHz] of the clock signal CLK2).

  As shown in FIG. 8, the positive integer (natural number) times the frequency f1 of the first clock signal CLK1 on which jitter is multiplied is twice the frequency f2 of the second clock signal CLK2 of the circuit that generates power supply noise ((2 × The jitter decreases when f2) / f1 = n, where n is a natural number).

  That is, when (2 × f2) / f1 = 1, (2 × f2) / f1 = 2, (2 × f2) / f1 = 3,..., The jitter of the first clock signal CLK1 may be reduced. I understand.

Here, for example, the jitter of the first clock signal CLK1 is reduced not only when it completely matches (2 × f2) / f1 = n, but also with the natural number n having a width (substantially). The effect of reducing the jitter is also exhibited for the natural number n) .

  FIG. 9 is a diagram for explaining the relationship between delay time and jitter by the jitter reduction circuit of this embodiment.

  In FIG. 9, the vertical axis indicates the period ([ps]) between the peaks of jitter riding on the first clock signal CLK1, and the horizontal axis indicates the delay time D1 ([ns]) applied to the first clock signal CLK1. The first delay time D1 given by the first delay control circuit 31 is shown.

  In FIG. 9, a curve L1 is obtained when the relationship of (2 × f2) / f1 = 2/3 is established, for example, when f1 = 200 [MHz] and f2 = 66.6 [MHz]. Is shown.

  In FIG. 9, a curve L2 is obtained when the relationship of (2 × f2) / f1 = 1/4 is established, for example, when f1 = 220 [MHz] and f2 = 27.5 [MHz]. Is shown.

  When the relationship shown in FIG. 8 described above ((2 × f2) / f1 = n, n is a natural number) is satisfied, the clock edge of the first clock signal CLK1 is similarly affected by the power supply noise of each cycle. The variation is the same every cycle, resulting in less jitter.

  As shown by the curve L1 in FIG. 9, when the relationship of (2 × f2) / f1 = 2/3 holds, the delay time (first delay time) D1 given to the first clock signal CLK1 is expressed as D1 = {1 Jitter can be reduced by setting / (2 × f2)} × 1.

  Further, as shown by the curve L1 in FIG. 9, when the relationship of (2 × f2) / f1 = 2/3 holds, D1 is changed to D1 = {1 / (2 × f2)} × 2 and D1 = { Jitter can also be reduced by setting 1 / (2 × f2)} × 3.

  That is, it can be seen that the jitter can be reduced by setting the first delay time D1 applied to the first clock signal CLK1 to D1 = {1 / (2 × f2)} × n (n is a natural number).

  Further, as shown by the curve L2 in FIG. 9, when the relationship of (2 × f2) / f1 = 1/4 holds, the first delay time D1 given to the first clock signal CLK1 is expressed as D1 = {1 / ( By setting 2 × f2)} × 1, jitter can be reduced.

  Note that in the curve L2 of FIG. 9, only the location of D1 = {1 / (2 × f2)} × 1 (D1 = 18.2 [ns]) is shown, but the other locations are the same as the curve L1. It is. That is, the jitter can be reduced by setting the first delay time D1 applied to the first clock signal CLK1 to D1 = {1 / (2 × f2)} × n (n is a natural number).

  Specifically, for example, by providing the first delay time D1 applied to the first clock signal CLK1, the jitter that has been close to 300 [ps] can be reduced to about 50 [ps].

  The first delay time D1 controlled by the first delay control circuit 31 with respect to the first clock signal CLK1 has been described above. However, the second delay controlled by the second delay control circuit 32 with respect to the second clock signal CLK2 is described. The same applies to the time D2.

Accordingly, when the first delay time (path delay) D1 of the first clock signal CLK1 with jitter satisfies the following relationship with the frequency f2 of the second clock signal CLK2 input to the circuit that generates power supply noise. , Less jitter.
D1 = {1 / (2 × f2)} × n (n is a natural number)

  The path delay D1 is a signal propagation time from the clock generation circuit to output to a digital circuit or an external circuit.

  This is because the delay time fluctuates when the power supply voltage fluctuates in the clock buffer. For example, the higher the power supply voltage, the smaller the delay, and the lower the power supply voltage, the larger the delay.

  When the path delay D1 becomes the same as the power supply noise cycle 1 / (2 × f2), the delay variation caused by the power supply noise during the propagation of the clock signal becomes the same every cycle, so the clock cycle between cycles. No longer fluctuates.

  That is, since the effect that the clock signal is propagated in a state where the power supply voltage is constant with the average value of the power supply noise voltage value is obtained, jitter is reduced.

  Note that the first delay time D1 given to the first clock signal CLK1 in order to reduce the jitter is not only in the case where D1 = {1 / (2 × f2)} × n completely coincides with the natural number n. Needless to say, the effect of reducing the jitter is also exerted on those having a thickness of.

  FIG. 10 is a timing chart for explaining the operation of the jitter reduction circuit of FIG. Here, reference numerals count1 and count2 correspond to the count value count output from the binary counter 111 in FIG.

  Here, the count value count1 indicates the count value output from the binary counter 111 in the first frequency measurement circuit 11, and the count value count2 indicates the count value output from the binary counter 111 in the second frequency measurement circuit 12. Indicates.

  The left half of FIG. 10 shows the case where the first clock signal CLK1 is not jittered and the first clock signal CLK1 is output as it is as the control clock signal CLK1 ′ (when CNT1 = “0”).

  In the right half of FIG. 10, the first clock signal CLK1 has jitter, and a signal obtained by giving a predetermined delay time D1 to the first clock signal CLK1 is output as the control clock signal CLK1 ′ (CNT1). = "1").

  In FIG. 10, the predetermined delay time D1 given to the first clock signal CLK1 is D1 = 1 / (2 × f2). Further, the relationship of (2 × f2) / f1 = 1/4 shown in the curve L2 of FIG. 9 described above is established between the frequencies f1 and f2 of the two clocks CLK1 and CLK2.

  As shown in FIG. 10, in the embodiment described with reference to FIGS. 2 to 7, first, the frequency of the first and second clock signals CLK <b> 1 and CLK <b> 2 by the first and second frequency measurement circuits 11 and 12. Is measured by counting with the reference clock signal ref-clk.

  Further, the first clock frequency data f1data and the second clock frequency data f2data are supplied from the first and second frequency measurement circuits 11 and 12 to the frequency comparison determination circuit 20, and the frequency comparison determination circuit 20 receives the control signals CNT1 and CNT2. Output.

  That is, as described with reference to FIGS. 3 and 4, the binary counter 111 starts counting, for example, with the rise of the first clock signal CLK1. Then, the first and second count values count1 and count2 are held in the register 112 as the first and second clock frequency data f1data and f2data when the first clock signal CLK1 falls.

  Specifically, the first clock frequency data f1data is “4”, and the second clock frequency data f2data is “16”.

  The frequency comparison / determination circuit 20 performs fixed-point arithmetic based on the first and second clock frequency data f1data and f2data obtained by the frequency measurement circuit.

  That is, as described with reference to FIG. 5, the first calculator 201 calculates (2 × f1data) / f2data, and the second calculator 202 calculates (2 × f2data) / f1data. .

  Furthermore, as described with reference to FIG. 6, the first and second determination circuits 203 and 204 based on the result of the calculation use a quotient obtained by the calculation of the first and second calculators 201 and 202 to calculate several decimal bits. The logical sum is taken and the first and second delay control signals CNT1 and CNT2 are output.

  That is, by taking the logical sum of several bits in the quotient of the operation, the natural number n is given a width, and the natural number having the width (error) satisfies the relationship of (2 × f2) / f1 = n. Determine whether or not.

  As described above, this is not only the case where (2 × f2) / f1 = n completely matches (formula is satisfied), but also the effect of reducing jitter not only when the natural number n has a width. This is because

  If the relationship of (2 × f2) / f1 = n is not satisfied with respect to the natural number having a width, the first and second delay control signals CNT1 and CNT2 are made active (“H”).

  Accordingly, as described with reference to FIG. 7, in the first and second delay control circuits 31 and 32, if the first and second delay control signals CNT1 and CNT2 are active (“H”), the first First and second delay times D1 and D2 are applied to the first and second clock signals CLK1 and CLK2.

  On the other hand, if the first and second delay control signals CNT1 and CNT2 are inactive ("L"), the first and second delay control circuits 31 and 32 receive the input first and second clock signals CLK1, CLK2 is output as it is.

  FIG. 11 is a diagram for explaining the conditions for low jitter in the jitter reduction circuit of this embodiment. Here, f1 = 200 [MHz] and f1data = 20. That is, a case is shown in which counting is performed with a reference clock signal ref-clk of 4 [GHz].

  As shown in FIG. 11, when the frequency of the second clock signal CLK2 is 100, 200 and 400 [MHz] with respect to the first clock signal CLK1 having a frequency of 200 [MHz], (2 × f2) / f1. And (2 × f1data) / f2data are 1.0, 2.0, and 4.0.

  For example, when the frequency of the second clock signal CLK2 is 100 [MHz], (2 × f2) / f1 = 1, the first delay control signal CNT1 is inactive (“L”), and the first delay control circuit 31 Outputs the first clock signal CLK1 as it is as the first control clock signal CLK1 ′.

  On the other hand, for example, when the frequency of the second clock signal CLK2 is 150 [MHz], (2 × f2) / f1 and (2 × f1data) /f2data=1.5. At this time, the first delay control circuit 31 is The first clock signal CLK1 is output with a predetermined first delay time D1.

  Here, the first delay time D1 when the frequency of the second clock signal CLK2 is 150 [MHz] is (2 × f2) /f1=1.5, and the first delay control circuit 31 is, for example, D1 = 1 / (2 × f2) ≈3.3 [ns].

  Then, the first delay control circuit 31 gives a first delay time D1 of 3.3 [ns] to the first clock signal CLK1, and outputs it as the first control clock signal CLK1 ′. At this time, the first delay control signal CNT1 is active (“H”).

  With the above control, the amount of delay variation of the clock signal with jitter can be made the same every cycle, and the jitter can be reduced. Further, even for a semiconductor integrated circuit having a function of changing the frequency of the clock signal, the path delay (delay time) can be controlled according to the changed clock frequency, and a dynamic jitter countermeasure can be taken.

  As described above, according to the present embodiment, it is possible to reduce clock jitter in a semiconductor integrated circuit that operates with a plurality of clock signals without performing power supply separation in each clock circuit, and to respond to dynamic clock frequency changes. Jitter countermeasures can be provided.

  In the above description, an example of a semiconductor integrated circuit using two clock signals having different frequencies has been described. However, the number of clock signals is not limited to two, and a larger number may be used. The control is performed for any two clock signals.

Regarding the embodiment including the above examples, the following supplementary notes are further disclosed.
(Appendix 1)
A first frequency measuring circuit for measuring a first frequency of the first clock signal;
A second frequency measuring circuit for measuring a second frequency of the second clock signal;
A frequency comparison determination circuit that compares the measured first and second frequencies and determines whether the first and second frequencies have a predetermined relationship;
A first delay control circuit that receives a first control signal from the frequency comparison determination circuit and controls a delay of the first clock signal to reduce jitter due to the second clock signal. Reduction circuit.

(Appendix 2)
In the jitter reduction circuit according to attachment 1,
When the first frequency is f1 and the second frequency is f2, when the 2 × f2 / f1 is a natural number having a width, the comparison / determination circuit performs the first delay control circuit in the first delay control circuit. When the first control signal is output so as not to delay the one clock signal, and 2 × f2 / f1 is not a natural number having a width, the first clock signal is added to the first clock signal by the first delay control circuit. A jitter reduction circuit for outputting the first control signal so as to give one delay time.

(Appendix 3)
In the jitter reduction circuit according to attachment 2,
The comparison determination circuit includes:
A first calculator that calculates 2 × f2 / f1,
A jitter reduction circuit comprising: a first determination circuit that outputs a first control signal by taking a logical sum of several bits of a decimal value by a quotient obtained by an operation of the first arithmetic unit.

(Appendix 4)
In the jitter reduction circuit according to appendix 2 or 3,
The jitter reduction circuit according to claim 1, wherein the first delay time is given by {1 / (2 × f2)} × n, where n is a natural number.

(Appendix 5)
In the jitter reduction circuit according to any one of appendices 1 to 4,
A jitter reduction circuit comprising: a second delay control circuit that receives a second control signal from the frequency comparison determination circuit and controls a delay of the second clock signal to reduce jitter due to the first clock signal. .

(Appendix 6)
In the jitter reduction circuit according to attachment 5,
When the first frequency is f1 and the second frequency is f2, when the 2 × f1 / f2 is a natural number having a width, the comparison / determination circuit performs the second delay control circuit in the second delay control circuit. When the second control signal is output so as not to give a delay to the two clock signals, and 2 × f1 / f2 is not a natural number having a width, the second delay control circuit adds the second clock signal to the second clock signal. A jitter reduction circuit for outputting the second control signal so as to give two delay times.

(Appendix 7)
In the jitter reduction circuit according to attachment 6,
The comparison determination circuit includes:
A second computing unit for computing 2 × f1 / f2;
A jitter reduction circuit comprising: a second determination circuit that outputs a second control signal by calculating a logical sum of several bits of a decimal value by a quotient obtained by an operation of the second arithmetic unit.

(Appendix 8)
In the jitter reduction circuit according to appendix 6 or 7,
The jitter reduction circuit according to claim 1, wherein the second delay time is given by {1 / (2 × f1)} × n, where n is a natural number.

(Appendix 9)
A semiconductor integrated circuit having the jitter reduction circuit according to any one of appendices 1 to 4, further comprising:
A first internal circuit for receiving a first control clock signal from the first delay control circuit;
And a second internal circuit for receiving the second clock signal.

(Appendix 10)
A semiconductor integrated circuit having the jitter reduction circuit according to any one of appendices 5 to 8, further comprising:
A first internal circuit for receiving a first control clock signal from the first delay control circuit;
And a second internal circuit for receiving a second control clock signal from the second delay control circuit.

DESCRIPTION OF SYMBOLS 1,50 Semiconductor integrated circuit 10 Jitter reduction circuit 11 1st frequency measurement circuit 12 2nd frequency measurement circuit 20 Frequency comparison determination circuit 31 1st delay control circuit 32 2nd delay control circuit 41 1st internal circuit 42 2nd internal circuit 51 Clock buffer 52 Data block 53 Clock driver 54 Data driver 111 Binary counter 112 Register 113, 114 Inverter 201 First arithmetic unit 202 Second arithmetic unit 203 First determination circuit 204 Second determination circuit 301 to 30m Buffer 311, 312 Selection circuit 500 Semiconductor package

Claims (4)

A first frequency measuring circuit for measuring a first frequency of the first clock signal;
A second frequency measuring circuit for measuring a second frequency of the second clock signal;
A frequency comparison determination circuit that compares the measured first and second frequencies and determines whether the first and second frequencies have a predetermined relationship;
Receiving said first control signal from the frequency comparison determination circuit, have a, a first delay control circuit that reduces the jitter by the second clock signal to control the delay of the first clock signal,
The comparison determination circuit sets the first clock signal in the first delay control circuit when 2 × f2 / f1 is a substantially natural number when the first frequency is f1 and the second frequency is f2. The first control signal is output so as not to give a delay to the output signal. When 2 × f2 / f1 is not a natural number, the first delay control circuit gives the first delay time to the first clock signal. And outputting the first control signal to a jitter reduction circuit. The jitter reduction circuit according to claim 1 ,
The comparison determination circuit includes:
A first calculator that calculates 2 × f2 / f1,
A jitter reduction circuit comprising: a first determination circuit that outputs a first control signal by taking a logical sum of several bits of a decimal value by a quotient obtained by an operation of the first arithmetic unit. The jitter reduction circuit according to claim 1 or 2 ,
The jitter reduction circuit according to claim 1, wherein the first delay time is given by {1 / (2 × f2)} × n, where n is a natural number. A semiconductor integrated circuit having a jitter reduction circuit according to any one of claims 1 to 3 further
A first internal circuit for receiving a first control clock signal from the first delay control circuit;
And a second internal circuit for receiving the second clock signal.

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