JP5288979B2 - Clock phase estimation device - Google Patents

Description

  The present invention relates to a clock phase estimation device that estimates the phase of a clock used for demodulation.

  In a receiving apparatus of a wireless communication system, a process of synchronizing the timing of a clock used when demodulating a modulated signal with the timing of a clock when modulated by a transmitting apparatus is performed. This process is generally called clock synchronization. One of the technologies for realizing clock synchronization is to estimate the phase at the time of modulation (hereinafter referred to as “clock phase”) from the received analog signal, and to estimate the clock phase. There is a technique for establishing clock synchronization based on the above.

  Specifically, the received analog signal is amplified and frequency-converted to an intermediate frequency to perform quadrature detection. Here, the two components of the in-phase component and the quadrature component of the baseband signal after quadrature detection are added after squaring to obtain a clock phase estimation signal. Thereafter, DFT (Discrete Fourier Transform) processing is performed on the clock phase estimation signal to generate a frequency domain signal, and the clock phase is estimated. Such a technique is disclosed in the following Non-Patent Document 1.

Yoichi Matsumoto, et al. "A study of an all-digital high-speed clock recovery circuit -Storage type clock recovery method-" IEICE Technical Report SAT90-31 (P.13-18)

  However, according to the above conventional technique, when estimating the clock phase, if the roll-off rate of the waveform shaping filter on the transmission / reception side is small (in the case of a low roll-off rate), the estimation accuracy of the clock phase decreases. There was a problem.

  In addition, when performing clock phase estimation using the received signal with the low roll-off rate, an observation time of the received signal used for clock phase estimation (an integrator used in DFT processing) is used to improve estimation accuracy. It is necessary to lengthen the integration time. However, when receiving a discrete signal such as a burst signal, there is a problem that the estimation accuracy of the clock phase is lowered due to the influence of noise when there is no signal.

  The present invention has been made in view of the above, and an object of the present invention is to obtain a clock phase estimation device that can prevent a decrease in accuracy of estimation of a clock phase even in a received signal with a low roll-off rate.

  In order to solve the above-described problems and achieve the object, the present invention separately limits the in-phase component and the quadrature component of the signal used for clock phase estimation among the signals after the quadrature detection of the received signal. Limiter means for processing, clock component extraction means for individually extracting clock components from each signal after the limiter processing by performing waveform shaping using a filter having a higher roll-off rate than normal communication, and Each of the clock components extracted by the clock component extraction means is squared, the squared values are added, and the result is used as a clock phase estimation signal. Phase estimation means for estimating the clock phase based on the clock phase.

  According to the present invention, even in the case of a received signal with a low roll-off rate, it is possible to prevent a reduction in clock phase estimation accuracy.

  Embodiments of a clock phase estimation apparatus according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

Embodiment 1 FIG.
First, a receiving apparatus including a clock phase estimation apparatus (clock phase estimation unit) according to the present invention will be described. FIG. 1 is a diagram illustrating a configuration example of a receiving apparatus. The receiving apparatus includes an antenna unit 100, an RF unit 110, an IF unit 120, a quadrature detection unit 130, a clock phase estimation unit 140, a clock recovery unit 150, and a detection unit 160.

  In the receiving apparatus of the present embodiment, the antenna unit 100 receives a signal, the RF unit 110 amplifies the received signal, the IF unit 120 converts the amplified received signal to an intermediate frequency, and the quadrature detection unit 130 further Convert to baseband signal. The baseband signal includes two components, an in-phase component (Ich) and a quadrature component (Qch). The quadrature detection unit 130 outputs the baseband signal to the clock phase estimation unit 140 and the detection unit 160. The clock phase estimation unit 140 estimates the clock phase on the transmission device side from the baseband signal. Based on the estimated clock phase, the clock recovery unit 150 performs clock recovery for data sample extraction in the detection unit 160. In the present embodiment, a case will be described in which QPSK (Quadrature Phase Shift Keying) is adopted as a modulation method. In QPSK, since the amplitude component varies according to the change of the data symbol, the amplitude information includes a clock component.

  Next, the clock phase estimation unit 140 according to the present embodiment will be described. FIG. 2 is a diagram illustrating a configuration example of the clock phase estimation unit 140. The clock phase estimating unit 140 includes a limiter unit 1, a filter unit 2, a squarer 3, a filter unit 4, a squarer 5, an adder 6, a DFT (Discrete Fourier Transform) processing unit 7, The phase calculation unit 8 is configured. The DFT processing unit 7 includes a multiplier 71, an integrator 72, a multiplier 73, and an integrator 74.

  The limiter unit 1 suppresses the noise component of the baseband signal. The filter units 2 and 4 extract clock components. The squarer 3 squares the in-phase component of the filter unit 2 output. The squarer 5 squares the orthogonal component of the output of the filter unit 4. Thereafter, the adder 6 adds the square values calculated by the squarer 3 and the squarer 5. The DFT processing unit 7 performs DFT processing on the output signal of the adder 6. Specifically, the multiplier 71 multiplies the output signal of the adder 6 by a clock frequency component, and the integrator 72 averages the output signal of the multiplier 71 to perform an in-phase component (X ) Is calculated. The multiplier 73 multiplies the output signal of the adder 6 by the clock frequency component, and the integrator 74 averages the output signal of the multiplier 73 to calculate the orthogonal component (Y) of the clock. To do. The phase calculation unit 11 calculates a phase based on the in-phase component (X) and the quadrature component (Y).

  Next, the operation of the clock phase estimation unit 140 configured as described above will be described in more detail. The limiter unit 1 receives the in-phase component (Ich) and the quadrature component (Qch) of the baseband signal from the quadrature detection unit 130, and suppresses the noise component by passing this signal. At this time, the signal constellation after passing through the limiter unit 1 has a constant signal amplitude. FIG. 3 is a diagram illustrating the signal amplitude after passing through the limiter unit 1. The signal amplitude is constant and becomes a constant envelope, and the constellation is circular.

  The filter unit 2 inputs a signal after passing through the limiter unit 1. Further, the filter unit 4 inputs a signal after passing through the limiter unit 1. The filter units 2 and 4 extract a clock component from a signal having a constant amplitude component. FIG. 4 is a diagram illustrating a configuration example of the filter units 2 and 4. The filter units 2 and 4 have the same configuration, and include an inverse sinc correction filter unit 21 and a full roll-off filter unit 22. The inverse sinc correction filter unit 21 converts the signal after passing through the limiter unit 1 into an impulse response system. The full roll-off filter unit 22 shapes the signal converted by the inverse sinc correction filter unit 21 into a signal waveform having a higher roll-off rate than normal communication.

  Here, the roll-off rate will be described. FIG. 5 is a diagram showing the shape of the frequency spectrum when the roll-off rate α is changed. The roll-off rate α is changed from 0 to 1. Here, “T” is a symbol period. As the roll-off rate α is lower (closer to “0”), the occupied bandwidth is reduced and the frequency utilization efficiency is improved. However, because the signal waveform attenuates steeply from the passband to the stopband, the signal waveform has large fluctuations in the impulse response waveform other than the ideal sampling point (Nyquist point), and is easily affected by timing jitter. The error increases. On the other hand, as the roll-off rate α is higher (closer to “1”), the occupied bandwidth increases and the frequency utilization efficiency deteriorates. However, since the attenuation from the passband to the stopband becomes gradual, the signal waveform has a small fluctuation in the impulse response waveform other than at the Nyquist point, is not easily affected by timing jitter, and the clock phase estimation error is small.

  In this embodiment, the characteristics of a reception filter that has been generally used in the past are described in detail. “The larger the roll-off rate α, the gentler the signal waveform becomes, and it is less affected by timing jitter. The estimation error is reduced ”. That is, in normal communication, the lower the roll-off rate, the better the transmission efficiency. Therefore, when transmitting and receiving in a low roll-off rate state and estimating the clock phase, only the signal used for estimating the clock phase is normal. Waveform shaping is performed to increase the roll-off rate over communication. Thereby, the estimation error of the clock phase is reduced, and as a result, it is possible to prevent the estimation accuracy of the clock phase from being lowered.

  Therefore, the full roll-off filter unit 22 extracts a clock component from a signal having a constant amplitude component whose noise component is suppressed by the limiter unit 1, and the extracted signal has a pseudo full roll-off rate α that is high ( By shaping the waveform into a waveform close to α = 1 or close to α = 1, the accuracy of estimating the clock phase is prevented. An inverse sinc correction filter unit 21 having inverse sinc correction characteristics is provided in front of the full roll-off filter unit 22, and a signal that has become a rectangular wave by the limiter processing of the limiter unit 1 is returned to the impulse response system. The frequency spectrum of the inverse sinc correction filter unit 21 is expressed by Expression (1).

H (f) = (πfT) / sin (πfT) (1)
("T" is a symbol period)

  The clock phase estimation unit 140 according to the present embodiment includes the limiter unit 1 and the filter units 2 and 4, and performs the above processing, so that a signal used for clock phase estimation has a higher roll-off rate than normal communication. Shape into a waveform. The processes after the filter process by the filter units 2 and 4 are the same as the conventional processes. For example, the squarer 3 inputs an in-phase component that is an output of the filter unit 2 and calculates a square value. The squarer 5 receives an orthogonal component that is an output of the filter unit 4 and calculates a square value. The adder 6 adds the outputs from the squarers 3 and 5 to generate a clock phase estimation signal.

  Thereafter, the DFT processing unit 7 performs DFT processing and extracts a signal corresponding to the clock frequency component. Specifically, the DFT processing unit 7 multiplies the clock phase estimation signal from the adder 6 by “cos (ω · k · Ts)”, which is a clock frequency component, by the multiplier 71, and then integrates the integrator. The in-phase component (X) of the clock is obtained by averaging at 72. Similarly, the clock phase estimation signal from the adder 6 is multiplied by the clock frequency component “sin (ω · k · Ts)” by the multiplier 73 and then averaged by the integrator 74. Obtain the orthogonal component (Y) of the clock. “Ω” is an angular frequency, “k” is a sample number, and “Ts” is a sample period. Finally, the phase calculation unit 8 calculates (estimates) the clock phase θ from Equation (2) based on the in-phase component (X) and the quadrature component (Y), and sends the estimated clock phase θ to the clock recovery unit 150. Output.

θ = tan ⁻¹ (Y / X) (2)

  As described above, in the present embodiment, in the clock phase estimation unit, the noise component is suppressed by the limiter process, the signal after passing through the limiter is corrected, and a full / higher roll-off rate is obtained than in normal communication. After shaping the waveform into a roll-off waveform signal, the clock phase was estimated. As a result, it is possible to prevent a decrease in the estimation accuracy of the clock phase even in a received signal with a low roll-off rate.

  In addition, by suppressing the noise component, it is possible to prevent a decrease in accuracy of estimation of the clock phase even in a low C / N (Carrier to Noise Ratio).

  Furthermore, since it is possible to prevent a decrease in clock phase estimation accuracy, it is possible to suppress timing jitter during clock recovery. Further, it is possible to avoid deterioration in communication quality without degrading accuracy when extracting sample data corresponding to the Nyquist point.

  In this embodiment, the method for estimating the clock phase by performing the DFT process based on the clock phase estimation signal that is the output signal of the adder 6 is described, but the present invention is not limited to this. For example, the clock phase can be estimated by replacing the processing after DFT with processing such as a zero cross method.

  In this embodiment, QPSK is described as an example of the modulation signal, but the present invention is not limited to this. For example, the present invention can also be applied to a modulation scheme having a constant envelope such as 8PSK, 16QAM (16 Quadrature Amplitude Modulation), or the like, or GMSK (Gaussian filtered Minimum Shift Keying).

  In this embodiment, the clock component extraction filter process is configured to perform a full roll-off filter process after the inverse sinc correction filter process, but there is no particular rule regarding the context of the process. . Therefore, the inverse sinc correction filter process may be performed after the full roll-off filter process. In addition, in order to reduce the filter processing, a convolution of the impulse response used in the inverse sinc correction filter and the full roll-off filter is used as a filter coefficient, so that, for example, a single FIR (Finite Impulse Response) filter is used. May be.

Embodiment 2. FIG.
Although the first embodiment has been described on the assumption that a continuous signal is a received signal, the present embodiment will describe a case where a burst signal that is a discrete signal is received. Here, differences from the first embodiment will be described.

  FIG. 6 is a diagram illustrating a configuration example of the clock phase estimation unit 140 according to the present embodiment. The clock phase estimation unit 140 includes squarers 9 and 10, an adder 11, a filter unit 12, and a multiplier 13. The squarer 9 calculates the square value of the in-phase component of the baseband signal. The squarer 10 calculates the square value of the orthogonal component of the baseband signal. The adder 11 adds the square values from the squarers 9 and 10 to obtain signal power. The filter unit 12 smoothes the signal power. The multiplier 13 weights the clock phase estimation signal in proportion to the signal power after smoothing. Other configurations are the same as those of the first embodiment described above, and thus description thereof is omitted.

  Next, the operation of the clock phase estimation unit 140 of this embodiment will be described in detail. The squarer 9 calculates the square value of the in-phase component (Ich) of the baseband signal from the quadrature detection unit 130. The squarer 10 calculates the square value of the quadrature component (Qch). The adder 11 adds the square values from the squarers 9 and 10 to calculate the signal power of the received signal. Since the signal power includes a noise component, the filter unit 12 smoothes the signal power. Smoothing can be realized, for example, by performing a simple filtering process such as a moving average filter. The multiplier 13 weights the clock phase estimation signal output from the adder 6 in proportion to the smoothed signal power output from the filter unit 12. The multiplier 13 outputs the weighted clock phase estimation signal to the DFT processing unit 7. The subsequent processing is the same as the processing described above.

  In general, in a burst signal, noise increases during a period in which there is no signal (not received). Therefore, since the clock phase estimation signal calculated during that period is affected by noise, the accuracy is reduced even if the clock phase is estimated based on this clock phase estimation signal. In the DFT processing unit 7, the time required for integration in the integrators 72 and 74 (observation period) is longer than the symbol size of the burst signal. Therefore, the observation period includes both a period during which the receiving apparatus receives a signal and a period during which the signal is not received. As a result, the DFT processing is performed based on both the clock phase estimation signal affected by noise and the clock phase estimation signal not affected by noise. The estimation accuracy of was reduced.

  Therefore, in this embodiment, the clock phase estimation signal output from the adder 6 is weighted by multiplying the signal power. The signal power is large during the period in which the receiving apparatus receives the signal, and the signal power is small during the period in which the signal is not received. Therefore, the value obtained by multiplying the clock phase estimation signal by the signal power during the period in which the receiving apparatus receives the signal is larger than the value obtained by multiplying the clock phase estimation signal by the signal power in the period during which no signal is received. Value. That is, the weight of the clock phase estimation signal during the period of receiving the signal is increased, and the weight of the clock phase estimation signal during the period of not receiving the signal is decreased. Thereby, in the DFT processing, the influence degree of the clock phase estimation signal affected by the noise can be reduced, and the deterioration of the accuracy of the clock phase estimation can be prevented.

  As described above, in this embodiment, the clock phase estimation signal for estimating the clock phase is weighted in proportion to the signal power of the received signal. Thereby, in the case of receiving a burst signal, it is possible to prevent a decrease in accuracy of estimating the clock phase.

  Further, since the clock phase can be estimated with high accuracy, it is not necessary to insert a preamble pattern (known pattern) in advance in the burst signal so that the clock phase component can be easily extracted. Thereby, it is possible to prevent a decrease in transmission efficiency due to the preamble pattern insertion.

Embodiment 3 FIG.
In this embodiment, a case will be described in which the receiving apparatus is compatible with diversity. As in the second embodiment, each branch of the diversity-compatible receiving apparatus is configured to weight the clock phase estimation signal in proportion to the signal power. Here, differences from the above-described second embodiment will be described.

  FIG. 7 is a diagram illustrating a configuration example of the clock phase estimation unit 140 according to the present embodiment. The clock phase estimation unit 140 includes branches # 1 and # 2 and an adder 14. The branches # 1 and # 2 have the same configuration, and the configuration up to the previous stage of input to the DFT processing unit 7 in the second embodiment (limiter unit 1, filter unit 2, squarer 3, filter unit 4, squarer 5, the adder 6, the squarers 9, 10, the adder 11, the filter unit 12, and the multiplier 13). The adder 14 synthesizes a clock phase estimation signal weighted in proportion to the signal power of the received signal in each branch. Since other configurations are the same as those in the second embodiment, description thereof is omitted.

  Next, the operation of the clock phase estimation unit 140 of this embodiment will be described in detail. In each branch, as in the second embodiment, the clock phase estimation signal is weighted in proportion to the signal power of the received signal. Since the receiving apparatus according to the present embodiment is compatible with diversity, it is considered that the signal power of the received signal is different for each branch. Therefore, by performing weighting based on the signal power, it is possible to attach importance to the clock phase estimation signal of the branch having a good reception state.

  Thereafter, the adder 14 combines the weighted clock phase estimation signals output from the respective branches. In the combined clock phase estimation signal, the ratio of the clock phase estimation signal of the branch having a good reception state is large. The adder 14 outputs the combined clock phase estimation signal to the DFT processing unit 7. The subsequent processing is the same as the processing described above.

  As described above, in this embodiment, the clock phase estimation signal for estimating the clock phase is weighted in proportion to the signal power for each branch, and then the signal of each branch is synthesized. It was. As a result, the clock phase estimation can be performed with an emphasis on the clock phase estimation signal of the branch in a good reception state, so that it is possible to prevent a decrease in the estimation accuracy of the clock phase even during diversity reception.

  In the present embodiment, the case where there are two branches has been described. However, the present invention is not limited to this. By increasing the clock phase estimation signal for each branch input to the adder 14, it is possible to handle diversity reception of two or more branches.

  Moreover, although this Embodiment demonstrated based on Embodiment 2, it is possible to apply also when not weighting like Embodiment 1. FIG.

  As described above, the clock phase estimation apparatus according to the present invention is useful for estimating the phase of a clock used for demodulation, and is particularly suitable for a reception apparatus that receives a signal with a low roll-off rate.

It is a figure which shows the structural example of a receiver. 3 is a diagram illustrating a configuration example of a clock phase estimation unit according to the first embodiment. FIG. It is a figure which shows the constellation of the signal after a limiter part passage. It is a figure which shows the structural example of a filter part. It is a figure which shows the frequency spectrum shape when changing a roll-off rate. FIG. 10 is a diagram illustrating a configuration example of a clock phase estimation unit according to the second embodiment. FIG. 10 is a diagram illustrating a configuration example of a clock phase estimation unit according to the third embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Limiter part 2, 4, 12 Filter part 3, 5, 9, 10 Squarer 6, 11, 14 Adder 7 DFT processing part 8 Phase calculation part 13, 71, 73 Multiplier 72, 74 Integrator 100 Antenna part 110 RF unit 120 IF unit 130 Quadrature detection unit 140 Clock phase estimation unit 150 Clock recovery unit 160 Detection unit

Claims (9)

Limiter means for individually performing limiter processing on the in-phase component and the quadrature component of the signal used for clock phase estimation among the signals after quadrature detection of the received signal;
A clock component extracting means for individually extracting a clock component from each signal after the limiter processing by performing waveform shaping using a filter having a higher roll-off rate than normal communication;
Clock phase estimation signal calculation means that squares each clock component extracted by the clock component extraction means, adds the squared values, and uses the result as a clock phase estimation signal;
Phase estimation means for estimating the clock phase based on the clock phase estimation signal;
With
The clock component extraction means includes
An inverse sinc correction filter means for converting the signal after the limiter processing into an impulse response signal by an inverse sinc function;
Full roll-off filter means for shaping the converted signal into a signal waveform having a higher roll-off rate than normal communication;
A clock phase estimation apparatus comprising: Limiter means for individually performing limiter processing on the in-phase component and the quadrature component of the signal used for clock phase estimation among the signals after quadrature detection of the received signal;
A clock component extracting means for individually extracting a clock component from each signal after the limiter processing by performing waveform shaping using a filter having a higher roll-off rate than normal communication;
Clock phase estimation signal calculation means that squares each clock component extracted by the clock component extraction means, adds the squared values, and uses the result as a clock phase estimation signal;
Phase estimation means for estimating the clock phase based on the clock phase estimation signal;
With
The clock component extraction means includes
Full roll-off filter means for shaping the signal after the limiter processing into a signal waveform having a higher roll-off rate than normal communication;
An inverse sinc correction filter means for converting the shaped signal into an impulse response signal by an inverse sinc function;
Features and to torque lock phase estimation apparatus that comprises a. The clock phase estimation apparatus according to claim 1 or 2 , wherein the full roll-off filter means sets a roll-off rate to 1. The phase estimation means includes
4. The clock phase estimation apparatus according to claim 1 , wherein DFT (Discrete Fourier Transform) processing is performed on the clock phase estimation signal.   Limiter means for individually performing limiter processing on the in-phase component and the quadrature component of the signal used for clock phase estimation among the signals after quadrature detection of the received signal;
  A clock component extracting means for individually extracting a clock component from each signal after the limiter processing by performing waveform shaping using a filter having a higher roll-off rate than normal communication;
  Clock phase estimation signal calculation means that squares each clock component extracted by the clock component extraction means, adds the squared values, and uses the result as a clock phase estimation signal;
  Phase estimation means for estimating the clock phase based on the clock phase estimation signal;
  Average power calculating means for obtaining a received average power based on the signal after orthogonal detection of the received signal;
  Weighting means for weighting the clock phase estimation signal calculated by the clock phase estimation signal calculation means based on the received average power;
  With
  The clock phase estimation device, wherein the phase estimation means estimates a clock phase based on the weighted clock phase estimation signal. further,
Average power calculating means for obtaining a received average power based on the signal after orthogonal detection of the received signal;
Weighting means for weighting the clock phase estimation signal calculated by the clock phase estimation signal calculation means based on the received average power;
With
It said phase estimation means, the clock phase estimation apparatus according to any one of claims 1-4, characterized in that to estimate the clock phase on the basis of the clock phase estimation signal after the weighting. A clock phase estimation device in a diversity-compatible receiving device including a plurality of branches,
For each branch, the limiter means, the clock component extraction means, the clock phase estimation signal calculation means, the average power calculation means, and the weighting means,
further,
Synthesizing means for synthesizing clock phase estimation signals weighted by each branch;
With
7. The clock phase estimation apparatus according to claim 5 , wherein the phase estimation unit estimates a clock phase based on the clock phase estimation signal synthesized by the synthesis unit.   A clock phase estimation device in a diversity-compatible receiving device including a plurality of branches,
  For each branch,
  Limiter means for individually performing limiter processing on the in-phase component and the quadrature component of the signal used for clock phase estimation among the signals after quadrature detection of the received signal;
  A clock component extracting means for individually extracting a clock component from each signal after the limiter processing by performing waveform shaping using a filter having a higher roll-off rate than normal communication;
  Clock phase estimation signal calculation means that squares each clock component extracted by the clock component extraction means, adds the squared values, and uses the result as a clock phase estimation signal;
  Phase estimation means for estimating the clock phase based on the clock phase estimation signal;
  With
  further,
  Synthesizing means for synthesizing the clock phase estimation signal calculated by each branch;
  With
  The clock phase estimation apparatus, wherein the phase estimation means estimates a clock phase based on the clock phase estimation signal synthesized by the synthesis means. A clock phase estimation device in a diversity-compatible receiving device including a plurality of branches,
For each branch, the limiter means, the clock component extraction means, and the clock phase estimation signal calculation means,
further,
Synthesizing means for synthesizing the clock phase estimation signal calculated by each branch;
With
It said phase estimation means, the clock phase estimation apparatus according to any one of claims 1-4, characterized in that to estimate the clock phase on the basis of the clock phase estimation signal after the combining by the combining means.

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