JP5275673B2 - Multi-core system, vehicle gateway device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multi-core system and a gateway device for a vehicle for protecting data between zones in a multi-core system for varying the number of CPU cores in each zone. <P>SOLUTION: In this multi-core system 100 having a plurality of fixed core groups 11A and 11B having one or more cores and a pool core group 12 having a plurality of cores, the fixed core groups 11A and 11B are respectively connected to exclusive memories 13A and 13B, and the pool core group 12 is connected to all the exclusive memories 13A and 13B, and the core A which is equal to or more than 0 of the pool core group 12 is made to cooperate with the fixed core group 11A, and the core B which is equal to or more than 0 of the pool core group which is different from the core A is made to cooperate with the fixed core group 11B, and the core R which is equal to or more than 1 of the pool core group which is different from the core A and the core B relays the fixed core group A and the fixed core group B. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a multi-core system having a plurality of cores, and more particularly to a multi-core system in which a core is divided into zones and the number of cores per zone is variable.

A multi-core system in which a plurality of CPU cores are mounted on one die is known for reducing power consumption, leakage current, suppressing heat generation, and the like for a single core mounting one CPU core on one die. Since the processing efficiency of the multi-core system increases or decreases depending on the number of CPU cores assigned to a job, a technique for assigning a necessary number of CPU cores according to an execution job has been proposed (for example, see Patent Document 1). Patent Document 1 describes a multi-core system in which the number of CPU cores used simultaneously for each job class is registered in the job class definition table, and the management program allocates a predetermined number of CPU cores for each execution job. .
Japanese Patent No. 3541212

  However, since the multi-core system described in Patent Document 1 simply assigns a predetermined number of CPU cores, a group of CPU cores (hereinafter referred to as zones) assigned to different execution jobs may access the same memory as other zones. There is a problem that data protection between zones is not sufficient. For example, if the firewall server function is implemented in a multi-core system, and the firewall policy is dynamically changed with a single chip and the speeding up of filtering is taken into consideration, security is ensured that data access between zones is easy. Hard to secure.

  In view of the above-described problems, an object of the present invention is to provide a multi-core processor system in which the number of CPU cores for each zone is variable, and a multi-core system and a vehicle gateway device that improve data protection between zones.

In view of the above problems, the present invention provides a multi-core system having a plurality of fixed core groups having one or more cores and a pool core group having a plurality of cores, wherein each of the fixed core groups is connected to a dedicated memory, The pool core group is connected to all the dedicated memories, and the pool core group is assigned with one or more of a plurality of processes executed by at least one predetermined fixed core group of the plurality of fixed core groups. One or more assigned cores execute one or more of a plurality of processes assigned by accessing only a dedicated memory connected to the predetermined fixed core group to which the process is assigned, and one of the predetermined fixed core groups or more cores, and one or more cores of the stationary core groups other than the predetermined fixed core groups, perform each fixed core group access to each of the dedicated memory One or more of the plurality of processes is executed, and one or more cores of the pool core group other than the assigned core read data stored in the dedicated memory in which the predetermined fixed core group is connected to the predetermined fixed core group Stored in the dedicated memory connected to a fixed core group other than the predetermined fixed core group, or a fixed core group other than the predetermined fixed core group stored in the dedicated memory connected to the fixed core group. Data is read out and stored in the dedicated memory connected to the predetermined fixed core group or in the dedicated memory different from the read-out dedicated memory.

  According to the present invention, when the processing load is high in the fixed core group, processing can be performed using the cores of the pool core group, so that the processing load of the entire multi-core system can be reduced. Moreover, since each fixed core group has a dedicated memory, it is easy to ensure security between the fixed core groups.

Moreover, in one form of this invention, a firewall is implement | achieved by the core of the said pool core group other than the said allocation core , It is characterized by the above-mentioned.

  According to the present invention, the pool core group functions as a firewall, so that security between the fixed core groups can be ensured.

The number of the allocated cores or the number of cores of the pool core group other than the allocated cores that write data from the dedicated memory to another dedicated memory is variable. According to the present invention, since the number of cores used by the fixed core group can be made variable, it is possible to flexibly cope with changes (addition / deletion) of data processing amount and hardware.

  The multi-core system according to claim 1, wherein a core of the pool core group is a general-purpose core. According to the present invention, since a general OS can be executed in a pool core group, software portability can be improved.

Further, the number of the assigned cores , or the number of cores of the pool core group other than the assigned core that writes data from the dedicated memory to another dedicated memory is specified by setting information stored in a storage unit. It is characterized by that. According to the present invention, the number of cores A and the number of cores B can be designated from the outside.

The number of allocation cores, the processing to allocate core is dynamically changed according to the load condition of the predetermined fixed core group assigned, it is characterized.

  According to the present invention, the necessary minimum number of cores can be secured by the processing load, so even when a processing request is generated from the other fixed core group, the fixed core group that has previously requested processing occupies the cores of the pool core group. Can be prevented.

  A multi-core processor system in which the number of CPU cores for each zone is variable, and a multi-core system and a vehicle gateway device that improve data protection between zones can be provided.

  Hereinafter, the best mode for carrying out the present invention will be described with reference to the drawings.

  FIG. 1 shows a configuration diagram of a multi-core system 100 of the present embodiment. As shown in FIG. 1, the multi-core system according to the present embodiment is divided into a plurality of computing zones A and B, and the number of cores in the computing zones A and B can be increased or decreased. By passing data between A and B, the zones are protected from each other (hereinafter simply referred to as zones when computing zone A, computing zone B, and routing zone 14 are not distinguished).

  1 is a one-chip type having a plurality of CPU cores and a plurality of caches in one die (hereinafter referred to as a chip). The multi-core system 100 includes a zone fixed core group 11A having one or more CPU cores, a cache 13A, a pool zone core group 12 having a plurality of CPU cores, a zone fixed core group 11B having one or more CPU cores, and a cache 13B. . Each CPU core includes an arithmetic circuit (ALU (Arithmetic Logic Unit)), a program counter, an internal cache, a register, and the like.

  In such a configuration, the multi-core system 100 sets whether the CPU core of the pool zone core group 12 belongs to the zone fixed core group 11A or the zone fixed core group 11B based on the core configuration information 16 stored in advance, for example. (There is a CPU core that is not assigned to any of them, and the CPU core that is not assigned corresponds to the CPU core R in the claims). Thereby, the CPU core of the zone fixed core group 11A and the CPU core of the pool zone core group 12 form one computing zone A, and the CPU core of the zone fixed core group 11B and the CPU core of the pool zone core group 12 are one. One computing zone B is formed. Each CPU core in the computing zone A and each CPU core in the computing zone B cooperate to execute a series of processes.

  Therefore, for example, the number of CPU cores included in one zone allocated to a predetermined series of processes can be increased or decreased. Note that a series of processes does not mean one OS or a single function, but a plurality of processes on one OS and a plurality of processes executed on each OS when a plurality of OSs are executed. including. A virtual machine (for example, Java (registered trademark) VM) may be executed on the OS. In this case, since the virtual machine absorbs an execution environment specific to the OS, the versatility required for the general-purpose core can be reduced.

  The core configuration information 16 is stored in advance in the nonvolatile memory of the pool zone core group 12. The core configuration information 16 defines an initial state at the time of startup, for example. Thereby, the number of CPU cores assigned to the computing zones A and B at the time of activation can be determined.

  FIG. 2A shows an example of the core configuration information 16. In FIG. 2A, allocation to the computing zone A, the computing zone B, or the routing zone 14 is determined for each CPU core.

  The core configuration information 16 may be transmitted from the outside and stored. Thereby, assignment of CPU cores can be designated from the outside, and the number of CPU cores assigned to the computing zones A and B can be made variable.

  In FIG. 2B, the number of CPU cores in the initial state assigned to the computing zone A, the computing zone B, and the routing zone 14 is determined, and the range of increase / decrease is specified. With the core configuration information 16 as shown in FIG. 2B, it is possible to increase the number of CPU cores allocated to processing with a heavy load while maintaining the lower and upper limits allocated to the computing zones A and B. it can. The initial state, lower limit, and upper limit core configuration information 16 may be determined by an allocation rate such as a percentage instead of the number of CPU cores.

  Further, as shown in FIG. 2A or FIG. 2B, the routing of the pool zone core group 12 is performed without setting the number of CPU cores assigned to the computing zones A and B in the initial state in the core configuration information 16. All except for at least one CPU core (corresponding to the CPU core R in the claims) assigned to the zone 14 is left unassigned, and the CPU core is assigned to the computing zone A, B or the routing zone 14 depending on the load situation. May be assigned.

  2A and 2B also define the assignment of the routing zone 14, but a CPU core that is not assigned to any of the computing zones A and B may be assigned to the routing zone 14. In this case, the capacity of the core configuration information 16 can be suppressed.

  The cache 13A is a cache memory dedicated to the fixed zone core group 11A, and the cache 13B is a cache memory dedicated to the fixed zone core group 11B. The CPU core of the pool zone core group 12 assigned to the computing zone A can access only the cache 13A, and the CPU core of the pool zone core group 12 assigned to the computing zone B can access the cache 13B. Is only accessible. Therefore, even if the zone to which the CPU core of the pool zone core group 12 belongs is variable, data communication is not performed directly from the computing zone A to B (or vice versa) during processing.

  The CPU cores of the pool zone core group 12 are connected to all the caches 13A and 13B. The pool zone core group 12 constitutes a routing zone 14 by CPU cores that are not assigned to either the computing zone A or B. The CPU core of the routing zone 14 is responsible for data communication from the caches 13A to 13B or from the caches 13B to 13A, and data communication between the computing zones A and B can be executed only by the routing zone 14. Note that the number of CPU cores in the routing zone 14 is also variable.

  By the way, in the multi-core system 100, at least the CPU cores of the pool zone core group 12 are composed of general-purpose cores. For example, the general-purpose core means that a general OS (for example, LINUX (registered trademark), Window (registered trademark), UNIX (registered trademark)) operates, and does not necessarily mean that the market share or the number of shipments is large. The CPU cores of the zone-fixed core groups 11A and 11B may be general-purpose cores or dedicated cores specialized for specific processing.

  The CPU cores of the zone-fixed core group 11A or 11B may be homogeneous with the same architecture or heterogeneous with different architectures. All of the pool zone core groups 12 are homogeneous cores.

  With such a configuration, since data communication between zones always passes through the pool zone core group 12, security between zones can be improved. Since the number of CPU cores in the computing zone A or B can be increased, it is possible to flexibly cope with load fluctuations. Since the number of CPU cores allocated to the routing zone 14 can be increased, the quality of data communication between the zones can be improved. In addition, since the CPU core of the pool zone core group 12 can operate a general OS, general server software (for example, a firewall) can be easily ported.

[Example of application to vehicles]
An application example of the multi-core system 100 to a vehicle will be described. FIG. 3A shows a schematic diagram of a vehicle system 200 having the multi-core system 100. The vehicle system 200 in FIG. 2 is controlled by a multi-core system 100, and the multi-core system 100 is fixed to a printed circuit board 110 together with I / Os 27A and 27B and external memories 15A and 15B. The I / O 27A is connected to the communication device 21 via a CAN (controller area network) or a dedicated line, and the I / O 27B is similarly connected to the in-vehicle device 22.

  The communication device 21 is connected to, for example, a mobile phone base station or a wireless LAN access point and communicates with a predetermined server to receive information such as traffic information and map data. Road-to-vehicle communication or vehicle-to-vehicle communication may be performed. For example, when communicating with a mobile phone base station, the communication device 21 receives, for example, an 800 MHz band radio wave, performs amplification, filtering, distortion correction, etc., extracts a baseband signal, demodulates it according to QPSK, etc. Information is received by performing error correction and protocol processing. When transmitting information, the information is subjected to protocol processing, error correction processing, baseband signal generation processing, mixing with a carrier wave, etc., and the modulated wave is amplified by an amplifier and transmitted from an antenna.

  The in-vehicle device 22 is, for example, a control system such as an engine or a brake, a body system such as a meter display or a door lock, or an in-vehicle device such as a navigation device, and is controlled by the multi-core system 100 or received by the multi-core system 100. Executes control using. That is, the in-vehicle device 22 includes a controlled device such as a motor and a control device such as an ECU (Electronic Control Unit).

  The operation procedure of the vehicle system 200 will be described with reference to the flowchart of FIG. In the operation procedure of FIG. 4, the CPU core assignment of the pool zone core group 12 is dynamically switched.

  For example, when the multi-core system 100 is activated by ignition on, each CPU core of the pool zone core group 12 reads the core configuration information 16 and determines whether it belongs to the computing zone A, the computing zone B, or the routing zone 14. (S10).

  When the zone is determined, the program stored in the external memory 15A or 15B is read in order to execute the processing determined for each of the computing zone A, the computing zone B, and the routing zone 14 (S20). In this embodiment, the computing zone A implements an information transmission / reception unit 23 with the server, the computing zone B implements a control unit 25 that controls the in-vehicle device 22, and the routing zone 14 includes the gateway 26 and the resource distribution unit 24. Is realized.

  FIG. 3B shows a functional block diagram of the vehicle system 200. After activation, each functional block executes the following processing (S30). The functional block processing will be described.

  The information transmitting / receiving unit 23 determines, for example, whether or not the communication device 21 is communicable with the base station, and receives data such as traffic information and road map update information from the server if possible.

  The gateway 26 mainly performs data format conversion and filtering, and absorbs differences in data configuration and transmission speed transmitted and received between the server and the in-vehicle device 22 (hereinafter referred to as relay processing). For example, a CAN header or error correction code is attached to data transmitted from the server, and format conversion is performed to generate a predetermined data frame. In addition, since all the in-vehicle devices 22 do not need data transmitted from the server, transmission destination information for designating a predetermined in-vehicle device 22 in accordance with a predetermined filtering rule is included in the header. Conversely, when information is transmitted from the vehicle to the server, the header, error correction code, and the like are deleted from the CAN data frame, and only the data is extracted.

  When the gateway 26 relays the data subjected to the relay process, the gateway 26 acquires the address of the cache 13A where the data is stored from the information transmitting / receiving unit 23, and stores the data read from the cache 13A in the cache 13B. The control unit 25 reads the data in the cache 13B and controls the in-vehicle device 22 based on the data. For example, if the data is information that informs a traffic jam on a curve with a poor forward view, the driver is alerted by braking by the brake ECU, lighting of a meter lamp, or the like.

  When the vehicle transmits the vehicle speed and position information of the host vehicle as a probe car to the server, the control unit 25 acquires the vehicle speed and position information from the in-vehicle device 22 every predetermined cycle time, and makes a relay request to the gateway 26. The gateway 26 acquires the address of the cache 13B where the data is stored from the control unit 25, stores the data read from the cache 13B in the cache 13A, and requests the information transmission / reception unit 23 to transmit to the server.

  Thus, since the computing zones A and B communicate via the shared memory, high-speed data communication is possible.

  Further, the resource distribution unit 24 monitors the load states of the computing zones A and B, and distributes the resources of the pool zone core group 12 to the computing zones A and B (S40). Since the resource distribution unit 24 can be realized by a program executed by the same CPU core as that of the gateway 26, the routing zone 14 may have one CPU core.

  The resource distribution unit 24 calculates, for example, the average of the CPU load rates of the CPU cores of the computing zone A and the average of the CPU load rates of the CPU cores of the computing zone B every predetermined time, and the pool zone core group Twelve CPU cores are distributed to computing zone A or B.

CPU load factor of computing zone A >> CPU load factor of computing zone B When there are unassigned CPU cores in the pool zone core group 12, the resource distribution unit 24 uses unassigned CPU cores as computing zones. Assign to A. When there is no unassigned CPU core in the pool zone core group 12, the resource distribution unit 24 assigns the CPU core of the computing zone B to the computing zone A.

-CPU load factor of computing zone B >> CPU load factor of computing zone A When there are unassigned CPU cores in the pool zone core group 12, the resource distributor 24 assigns unassigned CPU cores to the computing zone. Assign to B. When there is no unassigned CPU core in the pool zone core group 12, the resource distribution unit 24 assigns the CPU core of the computing zone A to the computing zone B.

  Note that the resource distribution unit 24 may distribute the CPU cores of the pool zone core group 12 in response to a request from the computing zone A or B instead of determining the CPU core allocation. In this case, the resource distribution unit 24 assigns a priority to the computing zone A or B that has been requested from an unassigned CPU core, and if there is no unassigned CPU core, permits the other computing zone without a request. The CPU core is assigned to the requested computing zone.

  As described above, the multi-core system 100 executes the program while dynamically switching the CPU core assignment of the pool zone core group 12. Since the CPU cores of the pool core group 12 are general-purpose cores, various programs can be executed. Therefore, the number of CPU cores allocated to the computing zones A and B can be flexibly increased or decreased according to the processing load of the programs.

[Modification]
In FIG. 3B, the gateway 26 is realized in the routing zone 14, but a firewall may be realized instead of or together with the gateway 26. Since the CPU core of the pool zone core group 12 is a general-purpose core, a firewall program running on a general OS or a virtual machine can be executed and portability is high, and an increase in cost when applied to embedded software can be suppressed. The firewall permits access from the inside to an external server, but restricts access from the outside based on, for example, header information (address, port number, etc.) of the IP packet. The firewall in the routing zone 14 can dynamically change the firewall policy that determines this restriction aspect. Further, by mounting an associative memory in the caches 13A and 13B, a high-speed firewall can be realized with one chip.

  In this embodiment, the computing zones A and B are two, but the number of computing zones may be three or more. FIG. 5 shows a block diagram of a multi-core system 100 having three computing zones A, B, and C. 5 that are the same as those in FIG. 1 are assigned the same reference numerals, and descriptions thereof are omitted.

  In FIG. 5, a third zone-fixed core group 11C and a pair of third cache 13C are provided. Since the caches 13A to 13C are independent of each other, and the pool zone core group 12 is connected to the caches 13A to 13C, data communication between zones can be protected as in the above embodiment. The same configuration can be made with four or more computing zones.

  As described above, since the multi-core system 100 always passes data communication between zones via the pooled zone core group 12, security between zones can be improved. Data communication between zones is fast because it is via a shared memory.

  Since the number of CPU cores in the computing zone A or B can be increased within the range of the number of CPU cores in the pool zone core group 12, it is possible to flexibly cope with load fluctuations. When the load is small, the power consumption can be reduced by not assigning the CPU core of the pool zone core group 12 to any of the computing zones A or B.

  Further, since the number of CPU cores assigned to the routing zone 14 can be increased by increasing the number of CPU cores not assigned to the computing zone A or B, the quality of data communication between zones (speed, relay processing, Firewall processing, etc.).

  In addition, since the CPU core of the pool zone core group 12 can operate a general OS, the portability of software is high.

  In the first embodiment, the multi-core system 100 has a one-chip configuration that is sealed in one semiconductor package. However, the multi-core system 100 is sealed in a plurality of semiconductor packages and realized on an SOC (System On a Chip) or a substrate. May be.

  FIG. 6A is a perspective view of the SOC multi-core system 100, and FIG. 6B is a perspective view of the multi-core system 100 configured on a substrate. The same parts as those in FIG. If the multi-core system 100 is not configured as a single chip as shown in FIG. 6A or 6B, the number of CPU cores can be increased by increasing the number of chips, so that it is not necessary to rely on circuit integration density. The multi-core system 100 according to the present embodiment can be easily realized.

  FIG. 7 shows a configuration diagram of the multi-core system 100 of the present embodiment. In FIG. 7, the same parts as those in FIG. In the multi-core system 100 of FIG. 7, the zone fixed core group 11A, the zone fixed core group 11B, the pool zone core group 12, the external memory 15A, and the external memory 15B are configured as separate chips. Each chip is connected by a bonding wire or flip chip in the SOC, and is connected by a printed wiring on the substrate.

  In this embodiment, since the pool zone core group 12 is connected to the external memory 15A and the external memory 15B, data communication is performed between the computing zones A and B via the external memories 15A and 15B. In the first embodiment, the external memories 15A and 15B are cache memories instead of the external memories 15A and 15B. This is in accordance with a convention in which the memory outside the chip is not called a cache, and the functions of the external memories 15A and 15B are the same as those in the first embodiment. It is the same as 13A and 13B. Therefore, it is preferable that the external memories 15A and 15B are high-access-speed memories such as DRAM, FeRAM (Ferroelectric Random Access Memory), and MRAM (Magnetoresistive Random Access Memory). Each CPU core includes a cache memory.

  In this embodiment, the CPU cores of the zone fixed core groups 11A and 11B and the pool zone core group 12 are all general-purpose cores. This facilitates the configuration of the computing zones A and B.

Other configurations are the same as those of the first embodiment. That is,
The CPU core of the zone fixed core group 11A and the CPU core of the pool zone core group 12 form one computing zone A, and the CPU core of the zone fixed core group 11B and the CPU core of the pool zone core group 12 are one computer. Forming zone B.
Based on the core configuration information 16, it is determined whether the CPU core of the pool zone core group 12 belongs to the zone fixed core group 11A or the zone fixed core group 11B.
Each computing zone has its own external memory.
The CPU core of the pool zone core group 12 can share all the external memories 15A and 15B.
The pool zone core group 12 has unassigned CPU cores in both the computing zones A and B, and forms a routing zone 14.

Such a configuration provides the following effects.
Since data communication between zones always passes through the pool zone core group 12, security between zones can be improved.
-Data communication between zones is fast because it passes through the external memories 15A and 15B.
In addition, since the number of CPU cores assigned to the routing zone 14 can be increased by increasing the number of CPU cores not assigned to the computing zone A or B, the quality of data communication between zones (speed, relay, etc.) Processing, firewall processing, etc.).
In addition, since the CPU core of the pool zone core group 12 can operate a general OS executed on the server, the portability of software is high.
Since the number of CPU cores in the computing zone A or B can be increased within the range of the number of CPU cores in the pool zone core group 12, it is possible to flexibly cope with load fluctuations.

1 is a configuration diagram of a multi-core system (Example 1). FIG. It is a figure which shows an example of core structure information. It is the schematic of the system for vehicles which has a multi-core system. It is a flowchart figure which shows the operation | movement procedure of a multi-core system. It is a block diagram of a multi-core system having three computing zones. It is a perspective view of the multi-core system comprised by SOC or a board | substrate. FIG. 6 is a configuration diagram of a multi-core system (Example 2).

Explanation of symbols

11A to C Zone fixed core group 12 Pool zone core group 13A to C Cache 14 Routing zone 15A and B External memory 16 Core configuration information 100 Multicore system

Claims (9)

In a multi-core system having a plurality of fixed core groups having one or more cores and a pool core group having a plurality of cores,
The fixed core groups are each connected to a dedicated memory, and the pool core group is connected to all the dedicated memories,
One or more assigned cores of the pool core group to which one or more of a plurality of processes executed by at least one or more predetermined fixed core groups of the plurality of fixed core groups are assigned are the predetermined to which a process is assigned. Access only the dedicated memory connected to the fixed core group and execute the assigned process.
It said predetermined fixed core groups of one or more cores, and one or more cores of the stationary core groups other than the predetermined fixed core groups, a plurality of the fixed core groups to access and run to each of the dedicated memory Perform one or more of the processes,
One or more cores of the pool core group other than the allocated cores read out data stored in the dedicated memory connected to the predetermined fixed core group by the predetermined fixed core group, and fixed cores other than the predetermined fixed core group Stored in the dedicated memory connected to the group, or a fixed core group other than the predetermined fixed core group reads data stored in the dedicated memory connected to the fixed core group, and the predetermined fixed core group Store in the dedicated memory different from the connected dedicated memory or the read-out dedicated memory,
Multi-core system characterized by that.   The multi-core system according to claim 1, wherein a firewall is realized by cores of the pool core group other than the assigned cores.   The number of cores of the pool core group other than the allocated core that writes data from the dedicated memory to another dedicated memory is variable. Multi-core system.   The multi-core system according to claim 1, wherein a core of the pool core group is a general-purpose core.   The number of allocated cores, or the number of cores of the pool core group other than the allocated core that writes data from the dedicated memory to another dedicated memory is specified by setting information stored in a storage unit. The multi-core system according to claim 3, wherein:   4. The multi-core system according to claim 3, wherein the number of the assigned cores is dynamically changed according to a load state of the predetermined fixed core group to which processing is assigned to the assigned cores.   The multi-core system according to claim 1, wherein the plurality of fixed core groups, the pool core group, and the dedicated memory are packaged in one chip.   The multi-core system according to claim 1, wherein each of the plurality of fixed core groups, the pool core group, and the dedicated memory is packaged in one chip. A multi-core system according to any one of claims 1 to 8,
The vehicular gateway device, wherein the multi-core system realizes a relay processing unit that relays transmission / reception of information between the in-vehicle device and the outside.

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