JP5267154B2 - Circuit delay verification device, method and program for semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently perform circuit delay verification for predicting a maximum operating frequency for a semiconductor integrated circuit being designed, in consideration of manufacturing variations of the semiconductor integrated circuit. <P>SOLUTION: A circuit delay verification device 10 for a semiconductor integrated circuit includes: a variation delay sensitivity generation means for deriving a variation delay sensitivity characteristic; a circuit scale information management means for deriving a circuit scale characteristic; an operating frequency information management means for deriving an operating frequency characteristic; an unconsidered delay time generation means for generating an unconsidered delay time characteristic; and a circuit delay time calculation means for generating a circuit delay time characteristic in consideration of manufacturing variations in the semiconductor integrated circuit, from the variation delay sensitivity characteristic, the circuit scale characteristic, the operating frequency characteristic and the unconsidered delay time characteristic, and managing the generated circuit delay time characteristic. The generated circuit delay time characteristic is used to perform circuit delay verification for the semiconductor integrated circuit. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a circuit delay verification apparatus, method, and program for analyzing a signal propagation delay time in a semiconductor integrated circuit, and in particular, confirms and verifies whether or not the semiconductor integrated circuit operates at a predetermined frequency or more at a circuit design stage. The present invention relates to a circuit delay verification apparatus, method, and program for a semiconductor integrated circuit.

Circuit delay verification in a conventional semiconductor integrated circuit is performed in consideration of various margins in signal propagation delay time using parameters such as a power supply voltage range, an operating temperature range of the semiconductor integrated circuit, and a delay verification error in a circuit delay verification device. ing. Tools such as a circuit delay verification device and a circuit delay verification program for performing circuit delay verification in this semiconductor integrated circuit are also widely known, and it is possible to perform circuit delay verification with excellent efficiency.
However, in recent years, as the speed and scale of semiconductor integrated circuits have rapidly increased, the miniaturization of semiconductor manufacturing processes and the degree of semiconductor integration have accelerated. As a result, the manufacturing variation of the semiconductors that make up the semiconductor integrated circuit has increased, and the effect of this manufacturing variation on the maximum operating frequency of the semiconductor integrated circuit has increased. The need to do is growing.
On the other hand, there has been proposed a method of statistically calculating the influence of semiconductor manufacturing variations on the maximum operating frequency of a semiconductor integrated circuit and performing circuit delay verification (see Patent Document 1 and Patent Document 2). These technologies verify circuit delays that do not take into account semiconductor manufacturing variations, and verify variations in signal propagation delays for higher-order delay paths that have extracted paths with large signal propagation delay times between inputs and outputs in semiconductor integrated circuits. In combination with statistically performed circuit delay verification, circuit delay verification of a semiconductor integrated circuit in consideration of semiconductor manufacturing variations is executed.

  On the other hand, there has been proposed a technique for executing circuit timing analysis in consideration of manufacturing variations in a semiconductor integrated circuit using basic characteristics of cells in a semiconductor integrated circuit, that is, delay time characteristics in cells (see Patent Document 3). While this technology used to derive the basic characteristics of a cell in a semiconductor integrated circuit using a uniform variation coefficient, it has taken into account variations in the gate width of the transistors that make up the cell. The basic characteristic of the cell of the semiconductor integrated circuit is derived using the variation coefficient considering the above, and the circuit timing analysis in the semiconductor integrated circuit is executed using this basic characteristic.

JP 2004-252831 A JP 2008-102837 A Japanese translation of PCT publication No. 2008-112383

However, in these techniques, it has been difficult to perform circuit delay verification in consideration of manufacturing variation in a semiconductor integrated circuit as efficiently as conventional circuit delay verification that does not consider manufacturing variation.
For example, as shown in FIG. 15, a statistical circuit delay verification method such as Patent Document 1 and Patent Document 2 uses a conventional circuit delay verification that does not consider manufacturing variations and a path with a large delay time in a semiconductor integrated circuit. Two circuit delay verification procedures, including analysis of circuit delay variation of a certain upper delay path group, are required, and there is a problem that the processing time for circuit verification becomes long in the circuit design stage of the semiconductor integrated circuit.

  Further, the circuit timing analysis technique as disclosed in Patent Document 3 is a circuit timing analysis that takes into account variations in the gate width of the transistors constituting the cells in the semiconductor integrated circuit, and takes into account manufacturing variations for the cells. Therefore, as shown in FIG. 16, when performing the timing analysis in the entire semiconductor integrated circuit, it is necessary to derive the delay time characteristics for each cell and individually execute the timing verification for each cell. In the design stage, the circuit verification process becomes complicated.

  In order to solve the above-described problems, the present invention provides a circuit delay of a semiconductor integrated circuit in consideration of manufacturing variations in a semiconductor integrated circuit in which operation at a predetermined maximum operating frequency is confirmed in a semiconductor integrated circuit design stage. The purpose is to provide verification methods.

  In order to achieve the above object, the present invention provides a circuit delay verification device for a semiconductor integrated circuit that confirms that a semiconductor integrated circuit operates at a predetermined frequency or more in a design stage. A variation delay sensitivity creating means for deriving a variation delay sensitivity characteristic indicating the degree of influence of a signal propagation on a delay time of an arbitrary circuit, and a circuit scale for deriving a circuit scale characteristic for identifying a circuit scale in a semiconductor integrated circuit Information management means, operating frequency information management means for deriving operating frequency characteristics that specify the level of the operating frequency of a semiconductor integrated circuit, and circuit delay time characteristics that depend on the operating environment of the semiconductor integrated circuit without taking into account semiconductor manufacturing variations A non-considered delay time generating means for generating an unconsidered delay time characteristic, the variation delay sensitivity characteristic and the circuit A circuit delay time calculating means for creating and managing a circuit delay time characteristic considering manufacturing variations in a semiconductor integrated circuit from the scale characteristic, the operating frequency characteristic, and the non-considered delay time characteristic is provided. To do.

  According to the present invention, in a circuit delay verification device for a semiconductor integrated circuit, a circuit delay considering a manufacturing variation in a semiconductor integrated circuit created from a variation delay sensitivity characteristic, a circuit scale characteristic, an operating frequency characteristic, and an unconsidered delay time characteristic. By performing the circuit delay verification using the time characteristic, the circuit delay verification considering the manufacturing variation in the semiconductor integrated circuit can be performed with the same efficiency as the conventional circuit delay verification not considering the manufacturing variation.

1 is a functional block diagram showing a configuration of a circuit delay verification device for a semiconductor integrated circuit according to a first embodiment of the present invention; It is a flowchart which shows the operation | movement procedure of the circuit delay verification apparatus of the semiconductor integrated circuit of this invention. It is a functional block diagram which shows the structure of the circuit delay verification apparatus of the semiconductor integrated circuit concerning the 2nd Embodiment of this invention. It is a conceptual diagram which illustrates notionally the circuit delay library of this invention. It is a flowchart which shows the circuit delay verification procedure of the semiconductor integrated circuit of this invention. It is a figure which shows the circuit model by a logic gate level about the circuit which outputs NOT ((IN0 | IN1) & (IN2 | IN3)) of a semiconductor integrated circuit. FIG. 5 is a diagram illustrating a logical change of an output “OUT” due to a logical change of an input “IN0” in the model circuit illustrated in FIG. 4 under a condition that does not consider semiconductor manufacturing variations. FIG. 7 is a diagram showing a logical change of an output “OUT” due to a logical change of an input “IN0” in the model circuit shown in FIG. 6 when semiconductor manufacturing variations are taken into account. FIG. 7 is a diagram representing the circuit shown in FIG. 6 by transistor level. It is a figure which shows an example of the circuit delay library of the semiconductor integrated circuit created in the circuit delay verification apparatus of the semiconductor integrated circuit of this invention. It is a figure which shows an example of the circuit delay library of the semiconductor integrated circuit with the large variation delay sensitivity characteristic, the high operating frequency, or the circuit scale which is produced in the circuit delay verification apparatus of the semiconductor integrated circuit of this invention. The coefficient N of the one-sided appearance probability Nσ in the standard normal distribution function of the manufacturing variation in the semiconductor integrated circuit to be taken into account as the circuit scale of the semiconductor integrated circuit increases, which is created in the circuit delay verification device of the semiconductor integrated circuit of the present invention. It is a figure which shows an example of the circuit delay library of the increased semiconductor integrated circuit. It is a functional block diagram which shows the structure of the circuit delay verification apparatus of the semiconductor integrated circuit concerning the 3rd Embodiment of this invention. It is a functional block diagram which shows the structure of the circuit delay verification apparatus of the semiconductor integrated circuit concerning the 4th Embodiment of this invention. It is a flowchart which shows the prior art example of the circuit delay verification procedure of the semiconductor integrated circuit which considered the manufacture dispersion | variation in a semiconductor integrated circuit. 6 is a flowchart showing a procedure of circuit timing analysis in consideration of manufacturing variation in a semiconductor integrated circuit using basic characteristics of cells in the semiconductor integrated circuit.

  Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment]
FIG. 1 is a functional block diagram showing an outline of a circuit delay verification apparatus 10 for a semiconductor integrated circuit according to the first embodiment.
The circuit delay verification device for a semiconductor integrated circuit according to the present embodiment has a circuit delay time characteristic that takes into account manufacturing variations in a semiconductor integrated circuit from a variation delay sensitivity characteristic, a circuit scale characteristic, an operating frequency characteristic, and an unconsidered delay time characteristic. To create.
Here, the delay time characteristic is represented by a change in the amount of delay time of signal propagation with respect to a change in the load capacity of the circuit in the target circuit, and is derived by simulation for obtaining the delay time characteristic.

  The variation delay sensitivity characteristic depends on the delay sensitivity, which is the degree of influence of the manufacturing variation of the semiconductors that make up this semiconductor integrated circuit on the delay time of signal propagation in this circuit block in the design data of the semiconductor integrated circuit. The data describes the delay time characteristics of signal propagation in this circuit. For example, the longer the gate length of a circuit, that is, the more the transistors arranged in series at the transistor level, the higher the delay sensitivity of signal propagation with respect to semiconductor manufacturing variations. In this case, in the delay time characteristic, when the load capacity of the circuit increases, the increase amount of the delay time also varies greatly. Further, as the gate width increases, that is, as the number of transistors arranged in parallel at the transistor level increases, the delay sensitivity of signal propagation with respect to semiconductor manufacturing variations decreases. In this case, in the delay time characteristics, even if the load capacity of this circuit is increased, there is no significant change in the increase amount of the delay time.

  The circuit scale characteristic is the total amount of the path having the maximum delay time of signal propagation appearing in the semiconductor integrated circuit and the path having the delay time close to the maximum delay time, and the degree of the circuit scale of the semiconductor integrated circuit. This data identifies

  The operating frequency characteristic is data specifying the level of the operating frequency of the semiconductor integrated circuit, which is derived by the square root of the operating frequency of the semiconductor integrated circuit.

  The non-considered delay time characteristic is data in which the delay time characteristic of signal propagation of this circuit depending on the operating environment of the semiconductor integrated circuit is described without considering semiconductor manufacturing variations. Here, the operating environment of the semiconductor integrated circuit includes, for example, an operating temperature range and an operating power supply voltage range.

As shown in FIG. 1, a circuit delay verification device 10 for a semiconductor integrated circuit includes a variation delay sensitivity management unit 101 that creates variation delay sensitivity characteristics, a circuit scale information management unit 102 that derives circuit scale characteristics, and an operating frequency characteristic. Operating frequency information management unit 103 for deriving data, an unconsidered delay time creation unit 104 for creating an unconsidered delay time characteristic, and a circuit delay time for creating and managing a delay time characteristic considering manufacturing variations in a semiconductor integrated circuit It is comprised with the calculating part 105. FIG.
These components are installed in the circuit delay verification device 10 of the semiconductor integrated circuit described above by installing a computer program in a computer having a CPU (Central Processing Unit), a memory, an interface, and a storage device. Computer hardware resources and software are realized in cooperation.

  The variation delay sensitivity management unit 101 is a delay sensitivity which is a degree of influence of the manufacturing variation of the semiconductor constituting the semiconductor integrated circuit on the delay time of signal propagation in this circuit in an arbitrary circuit block of the design data of the semiconductor integrated circuit. The variation delay sensitivity characteristic in which the delay time characteristic of the signal propagation in this circuit is described is created, and the variation delay sensitivity characteristic is stored in a storage unit (not shown).

  The circuit scale information management unit 102 derives circuit scale characteristics that specify the scale of the semiconductor integrated circuit, and stores the circuit scale characteristics in a storage unit (not shown).

  The operating frequency information management unit 103 derives an operating frequency characteristic that specifies the level of the operating frequency in the semiconductor integrated circuit, and stores this operating frequency characteristic in a storage unit (not shown).

  The unconsidered delay time creation unit 104 creates an unconsidered delay time characteristic that does not take into account manufacturing variations in the semiconductor integrated circuit and depends on the operating environment of the semiconductor integrated circuit. Remember.

  The circuit delay time calculation unit 105 includes the variation delay sensitivity characteristic created and stored by the variation delay sensitivity management unit 101, the circuit scale characteristic derived and stored by the circuit scale information management unit 102, and the operation frequency information management unit 103. A circuit delay time characteristic that takes into account manufacturing variations in a semiconductor integrated circuit is created from the derived and stored operating frequency characteristic and the unconsidered delay time characteristic created and stored by the unconsidered delay time creation unit 104, and illustrated in FIG. The circuit delay time characteristics are stored in the storage unit that does not. Here, the circuit delay time characteristic is calculated based on a predetermined condition stored in a storage unit (not shown) that associates the unaccounted delay time characteristic, the variation delay sensitivity characteristic, the circuit scale characteristic, and the operating frequency characteristic. This is data describing the delay time characteristics of the target circuit created and implemented.

Next, the operation of the circuit delay verification device 10 according to this exemplary embodiment will be described.
FIG. 2 is a flowchart showing an operation procedure for creating a circuit delay time in the circuit delay verification device 10 according to the present exemplary embodiment. As shown in FIG. 2, the circuit delay verification apparatus 10 takes in the design data of the prepared semiconductor integrated circuit from an interface (not shown), and stores the fetched design data in a storage unit (not shown) (S1).
Based on the fetched design data, the unconsidered delay time creation unit 104 creates an unconsidered delay time characteristic and stores the unconsidered delay time characteristic in a storage unit (not shown) (S2-a), thereby managing variation delay sensitivity. The unit 101 creates a variation delay sensitivity characteristic and stores the variation delay sensitivity characteristic in a storage unit (not shown) (S2-b), and the circuit scale information management unit 102 derives the circuit scale characteristic and stores it in a storage unit (not shown). The circuit scale characteristic is stored (S2-c), and the operating frequency information management unit 103 derives the operating frequency characteristic and stores this operating frequency characteristic in a storage unit (not shown) (S2-d).
The circuit delay time calculation unit 105 is created or derived based on the design data of the semiconductor integrated circuit and stored in a storage unit (not shown), a non-considered delay time characteristic, a variation delay sensitivity characteristic, a circuit scale characteristic, an operation Based on the frequency characteristics, a circuit delay time characteristic in the design data in consideration of manufacturing variations in the semiconductor integrated circuit is created, and the circuit delay time characteristic is stored in a storage unit (not shown) (S3).
When design data of a semiconductor integrated circuit fetched in a storage unit (not shown) is updated due to design change or redesign ("Yes" in S4), the circuit delay verification device 10 updates the semiconductor integrated circuit updated. Circuit design data is fetched from an interface (not shown), and the fetched design data is stored in a storage unit (not shown) (S1).
On the other hand, when there is no update of the design data of the semiconductor integrated circuit captured in the storage unit (not shown) (“No” in S4), the creation of the circuit delay time characteristic in this design data is completed, and the circuit delay verification device 10 The creation of the circuit delay time characteristic ends.

In this way, by creating a circuit delay time characteristic that takes into account manufacturing variations in a semiconductor integrated circuit from unaccounted delay time characteristics, variation delay sensitivity characteristics, circuit scale characteristics, and operating frequency characteristics, the circuit delay time characteristics are used. Thus, the circuit delay verification program can be executed, and the circuit delay verification can be performed in consideration of manufacturing variations in the semiconductor integrated circuit.
In addition, since the circuit delay verification device 10 according to the present embodiment creates circuit delay time characteristics using design data in the semiconductor integrated circuit, the circuit delay time characteristics in parallel with the circuit design of the semiconductor integrated circuit. The circuit delay verification at the design stage of the semiconductor integrated circuit can be made more efficient.

[Second Embodiment]
Next, a second embodiment of the present invention will be described.
The circuit delay verification apparatus for a semiconductor integrated circuit according to the present embodiment creates a circuit delay library in which a delay time characteristic of signal propagation is described in consideration of manufacturing variations in the semiconductor integrated circuit, and uses this to create a semiconductor integrated circuit The circuit delay verification is performed.

FIG. 3 is a functional block diagram showing an outline of the circuit delay verification device 20 of the semiconductor integrated circuit according to the present embodiment. As shown in FIG. 3, the circuit delay verification device 20 includes a variation delay sensitivity management unit 101 that creates variation delay sensitivity characteristics, a circuit scale information management unit 102 that derives circuit scale characteristics, and an operation that derives operating frequency characteristics. A frequency information management unit 103, an unconsidered delay time creation unit 104 that creates an unaccounted delay time characteristic, and a delay time characteristic that takes into account manufacturing variations in a semiconductor integrated circuit and creates a circuit delay library using the delay time characteristic And a circuit delay time calculation unit 205.
The circuit delay time calculation unit 205 uses a delay time characteristic creation unit 206 that creates a circuit delay time characteristic in consideration of manufacturing variations in a semiconductor integrated circuit, and a circuit using the circuit delay time characteristic created by the delay time characteristic creation unit 206. The circuit delay library creating unit 207 creates a delay library.
These components are installed in the circuit delay verification device 20 of the semiconductor integrated circuit described above by installing a computer program in a computer having a CPU (Central Processing Unit), a memory, an interface, and a storage device. Computer hardware resources and software are realized in cooperation.
In addition, the variation delay sensitivity management unit 101, the circuit scale information management unit 102, the operating frequency information management unit 103, and the unconsidered delay time creation unit 104 of the circuit delay verification device 20 of the semiconductor integrated circuit according to the present embodiment include: The variation delay sensitivity management unit 101, the circuit scale information management unit 102, the operating frequency information management unit 103, and the unconsidered delay time creation unit 104 of the circuit delay verification device 10 of the semiconductor integrated circuit according to the first embodiment have the same configuration. In this case, the same reference numerals are used here, and detailed descriptions thereof are omitted.

Here, the circuit delay library is a program file used in a circuit delay verification program that executes circuit delay verification of a semiconductor integrated circuit. In the circuit delay verification method, as described at the beginning, circuit delay verification is performed in consideration of a power supply voltage range, an operating temperature range of a semiconductor integrated circuit, a delay verification error in a circuit delay verification device, and the like. The circuit delay library used in the verification technique describes circuit delay time characteristics in consideration of these elements in a semiconductor integrated circuit, and this circuit delay library is widely used.
The circuit delay library created in the circuit delay verification device 20 of the semiconductor integrated circuit according to the present embodiment is a circuit delay library created using the signal propagation delay time characteristics in consideration of manufacturing variations in the semiconductor integrated circuit. Therefore, unlike the conventional circuit delay library, this is a circuit delay library in which manufacturing variations of the semiconductor integrated circuit are taken into consideration. FIG. 4 is a conceptual diagram conceptually illustrating a circuit delay library created in the circuit delay verification device 20 of this semiconductor integrated circuit. “0σ” shown in FIG. 4 indicates a case where there is no manufacturing variation in the semiconductor integrated circuit. “Nσ” indicates a one-sided appearance probability of the standard normal distribution function obtained by multiplying the standard deviation σ of the standard normal distribution function of the manufacturing variation in the semiconductor integrated circuit by the coefficient N. In other words, a circuit delay library that takes into account manufacturing variation in a semiconductor integrated circuit is a program that describes the presence or absence of manufacturing variation in a semiconductor integrated circuit and the delay time characteristics of the circuit according to the appearance probability of the standard normal distribution function of this manufacturing variation. It is a file.

Next, the operation of the circuit delay verification device 20 of the semiconductor integrated circuit according to the present embodiment will be described while focusing on the operation of the circuit delay time calculation unit 205.
The delay time characteristic creation unit 206 of the circuit delay time calculation unit 205 includes a variation delay sensitivity characteristic created and stored by the variation delay sensitivity management unit 101, a circuit scale characteristic derived and stored by the circuit scale information management unit 102, A circuit delay time that takes into account manufacturing variations in a semiconductor integrated circuit from the operating frequency characteristic derived and stored by the operating frequency information management unit 103 and the unconsidered delay time characteristic created and stored by the unconsidered delay time creating unit 104 A characteristic is created and the circuit delay time characteristic is stored in a storage unit (not shown). This circuit delay time characteristic is created by performing an operation based on a predetermined condition stored in a storage unit (not shown) that associates an unconsidered delay time characteristic, a variation delay sensitivity characteristic, a circuit scale characteristic, and an operating frequency characteristic. This is data describing the delay time characteristics of the target circuit.
The circuit delay library creating unit 207 of the circuit delay time calculating unit 205 creates a circuit delay library using the circuit delay time characteristics taking into account manufacturing variations in the semiconductor integrated circuit created by the delay time characteristic creating unit 206, and The circuit delay library is stored in a storage unit (not shown).

  As described above, the circuit delay verification using the circuit delay verification device 20 of the semiconductor integrated circuit according to the present embodiment is a circuit delay library in consideration of manufacturing variations in the semiconductor integrated circuit created by the circuit delay time calculation unit 205. The circuit delay verification of the semiconductor integrated circuit is performed by using the circuit delay library.

  FIG. 5 is a flowchart showing a procedure of circuit delay verification using the circuit delay verification device 20 of the semiconductor integrated circuit according to the present embodiment. As shown in FIG. 5, the circuit delay library creation unit 207 performs circuit delay verification of the semiconductor integrated circuit using the circuit delay time characteristics taking into account manufacturing variations in the semiconductor integrated circuit created by the delay time characteristics creation unit 206. A circuit delay library is created to store the circuit delay library in a storage unit (not shown) in the circuit delay verification apparatus 20 (S11).

  Next, the circuit delay verification device 20 takes in the design data of the prepared semiconductor integrated circuit from an interface (not shown), and stores the fetched design data in a storage unit (not shown) (S12). A timing analysis of signal propagation in the semiconductor integrated circuit that does not consider manufacturing variations is performed on the fetched design data of the semiconductor integrated circuit using the circuit delay library created by the circuit delay verification device 10 (S13).

  When the signal propagation timing analysis is performed on the design data of the semiconductor integrated circuit and it is confirmed that there is no problem in the operation of the semiconductor integrated circuit at a desired frequency or higher (“Yes” in S14), the semiconductor integrated circuit The circuit design is completed (S15).

If it is confirmed as a result of timing analysis that the semiconductor integrated circuit has a problem in operation at a desired frequency or higher ("No" in S14), redesign is performed on the circuit design data (S16). .
After the redesign of the semiconductor integrated circuit is completed, the circuit delay verification device 20 takes in the circuit design data from an interface (not shown) and stores it in a storage unit (not shown) (S12). Timing analysis is performed using the circuit delay library created by the circuit delay verification device 20 (S13), and until it can be confirmed from the result of the timing analysis of the design data that there is no problem in operation at a desired frequency or higher. Repeat the procedure.
Here, the circuit delay library created by the circuit delay verification device 20 can be prepared in parallel with the redesign of the semiconductor integrated circuit. At the same time as the redesign is completed, the circuit delay library corresponding to the design data is prepared. Can be prepared.

  Thus, by preparing a circuit delay library in consideration of manufacturing variations in semiconductor integrated circuits, it is possible to use a circuit delay verification method that does not consider manufacturing variations in semiconductor integrated circuits. The circuit delay verification can be performed in consideration of manufacturing variations in the semiconductor integrated circuit with the same efficiency as the circuit delay verification by the verification method.

[Detailed explanation of circuit delay time characteristics and circuit delay library]
Next, circuit delay time characteristics and a circuit delay library created by the circuit delay verification device 20 according to the present embodiment will be described with reference to the drawings. Here, a CMOS logic gate 601 for outputting NOT ((IN0 | IN1) & (IN2 | IN3)) shown in FIG. 6 is a part of a circuit block in a semiconductor integrated circuit, and this circuit block is taken as an example in this embodiment. A circuit delay time characteristic and a circuit delay library created by the circuit delay verification device 20 according to the embodiment will be described.

[Circuit delay time characteristics and circuit delay library when semiconductor manufacturing variations are not taken into account]
With respect to the circuit block shown in FIG. 6, the circuit delay time characteristics and the circuit delay library will be described in the case where the manufacturing variation of the semiconductor constituting the logic gate 601 in this circuit is not considered.
In the case of CMOS logic gate 601 with inputs IN0 to IN3 as inputs, if manufacturing variations of semiconductors constituting the logic gate 601 are not taken into account, IN1 = IN2 = logic 0, IN3 = logic 1, and the value of IN0 is from logic 1 to logic 1. When it changes to 0, the output OUT changes from logic 0 to logic 1 after a certain delay time from the logic change at IN0, as shown in FIG. For this fixed delay time, the delay time characteristic of signal propagation at the output OUT derived by changing C _load 602 corresponding to the load capacity of this circuit by simulation is a delay that does not take into account manufacturing variations in the circuit block shown in FIG. This is a time characteristic, that is, an unconsidered delay time characteristic created by the unconsidered delay time creating unit 104.

  Next, the variation delay sensitivity characteristic in the circuit block shown in FIG. 6 will be described. Although the variation delay sensitivity characteristic of this circuit is created in the variation delay sensitivity management unit 101, if the semiconductor manufacturing variation is not considered, the delay sensitivity of signal propagation in this circuit is very low, that is, the circuit delay time of this circuit. In creating the characteristics, it is not necessary to consider the variation delay sensitivity characteristics. Here, the conditions that do not take into account semiconductor manufacturing variations include, for example, the case where the semiconductor manufacturing process is very stable and the case where the semiconductor elements constituting the circuit are very large.

  Next, in the circuit scale information management unit 102 and the operating frequency information management unit 103, a circuit scale characteristic that specifies the circuit scale of the semiconductor integrated circuit and an operating frequency characteristic that specifies the level of the operating frequency of the semiconductor integrated circuit. These characteristics are derived and stored in a storage unit (not shown).

Next, the delay time characteristic creating unit 206 of the circuit delay time calculating unit 205 includes the unconsidered delay time characteristic created by the unconsidered delay time creating unit 104 and the circuit scale characteristic derived by the circuit scale information managing unit 102. The circuit delay time characteristic in the circuit block shown in FIG. 6 is created from the operating frequency characteristic derived in the operating frequency information management unit 103 based on a predetermined condition stored in a storage unit (not shown), and is not shown. The circuit delay time characteristic is stored in the storage unit.
The circuit delay library creation unit 207 of the circuit delay time calculation unit 205 uses the delay time characteristics when the semiconductor manufacturing variation created by the delay time characteristic creation unit 206 is not considered in the components of the circuit block shown in FIG. Then, a circuit delay library of this circuit is created, and the created circuit delay library is stored in a storage unit (not shown).

  The circuit delay library created here without considering the manufacturing variation of the semiconductor of the circuit block shown in FIG. 6 is a circuit delay library having a delay time characteristic indicated by “0σ” in the conceptual diagram of the circuit delay library shown in FIG. It will approach. That is, the circuit delay library has a delay time characteristic when there is no manufacturing variation in the semiconductor integrated circuit.

[Circuit delay time characteristics and circuit delay library when semiconductor manufacturing variation is taken into account]
Next, with respect to the circuit block shown in FIG. 6, the circuit delay time characteristics and the circuit delay library will be described in the case of considering the manufacturing variation of the semiconductor constituting the logic gate 601 in this circuit.
In the circuit block shown in FIG. 6, when IN1 = IN2 = logic 0 and IN3 = logic 1 and the value of IN0 changes from logic 1 to logic 0, the output OUT becomes logic 0 after a certain delay time from the logic change at IN0. However, by considering the semiconductor manufacturing variation, as shown in FIG. 8, the logic change delay time at the output OUT increases as compared with the case where the semiconductor manufacturing variation is not considered. That is, the delay time characteristic when the semiconductor manufacturing variation of the circuit block shown in FIG. 6 is taken into account tends to increase as compared with the case where the semiconductor manufacturing variation is not taken into consideration.

  As described above, the unconsidered delay time management unit 104 creates an unconsidered delay time characteristic that does not consider manufacturing variations in the circuit, and stores the unconsidered delay time characteristic in a storage unit (not shown).

Next, the variation delay sensitivity management unit 101 creates variation delay sensitivity characteristics representing the degree of influence of semiconductor manufacturing variations in this circuit on the signal propagation delay time in this circuit.
Here, the variation delay sensitivity characteristic will be described with reference to FIG. 9 showing the circuit of FIG. 6 at the transistor level. The input signal IN0 of interest is connected to the pMOS transistor 901 and the nMOS transistor 905 as shown in FIG. In this circuit, the transistors related to the delay time characteristic at the output OUT due to the change of the value of IN0 from logic 1 to logic 0 under the conditions of IN1 = IN2 = logic 0 and IN3 = logic 1 are pMOS transistor 901 and This is a pMOS transistor 902. Therefore, in the circuit in which the pMOS transistor 901 and the pMOS transistor 902 are connected, the manufacturing variation of these transistors is directly related to the delay sensitivity of this circuit, and the variation delay sensitivity characteristic in the circuit block of FIG.
The variation delay sensitivity management unit 101 stores the variation delay sensitivity characteristic created in a storage unit (not shown).

  Next, in the circuit scale information management unit 102 and the operating frequency information management unit 103, a circuit scale characteristic that specifies the circuit scale of the semiconductor integrated circuit and an operating frequency characteristic that specifies the level of the operating frequency of the semiconductor integrated circuit. These characteristics are derived and stored in a storage unit (not shown).

Next, the delay time characteristic creation unit 206 of the circuit delay time calculation unit 205 includes the unconsidered delay time characteristic created by the unconsidered delay time creation unit 104 and the variation delay sensitivity characteristic created by the variation delay sensitivity management unit 101. 6 based on a predetermined condition stored in a storage unit (not shown) from the circuit scale characteristic derived by the circuit scale information management unit 102 and the operation frequency characteristic derived by the operation frequency information management unit 103. The circuit delay time characteristics in the circuit block shown in FIG. 2 are created, and the circuit delay time characteristics are stored in a storage unit (not shown).
The circuit delay library creation unit 207 of the circuit delay time calculation unit 205 uses the delay time characteristics when the semiconductor manufacturing variation created by the delay time characteristic creation unit 206 is not considered in the components of the circuit block shown in FIG. Then, a circuit delay library of this circuit is created, and the created circuit delay library is stored in a storage unit (not shown).

  The circuit delay library created here without considering the manufacturing variation of the semiconductor of the circuit block shown in FIG. 6 is a circuit delay library having a delay time characteristic indicated by “Nσ” in the conceptual diagram of the circuit delay library shown in FIG. Become. That is, the circuit delay library has a delay time characteristic corresponding to the one-sided appearance probability of the standard normal distribution function of the manufacturing variation in the semiconductor integrated circuit.

  Here, the one-sided appearance rate Nσ of the standard normal distribution function of the manufacturing variation in the semiconductor integrated circuit in this circuit delay library can be determined according to the variation delay sensitivity characteristic of this circuit. That is, the delay time characteristic of this circuit corresponding to the one-sided appearance rate of the standard normal distribution function of the manufacturing variation in the semiconductor integrated circuit is determined according to the transistor manufacturing variation related to the circuit delay time characteristic. Is possible. Details will be described below.

In FIG. 9, attention is focused on a transistor connected to an input signal causing a logic change, that is, a pMOS transistor 901. When the threshold voltage V _th of this transistor is increased by ΔV _th and a simulation for obtaining the delay time at the output OUT is performed, as shown in FIG. 8, the output OUT does not take manufacturing variations into consideration, that is, the threshold voltage V _th. In this case, the delay time increases. With respect to this delay time, the delay time characteristic of signal propagation at the output OUT derived by changing C _load 602 corresponding to the load capacity of this circuit by simulation indicates that this is the case when the threshold voltage of the pMOS transistor 901 is increased by ΔV _th. It becomes the delay time characteristic of the circuit.
When the semiconductor manufacturing process is finalized, a change in the threshold voltage of the pMOS transistor 901 is determined by the coefficient N in the standard deviation of the manufacturing variation in the semiconductor integrated circuit in accordance with the gate length and gate width of the pMOS transistor 901 of interest. It can be derived by experiment whether it corresponds to the quantity ΔV _th .
Therefore, a value that is the one-sided appearance rate Nσ of the standard normal distribution function of the manufacturing variation is calculated from the relationship between the coefficient N in the standard deviation of the manufacturing variation in the semiconductor integrated circuit derived from the experimental result and the change amount ΔV _th of the threshold voltage. Then, a circuit delay library for this circuit may be created as shown in FIG. Further, for example, a simulation is performed to obtain the delay time characteristic with the threshold voltage change amount ΔV _th of the pMOS transistor 901 as an arbitrary fixed value, and the delay time characteristic is corrected using the relationship between N and ΔV _th derived from the experimental results, A circuit delay library as shown in FIG. 8 may be created.

  Next, features of the circuit delay library created in the circuit delay verification device 20 of the semiconductor integrated circuit according to the present embodiment will be described. 9 and 10 are diagrams illustrating an example of a circuit delay library of a semiconductor integrated circuit. Details will be described below with reference to these drawings.

  In a semiconductor integrated circuit, when the delay sensitivity due to semiconductor manufacturing variation is large, that is, when the variation delay sensitivity characteristic of the semiconductor integrated circuit is large, the feature of the circuit delay library is the standard normal distribution function of the manufacturing variation in the semiconductor integrated circuit. The difference in delay time amount between the delay time characteristics according to the one-side appearance rate Nσ becomes large. That is, in the circuit corresponding to the example of the circuit delay library shown in FIG. 10 and the circuit corresponding to the example of the circuit delay library shown in FIG. 11, the circuit corresponding to the circuit delay library shown in FIG. The variation delay sensitivity is higher than the circuit corresponding to the circuit delay library shown.

In addition, in the semiconductor integrated circuit, when the operating frequency of the semiconductor integrated circuit increases, that is, when the operating frequency characteristics of the semiconductor integrated circuit increase, the circuit delay library is characterized by an increase in the amount of increase in the circuit delay time. Have. Further, when the circuit scale characteristic of the semiconductor integrated circuit is increased, the increase amount of the circuit delay time is increased similarly to the operation frequency characteristic. That is, the semiconductor integrated circuit corresponding to the example of the circuit delay library shown in FIG. 10 and the semiconductor integrated circuit corresponding to the example of the circuit delay library shown in FIG. The semiconductor integrated circuit has a higher operating frequency or a larger circuit scale than the semiconductor integrated circuit corresponding to the circuit delay library shown in FIG.
Further, as the circuit scale of a semiconductor integrated circuit increases, it becomes necessary to consider manufacturing variations in a larger semiconductor integrated circuit. In this case, it is necessary to create a circuit delay library that takes into account the delay time characteristics of the circuit corresponding to a value with a large one-sided appearance rate Nσ of the standard normal distribution function of manufacturing variation in a semiconductor integrated circuit. An example of the circuit delay library in this case is shown in FIG.

  As described above, the circuit delay library created in the circuit delay verification device for a semiconductor integrated circuit according to the present embodiment takes into account manufacturing variations in the semiconductor integrated circuit, and further flexibly adapts to the scale and operating frequency of the semiconductor integrated circuit. It is a corresponding circuit delay library. Therefore, by preparing this circuit delay library, it is possible to take into account the manufacturing variations of the semiconductors that make up the semiconductor integrated circuit, and at the same time consider the manufacturing variations in the semiconductor integrated circuit that flexibly supports the scale and operating frequency of the semiconductor integrated circuit. Delay verification is possible. Further, by using this circuit delay library in the conventional circuit delay verification method, it is possible to perform circuit delay verification considering the manufacturing variation in the semiconductor integrated circuit with the same efficiency as the circuit delay verification.

[Third Embodiment]
Next, a third embodiment of the present invention will be described.
The circuit delay verification device for a semiconductor integrated circuit according to the present embodiment includes a circuit delay time characteristic considering a manufacturing variation in a semiconductor integrated circuit from a variation delay sensitivity characteristic, a circuit scale characteristic, an operating frequency characteristic, and an unconsidered delay time characteristic. A circuit delay verification device for creating a circuit delay library, and in particular, the circuit scale characteristic of a semiconductor integrated circuit is obtained by reciprocal of the total amount of paths in which a delay time of signal propagation appearing in the semiconductor integrated circuit is larger than a predetermined delay time. Derived as a coefficient N of the standard deviation σ in the standard normal distribution function of the manufacturing variation in this semiconductor integrated circuit, and the product of this circuit scale characteristic, operating frequency characteristic, and variation delay sensitivity characteristic as A, the unconsidered delay time characteristic Deriving the circuit delay time characteristics in this semiconductor integrated circuit by calculating B × (1 + A) where B is B To do.

FIG. 13 is a functional block diagram showing an outline of the circuit delay verification device 30 of the semiconductor integrated circuit according to the present embodiment. As illustrated in FIG. 13, the circuit delay verification device 30 includes a variation delay sensitivity management unit 101 that creates variation delay sensitivity characteristics, a circuit scale information management unit 302 that derives circuit scale characteristics, and an operation that derives operating frequency characteristics. A frequency information management unit 103, an unconsidered delay time creation unit 104 that creates an unconsidered delay time characteristic, and a circuit delay time characteristic that takes into account manufacturing variations in a semiconductor integrated circuit and creates a circuit delay library using the circuit delay time characteristic The circuit delay time calculation unit 305 is configured.
The circuit delay time calculation unit 305 is a circuit that uses a delay time characteristic creation unit 306 that creates a circuit delay time characteristic in consideration of manufacturing variations in a semiconductor integrated circuit, and a circuit delay time characteristic created by the delay time characteristic creation unit 306. The circuit delay library creating unit 207 creates a delay library.
The delay time characteristic creation unit 306 includes a circuit delay time characteristic creation condition 307 that is a condition for creating a delay time characteristic in consideration of manufacturing variations in a semiconductor integrated circuit.
These components are installed in the circuit delay verification device 30 of the semiconductor integrated circuit by installing a computer program in a computer having a CPU (Central Processing Unit), a memory, an interface, and a storage device. Computer hardware resources and software are realized in cooperation.
Further, the variation delay sensitivity management unit 101, the operating frequency information management unit 103, and the unconsidered delay time creation unit 104 of the circuit delay verification device 30 of the semiconductor integrated circuit according to the present embodiment are related to the first embodiment. Since the variation delay sensitivity management unit 101, the operating frequency information management unit 103, and the unconsidered delay time creation unit 104 of the circuit delay verification device 10 of the semiconductor integrated circuit have the same configuration and function, the same reference numerals are used here. Detailed description thereof will be omitted.

  Next, the operation of the circuit delay verification device 30 of the semiconductor integrated circuit according to the present embodiment will be described while focusing on the operations of the circuit scale information management unit 302 and the circuit delay time calculation unit 305.

The circuit scale information management unit 302 derives circuit scale characteristics that specify the scale of the semiconductor integrated circuit, and stores the circuit scale characteristics in a storage unit (not shown).
Here, as described in the first embodiment, the circuit scale characteristic of the semiconductor integrated circuit depends on the circuit scale represented by the total amount of paths having a predetermined signal propagation delay time in the semiconductor integrated circuit. This data specifies the circuit scale of the semiconductor integrated circuit. The circuit scale information management unit 302 according to the present embodiment is such that the inverse of the circuit scale of the semiconductor integrated circuit, that is, the inverse of the total amount of paths having a predetermined signal propagation delay time appearing in the semiconductor integrated circuit is A circuit scale characteristic that is a coefficient N of the standard deviation σ in the standard normal distribution function of the manufacturing variation is derived.

The delay time characteristic creation unit 306 of the circuit delay time calculation unit 305 includes a variation delay sensitivity characteristic created and stored by the variation delay sensitivity management unit 101, and a circuit scale characteristic derived and stored by the circuit scale information management unit 302. A circuit delay time that takes into account manufacturing variations in a semiconductor integrated circuit from the operating frequency characteristic derived and stored by the operating frequency information management unit 103 and the unconsidered delay time characteristic created and stored by the unconsidered delay time creating unit 104 A characteristic is created and the circuit delay time characteristic is stored in a storage unit (not shown).
The circuit delay time characteristic created by the delay time characteristic creation unit 306 in the present embodiment is created based on the circuit delay time characteristic creation condition 307. The circuit delay time characteristic creation condition 307 is to calculate B × (1 + A), where A is the product of the variation delay sensitivity characteristic, the circuit scale characteristic, and the operating frequency characteristic, and B is the unconsidered delay time characteristic. Thus, circuit delay time characteristics are created.
The circuit delay library creating unit 207 of the circuit delay time calculating unit 305 creates a circuit delay library using the circuit delay time characteristics taking into account manufacturing variations in the semiconductor integrated circuit created by the delay time characteristic creating unit 306, The circuit delay library is stored in a storage unit (not shown).

  As described above, the reciprocal of the total amount of paths having a predetermined signal propagation delay time appearing in the semiconductor integrated circuit is the coefficient N of the standard deviation σ in the standard normal distribution function of the manufacturing variation in the semiconductor integrated circuit. By deriving as circuit scale characteristics, it becomes possible to easily specify the circuit scale of the semiconductor integrated circuit, and according to the circuit scale characteristics, a circuit delay library that easily takes into account manufacturing variations in the semiconductor integrated circuit is created. be able to.

[Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described.
The circuit delay verification device for a semiconductor integrated circuit according to the present embodiment includes a circuit delay time characteristic considering a manufacturing variation in a semiconductor integrated circuit from a variation delay sensitivity characteristic, a circuit scale characteristic, an operating frequency characteristic, and an unconsidered delay time characteristic. A circuit delay verification apparatus for creating a circuit delay library, in particular, a semiconductor in which a circuit scale characteristic of a semiconductor integrated circuit is a total number of gates at a logic circuit level or a total number of transistors at a transistor level included in the semiconductor integrated circuit The reciprocal of the circuit scale of the integrated circuit is derived as the coefficient N of the standard deviation σ in the standard normal distribution function of the manufacturing variation in this semiconductor integrated circuit.

FIG. 14 is a functional block diagram showing an outline of the circuit delay verification device 40 of the semiconductor integrated circuit according to the present embodiment. As shown in FIG. 14, the circuit delay verification device 40 includes a variation delay sensitivity management unit 101 that creates variation delay sensitivity characteristics, a circuit scale information management unit 402 that derives circuit scale characteristics, and an operation that derives operating frequency characteristics. A frequency information management unit 103, an unconsidered delay time creation unit 104 that creates an unconsidered delay time characteristic, and a circuit delay time characteristic that takes into account manufacturing variations in a semiconductor integrated circuit and creates a circuit delay library using the circuit delay time characteristic The circuit delay time calculation unit 305 is configured.
These components are installed in the circuit delay verification device 40 of the semiconductor integrated circuit by installing a computer program in a computer having a CPU (Central Processing Unit), a memory, an interface, and a storage device. Computer hardware resources and software are realized in cooperation.
Further, the variation delay sensitivity management unit 101, the operating frequency information management unit 103, and the unconsidered delay time creation unit 104 of the circuit delay verification device 40 of the semiconductor integrated circuit according to the present embodiment are related to the first embodiment. Variation delay sensitivity management unit 101, operating frequency information management unit 103, unconsidered delay time creation unit 104 of circuit delay verification device 10 of the semiconductor integrated circuit, and circuit of circuit delay verification device 40 of the semiconductor integrated circuit according to the present embodiment The delay time calculation unit 305 has the same configuration and the same function as the circuit delay time calculation unit 305 of the circuit delay verification device 30 of the semiconductor integrated circuit according to the third embodiment. Detailed description thereof will be omitted.

  Next, the operation of the circuit delay verification device 40 of the semiconductor integrated circuit according to the present embodiment will be described while focusing on the operation of the circuit scale information management unit 402.

The circuit scale information management unit 402 derives circuit scale characteristics that specify the scale of the semiconductor integrated circuit, and stores the circuit scale characteristics in a storage unit (not shown). The circuit scale characteristic of the semiconductor integrated circuit is data specifying the circuit scale of the semiconductor integrated circuit depending on the circuit scale. The circuit scale characteristic of the semiconductor integrated circuit derived by the circuit scale information management unit 402 in this embodiment is The total number of gates at the logic circuit level included in the semiconductor integrated circuit or the total number of transistors at the transistor level is derived as the circuit scale of the semiconductor integrated circuit. That is, the circuit scale information management unit 402 derives the circuit scale characteristic by using the reciprocal of the circuit scale as the coefficient N of the standard deviation σ in the standard normal distribution function of the manufacturing variation in the semiconductor integrated circuit.
For example, when the total number of transistors included in the semiconductor integrated circuit is 300,000, the circuit scale characteristic derived by the circuit scale information management unit 402 in this embodiment is about 4.5. Similarly, the circuit scale characteristic is about 5 when the total number of transistors is 3.5 million, the circuit scale characteristic is about 5.5 when the total number of transistors is 50 million, and the circuit scale characteristic when the total number of transistors is 1 billion. The characteristic is about 6.

  The circuit delay time calculation unit 305 of the circuit delay verification device 40 according to the present embodiment is derived and stored by the variation delay sensitivity characteristic created and stored by the variation delay sensitivity management unit 101 and the circuit scale information management unit 402. Based on the circuit scale characteristics, the operating frequency characteristics derived and stored by the operating frequency information management unit 103, and the unconsidered delay time characteristics created and stored by the unconsidered delay time creating unit 104, manufacturing variations in the semiconductor integrated circuit are detected. A circuit delay time characteristic and a circuit delay library are taken into consideration, and the circuit delay time characteristic and the circuit delay library are stored in a storage unit (not shown).

  As described above, the circuit size characteristic is the number of gates at the logic circuit level included in the semiconductor integrated circuit or the inverse of the total number of transistors at the transistor level is the coefficient of the standard deviation σ in the standard normal distribution function of the manufacturing variation in the semiconductor integrated circuit. By deriving as the circuit scale characteristic of the semiconductor integrated circuit N, it becomes possible to easily specify the circuit scale of the semiconductor integrated circuit, and easily consider the manufacturing variation in the semiconductor integrated circuit according to this circuit scale characteristic. A circuit delay library can be created.

  The present invention provides a circuit that takes into account the manufacturing variations of these semiconductor integrated circuits in a circuit design process in a large-scale semiconductor integrated circuit, a highly integrated semiconductor integrated circuit, or a semiconductor integrated circuit that requires operation at a high frequency. The present invention can be applied to a circuit delay verification device for a semiconductor integrated circuit that performs delay verification and efficiently designs a semiconductor integrated circuit. That is, the present invention can be used for a circuit delay verification apparatus that efficiently implements design of a wide variety of semiconductor integrated circuits.

  DESCRIPTION OF SYMBOLS 10, 20, 30, 40 ... Circuit delay verification apparatus, 101 ... Variation delay sensitivity management part, 102, 302, 402 ... Circuit scale information management part, 103 ... Operating frequency information management part, 104 ... Unconsidered delay time management part, 105, 205, 305 ... circuit delay time calculation unit, 206, 306 ... delay time characteristic creation unit, 207 ... circuit delay library creation unit, 307 ... circuit delay time characteristic creation condition, 601 ... NOT ((IN0 | IN1) & ( IN2 | IN3)) output CMOS logic gate, 602... Load capacitance, 901 to 904... PMOS transistor, 905 to 908.

Claims (5)

A circuit delay verification device for a semiconductor integrated circuit that analyzes a signal propagation delay in a semiconductor integrated circuit and verifies whether the semiconductor integrated circuit operates at a predetermined frequency or more at a circuit design stage,
A variation delay sensitivity management means for deriving a variation delay sensitivity characteristic indicating a degree of influence of a semiconductor manufacturing variation on a delay time of signal propagation of an arbitrary circuit in a semiconductor integrated circuit;
Circuit scale information management means for deriving a circuit scale characteristic for specifying the size of the circuit scale in the semiconductor integrated circuit based on at least the maximum delay of the semiconductor integrated circuit;
Operating frequency information management means for deriving operating frequency characteristics for specifying the operating frequency level in a semiconductor integrated circuit;
An unconsidered delay time creating means for creating an unconsidered delay time characteristic representing a circuit delay time depending on the operating environment of the semiconductor integrated circuit, which does not take into account semiconductor manufacturing variations;
A circuit delay time calculation that takes into account manufacturing variations in a semiconductor integrated circuit is created from the variation delay sensitivity characteristic, the circuit scale characteristic, the operating frequency characteristic, and the non-considered delay time characteristic, and a circuit delay time calculation that manages the circuit delay time characteristic And a circuit delay verifying device for a semiconductor integrated circuit. The circuit delay verification device for a semiconductor integrated circuit according to claim 1,
The circuit scale management means derives a circuit scale characteristic having an inverse of the total amount of paths whose signal propagation delay time appearing in the semiconductor integrated circuit is larger than a predetermined delay time as an argument of the one-side appearance probability of the standard normal distribution function. ,
The circuit delay time computing means is characterized in that the operating frequency characteristic, the variation delay sensitivity characteristic, and the reciprocal number of the total amount of paths in which the delay time of signal propagation appearing in the semiconductor integrated circuit is larger than a predetermined delay time is a standard normal distribution function Creating the delay time characteristic derived by calculating B × (1 + A), where A is the product of the circuit scale characteristic, which is the one-side appearance rate, and B is the unaccounted delay time characteristic A circuit delay verification device for a semiconductor integrated circuit. The circuit delay verification device for a semiconductor integrated circuit according to claim 1,
The circuit scale management means derives circuit scale characteristics using an inverse of the circuit scale of the semiconductor integrated circuit as an argument of the one-sided appearance probability of the standard normal distribution function,
The circuit delay time calculation means uses A as the product of the operating frequency characteristic, the variation delay sensitivity characteristic, and the circuit scale characteristic in which the inverse of the scale of the semiconductor integrated circuit is a one-sided appearance rate of a standard normal distribution function. A circuit delay verifying device for a semiconductor integrated circuit, wherein the delay time characteristic derived by calculating B × (1 + A) when the unconsidered delay time characteristic is B is created. A circuit delay verification method for a semiconductor integrated circuit that analyzes a signal propagation delay in a semiconductor integrated circuit and verifies whether the semiconductor integrated circuit operates at a predetermined frequency or more at a circuit design stage,
A delay sensitivity management means for deriving a variation delay sensitivity characteristic representing a degree of influence of a semiconductor manufacturing variation on a signal propagation delay time of an arbitrary circuit in a semiconductor integrated circuit;
A circuit scale information management means for deriving a circuit scale characteristic for identifying the magnitude of the circuit scale in the semiconductor integrated circuit based on at least the maximum delay of the semiconductor integrated circuit;
An operating frequency information management means for deriving an operating frequency characteristic for specifying the operating frequency level in the semiconductor integrated circuit,
An unconsidered delay time creating means for creating an unconsidered delay time characteristic representing a circuit delay time depending on the operating environment of the semiconductor integrated circuit, which does not consider semiconductor manufacturing variations, and
A circuit delay time calculation means creates a circuit delay time characteristic considering manufacturing variations in a semiconductor integrated circuit from the variation delay sensitivity characteristic, the circuit scale characteristic, the operating frequency characteristic, and the non-considered delay time characteristic. A circuit delay verification method for a semiconductor integrated circuit, comprising: a circuit delay time calculation procedure for managing the circuit delay time. A program for operating a computer as a circuit delay verification device for a semiconductor integrated circuit that analyzes a signal propagation delay in the semiconductor integrated circuit and verifies that the semiconductor integrated circuit operates at a predetermined frequency or more at a circuit design stage. ,
In the computer,
A variation delay sensitivity management step for deriving a variation delay sensitivity characteristic representing the degree of influence of semiconductor manufacturing variations on the delay time of signal propagation of an arbitrary circuit in a semiconductor integrated circuit;
A circuit scale information management step for deriving a circuit scale characteristic for identifying the size of the circuit scale in the semiconductor integrated circuit based on at least the maximum delay of the semiconductor integrated circuit;
An operating frequency information management step for deriving an operating frequency characteristic that specifies the level of the operating frequency in the semiconductor integrated circuit;
An unconsidered delay time creation step for creating an unconsidered delay time characteristic that represents a circuit delay time that does not consider semiconductor manufacturing variations and depends on the operating environment of the semiconductor integrated circuit;
A delay time calculation step for creating and managing a circuit delay time characteristic considering manufacturing variations in a semiconductor integrated circuit from the variation delay sensitivity characteristic, the circuit scale characteristic, the operating frequency characteristic, and the non-considered delay time characteristic And a circuit delay verification program for a semiconductor integrated circuit.

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