JP5257828B2 - Circuit board and connection method thereof - Google Patents

Description

  The present invention relates to a circuit board and a connection method therefor, and more particularly, to a circuit board on which a planarizing film covering a wiring layer provided on the substrate is formed and a connection method therefor.

  2. Description of the Related Art In recent years, thin, lightweight, power-saving liquid crystal display devices and organic electroluminescence (hereinafter abbreviated as “organic EL”) as monitors for thin televisions and personal computers, and as display devices for mobile phones and portable music players. ) The spread of display devices is remarkable. In these display devices, an active matrix driving method having generally excellent display characteristics is employed.

  As is well known, a liquid crystal display panel and an organic EL display panel corresponding to the active matrix driving method have a plurality of display pixels arranged in a matrix on an insulating substrate, and display on each display pixel is displayed on the display pixel. A thin film transistor (TFT; pixel transistor or selection transistor) is provided as a selection switch for controlling a data (for example, gradation signal voltage) writing operation.

  Here, as a display pixel applied to an active matrix driving type organic EL display panel, a pixel circuit including a plurality of thin film transistors (TFTs) is known. As described, a planarization film (layer) is formed so as to cover the pixel circuit (a plurality of thin film transistors) provided on a substrate, and an organic EL element is stacked thereon. ing.

JP 2005-11793 A (Pages 7 to 11, FIG. 1)

In a display panel (circuit board) in which a planarization film is formed on a thin film transistor provided on a substrate as described above, the planarization film is outside a pixel formation region (pixel area) on the substrate, for example, Wiring terminals such as Flexible Printed Circuit (FPC) outside the board and COG (Chip)
On Glass), when it is formed up to the terminal area connected to the terminal part of the IC chip used for mounting (hereinafter referred to as “external wiring terminal part”), the planarizing film formed on the substrate A wiring layer (for example, a wiring layer directly or indirectly connected to the thin film transistor; hereinafter referred to as “TFT wiring layer”) formed in the opening and below the planarizing film in the opening and the external wiring A terminal structure for connecting the terminal part is employed.

  Here, the planarizing film needs to have a certain thickness in order to ensure flatness on the surface. However, in the opening formed in the planarizing film, for example, a conductive film containing conductive particles or a conductive film is formed. When connecting the TFT wiring layer and the external wiring terminal portion via an adhesive or the like, if the particle size of the conductive particles is smaller than the film thickness of the flattening film, the vertical direction through the conductive particles In this case, there is a problem that the continuity does not function sufficiently, resulting in poor connection and deterioration in manufacturing yield. Similarly, in COG mounting, if the thickness of the terminal portion of the IC chip is smaller than the thickness of the planarizing film, a connection failure occurs.

  Therefore, in view of the above-described problems, the present invention has a terminal structure (device structure) that can satisfactorily connect a wiring layer connected to a circuit element provided on a substrate and an external wiring terminal portion. It is an object of the present invention to provide a circuit board and a method for connecting the circuit board.

According to a first aspect of the present invention, there is provided a circuit board comprising: a wiring layer formed on the substrate; a planarization film in which an opening exposing a part of the wiring layer is formed; and the opening through the opening. The wiring layer is connected to the wiring layer and extends from the opening to a predetermined region on the planarizing film, and is connected to the wiring terminal portion outside the substrate in the predetermined region through conductive particles. A thin film transistor having a terminal electrode, a display element arranged on the substrate and having a pixel electrode, and a specific electrode connected directly or indirectly to the pixel electrode of the display element and driving the display element A plurality of display pixels, and the wiring layer is directly or indirectly connected to a power source and connected to the drive circuit. Power supply voltage line, Furthermore, corresponding to the predetermined region formed by extending the terminal electrode, the terminal electrode extends below the planarizing film and is formed in the same layer as the specific electrode of the thin film transistor. The terminal electrode is connected to the terminal electrode through a contact hole provided in the planarization film, and directly or indirectly connected to the specific electrode of the thin film transistor, and the terminal electrode is connected to the selection line. The pixel is formed of a single layer or a plurality of conductive layers including a conductive metal oxide layer having at least one terminal pad portion and a second terminal pad portion connected to the power supply voltage line and further having a light transmission characteristic. Formed in the same layer as the electrode, the drive circuit is formed below the planarization film, the display element is formed in an upper layer of the planarization film, the planarization film is made of an organic material, The pixel area in which a plurality of display pixels are arranged, and characterized in that it is formed so as to cover the area where the terminal electrodes are formed.

3. The circuit board connection method according to claim 2 , wherein the circuit board includes a wiring layer formed on the substrate, and a planarization film in which an opening exposing a part of the wiring layer is formed. A terminal electrode connected to the wiring layer through the opening and extending from the opening to a predetermined region on the planarization film; and a pixel electrode arranged on the substrate, A plurality of display pixels, comprising: a display element comprising: a display circuit having a thin film transistor that is directly or indirectly connected to the pixel electrode of the display element and has a specific electrode for driving the display element; The wiring layer includes a selection line that sets the display pixel to a selected state, and a power supply voltage line that is directly or indirectly connected to a power source and connected to the driving circuit. The terminal electrode extends Corresponding to the formed predetermined region, a contact hole is formed in the same layer as the specific electrode of the thin film transistor so as to extend below the planarizing film and provided in the planarizing film. The terminal electrode is connected directly or indirectly to the specific electrode of the thin film transistor, and the terminal electrode is connected to the first terminal pad portion connected to the selection line and the power supply voltage line A single terminal layer or a plurality of conductive layers including a conductive metal oxide layer having at least a light transmission property, and the driving circuit is formed in the same layer as the pixel electrode. The display element is formed below the planarization film, the display element is formed on an upper layer of the planarization film, the planarization film is made of an organic material, and a pixel element in which the plurality of display pixels are arranged. A, and is formed so as to cover the area where the terminal electrodes are formed, and characterized in that the predetermined area of the terminal electrodes via the conductive particles connecting the substrate external wiring terminal To do.

  According to the circuit board and the connection method thereof according to the present invention, it is possible to satisfactorily connect the wiring layer connected to the circuit element and the external wiring terminal portion.

  Hereinafter, a circuit board according to the present invention, a method for manufacturing the circuit board, and a method for connecting the circuit boards will be specifically described. Here, after first showing the basic structure of the circuit board according to the present invention and referring to its function and effect, an embodiment when applied to an organic EL display panel will be described in detail.

<Basic structure of circuit board>
FIG. 1 is a schematic configuration diagram showing a first example of a connection structure between a wiring layer and an external wiring terminal portion, which is applied to a circuit board according to the present invention. FIG. 2 is a schematic configuration diagram showing a second example of the connection structure between the wiring layer and the external wiring terminal portion, which is applied to the circuit board according to the present invention. Here, FIG. 1 (a) and FIG. 2 (a) are main part plan views of a terminal structure applied to the circuit board according to the present invention, and FIG. 1 (b) is shown in FIG. 1 (a). FIG. 2 is a schematic cross-sectional view showing a cross section along the line IA-IA in this plan view (in this specification, “I” is used as a symbol corresponding to the Roman numeral “1” shown in FIG. 1 for convenience). 2B is a line IIC-IIC in the plan view shown in FIG. 2A (in this specification, as a symbol corresponding to the Roman numeral “2” shown in FIG. 2 for the sake of convenience). It is a schematic sectional drawing which shows the cross section along "II".

  The terminal structure of the circuit board according to the first example of the present invention is a connection structure between the board 1 and the film board 7, and for example, as shown in FIGS. 1 (a) and 1 (b), the film board 7 A plurality of external wirings connected to the IC chip are formed on one surface, and the external wiring includes the external wiring terminal portion 8 in the terminal connection region Rtm. A wiring layer 3 is formed on an insulating film 2 such as a gate insulating film provided on one surface of an insulating substrate 1 such as a glass substrate, and the wiring layer 3 is formed on a transistor (not shown) provided on the substrate 1. It is connected. Then, a relatively thick (about 2 μm to several tens of μm) planarizing film 4 made of an organic material is coated on the wiring layer 3, and the contact hole (opening) CH provided in the planarizing film 4 is formed. The terminal electrode 5 is formed so as to be connected to the wiring layer 3 and to have one end extending to the terminal connection region Rtm on the planarizing film 4. On the planarizing film 4 in the pixel area, a light emitting element having a pair of electrodes is formed as will be described later. The film substrate 7 is thermocompression bonded to the substrate 1 via an anisotropic conductive adhesive, and the external wiring terminal portion 8 of the film substrate 7 has an anisotropic conductive adhesive as shown in FIG. It is electrically connected to the terminal electrode 5 formed to extend to the terminal connection region Rtm through a plurality of minute conductive particles 6 dispersed in the adhesive 9 such as.

  Here, the wiring layer 3 formed below the planarizing film 4 is, for example, a circuit element such as a TFT provided in a pixel circuit formed in the pixel area on the substrate 1 (not shown; details will be described later). The gate electrode, the source, and the drain electrode are patterned to form the gate electrode, the source, and the drain electrode integrally or in the same layer, for example, directly or indirectly connected to the electrode. It may be.

  Further, as shown in FIGS. 1A and 1B, the wiring layer 3 extends below the planarizing film 4 corresponding to the terminal connection region Rtm in which the terminal electrode 5 extends. It may be formed. According to this, since the flatness of the upper surface of the flattening film 4 in the terminal connection region Rtm can be improved by making the flattening film 4 sufficiently thick, a pair of electrodes of a light emitting element on the flattening film 4 (described later). Since the pixel electrode 15 and the counter electrode 19) to be formed can be formed in a smooth region, it is possible to prevent the pair of electrodes from being short-circuited in the vertical direction due to the unevenness of the planarizing film 4, and to planarize the pair of electrodes. Regardless of the film thickness of the film 4, the terminal electrode 5 and the external wiring terminal portion 8, and thus the IC chip and the transistor provided on the substrate 1 can be satisfactorily connected.

  The terminal electrode 5 is formed by patterning a conductive layer that becomes an electrode (for example, an anode electrode or a cathode electrode of an organic EL element) that forms a display pixel formed in a pixel area on the planarizing film 4, for example. Or may be formed in the same layer. FIG. 1 shows a case where a single transparent electrode layer using a transparent electrode material such as tin-doped indium oxide (ITO), which becomes a pixel electrode of an organic EL element, is formed as the terminal electrode 5. It was.

  The planarizing film 4 is made of a resin material (organic material) such as acrylic, polyimide, or polyamide, and has a thickness of 2 μm to several tens of μm. Here, the cross section of the contact hole CH where the wiring layer 3 below the flattening film 4 is exposed has a flattening film as shown in FIG. 1B so that the terminal electrode 5 is not disconnected by the step of the contact hole CH. 4 is formed in a tapered shape (inclined cross section) so that the opening area increases from the lower surface (lower side of the drawing) to the upper surface (upper side of the drawing). Further, the external wiring terminal portion 8 is not limited to the wiring terminal portion of the film substrate 7 but may be a terminal portion such as a bump electrode of an IC chip used in COG mounting.

  That is, in the circuit board according to the present invention, the terminal connection region Rtm to which the terminal electrode 5 and the external wiring terminal portion 8 are connected is connected to the wiring layer 3 exposed below the terminal electrode 5 and the planarizing film 4. The contact hole CH is, for example, the extending direction of the terminal electrode 5 (the left-right direction in the drawing), and is separate both in plan (see FIG. 1 (a)) and in section (see FIG. 1 (b)). It is provided independently in the area.

  In the first example (FIG. 1) described above, a case where a single transparent electrode layer made of a transparent electrode material such as ITO is formed as the terminal electrode 5 is shown. However, as a second example of the circuit board, For example, as shown in FIGS. 2 (a) and 2 (b), a metal layer 5a having, for example, reflection characteristics is formed below the ITO transparent electrode layer 5b, and the metal layer is formed by the upper transparent electrode layer 5b. An electrode structure having a two-layer structure covering the upper surface and side surfaces of 5a may be applied. The metal layer 5a and the transparent electrode layer 5b function as pixel electrodes of the organic EL element.

  Next, after showing the comparative example of the circuit board according to the present invention (hereinafter referred to as “comparison target”) and verifying its characteristics, the effectiveness of the operational effects of the present invention will be described. Here, as shown in the prior art, in the panel substrate in which the planarization film is also formed around the terminal portion, the wiring layer formed below the planarization film in the opening provided in the planarization film A connection structure in which the external wiring terminal portion is connected is a comparison target.

  FIG. 3 is a schematic configuration diagram showing a first example (first comparison target) of a connection structure between a wiring layer to be compared and an external wiring terminal portion of the circuit board according to the present invention. FIG. 5 is a schematic configuration diagram showing a second example (second comparison target) of a connection structure between a wiring layer to be compared and an external wiring terminal portion of the circuit board according to the present invention. Here, FIG. 3A and FIG. 4A are plan views of main parts of a terminal structure applied to a circuit board according to each comparison target, and FIG. 3B is a plan view of FIG. Schematic sectional view showing a section taken along line IIIE-IIIE in this plan view (in this specification, “III” is used as a symbol corresponding to the Roman numeral “3” shown in FIG. 3 for convenience) 3 (a) is a plan view taken along the line IIIF-IIIF shown in FIG. 3 (b), and FIG. 4 (b) is an IVG- in the plan view shown in FIG. 4 (a). FIG. 5 is a schematic cross-sectional view showing a cross-section along line IVG (in this specification, “IV” is used as a symbol corresponding to the Roman numeral “4” shown in FIG. 4 for convenience); ) Is a plan view taken along the line IVH-IVH shown in FIG. Note that the same structure as the above-described basic structure (FIGS. 1 and 2) of the transistor according to the present invention will be described with the same reference numerals. Further, in the circuit board according to the comparison object, as shown in the second example (see FIG. 2) of the basic structure of the circuit board according to the present invention described above, the metal layer 5a and the transparent electrode layer 5b are used as terminal electrodes. The case where the electrode structure which consists of a two-layer structure which laminated | stacked is applied is shown.

  As shown in FIGS. 3A and 3B, for example, the terminal structure of the circuit board according to the first comparison object includes a wiring layer 103 formed on a substrate 101 with an insulating film 102 interposed therebetween. It is connected to the wiring layer 103 exposed in the opening TH provided in the planarization film 104 formed on the layer 103 so that the peripheral edge extends to the planarization film 104 near the opening TH. A terminal electrode 105 (metal layer 105a and transparent electrode layer 105b) is formed on the film substrate 107 and the like through the conductive particles 106 contained in the anisotropic conductive adhesive or the like in the opening TH. The external wiring terminal portion 108 is connected. That is, in the first comparison object, the opening TH corresponds to the terminal connection region Rtm of the circuit board according to the present invention described above.

  In such a circuit board, when the organic material is used as the planarizing film 104 in the same manner as in the present invention described above and a relatively thick layer of about 2 μm to several tens of μm is formed, FIG. As shown, the conductive particles 106 dispersed in the adhesive 110 such as an anisotropic conductive adhesive are in close contact with and connected (crimped) to both the terminal electrode 105 and the external wiring terminal portion 108. The conductive particles 106 need to have a size larger than the thickness of the planarization film 104.

  However, in order to reduce the contact resistance, that is, to increase the number of contact points between the conductive particles per unit area and the terminal portion, the general anisotropic conductive adhesive is a film of the planarizing film 104 using an organic material. Since the particle size of the conductive particles 106 is set smaller than the thickness (for example, about several to several tens of μm), there is a problem that connection failure occurs and the manufacturing yield is reduced. In this case, it is conceivable to use an anisotropic conductive adhesive containing conductive particles 106 having a particle size larger than the thickness of the planarizing film 104. However, such a product has a special specification and is highly available. There is a problem that it is difficult or expensive.

  On the other hand, as a connection structure for solving the problem shown in FIG. 3, for example, as shown in FIGS. 4A and 4B, at least the terminal connection region Rtm (that is, the terminal electrode 105 is formed on the circuit board). The wiring layer 103 on the substrate 101 is covered only with a relatively thin inorganic insulating film 109 such as silicon oxide or silicon nitride without forming a relatively thick planarizing film 104 made of an organic material around the region) In the opening TH formed in the inorganic insulating film 109, the terminal electrode 105 connected to the wiring layer 103 and the external wiring terminal such as the FPC 107 via the conductive particles 106 contained in the anisotropic conductive adhesive or the like. The circuit board connected to the unit 108 is a second comparison target. Here, it is assumed that a region on the substrate 101 other than the terminal connection region Rtm, such as a pixel area, is covered with a thin inorganic insulating film 109 and a relatively thick planarizing film 104 made of an organic material.

  In this case, a relatively thick planarizing film is not formed around the terminal connection region Rtm, and the inorganic insulating film 109 is formed to be as thin as several hundred nm. The terminal electrode 105 and the external wiring terminal can be applied by applying a commercially available anisotropic conductive adhesive without being affected by the particle size of the conductive particles 106 combined with the anisotropic conductive adhesive as in the comparison object 1 of FIG. The part 108 can be connected well.

  However, a circuit board having such a connection structure is applied to an organic EL display panel as described later, and a conductive layer serving as an electrode (for example, an anode electrode) constituting the organic EL element is etched on the inorganic insulating film 109. Thus, when the terminal electrode 105 is formed in the same formation process as the electrode, the conductive layer is etched on a planarizing film made of an organic material as a base layer of an electrode layer (ITO or the like) patterned in the pixel area. As a result, the conductive layer in the pixel area and the terminal electrode 105 cannot be etched uniformly because the etching rate of the conductive layer is slower than that in the case where the terminal pattern is adjacent to the terminal. There has been a problem in that there is a possibility of causing a short circuit between the electrodes 105 or a breakage of the electrodes constituting the organic EL element.

  Therefore, according to the present invention, as described above (see FIGS. 1 and 2), the circuit substrate on which the relatively thick planarizing film 4 made of an organic material is formed around the terminal connection region Rtm is flat. The wiring layer 3 disposed below the conversion film 4 and the terminal electrode 5 (or the metal layer 5a and the transparent electrode layer 5b) formed simultaneously with the electrodes by patterning the conductive layer to be an electrode such as an organic EL element ) Are electrically connected through a contact hole CH formed outside the terminal connection region Rtm, and the terminal electrode 5 (the metal layer 5a and the transparent layer) formed on the planarizing film 4 from the contact hole CH is formed. The electrode layer 5b) and the external wiring terminal portion 8 such as the film substrate 7 are electrically connected via the conductive particles 6 contained in the anisotropic conductive adhesive or the like in the terminal connection region Rtm on the planarizing film 4. Has a connected connection structure To have.

  According to this, since the terminal electrode 5 and the external wiring terminal portion 8 can be connected in the terminal connection region Rtm on the flattening film 4, the film thickness of the flattening film 4, the anisotropic conductive adhesive, etc. Good electrical connection can be realized without being affected by the particle size of the conductive particles 6 contained. In addition, by simultaneously patterning a single electrode layer made of the same electrode material (ITO or the like) formed on the same base layer (flattening film 4), the electrode of the terminal electrode 5 and the organic EL element, etc. Since it can be formed, the terminal electrode 5 having a good plane pattern can be formed without being affected by the etching rate.

<Specific examples of circuit boards>
Next, a display panel to which the above-described circuit board terminal structure is applied will be described with a specific example. Here, in the specific examples shown below, an organic EL element including a light emitting functional layer (organic EL layer) formed by applying an organic material is applied as a display element (light emitting element) constituting a display pixel. The case will be described.

  FIG. 5 is a schematic plan view showing an example of an arrangement state of display pixels applied to a display panel to which the circuit board according to the present invention is applied, and FIG. 6 is a diagram of the display panel to which the circuit board according to the present invention is applied. It is an equivalent circuit diagram showing a circuit configuration example of each display pixel (light emitting element and pixel driving circuit) arranged two-dimensionally. In the plan view shown in FIG. 5, for convenience of illustration, pixels provided in each display pixel (color pixel) when the display panel (insulating substrate) is viewed from one side (light emitting element formation side). Only the electrodes and the wiring layers are shown, and the display of the transistors and the like in the pixel driving circuit (see FIGS. 6 and 7) provided in each display pixel in order to drive the organic EL element (light emitting element) of each display pixel to emit light. Omitted. Further, in FIG. 5, hatching is shown for convenience in order to clarify the arrangement of the pixel electrode and each wiring layer.

  As shown in FIG. 5, for example, the circuit board according to the present invention is applied to a pixel area located at the center of one surface side of the insulating substrate 11 such as a glass substrate (the front side of the drawing in the direction perpendicular to the paper surface). A plurality of color pixels PXr, PXg, and PXb composed of three colors (R), green (G), and blue (B) are repeatedly arranged in the row direction (left and right in the drawing) (multiples of 3), and the column direction (drawing). A plurality of color pixels PXr, PXg, and PXb of the same color are arranged in the vertical direction. Here, one display pixel PIX is formed by combining the adjacent RGB color pixels PXr, PXg, and PXb.

  The display panel 10 protrudes from one surface side of the insulating substrate 11 and has a plurality of colors of the same color arranged in the column direction by banks (partition walls) 17 arranged with a fence-like or grid-like plane pattern. A pixel formation region (each color pixel region) of the pixel PXr, PXg, or PXb is defined. In addition, pixel electrodes (for example, anode electrodes) 15 are formed in the pixel formation regions of the respective color pixels PXr, PXg, or PXb, and in the column direction (vertical direction in the drawing) in parallel with the arrangement direction of the banks 17. ), And a selection line Ls and a power supply voltage line Lv (wiring layer) are arranged in parallel in a row direction (left-right direction in the drawing) orthogonal to the data line Ld. A terminal pad portion (terminal electrode) PDs is provided at one end portion of the selection line Ls, and a terminal pad portion (terminal electrode) PDv is also provided at one end portion of the power supply voltage line Lv.

  Here, each of the terminal pad portions PDs and PDv has a terminal structure equivalent to the above-described circuit board according to the present invention (see FIGS. 1 and 2), and is formed on the selection line Ls and the power supply voltage line Lv. Terminal electrodes are connected through contact holes opened in the planarizing film (not shown; see FIG. 12). As will be described later, the terminal electrode is formed in the same process by patterning a conductive layer to be the pixel electrode 15 (for example, an anode electrode of the organic EL element) formed on the planarizing film.

  Each color pixel PXr, PXg, PXb of the display pixel PIX includes, for example, a pixel driving circuit DC having one or more transistors (for example, amorphous silicon thin film transistors; circuit elements) on an insulating substrate 11, as shown in FIG. It has a circuit configuration including an organic EL element (display element) OLED that emits light when a light emission drive current generated by the pixel drive circuit DC is supplied to the pixel electrode 15.

  Specifically, as shown in FIG. 6, for example, the pixel drive circuit DC has a gate terminal at the selection line Ls, a drain terminal at the data line Ld arranged in the column direction of the display panel 10, and a source terminal at the contact point. A transistor (selection transistor) Tr11 connected to each of N11, a transistor (light emitting drive transistor) Tr12 having a gate terminal connected to the contact N11, a drain terminal connected to the power supply voltage line Lv, and a source terminal connected to the contact N12; And a capacitor Cs connected between the gate terminal and the source terminal of the Tr12.

  Here, n-channel thin film transistors (field effect transistors) are applied to the transistors Tr11 and Tr12. If the transistors Tr11 and Tr12 are p-channel type, the source terminal and the drain terminal are opposite to each other. The capacitor Cs is a parasitic capacitance formed between the gate and the source of the transistor Tr12, an auxiliary capacitance additionally provided between the gate and the source, or a capacitance component composed of these parasitic capacitance and auxiliary capacitance. is there.

  The organic EL element OLED has an anode terminal (pixel electrode 15 serving as an anode electrode) connected to the contact N12 of the pixel drive circuit DC and a cathode terminal (cathode electrode) formed integrally with the counter electrode 19, and has a predetermined reference. It is directly or indirectly connected to the voltage Vcom (for example, the ground potential Vgnd). Here, as shown in FIG. 5, the counter electrode 19 is a single electrode layer so as to face the pixel electrodes 15 of the plurality of display pixels PIX two-dimensionally arranged on the insulating substrate 11. (Solid electrode). Thereby, the reference voltage Vcom is commonly applied to the plurality of display pixels PIX.

  In the display pixel PIX shown in FIG. 5 (pixel drive circuit DC and organic EL element OLED shown in FIG. 6), the selection line Ls is connected to a selection driver (not shown), and the row of the display panel 10 is displayed at a predetermined timing. A selection signal Ssel for setting a plurality of display pixels PIX (color pixels PXr, PXg, PXb) arranged in the direction to a selected state is applied. The data line Ld is connected to a data driver (not shown), and a gradation signal Vpix corresponding to display data is applied at a timing synchronized with the selection state of the display pixel PIX.

  Further, the power supply voltage line Lv is directly or indirectly connected to a predetermined high potential power supply, for example, and display data is displayed on the pixel electrode 15 of the organic EL element OLED provided in each display pixel PIX (color pixels PXr, PXg, PXb). A predetermined high voltage (power supply voltage Vdd) having a potential higher than the reference voltage Vcom applied to the counter electrode 19 of the organic EL element OLED is applied in order to flow a light emission driving current according to the above.

  That is, in the pixel driving circuit DC shown in FIG. 6, the transistor Tr12 and the organic EL element OLED that are connected in series in each display pixel PIX are connected to both ends (the drain terminal of the transistor Tr12 and the cathode terminal of the organic EL element OLED). A power supply voltage Vdd and a reference voltage Vcom are respectively applied to apply a forward bias to the organic EL element OLED so that the organic EL element OLED can emit light, and further flows to the organic EL element OLED according to the gradation signal Vpix. The current value of the light emission drive current is controlled.

  The drive control operation in the display pixel PIX having such a circuit configuration is first performed at a selection level (on level; for example, high level) during a predetermined selection period from a selection driver (not shown) to the selection line Ls. By applying the selection signal Ssel, the transistor Tr11 is turned on and the display pixel PIX is set to the selected state. In synchronization with this timing, control is performed so that a gradation signal Vpix having a voltage value corresponding to display data is applied to the data line Ld from a data driver (not shown). As a result, a potential corresponding to the gradation signal Vpix is applied to the contact N11 (that is, the gate terminal of the transistor Tr12) via the transistor Tr11.

  In the pixel drive circuit DC having the circuit configuration shown in FIG. 2, the current value of the drain-source current of the transistor Tr12 (that is, the light emission drive current flowing through the organic EL element OLED) is the potential difference between the drain-source and the gate. -Determined by the potential difference between the sources. Here, the power supply voltage Vdd applied to the drain terminal (drain electrode) of the transistor Tr12 via the power supply voltage line Lv, and the cathode terminal (cathode electrode) of the organic EL element OLED via the counter electrode 19 described above. Since the reference voltage Vcom is a fixed value, the potential difference between the drain and source of the transistor Tr12 is fixed in advance by the power supply voltage Vdd and the reference voltage Vcom. Since the potential difference between the gate and source of the transistor Tr12 is uniquely determined by the potential of the gradation signal Vpix, the current value of the current flowing between the drain and source of the transistor Tr12 is controlled by the gradation signal Vpix. be able to.

  In this way, the transistor Tr12 is turned on in a conductive state corresponding to the potential of the contact N11 (that is, a conductive state corresponding to the gradation signal Vpix), and the transistor Tr12 and the organic EL element OLED are turned on from the power supply voltage Vdd on the high potential side. Since a light emission driving current having a predetermined current value flows through the reference voltage Vcom (ground potential Vgnd) on the low potential side through the organic EL element OLED, the luminance gradation corresponding to the gradation signal Vpix (that is, display data) The flash operates with. At this time, charges are accumulated (charged) in the capacitor Cs between the gate and the source of the transistor Tr12 based on the gradation signal Vpix applied to the contact N11.

  Next, in a non-selection period after the end of the selection period, by applying a selection signal Ssel of a non-selection level (off level; for example, low level) to the selection line Ls, the transistor Tr11 of the display pixel PIX is turned off, The display pixel PIX is set to a non-selected state, and the data line Ld and the pixel drive circuit DC (specifically, the contact N11) are electrically disconnected. At this time, the charge accumulated in the capacitor Cs is held, so that the voltage corresponding to the gradation signal Vpix is held at the gate terminal of the transistor Tr12 (that is, the potential difference between the gate and the source is held). It becomes a state.

  Accordingly, similarly to the light emission operation in the selected state, a predetermined light emission drive current flows from the power supply voltage Vdd to the organic EL element OLED via the transistor Tr12, and the light emission operation state is continued. This light emitting operation state is controlled so as to continue, for example, for one frame period until the next gradation signal Vpix is applied (written). Then, such a drive control operation is sequentially executed for every row, for example, for all the display pixels PIX (each color pixel PXr, PXg, PXb) two-dimensionally arranged on the display panel 10, thereby obtaining desired image information. An image display operation to be displayed can be executed.

  In FIG. 6, the pixel driving circuit DC provided in the display pixel PIX is written in each display pixel PIX (specifically, the gate terminal of the transistor Tr12 of the pixel driving circuit DC; the contact N11) according to display data. A voltage designation type gradation control method for controlling the current value of the light emission drive current to flow through the organic EL element OLED by adjusting (specifying) the voltage value of the gradation signal Vpix so that the light emission operation is performed at a desired luminance gradation. Although the circuit configuration corresponding to is shown, by adjusting (specifying) the current value of the current supplied (written) to each display pixel PIX according to the display data, the current value of the light emission drive current passed through the organic EL element OLED It is also possible to have a circuit configuration of a current designation type gradation control system that controls light emission and performs light emission operation at a desired luminance gradation.

(Device structure of display pixel)
Next, a specific device structure (planar layout and cross-sectional structure) of the display pixel (light emission drive circuit and organic EL element) having the circuit configuration as described above will be described, and application of the present invention will be described.

  FIG. 7 is a plan layout view showing an example of a display pixel applicable to a display panel to which the circuit board according to the present invention is applied. Here, a planar layout of one specific color pixel among the red (R), green (G), and blue (B) color pixels PXr, PXg, and PXb of the display pixel PIX shown in FIG. 5 is shown. In FIG. 7, the layer in which each transistor and wiring layer of the pixel driving circuit DC are formed is mainly shown, and hatching is performed for convenience in order to clarify the arrangement of each wiring layer and each electrode. Indicated. FIG. 8 is a schematic sectional view showing a sectional structure of the display pixel having the planar layout shown in FIG. FIG. 8A shows the VIIJ-VIIJ line in the planar layout shown in FIG. 7 (in this specification, “VII” is used as a symbol corresponding to the Roman numeral “7” shown in FIG. 7 for convenience). 8B is a schematic cross-sectional view showing a cross section taken along line VIIK-VIIK in the planar layout shown in FIG.

  Specifically, the display pixels PIX (color pixels PXr, PXg, PXb) shown in FIG. 6 are pixel formation regions (organic EL elements in the color pixels PXr, PXg, PXb) set on one surface side of the insulating substrate 11. In Rpx, for example, the selection line Ls and the power supply voltage line Lv extend so as to extend in the row direction (horizontal direction in the drawing) to the upper and lower edge regions of the planar layout as shown in FIG. And a data line Ld extending in the column direction (vertical direction in the drawing) in the left edge region of the planar layout so as to be orthogonal to the lines Ls and Lv. ing. A bank (detailed later) 17 is disposed in the right edge region of the planar layout so as to extend in the column direction across the color pixels adjacent to the right side.

  Here, for example, as shown in FIGS. 7 and 8, the data line Ld is provided on the lower side (insulating substrate 11 side) than the selection line Ls and the power supply voltage line Lv, and the gate electrodes Tr11g of the transistors Tr11 and Tr12. By patterning the gate metal layer for forming Tr12g, it is formed in the same layer as the gate electrodes Tr11g and Tr12g in the same process as the gate electrodes Tr11g and Tr12g. The data line Ld is connected to the drain electrode Tr11d of the transistor Tr11 through a contact hole CH11 provided in the gate insulating film 12 formed thereon.

  The selection line Ls and the power supply voltage line Lv are provided on the upper layer side than the data line Ld and the gate electrodes Tr11g and Tr12g, and are sources for forming the source electrodes Tr11s and Tr12s and drain electrodes Tr11d and Tr12d of the transistors Tr11 and Tr12. By patterning the drain metal layer, it is formed in the same process as the source electrodes Tr11s and Tr12s and the drain electrodes Tr11d and Tr12d.

  The selection line Ls is connected to the gate electrode Tr11g via a contact hole CH12 provided in the gate insulating film 12 located at both ends of the gate electrode Tr11g of the transistor Tr11. The power supply voltage line Lv is formed integrally with the drain electrode Tr12d of the transistor Tr12.

  For example, as shown in FIG. 7, each circuit element of the pixel drive circuit DC is arranged so that the transistor Tr11 shown in FIG. 6 extends in the row direction, and the transistor Tr12 extends in the column direction. Are arranged as follows. Here, each of the transistors Tr11 and Tr12 has a well-known field effect type thin film transistor structure, and is formed in a region corresponding to each of the gate electrodes Tr11g and Tr12g via the gate electrodes Tr11g and Tr12g and the gate insulating film 12, respectively. And the source electrodes Tr11s and Tr12s and the drain electrodes Tr11d and Tr12d formed so as to extend to both ends of the semiconductor layer SMC.

  Note that a channel made of silicon oxide or silicon nitride for preventing etching damage to the semiconductor layer SMC is provided on the semiconductor layer SMC where the source electrodes Tr11s and Tr12s and the drain electrodes Tr11d and Tr12d of the transistors Tr11 and Tr12 face each other. A protective layer BL is formed, and an ohmic connection between the semiconductor layer SMC and the source electrodes Tr11s and Tr12s and the drain electrodes Tr11d and Tr12d is provided between the source electrodes Tr11s and Tr12s and the drain electrodes Tr11d and Tr12d and the semiconductor layer SMC. An impurity layer OHM for realizing the above is formed.

  Then, to correspond to the circuit configuration of the pixel drive circuit DC shown in FIG. 6, the transistor Tr11 is selected via the contact hole CH12 in which the gate electrode Tr11g is provided in the gate insulating film 12, as shown in FIG. The drain electrode Tr11d is connected to the line Ls, and is connected to the data line Ld through a contact hole CH11 provided in the gate insulating film 12.

  As shown in FIGS. 7 and 8, the transistor Tr12 has a gate electrode Tr12g connected to the source electrode Tr11s of the transistor Tr11 via a contact hole CH13 provided in the gate insulating film 12, and the drain electrode Tr12d connected to the power supply voltage. The source electrode Tr12s is formed integrally with the line Lv, and is connected to the pixel electrode 15 of the organic EL element OLED via a contact hole CH14 provided in the inorganic insulating film 13 and the planarizing film 14.

  7 and 8, the capacitor Cs includes an electrode Eca formed integrally with the gate electrode Tr12g of the transistor Tr12 on the insulating substrate 11, and a source electrode of the transistor Tr12 on the gate insulating film 12. The electrode Ecb formed integrally with the Tr 12 s is provided so as to face the gate insulating film 12. Further, as described above, the contact hole CH14 is provided in the inorganic insulating film 13 and the planarization film 14 on the electrode Ecb, and is connected to the pixel electrode 15 of the organic EL element OLED via the contact hole CH14.

  As shown in FIGS. 7 and 8, the organic EL element OLED is formed on the inorganic insulating film 13 made of silicon oxide or the like formed so as to cover the pixel driving circuit DC (transistors Tr11, Tr12, capacitor Cs, etc.). A planarizing film 14 made of a resin material or the like for planarizing at least a region where the organic EL element is formed is formed, and penetrates the inorganic insulating film 13 and the planarizing film 14 on the planarizing film 14. A light composed of a reflective layer 15a having a light reflection characteristic and a transparent electrode layer 15b having a light transmission characteristic, which is connected to the source electrode Tr12s of the transistor Tr12 through a provided contact hole CH14 and supplied with a predetermined light emission drive current. On the planarizing film 14 between the pixel electrode (for example, anode electrode) 15 having transmission characteristics and the pixel electrode 15 between the adjacent display pixels PIX. It is formed in the pixel forming region Rpx defined by the formed interlayer insulating film 16 and the bank 17 disposed so as to protrude from the surface of the insulating substrate 11 (interlayer insulating film 16) (which is a region surrounded by the bank 17). The organic EL layer (light emitting functional layer) 18 composed of the hole transport layer 18a and the electron transport light emitting layer 18b and the pixel electrode 15 of each display pixel PIX arranged two-dimensionally on the insulating substrate 11 are opposed to each other. A counter electrode (for example, a cathode electrode) 19 composed of a single electrode layer (solid electrode) having light transmission characteristics provided in such a manner is sequentially laminated. The counter electrode 19 is provided so as to extend not only on each pixel formation region Rpx but also on the bank 17 that defines the pixel formation region Rpx.

  Here, in the panel structure shown in FIGS. 7 and 8, the selection line Ls and the power supply voltage line Lv are used as the source and drain metals for forming the source electrodes Tr11s and Tr12s and the drain electrodes Tr11d and Tr12d of the transistors Tr11 and Tr12. The layer is formed by patterning, the selection line Ls is connected to the gate electrode Tr11g of the transistor Tr11 via the contact hole CH12, the power supply voltage line Lv is formed integrally with the drain electrode Tr12d of the transistor Tr12, and the data The line Ld is formed by patterning a gate metal layer for forming the gate electrodes Tr11g and Tr12g of the transistors Tr11 and Tr12, and the drain electrode T of the transistor Tr11 is formed through the contact hole CH11. Although the case of connecting to r11d has been described, the display panel to which the circuit board according to the present invention is applicable is not limited to this, and the selection metal Ls and the power supply voltage line Lv are patterned by patterning the gate metal layer. The selection line Ls is formed without forming the contact holes CH11 and CH12 by forming the data line Ld above the gate insulating film 12 and forming the data line Ld on the gate insulating film 12 by patterning the source and drain metal layers. The data line Ld may be provided integrally with the gate electrode Tr11g and the drain electrode Tr11d. In this case, a contact hole for connecting the drain electrode Tr12d and the power supply voltage line Lv is formed instead.

  The bank 17 is a boundary region (a region between the pixel electrodes 15) between a plurality of display pixels PIX (each color pixel PXr, PXg, PXb) that is two-dimensionally arranged on the display panel 10, and is arranged in the column direction of the display panel 10. (The display panel 10 as a whole has a fence-like or grid-like plane pattern as shown in FIG. 5, for example). Here, as shown in FIGS. 7 and 8, the transistor Tr12 extends in the column direction of the display panel 10 (insulating substrate 11) in the boundary region, and the bank 17 For example, the transistor Tr12 is substantially covered and formed on the interlayer insulating film 16 formed between the pixel electrodes 15 in the pixel formation region Rpx of each display pixel PIX so as to continuously protrude from the surface of the insulating substrate 11. Yes. Thereby, the region (pixel formation region Rpx of the plurality of display pixels PIX arranged in the column direction (vertical direction in FIG. 5)) surrounded by the banks 17 extends in the column direction. It is defined as an application region of an organic compound material when forming the transport layer 18a and the electron transporting light emitting layer 18b).

Here, the bank 17 is formed using, for example, a photosensitive resin material, and at least its surface (side surface and upper surface) is liquid repellent with respect to the organic compound-containing liquid applied to the pixel formation region Rpx. Has been surface treated.
Further, as shown in FIGS. 8A and 8B, for example, as shown in FIGS. 8A and 8B, a protective insulating film is formed on the entire area of one surface of the insulating substrate 11 on which the pixel driving circuit DC, the organic EL element OLED, and the bank 17 are formed. A sealing layer 20 having a function as a (passivation film) is formed by coating. Furthermore, although not shown, a sealing substrate made of a glass substrate or the like may be bonded so as to face the insulating substrate 11.

  In such a display panel 10 (display pixel PIX), the light emission drive current having a predetermined current value is generated from the source of the transistor Tr12 based on the gradation signal Vpix corresponding to the display data supplied via the data line Ld. -The liquid crystal flows between the drains and is supplied to the pixel electrode 15 of the organic EL element OLED, so that the organic EL element OLED of each display pixel PIX (each color pixel PXr, PXg, PXb) has a desired luminance scale corresponding to the display data. Flashes in tone.

  Here, in the display pixel PIX having the device structure as shown in FIGS. 7 and 8, the transparent electrode layer 15b and the counter electrode 19 constituting the upper layer of the pixel electrode 15 have light transmission characteristics (high in visible light). In addition, the reflective layer 15a constituting the lower side of the pixel electrode 15 has light reflection characteristics (high reflectance with respect to visible light), so that light is emitted from the organic EL layer 18 of each display pixel PIX. The light is directly emitted to the visual field side (upper side in FIG. 8) through the counter electrode 19 having light transmission characteristics, and is reflected by the pixel electrode 15 (the reflective layer 15a constituting the lower layer) through the counter electrode 19. Is emitted to the visual field side. That is, the display panel 10 according to the present embodiment has a top emission type light emitting structure, and each circuit element and wiring layer of the pixel driving circuit DC formed on the insulating substrate 11 are as shown in FIG. The organic EL elements OLED formed on the planarizing film 14 are arranged so as to overlap in a plane.

  Note that, as described above, the present invention is not limited to a display panel (organic EL panel) having a top emission type light emitting structure, and the counter electrode 19 is formed of a conductive film having light reflection characteristics, and a pixel electrode. 15 is composed of only a transparent electrode layer such as ITO, and is applied to a display panel having a bottom emission type light emitting structure in which light emitted from the organic EL layer 18 is emitted to the insulating substrate 11 side. Also good.

  In the above-described display panel, the case where the display pixel PIX includes the organic EL element OLED that is a light emitting element and the pixel drive circuit DC including a plurality (two) of thin film transistors (TFTs) has been described. The invention is not limited to this. One or a plurality (two or more) of thin film transistors and capacitors are provided on a substrate (insulating substrate) that constitutes the display panel, and display pixels are formed by the functional elements. As long as it is driven, it can be applied well to other display panels and devices such as a liquid crystal display panel.

(Display panel manufacturing method)
Next, a method for manufacturing the display panel described above will be described.
9 to 11 are process cross-sectional views showing an example of a method for manufacturing a display panel to which the circuit board according to the present invention is applied. Here, in order to clarify the characteristics of the manufacturing method of the display panel to which the circuit board according to the present invention is applied, a part of the panel structure of the IIVJ-IIVJ section shown in FIG. 8A (transistor Tr12, capacitor Cs, The bank 17, the organic EL element OLED), the terminal pad portion PDs provided at the end portion of the selection line Ls shown in FIG. 5, and the terminal pad portion PDv provided at the end portion of the power supply voltage line Lv are extracted for convenience. The structure is shown and described. Further, the selection line Ls and the power supply voltage line Lv have a laminated wiring structure as will be described later in order to reduce resistance. 12 is a schematic cross-sectional view showing an example of a connection structure between a terminal pad portion and an external wiring terminal portion in a display panel to which the circuit board according to the present invention is applied, and FIG. 13 is an application of the circuit board according to the present invention. It is a schematic sectional drawing which shows the other example of the connection structure of the terminal pad part and external wiring terminal part in a display panel.

  In the display panel manufacturing method described above, first, as shown in FIG. 9A, display pixels PIX (respective color pixels PXr, PXg) set on one surface side (the upper surface side of the drawing) of an insulating substrate 11 such as a glass substrate. , PXb) in the pixel formation region Rpx, wiring layers such as the transistors Tr11 and Tr12, the capacitor Cs, the data line Ld, the selection line Ls, and the power supply voltage line Lv of the pixel drive circuit DC are formed (see FIGS. 7 and 8). .

  Specifically, the gate electrodes Tr11g, Tr12g, the electrode Eca on one side of the capacitor Cs formed integrally with the gate electrode Tr12g, and the data line Ld on the insulating substrate 11 are formed with the same gate metal layer. At the same time, the gate insulating film 12 made of silicon nitride is formed on the entire surface of the insulating substrate 11 by patterning.

  Next, a semiconductor layer SMC made of, for example, amorphous silicon or polysilicon is formed in a region corresponding to each of the gate electrodes Tr11g and Tr12g on the gate insulating film 12, and both ends of the semiconductor layer SMC are used for ohmic connection. Source electrodes Tr11s and Tr12s and drain electrodes Tr11d and Tr12d are formed through the impurity layer OHM.

  At this time, by patterning the same source and drain metal layers, the electrode Ecb on the other side of the capacitor Cs connected to the source electrode Tr12s is formed, and the selection line Ls and the power supply voltage line Lv are simultaneously formed. Here, the source electrodes Tr11s and Tr12s and drain electrodes Tr11d and Tr12d of the transistors Tr11 and Tr12, the electrode Ecb on the other side of the capacitor Cs, the selection line Ls, and the power supply voltage line Lv are connected as shown in FIG. For the purpose of reducing resistance and reducing migration, for example, a multilayer wiring comprising an aluminum alloy layer such as aluminum-titanium (AlTi) or aluminum-neodymium-titanium (AlNdTi) and a transition metal layer such as chromium (Cr) It may have a structure.

  Next, as shown in FIG. 9B, silicon oxide or silicon nitride is coated so as to cover the entire area of one surface of the insulating substrate 11 including the transistors Tr11 and Tr12, the capacitor Cs, the selection line Ls, and the power supply voltage line Lv. An inorganic insulating film 13 made of or the like is formed. Further, as shown in FIG. 9C, the entire area of one side of the insulating substrate 11 on which the inorganic insulating film 13 is formed (at least a pixel area in which display pixels PIX are arranged and terminal pad portions PDs and PDv to be described later). For example, an acrylic, epoxy or polyimide resin material (organic material) is applied so as to cover the region to be formed), and after prebaking, exposure, development and baking, a film of about 2 to 10 μm or more A planarizing film 14 having a thickness is formed.

  Specifically, the photosensitive acrylic resin material PC403 made by JSR can be applied satisfactorily for the planarizing film 14, and a solution containing such a resin material is applied onto the insulating substrate 11. The planarizing film 14 having a relatively thick film thickness of about 2 to over 10 μm and capable of satisfactorily relaxing the step on the surface of the insulating substrate 11 can be easily formed.

  After the patterning of the planarizing film 14 by pre-baking, exposure, development, and baking, the inorganic insulating film 13 is etched (dry etching) using the planarizing film 14 as a mask, and as shown in FIG. 9D, the source of the transistor Tr12 A contact hole (opening) CH14 exposing the upper surface of the electrode Tr12s (or the electrode Ecb on the other side of the capacitor Cs) is formed, in the vicinity of the end of the selection line Ls where the terminal pad portion PDs is provided, and the terminal pad In the vicinity of the end of the power supply voltage line Lv where the part PDv is provided, contact holes (openings) CHLs and CHLv in which the upper surfaces of the selection line Ls and the power supply voltage line Lv are exposed are formed simultaneously.

  Next, as shown in FIG. 10A, a metal material such as silver (Ag) or aluminum (Al) or the like is formed on the planarizing film 14 including the contact holes CH14, CHLs, and CHLv by using a sputtering method or the like. Forming a metal thin film having a light reflection characteristic (more specifically, having a high reflectance in the visible light range) made of an alloy material such as aluminum-neodymium-titanium (AlNdTi), and then forming the metal thin film And a reflective layer (which has a planar shape corresponding to each pixel formation region Rpx (formation region of the organic EL element OLED) and is electrically connected to the source electrode Tr12s of the transistor Tr12 exposed inside the contact hole CH14. (Reflective metal layer) 15a is formed.

  At the same time, the metal thin film is patterned to have a predetermined planar shape in the region where the terminal pad portions PDs and PDv are formed (corresponding to the terminal connection region Rtm described above), and is exposed inside the contact holes CHLs and CHLv. Metal layers Psa and Pva that are electrically connected are formed in the vicinity of the ends of the selected line Ls and the power supply voltage line Lv.

  Next, the entire surface of the insulating substrate 11 including the reflective layer 15a and the metal layers Psa and Pva is coated with tin-doped indium oxide (ITO) or zinc-doped indium oxide (Indium Zinc Oxide) by sputtering or the like. A conductive metal oxide layer (having light transmission characteristics) made of a transparent electrode material such as IZO), tungsten-doped indium oxide (IWO), or tungsten-zinc-doped indium oxide (IWZO); After forming a thin film with a thickness of about 50 nm, the conductive metal oxide layer is patterned to completely cover the reflective layer 15a as shown in FIG. 10B, and correspond to the pixel formation region Rpx. The transparent electrode layer 15b extending to the metal layer Psa and Pva are individually covered completely, and the terminal pad portions PDs, Electrode layer Psb extending the region for forming the dv, to form a Pvb. Here, ITO or the like used as a transparent electrode material can be polycrystallized when formed under a high temperature condition of 200 ° C. or higher, and the electrical resistance can be lowered and the conductivity can be increased.

  Thereby, on the planarizing film 14 near the end portion of the selection line Ls, the terminal pad portion PDs which is electrically connected to the selection line Ls and has a terminal electrode having a laminated structure including the metal layer Psa and the electrode layer Psb, and On the planarizing film 14 near the end of the power supply voltage line Lv, a terminal pad portion PDv having a laminated structure of electrode electrodes electrically connected to the power supply voltage line Lv and including the metal layer Pva and the electrode layer Pvb is formed. Is done.

  In this patterning step, the reflective layer 15a of the pixel electrode 15 is completely covered with the conductive metal oxide layer (transparent electrode layer 15b) on the upper surface and side surfaces, and the metal layers Psa and Pva of the terminal pad portions PDs and PDv are electrically conductive. Since the conductive metal oxide layer is completely covered with the conductive metal oxide layers (electrode layers Psb and Pvb) and is not exposed, patterning is performed by etching the conductive metal oxide layer. It is possible to prevent the battery reaction between the ITO (such as ITO) and the reflective layer 15a and the metal layers Psa and Pva, and the reflective layer 15a and the metal layers Psa and Pva are overetched or damaged by etching. Can be prevented.

  Next, a chemical vapor deposition method (CVD method) or the like is used to cover the entire area of the one surface side of the insulating substrate 11 including the pixel electrode 15 and the terminal pad portions PDs and PDv, for example, a silicon oxide film or a silicon nitride film. By forming an insulating layer made of an inorganic insulating material such as a film and then patterning, as shown in FIGS. 8A and 10C, adjacent display pixels PIX (color pixels PXr, PXg, PXb) and an opening where the upper surface of the pixel electrode 15 is exposed in each pixel formation region Rpx, and the terminal pad portions PDs and PDv. An interlayer insulating film 16 having an opening exposing the upper surface of the electrode layers Psb and Pvb is formed.

  Next, as shown in FIG. 10C, a bank 17 made of a photosensitive resin material such as polyimide or acrylic is formed on the interlayer insulating film 16 formed in the boundary region between adjacent display pixels PIX. Form. Specifically, a boundary region between display pixels PIX adjacent in the row direction is formed by patterning a photosensitive resin layer formed so as to cover the entire area of one surface side of the insulating substrate 11 including the interlayer insulating film 16. Then, a bank (partition) 17 having a fence-like or grid-like plane pattern (see FIG. 5) including a region extending in the column direction of the display panel 10 is formed.

  Thereby, the pixel formation region Rpx (the formation region of the organic EL layer 18 of the organic EL element OLED) of the plurality of display pixels PIX of the same color arranged in the column direction of the display panel 10 is surrounded and defined by the bank 17. The upper surface of the pixel electrode 15 whose outer edge is defined by the opening formed in the interlayer insulating film 16 is exposed.

  Next, after cleaning the insulating substrate 11 with pure water, the surface of the pixel electrode 15 exposed in each pixel formation region Rpx is subjected to, for example, oxygen plasma treatment or UV ozone treatment, so Applying a treatment to make the organic compound-containing liquid of the electron-transporting luminescent material lyophilic, and subsequently subjecting the insulating substrate 11 to a plasma treatment in, for example, a fluorine-based gas to repel the bank surface, or After immersing in a fluorine-based (fluorine compound) liquid-repellent treatment solution, the film is washed with alcohol or pure water and dried to form a liquid-repellent thin film (film) on the surface of the bank 17. The surface is made liquid repellent with respect to the organic compound-containing liquid.

  Thus, on the same insulating substrate 11, only the surface of the bank 17 is subjected to the liquid repellent treatment, and the surface of the pixel electrode 15 exposed to each pixel formation region Rpx defined by the bank 17 is not liquid repellent. (Liquidity) is maintained, so as will be described later, even when the organic EL-containing layer 18 (electron transporting light-emitting layer 18b) is formed by applying an organic compound-containing liquid, adjacent pixel formation regions It is possible to prevent leakage of the organic compound-containing liquid into Rpx and overcoming it, and to suppress color mixture between adjacent pixels, thereby enabling red, green, and blue color separation.

  As used herein, “liquid repellency” refers to an organic compound-containing liquid containing a hole transport material to be a hole transport layer 18a, which will be described later, and an electron transport light emission to be an electron transport light-emitting layer 18b. When the contact angle is measured by dropping an organic compound-containing liquid containing materials or an organic solvent used in these solutions onto an insulating substrate or the like and the contact angle is measured, the contact angle becomes 50 ° or more. It prescribes. In addition, “lyophilic” as opposed to “liquid repellency” is defined in the present embodiment as a state in which the contact angle is 40 ° or less, preferably 10 ° or less.

  Next, after applying a solution or dispersion of a hole transport material to the pixel formation region Rpx of each color surrounded (delimited) by the bank 17 by applying an inkjet method, a nozzle coating method, or the like, The hole transport layer 18a is formed by heating and drying. Subsequently, a solution or dispersion of an electron transporting light emitting material is applied on the hole transporting layer 18a, and then heated and dried to form the electron transporting light emitting layer 18b. As a result, as shown in FIG. 11A, the organic EL layer 18 composed of the hole transport layer 18a and the electron transport light emitting layer 18b is laminated on the pixel electrode 15 exposed in each pixel formation region Rpx.

  Specifically, as an organic compound-containing liquid (compound-containing liquid) containing an organic polymer-based hole transport material, for example, a polyethylenedioxythiophene / polystyrenesulfonic acid aqueous solution (PEDOT / PSS; polyethylenedioxy which is a conductive polymer) After applying thiophene PEDOT and a dispersion liquid of polystyrene sulfonic acid PSS as a dopant in an aqueous solvent) on the pixel electrode 15, the pixel electrode 15 is subjected to a heat drying treatment to remove the solvent. An organic polymer hole transport material is fixed thereon to form a hole transport layer 18a as a carrier transport layer.

  Further, as an organic compound-containing liquid (compound-containing liquid) containing an organic polymer-based electron-transporting light-emitting material, for example, a light-emitting material containing a conjugated double bond polymer such as polyparaphenylene vinylene-based or polyfluorene-based, tetralin, After applying a solution dissolved in an organic solvent or water such as tetramethylbenzene, mesitylene, xylene or the like onto the hole transport layer 18a, the solvent is removed by performing a heat drying process on the hole transport layer 18a. Then, an organic polymer electron transporting light emitting material is fixed to the electron transporting light emitting layer 18b which is a carrier transporting layer and also a light emitting layer.

  Thereafter, as shown in FIG. 11B, a light-transmissive conductive layer (transparent electrode layer) is formed on the insulating substrate 11 including at least the pixel formation region Rpx of each display pixel PIX, and the organic EL layer is formed. A common counter electrode (for example, cathode electrode) 19 is formed to face each pixel electrode 15 via 18 (hole transport layer 18a and electron transport light emitting layer 18b).

  Specifically, the counter electrode 19 is formed by forming a thin film made of a metal material such as barium, magnesium or lithium fluoride as an electron injection layer by, for example, vapor deposition or the like, and then transparently forming ITO or the like on the upper layer by sputtering or the like. A transparent film structure can be applied in which the electrode layers are stacked and formed in the thickness direction. Here, the counter electrode 19 is not only a region facing the pixel electrode 15 but also a single conductive layer (not shown) extending over the bank 17 that defines the pixel formation region Rpx (formation region of the organic EL element OLED). Solid electrode).

  Next, after the counter electrode 19 is formed, a sealing layer 20 made of a silicon oxide film, a silicon nitride film, or the like is formed as a protective insulating film (passivation film) over the entire surface of one surface of the insulating substrate 11 by using a CVD method or the like. Thus, the display panel 10 having a cross-sectional structure as shown in FIGS. 8 and 11C is completed. Although not shown, in addition to the panel structure as shown in FIGS. 8 and 11C, a sealing lid or a sealing substrate made of a glass substrate or the like so as to face the insulating substrate 11 is used. May be joined.

  Then, in the display panel 10 manufactured by the manufacturing method as described above, as shown in FIG. 12, for example, the display panel 10 is formed to extend on the planarizing film 14 in the vicinity of the end portion of the insulating substrate 11, and the interlayer insulating film The upper surface is exposed in the opening formed in 16, and the terminal pad portion PDs electrically connected to the selection line Ls and the power supply voltage line Lv disposed below the planarization film 14 and the inorganic insulating film 13, An anisotropic conductive adhesive in which a plurality of conductive particles 201 are dispersed in adhesive 209 is applied on PDv (electrode layers Psb, Pvb), and terminal pad portions PDs, PDv are applied to film substrates 202s, 202v, respectively. The terminal pad portions PDs and PDv are connected to the external wiring terminal portions 203s and 203v through the conductive particles 201 by thermocompression bonding, respectively.

  Thus, according to the display panel to which the circuit board according to the present invention is applied and the connection method thereof, the connection between the terminal pad portion and the selection line or the power supply voltage line below the planarization film, the terminal pad portion and the external wiring The connection with the terminal part is performed in a different region, and by having a connection structure in which the external wiring terminal part is connected to the terminal pad part extending on the flattening film, the film thickness and anisotropic conductivity of the flattening film Good electrical connection can be realized without being affected by the particle size of the conductive particles contained in the adhesive or the like.

  Further, by extending the selection line and the power supply voltage line below the planarization film on which the terminal pad portion is formed, the flatness of the upper surface of the planarization film is improved, and the terminal pad portion and the external wiring terminal portion are Can be satisfactorily connected, and a step corresponding to the thickness of the selection line and the power supply voltage line occurs between adjacent terminal pad portions, so that a short circuit between the terminal pad portions can be prevented.

  Further, when forming the metal layers Psa and Pva constituting the terminal pad portion and the electrode layers Psb and Pvb into the pixel electrodes (reflection layer and transparent electrode layer) constituting the organic EL element of the display pixel, the same process is performed. Since it can be formed simultaneously by application, the manufacturing process can be simplified. In particular, the terminal pad portion and the pixel electrode can be formed by simultaneously patterning a single electrode layer made of the same electrode material (ITO or the like) formed on the same base layer (planarization film). Therefore, it is possible to form the terminal pad portion and the pixel electrode having a good plane pattern without short circuit or breakage without being affected by the etching rate caused by the underlying layer.

  In the above embodiment, as the pixel electrode 15, the electrode layer Psb, Pvb, and the transparent electrode layer 15 b made of crystalline ITO or the like are formed on the planarizing film 14 with the reflective layer 15 a and the metal layers Psa, Pva interposed therebetween. However, the present invention is not limited thereto, and as shown in FIG. 13, electrode layers Psb and Pvb and a transparent electrode layer 15 b made of crystalline ITO or the like may be formed directly on the planarizing film 14.

  In the patterning process of the transparent electrode layer 15b and the electrode layers Psb and Pvb shown in FIGS. 12 and 13, the underlying layer of the transparent electrode layer 15b formed in the pixel formation region Rpx and the formation regions of the terminal pad portions PDs and PDv are formed. Since the underlying layers of the electrode layers Psb and Pvb to be formed are both the planarizing film 14 made of an organic resin material, the etching rate when patterning the conductive metal oxide layer made of crystalline ITO or the like can be improved. it can.

  Specifically, as shown in the second comparison object (see FIG. 4), an inorganic insulating film made of silicon nitride (SiN) is formed as a base layer of a conductive metal oxide layer made of crystalline ITO. The etching rate of the ITO film using an I-1 etching solution manufactured by Nagase ChemteX as an etchant for crystalline ITO is about 0.5 nm / sec (= 5 sec / sec), whereas the above-mentioned layer is used as a base layer. When the planarizing film made of the acrylic resin material PC403 made by JSR is formed, the etching rate of the ITO film using the above etchant is about 1.5 nm / sec (= 15 Å / sec), which is remarkable. Is different.

  Therefore, in the second comparative structure described above, the etching rate of the ITO film in the terminal pad portion is lower than that in the pixel formation region Rpx due to the difference in the underlying layer, and the ITO film has a pattern defect. In the display panel to which the circuit substrate according to the invention is applied, the planarizing film 14 made of a resin material is formed over the entire area of the insulating substrate 11 including the pixel formation region Rpx and the formation regions of the terminal pad portions PDs and PDv. Etching can be performed evenly and promptly, and the occurrence of pattern defects in the ITO film can be prevented.

  In the structure shown in FIG. 13, since the pixel electrode 15 is transparent, the organic EL display panel has a so-called bottom emission structure in which light emitted from the organic EL layer 18 is emitted to the insulating substrate 11 side. The electrode 19 is preferably light-reflective by a laminated structure of a low work function metal layer such as magnesium or barium and a high work function metal layer such as aluminum covering the metal layer.

  In the display panel of each embodiment described above, the selection line Ls directly or indirectly connected to the gate electrode Tr11g of the transistor Tr11 of the pixel drive circuit shown in FIG. 6 and the drain electrode Tr12d of the transistor Tr12 are connected. Although the case where the terminal structure of the circuit board according to the present invention is applied to the terminal pad portions PDs and PDv connected to the power supply voltage line Lv connected directly or indirectly has been described, the present invention is limited to this. The present invention is not applied to the terminal pad portion connected to the data line Ld connected to the source electrode Tr11s of the transistor Tr11 and the terminal pad portion connected to other bus wirings other than these wiring layers. Also good.

  Moreover, in the display panel of each embodiment described above, the case where a resin material (organic material) having a large film thickness and high flatness is used as the flattening film has been described, but the present invention is not limited to this. Alternatively, for example, a thick inorganic insulating film made of silicon oxide, silicon nitride, or the like may be used. In this case, since the planarity is inferior to the planarization film using the resin material, the selection line and the power supply voltage line are extended below the planarization film where the terminal pad portion is formed as described above. Accordingly, the flatness of the upper surface of the flattening film can be improved, and the terminal pad portion and the external wiring terminal portion can be satisfactorily connected.

It is a schematic block diagram which shows the 1st example of the connection structure of a wiring layer applied to the circuit board which concerns on this invention, and an external wiring terminal part. It is a schematic block diagram which shows the 2nd example of the connection structure of a wiring layer applied to the circuit board which concerns on this invention, and an external wiring terminal part. It is a schematic block diagram which shows the 1st example (1st comparison object) of the connection structure of the wiring layer used as a comparison object, and an external wiring terminal part of the circuit board based on this invention. It is a schematic block diagram which shows the 2nd example (2nd comparison object) of the connection structure of the wiring layer used as a comparison object, and an external wiring terminal part of the circuit board based on this invention. It is a schematic plan view which shows an example of the arrangement state of the display pixel applied to the display panel to which the circuit board based on this invention is applied. It is an equivalent circuit diagram showing a circuit configuration example of each display pixel (light emitting element and pixel driving circuit) two-dimensionally arranged on a display panel to which the circuit board according to the present invention is applied. It is a plane layout figure which shows an example of the display pixel applicable to the display panel to which the circuit board based on this invention is applied. It is a schematic sectional drawing which shows the cross-sectional structure in the display pixel which has the planar layout shown in FIG. It is process sectional drawing (the 1) which shows an example of the manufacturing method of the display panel to which the circuit board based on this invention is applied. It is process sectional drawing (the 2) which shows an example of the manufacturing method of the display panel to which the circuit board based on this invention is applied. It is process sectional drawing (the 3) which shows an example of the manufacturing method of the display panel to which the circuit board based on this invention is applied. It is a schematic sectional drawing which shows an example of the connection structure of the terminal pad part and external wiring terminal part in the display panel to which the circuit board based on this invention is applied. It is a schematic sectional drawing which shows the other example of the connection structure of the terminal pad part and external wiring terminal part in the display panel to which the circuit board based on this invention is applied.

Explanation of symbols

1 Substrate 2 Insulating film 3 Wiring layer 4 Flattening film 5 Terminal electrode 6 Conductive particle 7 Film substrate 8 External wiring terminal portion CH Contact hole

Claims (2)

A wiring layer formed on the substrate;
A planarization film in which an opening exposing a part of the wiring layer is formed;
The wiring layer is connected to the wiring layer through the opening, and is formed to extend from the opening to a predetermined region on the planarizing film, and is formed outside the substrate in the predetermined region through conductive particles. A terminal electrode connected to the wiring terminal portion of
A drive circuit comprising a display element arranged on the substrate and having a pixel electrode, and a thin film transistor which is directly or indirectly connected to the pixel electrode of the display element and has a specific electrode for driving the display element A plurality of display pixels, and
Have,
The wiring layer includes a selection line for setting the display pixel to a selected state, and a power supply voltage line connected directly or indirectly to a power source and connected to the driving circuit, and the terminal electrode extends. Corresponding to the predetermined region formed in this manner, the contact is formed in the same layer as the specific electrode of the thin film transistor so as to extend below the planarizing film and provided in the planarizing film. Connected to the terminal electrode through a hole and directly or indirectly to the specific electrode of the thin film transistor;
The terminal electrode has a first terminal pad portion connected to the selection line and a second terminal pad portion connected to the power supply voltage line, and further has a conductive metal oxide layer having at least light transmission characteristics. Formed in the same layer as the pixel electrode by a single layer or a plurality of conductive layers including,
The drive circuit is formed below the planarization film, the display element is formed in an upper layer of the planarization film,
The circuit board , wherein the planarizing film is made of an organic material and covers a pixel area where the plurality of display pixels are arranged and a region where the terminal electrode is formed . In the circuit board connection method,
The circuit board is
A wiring layer formed on the substrate;
A planarization film in which an opening exposing a part of the wiring layer is formed;
A terminal electrode connected to the wiring layer through the opening and extending from the opening to a predetermined region on the planarizing film;
A drive circuit comprising a display element arranged on the substrate and having a pixel electrode, and a thin film transistor which is directly or indirectly connected to the pixel electrode of the display element and has a specific electrode for driving the display element A plurality of display pixels, and
Have
The wiring layer includes a selection line for setting the display pixel to a selected state, and a power supply voltage line connected directly or indirectly to a power source and connected to the driving circuit, and the terminal electrode extends. Corresponding to the predetermined region formed in this manner, the contact is formed in the same layer as the specific electrode of the thin film transistor so as to extend below the planarizing film and provided in the planarizing film. Connected to the terminal electrode through a hole and directly or indirectly to the specific electrode of the thin film transistor;
The terminal electrode has a first terminal pad portion connected to the selection line and a second terminal pad portion connected to the power supply voltage line, and further has a conductive metal oxide layer having at least light transmission characteristics. Formed in the same layer as the pixel electrode by a single layer or a plurality of conductive layers including,
The drive circuit is formed below the planarization film, the display element is formed in an upper layer of the planarization film,
The planarization film is made of an organic material, and is formed so as to cover a pixel area where the plurality of display pixels are arranged, and a region where the terminal electrode is formed,
Wherein the predetermined area, the connection method for the circuit board, characterized in that via the conductive particles connecting the substrate external wiring terminal portions of said terminal electrodes.

Images