JP5254732B2 - Electronics - Google Patents

Description

The present invention relates to an electronic device such as a process controller provided with a deterioration detection device that detects deterioration of a backup capacitor that supplies power as a backup power supply when a main power supply is cut off.

  In the process controller that controls the plant equipment, it is necessary to retain the operation data at that time and use it at the next startup when the main power is cut off. When the main power is cut off, the data must be stored in the memory by some method. Conventionally, the data is saved to the static RAM (Random Access Memory) instantly within a few ms after the main power is cut off. A backup method using a battery or the like has been adopted. However, there are users who do not like battery backup because the controller operating temperature range is wider than the battery operating temperature range or the battery replacement is troublesome. In addition, due to the OS (Operating System) of the controller, necessary data may not be saved within a few ms after the main power is turned off.

  Therefore, a special backup power supply that does not use a battery is provided, and power is continuously supplied from the backup power supply to the CPU for a few seconds to several tens of seconds after the main power supply is cut off. A method of writing data to a (Only Memory) or the like is employed. Since the flash ROM is a non-volatile memory, no battery is required. Since no battery is used, the operating temperature range can be widened. As the backup power source, a large capacity (for example, 100 F) capacitor called an electric double layer capacitor is used. In this backup power supply, the electric double layer capacitor is charged during normal operation, and discharged when the main power supply is cut off to supply power to the CPU for several seconds to several tens of seconds.

The problem with such a backup power supply is that the electric double layer capacitor also has a longer life than the battery, but also has a life. In the case of an aluminum electrolytic capacitor that is used as a smoothing capacitor, even if the life approaches and the capacity decreases, the smoothing characteristics deteriorate and ripples and the like are only slightly increased. For such a decrease in the capacity of the smoothing capacitor, a large capacity is selected in advance. Even if a capacitor with a large capacity is used, the cost hardly increases.
On the other hand, since the electric double layer capacitor has a larger shape than the aluminum electrolytic capacitor, if a capacitor having a large capacity is selected in advance in anticipation of a decrease in capacity due to secular change, there is a problem that the cost increases and the space increases.

  When the capacity of the electric double layer capacitor used for the backup power supply decreases, the power is continuously supplied for the time (several seconds to several tens of seconds) necessary for the CPU to write operation data to the flash ROM when the main power supply is turned off. Thus, the operation data cannot be completely written to the flash ROM. For example, if it is necessary to supply power for only 9 seconds when at least 10 seconds are required for data writing, data cannot be written.

  The secular change of the capacity of the electric double layer capacitor is greatly influenced by the operating temperature environment. When the electric double layer capacitor is used in a temperature environment of 25 ° C., the deterioration rate is halved, for example, compared to the case where it is used in a temperature environment of 35 ° C. However, the manufacturer of the controller cannot grasp how many temperature environments the end user uses the process controller. Also, the operating current value increases or decreases depending on the combination of the controller I / O cards. Therefore, when the replacement cycle of the electric double layer capacitor is uniformly determined in consideration of the lifetime, the replacement cycle is determined under the harshest conditions. In this case, even if the replacement cycle is optimal for the user who uses the worst condition, the replacement cycle is too early for the user who uses the average usage condition, which results in unnecessary cost.

  In order to extend the replacement cycle of the electric double layer capacitor as much as possible, it is necessary to optimize the replacement cycle for each user. To determine the optimal replacement cycle, it is necessary to predict the life of the electric double layer capacitor. . Conventionally, a process controller maintenance support system has been proposed as means for predicting the life of a capacitor (see, for example, Patent Document 1). In this maintenance support system, power supply voltage data and ripple data are collected so as to grasp the deterioration state of the electrolytic capacitor.

JP 2003-248515 A

  In the maintenance support system disclosed in Patent Document 1, voltage and ripple data of an electrolytic capacitor used as a smoothing capacitor for a power supply are measured during normal operation. Therefore, in order to apply the technique disclosed in Patent Document 1 to the life prediction of the electric double layer capacitor of the backup power supply, the discharge characteristics of the electric double layer capacitor when the main power supply is cut off are predicted from the measurement data during energization. Therefore, it is difficult to predict the discharge characteristics, and it is difficult to detect deterioration of the electric double layer capacitor. Further, in the maintenance support system disclosed in Patent Document 1, it is necessary to measure voltage and ripple data, and it is difficult to perform measurement when the main power supply cannot supply power to the measurement circuit.

The present invention has been made to solve the above problems, and provides an electronic device capable of detecting deterioration of a backup capacitor such as an electric double layer capacitor and optimizing the replacement period of the backup capacitor for each user. For the purpose.

The electronic device according to the present invention includes a main power supply that supplies power during normal operation, a backup capacitor that supplies power as a backup power supply when the main power is turned off, and data to be retained when the main power is cut off. Data backup means for writing to the volatile memory, and the backup capacitor deterioration detecting device, the backup capacitor deterioration detecting device comprising: timing means for writing timing data in the nonvolatile memory, reads the timing data from the nonvolatile memory when activated by the main power, inoperable by the voltage drop of the backup capacitor from when the main power-off Margin time deriving means for obtaining a margin time until the And a warning means for generating a warning that should be replaced click-up capacitor, the clock means has a writing of the timing data starts after completion of writing of data by the data saving means, the margin time deriving means The time from the completion of data writing by the data saving means until the operation becomes impossible due to the voltage drop of the backup capacitor is obtained as the margin time .

  According to the present invention, the time data is written to the non-volatile memory when the main power supply is interrupted, and the time data is read from the non-volatile memory at the next start-up to obtain the margin time. Can be indirectly estimated, and it can be determined how much room is available for the required power. In this way, according to the present invention, the replacement period of the backup capacitor can be optimized for each user. Therefore, efficient operation suitable for the user's usage environment can be performed, and useless replacement of the backup capacitor can be prevented.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a backup capacitor deterioration detection apparatus according to an embodiment of the present invention. This backup capacitor deterioration detection device is mounted on, for example, a process controller that controls plant equipment.

  In FIG. 1, 1 is a main power supply circuit of a process controller, 2 is an electric double layer capacitor as a backup capacitor, 3 is a charging circuit for the electric double layer capacitor 2, and 4 is a regulator for stabilizing the output voltage of the electric double layer capacitor 2. Circuit 5 is a CPU of the process controller, 6 is an OR circuit composed of a diode that OR-connects the output of the main power supply circuit 1 and the output of the regulator circuit 4, and 7 is a power cut-off detection circuit that detects the power cut-off of the main power supply circuit 1. , 8 is an I / O interface circuit connected to plant equipment (not shown), 9 is a flash ROM which is a nonvolatile memory, 10 is an EEPROM which is also a nonvolatile memory, and 11 is that the electric double layer capacitor 2 should be replaced. Warning circuit for warning, 12 drops the output voltage of the OR circuit 6 to a voltage required by the CPU 5 It was a regulator circuit to stabilize. The electric double layer capacitor 2, the charging circuit 3, and the regulator circuit 4 constitute a backup power supply circuit.

  The CPU 5 executes processing as described below according to a program stored in an internal memory (not shown), the flash ROM 9 or the EEPROM 10. The CPU 5 constitutes data saving means, timing means, and margin time deriving means.

  During normal operation when the main power supply circuit 1 is on, the output voltage of the main power supply circuit 1 is supplied to the CPU 5 via the OR circuit 6 and the regulator circuit 12. At this time, the electric double layer capacitor 2 is charged by a charging voltage supplied from the main power supply circuit 1 via the charging circuit 3. The voltage output from the main power supply circuit 1 to the OR circuit 6 is, for example, 5.5V, and the voltage output to the charging circuit 3 is, for example, 6V. The output voltage of the electric double layer capacitor 2 is stabilized by the regulator circuit 4. Assuming that the output voltage of the electric double layer capacitor 2 is 6V and the voltage required by the CPU 5 is 3.3V, the regulator circuit 4 drops the output voltage of the electric double layer capacitor 2 to, for example, 5V or less and stabilizes it. Although the output voltage of the regulator circuit 4 is supplied to the OR circuit 6, the output voltage of the main power supply circuit 1 is higher. Therefore, when the main power supply circuit 1 is on, the main power supply circuit 1 and the OR circuit 6 and the regulator Electric power is supplied to the CPU 5 through the circuit 12. The regulator circuit 12 drops the output voltage of the OR circuit 6 to 3.3 V and stabilizes it.

  The CPU 5 collects data of plant input devices (for example, sensors, pressure gauges, flow meters, etc.) via the I / O interface circuit 8 and executes control calculations based on this data. The CPU 5 controls plant output devices (eg, switches, valves, pumps, etc.) via the I / O interface circuit 8. Thus, the plant equipment is controlled by the process controller.

Next, the operation when the main power supply is cut off due to, for example, maintenance of the apparatus will be described. When the main power supply circuit 1 is turned off, electric power is supplied from the electric double layer capacitor 2 to the CPU 5 through the regulator circuit 4, the OR circuit 6, and the regulator circuit 12.
On the other hand, when the main power supply circuit 1 is turned off, the power-off detection circuit 7 outputs a main power-off detection signal to the CPU 5.

  FIG. 2 is a flowchart showing the operation of the CPU 5 when the main power supply is interrupted. When the main power-off detection signal is input from the power-off detection circuit 7 (YES in step S1 in FIG. 2), the CPU 5 determines that the main power-off has occurred and flashes operation data to be held in, for example, a few seconds. Writing to the ROM 9 (step S2). Subsequently, the CPU 5 writes time-measurement data to the EEPROM 10 at regular intervals (for example, every second) until a reset occurs (step S3). As an example of the time measurement data, for example, there is an elapsed time from the write completion time. When the power supply voltage from electric double layer capacitor 2 falls below the lower limit voltage required for operation and a reset occurs (YES in step S4), the process in FIG.

  FIG. 3 is a diagram illustrating an example of the secular change of the capacitance of the electric double layer capacitor 2. In FIG. 3, C0 is an initial capacity, and CL is a lower limit capacity necessary for writing operation data. The capacity of the electric double layer capacitor 2 decreases with time, and finally falls below the lower limit capacity CL. Below the lower limit capacity CL, it becomes impossible for the CPU 5 to continuously supply power for the time required to write the operation data to the flash ROM 9, so that the operation data cannot be written to the flash ROM 9.

  FIG. 4 is a diagram showing the change over time of the output voltage of the electric double layer capacitor 2 and the voltage supplied from the electric double layer capacitor 2 to the CPU 5 via the regulator circuit 4, the OR circuit 6, and the regulator circuit 12. Here, the time when the main power interruption occurred is set to zero. In FIG. 4, VC0 is an initial output voltage of the electric double layer capacitor 2, VC1 is an output voltage when the electric double layer capacitor 2 deteriorates, V0 is an initial voltage supplied to the CPU 5, and V1 is an electric double layer capacitor 2. This is a voltage supplied to the CPU 5 when it deteriorates. ST is the completion time of writing operation data to the flash ROM 9, RT0 is the initial reset time, and RT1 is the reset time when the electric double layer capacitor 2 is deteriorated.

  As time elapses from when the main power is turned off, the electric double layer capacitor 2 is discharged, and the voltage of the electric double layer capacitor 2 gradually decreases as shown in FIG. When the voltage required for the CPU 5 is 3.3 V, the voltage of the electric double layer capacitor 2 needs to be about 4 V in consideration of the voltage drop in the regulator circuits 4 and 12. Therefore, the voltage supplied to the CPU 5 decreases from the time when the voltage of the electric double layer capacitor 2 falls below 4V. When the voltage supplied to the CPU 5 falls below the lower limit voltage necessary for operation, a reset occurs.

  As described above, the timing data is written in the EEPROM 10 until the reset occurs after the completion of the writing of the operation data to the flash ROM 9, so if the timing data is read from the EEPROM 10 when the main power supply circuit 1 is turned on again, It is possible to grasp the margin time from the write completion time to the reset time. As apparent from FIG. 4, the voltage drop of the electric double layer capacitor 2 is accelerated by the deterioration of the electric double layer capacitor 2, so that the occurrence of reset is accelerated and the margin time is also reduced. Therefore, it can be determined whether or not the electric double layer capacitor 2 should be replaced based on the margin time.

  FIG. 5 is a flowchart showing the operation of the CPU 5 when the main power is turned on. When main power supply circuit 1 is turned on (YES in step S10 in FIG. 5), CPU 5 is activated. The activated CPU 5 reads the time-measurement data from the EEPROM 10, and obtains a margin time from the write completion time to the reset time based on the time-measurement data (step S11). Then, the CPU 5 determines whether or not the margin time is equal to or less than a predetermined time (step S12).

  When the surplus time exceeds the predetermined time (NO in step S12), the CPU 5 determines that there is a surplus in the life of the electric double layer capacitor 2, ends the processing in FIG. The plant equipment is controlled as follows. Further, when the margin time is equal to or shorter than the predetermined time, the CPU 5 determines that the electric double layer capacitor 2 has reached the end of life and generates warning information indicating that the electric double layer capacitor 2 should be replaced in the warning circuit 11. (Step S13). As an example of a warning, there is a method of turning on a warning LED, for example. Further, warning information indicating that the electric double layer capacitor 2 should be replaced may be transmitted to another device via the network.

  As described above, in the present embodiment, the time data is written to the EEPROM 10 when the main power supply is interrupted, and the time data is read from the EEPROM 10 at the next start-up to obtain the margin time. The capacity drop of the double layer capacitor 2 can be estimated indirectly, and it can be determined how much margin is available for the required power. In this way, in this embodiment, the replacement cycle of the electric double layer capacitor 2 can be optimized for each user, so that efficient operation suitable for the user's use environment can be performed, and the electric double layer capacitor 2 is wasted. Exchange can be prevented. Usually, the process controller may be turned off, for example, once every weekend or month. If timekeeping data is written in the EEPROM 10 at the time of the stop, it can be determined whether or not there is a margin in the life of the electric double layer capacitor 2 at the next start-up.

  In this embodiment, the writing of timing data is started after the completion of the writing of the operation data to the flash ROM 9, but the present invention is not limited to this, and the writing of the timing data is started when the main power supply is interrupted. May be started.

  The present invention can be applied to a technique for detecting deterioration of a backup capacitor.

It is a block diagram which shows the structure of the deterioration detection apparatus of the backup capacitor which concerns on embodiment of this invention. It is a flowchart which shows operation | movement of CPU when the main power supply cutoff generate | occur | produces in embodiment of this invention. It is a figure which shows one example of the secular change of the capacity | capacitance of an electric double layer capacitor. It is a figure which shows the time change of the voltage supplied to CPU through the regulator circuit and OR circuit from the output voltage of an electric double layer capacitor and an electric double layer capacitor in embodiment of this invention. It is a flowchart which shows operation | movement of CPU at the time of starting in embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Main power supply circuit, 2 ... Electric double layer capacitor, 3 ... Charging circuit, 4, 12 ... Regulator circuit, 5 ... CPU, 6 ... OR circuit, 7 ... Power-off detection circuit, 8 ... I / O interface circuit, 9 ... flash ROM, 10 ... EEPROM, 11 ... warning circuit.

Claims (1)

A main power supply for supplying power during normal operation;
A backup capacitor that supplies power as a backup power source when the main power is cut off
Data saving means for writing data to be stored in the nonvolatile memory when the main power supply is interrupted;
A backup capacitor deterioration detection device,
The backup capacitor deterioration detection device is:
Power-off detection means for detecting main power-off,
Timing means for writing timing data in the non-volatile memory when the main power failure is detected,
Reading timing data from the nonvolatile memory when activated by the main power, the margin time derivation means for determining a margin time from the main power off until disabled by the voltage drop of the backup capacitor,
Warning means for generating a warning indicating that the backup capacitor should be replaced when the margin time is a predetermined time or less ,
The timing means starts writing the timing data after the data saving by the data saving means is completed,
The electronic device according to claim 1, wherein the margin time deriving unit obtains, as the margin time, a time from the completion of data writing by the data saving unit until the operation becomes impossible due to a voltage drop of the backup capacitor.

Images