JP5242068B2 - GaN-based semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a GaN-based semiconductor device in which a plurality of GaN-based semiconductor elements having a GaN-based semiconductor layer are formed on one substrate, and a method for manufacturing the same.

  GaN-based electronic devices have a larger band gap energy than GaAs-based materials, and have high heat resistance and excellent high-temperature operation. Therefore, field effect transistors using these materials, especially GaN / Al GaN-based semiconductors. (Field Effect Transistor: FET) is being developed.

  Conventionally, as a field effect transistor using a GaN-based semiconductor, a GaN-based HEMT (High Electron Mobility Transistor) composed of a gallium nitride-based compound semiconductor is known (see, for example, Patent Document 1). . In this GaN-based HEMT, a buffer layer is formed on a substrate as necessary, a carrier traveling layer and a carrier supply layer are epitaxially grown in order, and electrodes are further laminated.

As another prior art, a buffer layer having a structure in which a plurality of first layers made of AlN and second layers made of GaN are alternately stacked on a substrate made of silicon is provided. A structure for forming a gallium nitride based semiconductor region is known (see, for example, Patent Document 2).
JP 2006-173582 A JP 2003-59948 A

  Conventionally, a GaN-based semiconductor element such as the GaN-based HEMT described in Patent Documents 1 and 2 is a lateral element, so that a large element can be formed by connecting a plurality of GaN-based semiconductor elements. At that time, a large element is formed by connecting the gate, source, and drain of each element.

  When making such a large element, it is desirable to have a substrate made of the same material as GaN, but since a good quality substrate has not been obtained at present, a GaN-based semiconductor layer such as GaN is used as a silicon substrate, sapphire substrate, or SiC substrate. Often formed on top.

  However, when a large device having a high breakdown voltage and a large current is formed by forming a plurality of GaN-based semiconductor devices such as a GaN-based HEMT on a conductive substrate such as a silicon substrate, the leakage current of the buffer layer is large. As a result, the current is increased, and as a result, the breakdown voltage of the large element is lowered, and there is a problem that a high voltage cannot be applied to the large element. That is, when a conductive substrate such as a silicon substrate is used, the leak current of the buffer layer flows as a buffer leak current in the conductive substrate, and it has been difficult to realize a GaN-based semiconductor device having a high breakdown voltage and a large current. This is mainly because the conductivity of the silicon substrate and the insulating properties of the GaN / AlN laminated structure that is the buffer layer are incomplete.

  The present invention has been made in view of such conventional problems, and the object thereof is to reduce a leakage current flowing through a substrate even when a large element is formed using a conductive substrate such as a silicon substrate. Another object of the present invention is to provide a GaN-based semiconductor device capable of realizing a large element having a large current and a high breakdown voltage, and a method for manufacturing the same.

  In order to solve the above problems, a GaN-based semiconductor device according to the first aspect of the present invention is a GaN-based semiconductor device having at least a buffer layer and a semiconductor operating layer on a substrate, wherein at least the semiconductor operating layer is electrically connected. Insulating regions that are electrically insulated are formed.

  According to this aspect, at least the semiconductor operation layer is electrically insulated and separated by the insulating region, and the leakage current of the buffer layer is reduced. Therefore, even when a large element is formed using a conductive substrate such as a silicon substrate, a leak current flowing through the substrate can be reduced, and a large element having a large current and a high withstand voltage can be realized.

  A GaN-based semiconductor device according to another aspect of the present invention is characterized in that the insulating region is formed so as to separate a semiconductor operation layer on the substrate into a plurality of semiconductor operation layer regions.

  According to this aspect, since the semiconductor operation layer on the substrate is electrically insulated and separated into a plurality of semiconductor operation layer regions by the insulating region, even when a large element is formed using a conductive substrate such as a silicon substrate, A leak current flowing through the substrate can be reduced, and a large element having a large current and a high withstand voltage can be realized.

  The present invention is applied to, for example, the following three modes in which the semiconductor operation layer on the substrate is separated into a plurality of regions by the insulating region.

  (1) As shown in FIG. 1, the semiconductor operation layer 101 formed on the substrate 100 is separated into a plurality of independent semiconductor operation layer regions 103 by a plurality of insulating regions 102.

  (2) As shown in FIG. 2, the semiconductor operation layer 101 is separated into a plurality of semiconductor operation layer regions 103A partially continuous by a plurality of insulating regions 102A.

  (3) As shown in FIG. 3, the semiconductor operation layer 101 is arranged in an island shape (matrix shape) by the insulating region 102B and separated into a plurality of independent semiconductor operation layer regions 103B.

  In the GaN-based semiconductor device according to another aspect of the present invention, a plurality of unit elements are formed by each of the plurality of semiconductor operation layer regions and electrodes formed on the semiconductor operation layer regions, The plurality of unit elements function as one element by electrically connecting the electrodes of the unit elements.

  According to this aspect, a plurality of unit elements are formed by each semiconductor operation layer region in which the semiconductor operation layer on the substrate is electrically insulated and separated into a plurality of regions, and the electrode formed on each semiconductor operation layer region. By forming and electrically connecting the electrodes of the plurality of unit elements, the plurality of unit elements function as one element. Further, the semiconductor operation layer regions of the plurality of unit elements are electrically insulated and separated by the insulating regions, and the leakage current of the buffer layer in each unit element is reduced. Therefore, even when a large element is formed using a conductive substrate such as a silicon substrate, a leak current flowing through the substrate can be reduced, and a large element having a large current and a high withstand voltage can be realized.

Note that a leakage current hardly occurs in a region where the device does not operate as a design or a region where the gate electrode is formed and pinched off. For example, as shown in FIG. It is also good.
As described above, the “plurality of unit elements” in the present invention includes the following three forms.

  (1) As shown in FIG. 1, a plurality of unit elements 110 are formed by each semiconductor operation layer region 103 and electrodes (not shown) formed on each semiconductor operation layer region 103.

  (2) As shown in FIG. 2, a plurality of unit elements 110A are formed by each semiconductor operation layer region 103A and electrodes (not shown) formed on each semiconductor operation layer region 103A. (3) As shown in FIG. 3, a plurality of unit elements 110B are formed by each semiconductor operation layer region 103B and electrodes (not shown) formed on each semiconductor operation layer region 103B.

  In the GaN-based semiconductor device according to another aspect of the present invention, the insulating region is formed on the outer periphery of each of the plurality of unit elements. And formed on the outer periphery of the GaN-based semiconductor device.

  According to this aspect, the semiconductor operation layer region of each unit element is electrically insulated and separated by the insulating region formed on the outer periphery of each unit element, and the leakage current of the buffer layer of each unit element is reduced.

  The GaN-based semiconductor device according to another aspect of the present invention is characterized in that the plurality of semiconductor operation layer regions are electrically insulated until reaching the buffer layer by the insulating region.

  According to this aspect, since the plurality of semiconductor operation layer regions are electrically insulated and separated until reaching the buffer layer by the insulating region, even when a large element is formed using a conductive substrate such as a silicon substrate, The flowing leak current can be reduced, and a large element having a large current and a high breakdown voltage can be realized.

The GaN-based semiconductor device according to another aspect of the present invention is characterized in that the buffer layer is formed of a semiconductor layer mainly composed of Al _x Ga _1-x N or a stacked structure thereof.

According to this aspect, even when a semiconductor layer mainly composed of Al _x Ga _1-x N or a buffer layer having a stacked structure thereof is formed on a conductive substrate such as a silicon substrate, the buffer leak current is applied to the substrate. The flowing leak current can be reduced, and a large element having a large current and a high breakdown voltage can be realized.

In the GaN-based semiconductor device according to the present invention, the buffer layer is a semiconductor layer mainly composed of Al _x Ga _1-x N, a single layer of GaN, a single layer of AlN, or a stacked structure of AlN and GaN. It may consist of. Al _x Ga _1-x N may contain other elements such as B and P as appropriate. Moreover, as a laminated structure, for example, a structure in which GaN and AlN are alternately laminated can be used.

  In the GaN-based semiconductor device according to another aspect of the present invention, the insulating region is a region formed in the semiconductor operation layer on the substrate to a depth at which a high-resistance ion implantation region reaches at least the buffer layer. It is characterized by.

  According to this aspect, the semiconductor operation layer on the substrate is electrically insulated and separated to the depth reaching the buffer layer by the high resistance ion implantation region for each unit element. For this reason, even when a large element is formed using a conductive substrate such as a silicon substrate, the leak current flowing through the substrate as a buffer leakage current can be reduced, and a large element having a large current and a high withstand voltage can be realized. Become.

  In the GaN-based semiconductor device according to another aspect of the present invention, the ion implantation region is ion-implanted using ions of hydrogen, boron, nitrogen, fluorine, silicon, Mg, carbon, Zn, and the like. And

  According to this aspect, the ion implantation region is formed using ions such as hydrogen, boron, nitrogen, fluorine, silicon, Mg, carbon, and Zn.

  In the GaN-based semiconductor device according to another aspect of the present invention, the insulating region is formed by a groove having a depth that divides at least the semiconductor operation layer, and the plurality of unit elements form a first mesa structure by the groove. It is characterized by that.

  According to this aspect, each unit element is electrically insulated and separated to at least a depth at which the semiconductor operation layer is divided by the groove having a depth at which the semiconductor operation layer is divided. For this reason, even when a large element is formed using a conductive substrate such as a silicon substrate, the leak current flowing through the substrate as a buffer leakage current can be reduced, and a large element having a large current and a high withstand voltage can be realized. Become.

  The GaN-based semiconductor device according to another aspect of the present invention is characterized in that an insulating film made of an electrically high resistance material is embedded in the groove.

  According to this aspect, each unit element is electrically insulated and separated by the insulating film made of a high-resistance material embedded in a groove having a depth that divides at least the semiconductor operation layer. For this reason, even when a large element is formed using a conductive substrate such as a silicon substrate, the leak current flowing through the substrate as a buffer leakage current can be reduced, and a large element having a large current and a high withstand voltage can be realized. Become.

  The GaN-based semiconductor device according to another aspect of the present invention is characterized in that each of the semiconductor operation layer regions has a step, and the plurality of unit elements form a second mesa structure by the step. .

  According to this aspect, the semiconductor operation layer regions of the plurality of unit elements form the second mesa structure by the step, and the unit elements are electrically insulated and separated by the step forming the second mesa structure. Therefore, the characteristics of each unit element can be measured during the process of forming a large element by connecting electrodes of a plurality of units.

In the GaN-based semiconductor device according to another aspect of the present invention, the plurality of unit elements are formed of a semiconductor layer mainly composed of Al _x Ga _1-x N formed on the substrate, or a stacked structure thereof. A buffer layer, a channel layer made of GaN formed on the buffer layer, an electron supply layer made of AlGaN formed on the channel layer, and a gate electrode and a source electrode respectively formed on the electron supply layer And a drain electrode, each of which is a GaN-based heterojunction field effect transistor.

  According to this aspect, it is possible to realize a large element having a large current and a high breakdown voltage composed of a plurality of GaN-based heterojunction field effect transistors (Hetero-junction FETs: HFETs). For example, a large element having a gate width of 200 mm can be manufactured by connecting 1000 HFETs having a gate width of 200 μm with multilayer wiring.

  A GaN-based semiconductor device according to another aspect of the present invention is formed as a large element by connecting the gate electrodes, the source electrodes, and the drain electrodes with a multilayer wiring between the plurality of unit elements, respectively. It is characterized by that.

  According to this aspect, the gate electrodes, the source electrodes, and the drain electrodes of the GaN-based heterojunction field effect transistors that respectively constitute the plurality of unit elements are connected by the multilayer wiring, so that a large GaN-based HFET is formed. A large element with high current and high withstand voltage can be realized.

  The GaN-based semiconductor device according to another aspect of the present invention is characterized in that the plurality of unit elements are GaN-based MOS field effect transistors.

  According to this aspect, it is possible to realize a large element having a large current and a high breakdown voltage composed of GaN-based MOS field effect transistors that respectively constitute a plurality of unit elements.

  The GaN-based semiconductor device according to another aspect of the present invention is characterized in that the plurality of GaN-based semiconductor elements are GaN-based Schottky diodes.

  According to this aspect, it is possible to realize a large element having a large current and a high breakdown voltage composed of a GaN-based Schottky diode that constitutes each of the plurality of unit elements.

  A GaN-based semiconductor device according to another aspect of the present invention is characterized in that the plurality of unit elements include different types of GaN-based semiconductor elements.

  According to this aspect, by including different types of GaN-based semiconductor elements in the plurality of unit elements, GaN-based semiconductor integrated circuits including different types of GaN-based semiconductor elements, such as GaN-based Schottky diodes and GaN-based HFETs, Is an integrated circuit formed on a single substrate, and a GaN-based semiconductor integrated circuit with little leakage current flowing through the substrate, which is insulated and separated for each unit element, can be realized.

  In order to solve the above-described problem, a method for manufacturing a GaN-based semiconductor device according to the second aspect of the present invention includes a method for manufacturing a GaN-based semiconductor device having at least a buffer layer and a semiconductor operation layer on a substrate. Forming an insulating region that electrically insulates the semiconductor operation layer, separating the semiconductor operation layer on the substrate into a plurality of semiconductor operation layer regions, and forming electrodes on the plurality of semiconductor operation layer regions, respectively; And a step of forming a plurality of unit elements, and a step of electrically connecting the electrodes between the plurality of unit elements, wherein the plurality of unit elements function as one element. To do.

  According to this aspect, the semiconductor operating layer on the substrate is electrically insulated and separated into a plurality of semiconductor operating layer regions by the insulating region, and electrodes are formed on each semiconductor operating layer region to form a plurality of unit elements, The electrodes of the plurality of unit elements are electrically connected so that the plurality of unit elements function as one element. Therefore, even when a large element is formed using a conductive substrate such as a silicon substrate, a leak current flowing through the substrate can be reduced, and a large element having a large current and a high withstand voltage can be realized.

  In the method of manufacturing a GaN-based semiconductor device according to another aspect of the present invention, the step of forming the insulating region and separating the semiconductor operation layer on the substrate into a plurality of semiconductor operation layer regions includes the semiconductor operation on the substrate. Implanting the layer with ions such as hydrogen, boron, nitrogen, fluorine, silicon, Mg, carbon, Zn, etc. to a depth reaching the substrate or the vicinity of the substrate, and after the ion implantation, the ion implantation is performed. Forming a high resistance ion implantation region by performing heat treatment on the region.

  According to this aspect, the semiconductor operation layer on the substrate is ion-implanted with ions such as hydrogen to a depth reaching the substrate or the vicinity of the substrate, and after the ion implantation, the ion-implanted region is subjected to a heat treatment to increase the height. By forming the resistance ion implantation region, the semiconductor operation layer on the substrate is electrically isolated and separated to the depth reaching the buffer layer by the high resistance ion implantation region for each unit element. For this reason, even when a large element is formed using a conductive substrate such as a silicon substrate, the leak current flowing through the substrate as a buffer leakage current can be reduced, and a large element having a large current and a high withstand voltage can be realized. Become.

  In the method of manufacturing a GaN-based semiconductor device according to another aspect of the present invention, in the ion implantation step, the high resistance ion implantation region is formed to a depth reaching at least the buffer layer for each unit element. Features.

  According to this aspect, since the semiconductor operation layer on the substrate is electrically insulated and separated to the depth reaching the buffer layer for each unit element by the high resistance ion implantation region, a large element having a large current and a high breakdown voltage can be obtained. It becomes feasible.

  In the method for manufacturing a GaN-based semiconductor device according to another aspect of the present invention, the step of forming the insulating region and separating the semiconductor operating layer on the substrate into a plurality of semiconductor operating layer regions includes the plurality of semiconductor operations. Forming a mesa structure having a depth reaching the substrate in each of the plurality of semiconductor operation layer regions after forming electrodes on the layer regions, and an insulating film made of an electrically high resistance material in the mesa structure And a step of embedding.

  According to this aspect, the electrodes are formed on the plurality of semiconductor operation layer regions, respectively, and then the mesa structure having a depth reaching the substrate is formed on the plurality of semiconductor operation layer regions. And a fine electrode of about 2 μm can be formed. If a deep mesa structure is formed and an electrode is formed later, it is difficult to form a fine pattern with a resist or the like. That is, when a deep mesa structure is formed, a fine electrode of about 2 μm, for example, is formed with a gate electrode, so the mesa structure is embedded with a very thick resist (for example, a resist having a thickness of 4 to 5 μm). The patterning will be performed. When trying to form a 2 μm pattern with a thick resist, the conditions are not so good.

  In the method for manufacturing a GaN-based semiconductor device according to another aspect of the present invention, the step of forming the insulating region and separating the semiconductor operating layer on the substrate into a plurality of semiconductor operating layer regions includes: A step of forming a first mesa structure having a shallow depth in the operation layer region; and a depth reaching the substrate in the plurality of semiconductor operation layer regions after forming electrodes on the plurality of semiconductor operation layer regions, respectively. Forming the second mesa structure, and embedding an insulating film made of an electrically high resistance material in the first mesa structure and the second mesa structure.

  According to this aspect, for each of the plurality of unit elements, the insulating film made of a high-resistance material embedded in the first mesa structure having a shallow depth and in the second mesa structure having a depth reaching the substrate is used to form the substrate. It is electrically isolated to a depth that reaches For this reason, even when a large element is formed using a conductive substrate such as a silicon substrate, the leak current flowing through the substrate as a buffer leakage current can be reduced, and a large element having a large current and a high withstand voltage can be realized. Become.

  In addition, by forming the first mesa structure having a shallow depth in the GaN-based semiconductor layer at each boundary portion of the plurality of GaN-based semiconductor elements, the plurality of GaN-based semiconductor elements can be formed by the first mesa structure. Therefore, the characteristics of each GaN-based semiconductor element can be measured during the process of forming a large element by connecting the electrodes of a plurality of GaN-based semiconductor elements. Furthermore, a fine electrode can be formed by forming the second mesa structure having a depth reaching the substrate after forming the electrode.

According to the present invention, since a plurality of GaN-based semiconductor elements are electrically insulated and separated for each element up to the substrate or to the vicinity of the substrate, even when a large element is formed using a conductive substrate such as a silicon substrate. The leakage current flowing through the substrate can be reduced, and a large element having a large current and a high breakdown voltage can be realized. For example, whereas a conventional buffer leakage current was 10 ^-6 A stand at 200V, 10 ^-9 to 10 ^-10, has made it possible to reduce the order of three digits to 4 digits. As a result, an element having a high breakdown voltage and a low leakage current can be realized, and a breakdown voltage of about 600 V, which was conventionally about 600 V, can be obtained. Therefore, application to high voltage inverters and converters becomes possible. From the above, it is possible to realize a GaN-based semiconductor device such as a GaN-based field effect transistor having a high breakdown voltage and a low leakage current.

  Next, embodiments embodying the present invention will be described with reference to the drawings. In the description of each embodiment, similar parts are denoted by the same reference numerals, and redundant description is omitted.

  In the GaN-based semiconductor device according to each of the following embodiments, as shown in FIG. 1 as an example, a semiconductor operation layer 101 formed on a substrate 100 is electrically connected to a plurality of semiconductor operation layer regions 103 by an insulating region 102. Isolated. A plurality of unit elements 110 are formed by each semiconductor operation layer region 103 and electrodes (not shown) formed on each semiconductor operation layer region 103. A plurality of unit elements 110 are formed by each of the plurality of semiconductor operation layer regions 103 and the electrodes formed on each semiconductor operation layer region 103. The plurality of unit elements 110 function as one element by electrically connecting the electrodes of the plurality of unit elements. By such a plurality of unit elements 110, the GaN-based semiconductor device according to each embodiment is formed as a large element (one element).

(First embodiment)
A GaN-based semiconductor device 20 according to the first embodiment will be described with reference to FIGS.

  4 is a cross-sectional view showing a part of the GaN-based semiconductor device 20 according to the first embodiment, and FIG. 5 is a perspective view schematically showing a part of the GaN-based semiconductor device 20. 6 and 7 are plan views showing the structure of a multilayer wiring that connects corresponding electrodes of a plurality of GaN-based heterojunction field effect transistors (HFETs) 10 constituting the GaN-based semiconductor device 20. FIG.

  This GaN-based semiconductor device 20 has the following configuration.

  A buffer layer 2 is formed on one silicon (111) substrate 1, a channel layer 3 is formed on the buffer layer 2, and an electron supply layer 4 is formed on the channel layer 3. The channel layer 3 and the electron supply layer 4 correspond to the semiconductor operation layer 101 shown in FIG. Therefore, in the following description, the semiconductor operation layer composed of the channel layer 3 and the electron supply layer 4 is referred to as a semiconductor operation layer 101.

  An ion implantation region 9 that electrically isolates the semiconductor operation layer 101 on the silicon substrate 1 into a plurality of semiconductor operation layer regions is formed. The ion implantation region 9 corresponds to the insulating region 102 shown in FIG. In FIG. 4, two semiconductor operation regions each including the channel layer 3 and the electron supply layer 4 that are electrically insulated and separated by the ion implantation region 9 are shown. These semiconductor operation regions correspond to the semiconductor operation region 103 shown in FIG. Therefore, in the following description, a semiconductor operation region composed of the channel layer 3 and the electron supply layer 4 that are electrically insulated and separated by the ion implantation region 9 is referred to as a semiconductor operation layer region 103.

  A plurality of semiconductor operation layer regions 103 that are insulated and separated by the ion implantation region 9 and electrodes (gate electrode 5, source electrode 6 and drain electrode 7) formed on each semiconductor operation layer region 103. Each of the unit elements is formed. In FIG. 4, two GaN-based heterojunction field effect transistors (hereinafter referred to as “GaN-based HFET”) 10 are shown as unit elements that are insulated and separated by the ion implantation region 9.

  A plurality of unit elements function as one element by electrically connecting the electrodes of the plurality of unit elements. FIG. 5 shows a state in which the gate electrodes 5, the source electrodes 6, and the drain electrodes 7 of the two GaN-based HFETs 10 that are unit elements are electrically connected to each other through multilayer wiring such as contact lines 21 a, 22 a, and 23 a. It is. Thus, the GaN-based semiconductor device 20 shown in FIGS. 4 and 5 is a large element in which a plurality of GaN-based HFETs 10 (unit elements) function as one element.

  The plurality of semiconductor operation layer regions 103 are electrically insulated until reaching the buffer layer 2 by the ion implantation region (insulating region) 9.

The buffer layer 2 is composed of a semiconductor layer mainly composed of Al _x Ga _1-x N or a stacked structure thereof. In the present embodiment, as an example, the buffer layer 2 has a stacked structure in which AlN and GaN are alternately stacked.

  In the plurality of ion implantation regions 9, ions such as hydrogen, boron, nitrogen, fluorine, silicon, Mg, carbon, and Zn are ion implanted.

  A plurality of GaN-based HFETs 10 constituting the GaN-based semiconductor device 20 include a buffer layer 2 formed on the silicon substrate 1, a channel layer 3 made of GaN formed on the buffer layer 2, and a channel layer 3. An electron supply layer 4 made of AlGaN and a gate electrode 5, a source electrode 6 and a drain electrode 7 respectively formed on the electron supply layer 4 are provided.

  In each GaN-based HFET (unit element) 10, the surface of the channel layer 3 made of undoped GaN corresponding to the channel length L is heterojunctioned with the electron supply layer 4 made of undoped AlGaN. A two-dimensional electron gas 8 is generated at the interface of the portion. Therefore, the two-dimensional electron gas 8 becomes a carrier and the channel layer 3 exhibits conductivity. The source electrode 6 and the drain electrode 7 are formed, for example, by laminating Ti, an alloy of Al and Si, and W in this order from the region closest to the electron supply layer (AlGaN layer) 4.

  The GaN-based semiconductor device 20 configured as a large element FET by connecting a plurality of GaN-based HFETs 10 can be manufactured as follows. That is, the growth apparatus was a MOCVD (Metal Organic Chemical Vapor Deposition) apparatus, and the substrate was the silicon substrate 1.

(1) A procedure for producing the layer structure of the GaN-based semiconductor device 20 shown in FIG. 4 will be described.
First, the silicon (111) substrate 1 is introduced into the MOCVD apparatus, and the vacuum inside the MOCVD apparatus is evacuated to 1 × 10 ⁻⁶ hPa or less with a turbo pump. The temperature was raised to ° C. When the temperature is stabilized, the substrate 1 is rotated at 900 rpm, trimethylaluminum (TMA) as a raw material is introduced into the surface of the substrate 1 at a flow rate of 100 cm ³ / min, and ammonia is supplied at a flow rate of 12 liters / min. Made growth. The growth time is 4 min and the thickness of the buffer layer 2 is about 50 nm.

Thereafter, trimethylgallium (TMG) was introduced onto the buffer layer 2 at a flow rate of 100 cm ³ / min and ammonia at a flow rate of 12 liter / min to grow the electron transit layer 3 made of a GaN layer. The growth time was 500 sec, and the film thickness of the electron transit layer 3 was 400 nm.

Next, trimethylaluminum (TMA) was introduced at a flow rate of 50 cm ³ / min, trimethylgallium (TMG) at 100 cm ³ / min, and ammonia at a flow rate of 12 liters / min, and the electron supply layer 4 composed of an Al0.25Ga0.75N layer was formed. Made growth. The growth time is 40 sec, and the thickness of the electron supply layer 4 is 20 nm. In this way, the layer structure shown in FIG. 4 is completed.

  (2) Next, a process of forming the high resistance ion implantation region 9 in the electron supply layer 4, the channel layer 3, and the buffer layer 2 constituting the semiconductor operation layer 101 to a depth reaching the silicon substrate 1 will be described. .

First, in order to electrically insulate and isolate the semiconductor operation layer 101 (electron supply layer 4 and channel layer 3) on the silicon substrate 1 to a depth reaching the silicon substrate 1 in a plurality of semiconductor operation layer regions 103, SiO ₂ or the like. An insulating film is formed, patterned, and ion-implanted. This ion implantation is performed to a depth reaching the silicon substrate using atoms (ions) such as hydrogen and nitrogen. The acceleration voltage is 50 keV, and the dose is about 1e15 cm ⁻² . In addition to hydrogen and nitrogen, atoms (ions) such as boron, fluorine, silicon, Mg, carbon, and Zn may be used for this ion implantation.

  After ion implantation, the ion-implanted region is subjected to heat treatment to form a high-resistance ion-implanted region 9.

(3) After the ion-implanted region 9 is formed in this way, patterning is performed to mask the SiO ₂ film where the gate electrode 5 is to be formed, and where the source electrode 6 and the drain electrode 7 are to be formed. The surface of the electron supply layer 4 was exposed, and an alloy film of Ti, Al and Si, and W were sequentially deposited thereon to form a source electrode 6 and a drain electrode 7.

Next, the mask is removed, and conversely, a SiO ₂ mask is formed which covers the source electrode 6 and the drain electrode 7 and has an opening in the portion to become the gate electrode 5, and deposits Ni and Au to deposit the gate. An electrode 5 was formed.

  (4) Thereafter, corresponding electrodes of the plurality of GaN-based HFETs 10, that is, the gate electrodes 5, the source electrodes 6, and the drain electrodes 7 are contacted with each other as shown in FIG. 5 by contact lines 21a, 22a, 23a, etc. Connect with multi-layer wiring.

(5) Thereafter, as shown in FIG. 5, the plurality of GaN HFETs (unit elements) 10 as a whole are made of an electrically high resistance material except for the multilayer wiring such as the contact lines 21a, 22a, and 23a. Cover with insulating film 11. The insulating film 11 is made of an electrically high resistance material such as SiO 2 or polyimide.
Thus, the GaN-based semiconductor device 20 as the large element FET is completed.

  The gate width of each GaN-based HFET 10 is about 200 μm, but a large element FET is formed by connecting them with multilayer wiring. Specifically, 1000 GaN HFETs 10 having a gate width of 200 μm were connected to produce a large element FET having a gate width of 200 mm.

  Next, in the GaN-based semiconductor device 20 shown in FIG. 4, a structure in which a plurality of GaN-based HFETs 10 are connected by multilayer wiring will be described with reference to FIGS. In FIG. 5, reference numeral “21 a” denotes a gate contact line that connects the corresponding gate electrodes 5 of the plurality of GaN-based HFETs 10. Reference numeral “22a” is a source contact line for connecting corresponding source electrodes 6 to each other, and reference numeral “23a” is a drain contact line for connecting corresponding drain electrodes 7 to each other.

  As shown in FIG. 6, on the electron supply layer 4 of each GaN-based HFET (unit element) 10, a striped gate lead-out wiring 21 extending in one direction and a direction perpendicular to the gate lead-out wiring 21 and spaced from each other A plurality of striped source bus lines 22 arranged at intervals, a plurality of striped drain bus lines 23 arranged at intervals on both sides of the source bus lines 22, and an insulating layer (not shown). A source connection pad 24 connected on the electron supply layer 4 to one end of the source bus line 22 straddling the gate lead-out line 21 in an arch shape, and a drain connection pad connected to the other end of the drain bus line 23 25 are formed.

  On the electron supply layer 4, a gate bus line 26 is formed between the source bus line 22 and the drain bus line 23 and at a distance from the source bus line 21. A gate lead electrode 21 is connected.

  As shown in FIGS. 6 and 7, the plurality of drain electrodes 7 are connected in a comb-teeth shape on both sides of the drain bus line 23 in a direction orthogonal to the drain bus line 23. The source electrode 6 disposed parallel to the drain electrode 7 is connected in a comb shape. Note that, at a portion where the source electrode 6 and the gate bus line 26 intersect, the source electrode 6 is connected to the source bus line 22 across the gate bus line 26 in an arch shape via an insulating layer (not shown).

  In such a region between the source electrode 6 and the drain electrode 7, there is a channel region meandering in an S shape along the longitudinal direction of the source bus line 22 and the drain bus line 23, and the channel region has a gate electrode. 5 is arranged in a meandering manner in an S shape and is connected to the side of the gate bus line 26.

As shown in FIG. 6, the gate lead-out wiring 21 is connected to the gate connection pad 27 that is arranged at an interval inside the concave region formed in the source connection pad 24. The gate pattern, that is, the gate lead-out wiring 21, the gate electrode 7, the gate bus line 26, and the gate connection pad 27 are made of the same metal, and the drain pattern and the source pattern are also made of the same metal.
According to 1st Embodiment comprised as mentioned above, there exist the following effects.

  A semiconductor operation layer 101 (see FIG. 1) composed of the channel layer 3 and the electron supply layer 4 on the silicon substrate 1 is electrically insulated and separated into a plurality of semiconductor operation layer regions 103 by the high-resistance ion implantation region 9. For this reason, even when a large element is formed using a conductive substrate such as the silicon substrate 1, a leak current flowing through the substrate can be reduced, and a large element having a large current and a high withstand voltage can be realized.

  Since the plurality of semiconductor operation layer regions 103 are electrically insulated until reaching the buffer layer 2 by the ion implantation region 9, even when a large element is formed using a conductive substrate such as the silicon substrate 1, As a buffer leakage current in the GaN-based HFET 10, a leakage current flowing through the silicon substrate 1 can be reduced, and a large element having a large current and a high withstand voltage can be realized.

  Each semiconductor operation layer region 103 in which the semiconductor operation layer 101 on the silicon substrate 1 is electrically insulated and separated into a plurality of regions, and electrodes (gate electrode 5, source electrode 6) formed on each semiconductor operation layer region 103 And the drain electrode 7) form a plurality of GaN-based HFETs (unit elements) 10 respectively. By electrically connecting the electrodes of the plurality of GaN-based HFETs 10, the plurality of GaN-based HFETs 10 function as one element. Further, the semiconductor operation layer regions 103 of the plurality of GaN-based HFETs 10 are electrically insulated and separated by the high-resistance ion implantation regions 9, and the leakage current of the buffer layer in each GaN-based HFET 10 is reduced. For this reason, even when a large element is formed using a conductive substrate such as the silicon substrate 1, a leak current flowing through the substrate can be reduced, and a large element having a large current and a high withstand voltage can be realized.

  A plurality of GaN-based HFETs 10 are electrically insulated and separated to a depth reaching the silicon substrate 1 by high-resistance ion implantation regions 9. For this reason, even when a large element is formed using a conductive substrate such as the silicon substrate 1, the leakage current flowing through the silicon substrate 1 as a buffer leakage current can be reduced. Therefore, the GaN-based semiconductor device 20 as a large element FET having a large current and a high breakdown voltage can be manufactured.

  Even when the buffer layer 2 having a laminated structure of AlN and GaN is formed on a conductive substrate such as the silicon substrate 1, the leak current flowing through the silicon substrate 1 as a buffer leak current can be reduced, and a large current A GaN-based semiconductor device 20 as a high-voltage large element FET can be realized.

(Second Embodiment)
Next, a GaN-based semiconductor device 20A according to the second embodiment will be described with reference to FIGS.

  This GaN-based semiconductor device 20A has the following configuration.

  An insulating region that electrically isolates and isolates the semiconductor operation layer 101 (see FIG. 1) formed of the channel layer 3 and the electron supply layer 4 formed on the silicon substrate 1 into a plurality of semiconductor operation layer regions 103 is at least a semiconductor operation. A plurality of GaN-based HFETs (unit elements) 10 form a first mesa structure 12 by the grooves.

  In the present embodiment, the semiconductor operation layer 101 is electrically insulated and separated to the depth reaching the silicon substrate 1 by the grooves forming the first mesa structure 12, thereby forming a plurality of semiconductor operation layer regions 103.

  Each of the plurality of semiconductor operation layer regions 103 insulated and separated by the grooves forming the first mesa structure 12 and the electrodes (gate electrode 5, source electrode 6 and drain electrode) formed on each semiconductor operation layer region 103 7), a plurality of GaN-based HFETs 10 are formed. In FIG. 8, two GaN-based HFETs 10 are shown as unit elements that are insulated and separated by grooves forming the first mesa structure 12.

  By electrically connecting the electrodes of the plurality of GaN-based HFETs 10, the plurality of GaN-based HFETs 10 function as one element. FIG. 9 shows a state in which the gate electrodes 5, the source electrodes 6, and the drain electrodes 7 of the two GaN-based HFETs 10 are electrically connected by multilayer wiring such as contact lines 21 a, 22 a, and 23 a. As described above, the GaN-based semiconductor device 20A shown in FIGS. 8 and 9 is a large element in which a plurality of GaN-based HFETs 10 function as one element.

In the groove forming the first mesa structure 12, as shown in FIG. 9, an insulating film 11 made of an electrically high resistance material is embedded.
Other configurations are the same as those in the first embodiment.

  In this embodiment, after the epitaxial structure is formed on the silicon substrate 1, the first mesa structure 12 is formed by performing etching (dry etching) up to the silicon substrate 1 using chlorine-based ICP or the like.

  According to 2nd Embodiment comprised as mentioned above, there exist the following effects.

  A plurality of semiconductor operation layer regions 103 are formed by electrically insulating and isolating the semiconductor operation layer 101 to a depth reaching the silicon substrate 1 by the grooves forming the first mesa structure 12.

  In addition, since the insulating film 11 made of an electrically high resistance material is embedded in the groove forming the first mesa structure 12, the groove and the insulating film embedded in the groove are provided for each GaN-based HFET 10. 11 is electrically insulated and separated to a depth reaching the silicon substrate 1. For this reason, even when a large element is formed using a conductive substrate such as the silicon substrate 1, the leakage current flowing through the silicon substrate 1 as a buffer leakage current can be reduced. Therefore, the GaN-based semiconductor device 20A as a large element FET having a large current and a high breakdown voltage can be realized.

(Third embodiment)
Next, a GaN-based semiconductor device 20B according to the third embodiment will be described with reference to FIG.
This GaN-based semiconductor device 20B has the following configuration.

  The semiconductor operation layer 101 (see FIG. 1) formed of the channel layer 3 and the electron supply layer 4 formed on the silicon substrate 1 is formed by a groove that forms the first mesa structure 12 as in the second embodiment. A plurality of semiconductor operation layer regions 103 are formed by being electrically insulated and separated to a depth reaching the silicon substrate 1.

Each semiconductor operation layer region 103 has a step, and the plurality of GaN-based HFETs (unit elements) 10 form the second mesa structure 13 due to the step. In FIG. 10, two GaN-based HFETs 10 are shown as a plurality of unit elements that are insulated and separated by grooves forming the first mesa structure 12.
Other configurations are the same as those in the first embodiment.

  According to 3rd Embodiment comprised as mentioned above, in addition to the effect which the said 1st Embodiment show | plays, there exist the following effects.

  Each semiconductor operation layer region 103 of the plurality of GaN-based HFETs (unit elements) 10 forms a second mesa structure 13 by a step, and the steps forming the mesa structure 13 electrically connect each GaN-based HFET 10 electrically. Isolated. For this reason, the characteristic of each GaN-type HFET 10 can be measured during the process of connecting the electrodes of a plurality of GaN-type HFETs 10 to form a large element.

(Fourth embodiment)
Next, a GaN-based semiconductor device 20C according to the fourth embodiment will be described with reference to FIG.

  In this GaN-based semiconductor device 20C, a GaN-based MOS field effect transistor (hereinafter referred to as “GaN-based MOSFET”) 10A is formed as a plurality of unit elements on one silicon (111) substrate 31, and a plurality of GaN-based semiconductor devices 20C are formed. This is a large element FET produced by connecting corresponding electrodes of the system MOSFET 10A with multilayer wiring.

The plurality of GaN-based MOSFETs 10A include a buffer layer 32 made of AlN formed on one silicon (111) substrate 31, a p-type GaN active layer 33 formed on the buffer layer 32, and a p-type GaN active layer 3 An n ⁺ type source region 34 s and an n ⁺ type drain region 34 d formed on the surface are provided. In this embodiment, the p-type GaN active layer 33, the n ⁺ -type source region 34s and the n ⁺ -type drain region 34d correspond to the semiconductor operation layer 101 (see FIG. 1) shown in FIG. Therefore, in the following description, the semiconductor operation layer composed of the p-type GaN active layer 33 and the n ⁺ type source region 34 s and the n ⁺ type drain region 34 d is referred to as the semiconductor operation layer 101 as in the above embodiments.

Further, the plurality of GaN-based MOSFETs 10A include a source electrode (S) 36 and a drain electrode (D) 37 that are in ohmic contact with the n ⁺ type source region 34s and the n ⁺ type drain region 34d, respectively, and the surface of the p type GaN active layer 3 And an insulating film 35 formed in a region between the source electrode 36 and the drain electrode 37 and a gate electrode 38 formed on the insulating film 35.

  The GaN-based semiconductor device 20C has the following configuration.

  An insulating region that electrically isolates and isolates the semiconductor operating layer 101 into a plurality of semiconductor operating layer regions 103 (see FIG. 1) is formed by grooves having a depth that divides at least the semiconductor operating layer 101, and a plurality of GaN-based layers A MOSFET (unit element) 10A forms a first mesa structure 12 by the groove.

  In the present embodiment, the semiconductor operation layer 101 is electrically insulated and separated to the depth reaching the silicon substrate 1 by the grooves forming the first mesa structure 12a, and a plurality of semiconductor operation layer regions 103 are formed.

  Each of the plurality of semiconductor operation layer regions 103 that are insulated and separated by the grooves forming the first mesa structure 12a, and electrodes (source electrode 36, drain electrode 37, and gate electrode) formed on each semiconductor operation layer region 103 38), a plurality of GaN-based MOSFETs 10A are formed. In FIG. 11, two GaN-based MOSFETs 10A are shown as unit elements that are insulated and separated by the grooves forming the first mesa structure 12a.

  By electrically connecting the electrodes of the plurality of GaN-based MOSFETs 10A, the plurality of GaN-based MOSFETs 10A function as one element. As described above, the GaN-based semiconductor device 20C shown in FIG. 11 is a large element in which a plurality of GaN-based MOSFETs (unit elements) 10A function as one element.

As in the fourth embodiment shown in FIG. 9, an insulating film 11 made of an electrically high resistance material is embedded in the groove forming the first mesa structure 12.
Other configurations are the same as those in the first embodiment.
According to 4th Embodiment comprised as mentioned above, there exist the following effects.

  A plurality of GaN-based MOSFETs (unit elements) 10A are electrically separated by a mesa structure 12a having a depth reaching the silicon substrate 31, and by an insulating film 11 made of a high resistance material embedded in the mesa structure 12a. Electrical isolation is performed up to a depth reaching the silicon substrate 31. For this reason, even when the large element FET is formed using a conductive substrate such as the silicon substrate 31, the leakage current flowing through the silicon substrate 31 as a buffer leakage current can be reduced. Therefore, the GaN-based semiconductor device 20C as a large element FET having a large current and a high breakdown voltage can be manufactured.

(Fifth embodiment)
Next, a GaN-based semiconductor device 20D according to the fifth embodiment will be described with reference to FIG.

  In this GaN-based semiconductor device 20D, a GaN-based Schottky diode 10B is formed as a plurality of unit elements on a single silicon (111) substrate 41, and corresponding electrodes of the plurality of GaN-based Schottky diodes 10B are multilayered. It is a large element connected by wiring.

  The plurality of GaN-based Schottky diodes 10 </ b> B are formed on the drift layer 43, the buffer layer 42 made of GaN formed on one silicon substrate 41, the drift layer 43 made of GaN formed on the buffer layer 42, and the like. And a Schottky electrode 44 that forms a Schottky junction with the drift layer 43, and an ohmic electrode 45 formed on the back surface of the silicon substrate 41.

  The characteristics of the GaN-based semiconductor device 20D are as follows.

  An insulating region that electrically isolates and isolates the semiconductor operating layer 101 into a plurality of semiconductor operating layer regions 103 (see FIG. 1) is formed by grooves having a depth that divides at least the semiconductor operating layer 101, and a plurality of GaN-based layers A Schottky diode (unit element) 10B forms a first mesa structure 12b by the groove.

  In the present embodiment, the semiconductor operating layer 101 is electrically insulated and separated to the depth reaching the silicon substrate 41 by the grooves forming the first mesa structure 12b, thereby forming a plurality of semiconductor operating layer regions 103.

  Each of the plurality of semiconductor operation layer regions 103 that are insulated and separated by the grooves forming the first mesa structure 12b, and electrodes (Schottky electrode 44 and ohmic electrode 45) formed on each semiconductor operation layer region 103, Thus, a plurality of GaN-based Schottky diodes 10B are formed. In FIG. 12, two GaN-based Schottky diodes 10B are shown as unit elements that are insulated and separated by the grooves forming the first mesa structure 12b.

  By electrically connecting the electrodes of the plurality of GaN-based Schottky diodes 10B, the plurality of GaN-based Schottky diodes 10B function as one element. As described above, the GaN-based semiconductor device 20D shown in FIG. 12 is a large element in which a plurality of GaN-based Schottky diodes (unit elements) 10B function as one element.

  In the groove forming the first mesa structure 12b, the insulating film 11 made of an electrically high resistance material is buried, as in the fourth embodiment shown in FIG.

Other configurations are the same as those in the first embodiment.
According to 5th Embodiment comprised as mentioned above, there exist the following effects.

  A plurality of GaN-based Schottky diodes (unit elements) 10B are electrically separated by a mesa structure 12b having a depth reaching the silicon substrate 41, and an insulating film made of a high resistance material embedded in the mesa structure 12b 11 is electrically insulated and separated to a depth reaching the silicon substrate 31. Therefore, even when a large element FET is formed using a conductive substrate such as the silicon substrate 41, the leak current flowing through the silicon substrate 41 as a buffer leak current can be reduced. Therefore, the GaN-based semiconductor device 20D as a large element FET having a large current and a high breakdown voltage can be manufactured.

(Sixth embodiment)
Next, a GaN-based semiconductor device 20E according to the sixth embodiment will be described with reference to FIG.

  This GaN-based semiconductor device 20E has the following configuration.

  In the third embodiment shown in FIG. 10, a plurality of GaN-based HFETs (unit elements) 10 that are insulated and separated by the grooves forming the first mesa structure 12 have one set of electrodes (gate electrode 5, source electrode 6). And a drain electrode 7) are respectively formed.

  On the other hand, in the GaN-based semiconductor device 20E according to the present embodiment, two sets of electrodes (gates) are included in the plurality of GaN-based HFETs (unit elements) 10C that are insulated and separated by the grooves forming the first mesa structure 12. An electrode 5, a source electrode 6 and a drain electrode 7) are respectively formed. Other configurations are the same as those in the first embodiment.

  According to 6th Embodiment comprised as mentioned above, there exist the following effects similarly to the said 3rd Embodiment.

  Each semiconductor operation layer region 103 of the plurality of GaN-based HFETs (unit elements) 10C forms the second mesa structure 13 by a step, and the steps forming the mesa structure 13 electrically connect each GaN-based HFET 10 electrically. Isolated. For this reason, the characteristic of each GaN-type HFET 10 can be measured during the process of connecting the electrodes of a plurality of GaN-type HFETs 10 to form a large element.

  In addition, this invention can also be changed and embodied as follows.

  In each of the above embodiments, a plurality of GaN-based semiconductor elements (GaN-based HFETs 10 and 10C, GaN-based MOSFET 10A, and GaN-based Schottky diode 10B) that are unit elements are insulated and separated to a depth reaching the silicon substrate. The present invention is not limited to this, and can also be applied to a GaN-based semiconductor device that is insulated and separated at least to a depth reaching the buffer layer. In addition, it is preferable that the plurality of GaN-based semiconductor elements are insulated and separated to a depth reaching the silicon substrate because the insulation effect is large and the leakage current flowing through the silicon substrate is smaller. Further, the deeper the insulation, the better, and even if the insulation is performed up to the middle of the buffer layer, the effect is shown to some extent.

  In each of the above embodiments, the description has been given of the case where a plurality of GaN-based semiconductor elements have a buffer layer. However, the present invention can also be applied to a GaN-based semiconductor device including a plurality of GaN-based semiconductor elements without a buffer layer. . In this case, a plurality of GaN-based semiconductor elements are electrically insulated to the substrate or to the vicinity of the substrate for each element.

  -As a plurality of GaN-based semiconductor elements constituting the GaN-based semiconductor device, in addition to the semiconductor elements described in the above embodiments, GaN-based semiconductor devices configured using diodes using GaN, bipolar transistors, etc. The present invention is applicable.

  In each of the above embodiments, a silicon substrate is used, but the present invention is also applied to a configuration using a conductive substrate other than a silicon substrate or a sapphire substrate. For example, the present invention can also be applied to a GaN-based semiconductor device including a plurality of GaN-based semiconductor elements configured using a SiC substrate, a sapphire substrate, a GaN substrate, an MgO substrate, and a ZnO substrate. Although the sapphire substrate is an insulating substrate, a leak current flowing through the sapphire substrate can be reduced also in the case of a GaN-based semiconductor device including a plurality of GaN-based semiconductor elements configured using the sapphire substrate.

  In the GaN-based semiconductor device 20C shown in FIG. 11, a deep mesa structure is formed by forming an ion implantation region similar to that of the first embodiment shown in FIG. 4 or similarly to the second embodiment shown in FIG. The present invention can be applied to a GaN-based semiconductor device having a structure in which the insulating layer is electrically insulated and separated to at least the depth reaching the buffer layer.

  Similarly, in the GaN-based semiconductor device 20D shown in FIG. 12, by forming an ion implantation region similar to that of the first embodiment shown in FIG. 4, a GaN-based structure that is insulated and separated to at least the depth reaching the buffer layer The present invention can also be applied to semiconductor devices.

Explanatory drawing which shows one form by which the semiconductor operation layer on a board | substrate is isolate | separated into a some area | region by the insulation area | region. Explanatory drawing which shows another form by which the semiconductor operation | movement layer on a board | substrate is isolate | separated into a several area | region by the insulation area | region. Explanatory drawing which shows another form from which the semiconductor operation layer on a board | substrate is isolate | separated into a some area | region by the insulation area | region. 1 is a cross-sectional view showing a part of a GaN-based semiconductor device according to a first embodiment of the present invention. 1 is a perspective view schematically showing a part of a GaN-based semiconductor device according to a first embodiment. The top view which shows the structure of the multilayer wiring of the GaN-type semiconductor device. The top view which expanded and showed a part of FIG. Sectional drawing which shows a part of GaN-type semiconductor device which concerns on 2nd Embodiment of this invention. The perspective view which shows typically a part of GaN-type semiconductor device which concerns on 2nd Embodiment. Sectional drawing which shows a part of GaN-type semiconductor device which concerns on 3rd Embodiment. Sectional drawing which shows a part of GaN-type semiconductor device which concerns on 4th Embodiment. Sectional drawing which shows a part of GaN-type semiconductor device which concerns on 5th Embodiment. Sectional drawing which shows a part of GaN-type semiconductor device which concerns on 6th Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,31,42 ... Silicon substrate 2,32,42 ... Buffer layer 3 ... Channel layer 4 ... Electronic supply layer 9 ... Ion implantation area | region 10,10C ... GaN type HFET
10A ... GaN-based MOSFET
DESCRIPTION OF SYMBOLS 10B ... GaN type | mold Schottky diode 11 ... Insulating film 12 ... Mesa structure 13 ... Mesa structure 20, 20A, 20B, 20C, 20D, 20E ... GaN type semiconductor device 100 ... Substrate 101 ... Semiconductor operating layer 102, 102A, 102B ... Insulation Region 103, 103A, 103B ... Semiconductor operation layer region 110, 110A, 110B ... Unit element

Claims (16)

On a substrate, a GaN-based semiconductor device having at least a buffer layer and a semiconductor operation layer provided above the buffer layer,
Forming a first insulating region that electrically separates the semiconductor operation layer into a plurality of semiconductor operation layer regions without separating the buffer layer into a plurality of buffer layer regions by grooves ;
A plurality of unit elements are formed by each of the plurality of semiconductor operation layer regions and the electrodes formed in a comb shape on each semiconductor operation layer region, and the electrodes of the plurality of unit elements are partly connected to each other. By electrically connecting with the wiring provided above the first insulating region, the plurality of unit elements function as one element,
A GaN-based semiconductor device, wherein a second insulating region having a mesa structure with a depth reaching the substrate is formed on an outer periphery of the one element.   2. The GaN-based semiconductor device according to claim 1, wherein the first insulating region is formed on an outer periphery of each of the plurality of unit elements.   3. The GaN-based semiconductor device according to claim 1, wherein the plurality of semiconductor operation layer regions are electrically insulated by the first insulation region until reaching the buffer layer. 4. 4. The GaN-based semiconductor device according to claim 1, wherein the buffer layer is formed of a semiconductor layer mainly composed of Al _x Ga _1-x N or a stacked structure thereof. 5.   5. The first insulating region according to claim 1, wherein the first insulating region is a region formed in the semiconductor operation layer on the substrate to a depth at which a high resistance ion implantation region reaches at least the buffer layer. The GaN-based semiconductor device according to any one of the above.   The GaN-based semiconductor device according to claim 5, wherein the ion-implanted region is ion-implanted using ions of hydrogen, boron, nitrogen, fluorine, silicon, Mg, carbon, Zn, or the like. 5. The first insulating region according to claim 1, wherein the first insulating region is formed by a groove having a depth that divides at least the semiconductor operation layer, and the plurality of unit elements form a mesa structure by the groove. The GaN-based semiconductor device according to any one of the above.   The GaN-based semiconductor device according to claim 7, wherein an insulating film made of an electrically high resistance material is embedded in the groove. The plurality of unit elements are formed of a semiconductor layer mainly formed of Al _x Ga _1-x N formed on the substrate, or a buffer layer made of a laminated structure thereof, and GaN formed on the buffer layer. A GaN-based heterojunction electric field comprising: a channel layer comprising: an electron supply layer comprising AlGaN formed on the channel layer; and a gate electrode, a source electrode, and a drain electrode formed on the electron supply layer, respectively. The GaN-based semiconductor device according to claim 1, wherein the GaN-based semiconductor device is an effect transistor.   The GaN-based semiconductor according to claim 9, wherein the GaN-based semiconductor is formed as a large element by connecting the gate electrodes, the source electrodes, and the drain electrodes with a multilayer wiring between the plurality of unit elements. device.   The GaN-based semiconductor device according to claim 1, wherein the plurality of unit elements are GaN-based MOS field effect transistors.   The GaN-based semiconductor device according to claim 1, wherein the plurality of GaN-based semiconductor elements are GaN-based Schottky diodes. On a substrate, in a method of manufacturing a GaN-based semiconductor device having at least a buffer layer and a semiconductor operation layer provided above the buffer layer,
Forming a first insulating region that electrically isolates the semiconductor operation layer into a plurality of semiconductor operation layer regions without separating the buffer layer into a plurality of buffer layer regions by grooves ;
Forming a plurality of unit elements by forming electrodes in a comb-teeth shape on the plurality of semiconductor operation layer regions; and
A step of electrically connecting a part of the electrodes between the plurality of unit elements by a wiring provided above the first insulating region, and causing the plurality of unit elements to function as one element;
Forming a second insulating region having a mesa structure with a depth reaching the substrate on an outer periphery of the one element. A method for manufacturing a GaN-based semiconductor device, comprising: Forming the first insulating region and separating the semiconductor operation layer on the substrate into a plurality of semiconductor operation layer regions;
Implanting the semiconductor operation layer on the substrate with ions of hydrogen, boron, nitrogen, fluorine, silicon, Mg, carbon, Zn, etc., to a depth reaching the substrate or the vicinity of the substrate;
The method for manufacturing a GaN-based semiconductor device according to claim 13, further comprising a step of performing a heat treatment on the ion-implanted region after the ion implantation to form a high-resistance ion-implanted region layer.   15. The method of manufacturing a GaN-based semiconductor device according to claim 14, wherein, in the ion implantation step, the high resistance ion implantation region is formed to a depth reaching the buffer layer for each unit element. On a substrate, in a method of manufacturing a GaN-based semiconductor device having at least a buffer layer and a semiconductor operation layer provided above the buffer layer,
Forming a first insulating region that electrically isolates the semiconductor operation layer into a plurality of semiconductor operation layer regions without separating the buffer layer into a plurality of buffer layer regions by grooves ;
Forming a plurality of unit elements by respectively forming electrodes on the plurality of semiconductor operation layer regions;
A step of electrically connecting the electrodes between the plurality of unit elements and causing the plurality of unit elements to function as one element;
Forming a second insulating region having a mesa structure with a depth reaching the substrate on the outer periphery of the one element;
Forming the first insulating region and separating the semiconductor operation layer on the substrate into a plurality of semiconductor operation layer regions;
After forming an electrode on each of the plurality of semiconductor operation layer regions,
Forming a mesa structure having a depth reaching the buffer layer in the plurality of semiconductor operation layer regions;
Burying an insulating film made of an electrically high resistance material in the mesa structure.

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