JP5233336B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device with high productivity, and a method of manufacturing the semiconductor device. <P>SOLUTION: The semiconductor device 1a includes a support substrate 10, a plurality of wiring lines 12 disposed selectively on the principal surface of the support substrate 10, semiconductor elements 20a and 20b mounted on the support substrate 10, a semiconductor element 21 which controls at least one of those semiconductor elements 20a and 20b, and a wiring support base 30 where a plurality of conductive patterns 40 are selectively disposed. Then the semiconductor elements 20a and 20b and semiconductor element 21, or the semiconductor elements 20a and 20 or semiconductor element 21 and wiring lines 12 are electrically connected through at least one conductive pattern 40. With such a configuration, the semiconductor device whose productivity is high and which is thin and compact can be achieved. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a multichip module type semiconductor device in which a plurality of semiconductor elements are mounted and a method for manufacturing such a semiconductor device.

Multi-chip modules are one of the elemental technologies that make small TVs and mobile phones smaller and lighter.
The multi-chip module is characterized in that a plurality of semiconductor elements are enclosed in one package and each semiconductor element is connected by wiring to improve system performance.

Among them, a multi-chip power device in which power semiconductor elements and control ICs are two-dimensionally arranged on the same support substrate and these elements are wired with bonding wires has attracted attention (for example, see Patent Document 1). ).
JP 2003-218309 A

However, in the device disclosed in the preceding example, a plurality of bonding wires are used between a plurality of elements or between elements and wirings.
Such bonding wire formation requires a lot of time, and there is a problem that the productivity of the device is not improved.

  The present invention has been made in view of such a point, and an object thereof is to provide a highly productive semiconductor device (multichip power device) and a method for manufacturing the semiconductor device.

In one aspect of the present invention, in order to solve the above problems, the present invention is one of a printed wiring board, a ceramic wiring board, a silicon wiring board, and an insulating film-coated metal wiring board, and a plurality of cavities are formed on the main surface. a supporting substrate that is, a plurality of first wires which are selectively arranged on the main surface of the supporting substrate, at least one first semiconductor element mounted on the cavity formed in the support substrate And at least one second semiconductor element mounted in the cavity formed on the support substrate and controlling the first semiconductor element, and disposed on the first wiring on the main surface of the support substrate. A wiring support base material on which a plurality of second wirings are selectively arranged on a main surface opposite to the first wiring, and the first semiconductor element and the second semiconductor element Or the first semiconductor And child or the second semiconductor element and the first wiring, the semiconductor device characterized by being electrically connected via the solder layer through at least one of said second wiring is provided.

In one embodiment of the present invention, as a means for manufacturing such a semiconductor device, a support substrate in which a plurality of cavities are formed on a main surface and a plurality of first wirings are selectively disposed on the main surface is provided. Preparing, mounting at least one first semiconductor element and at least one second semiconductor element for controlling the first semiconductor element in the cavity formed in the support substrate ; A step of disposing a solder material on a part of the first wiring, the electrode of the first semiconductor element, and the electrode of the second semiconductor element; and a plurality of second wirings selectively on the main surface Placing the opposite side of the main surface of the arranged wiring support base on the first wiring, the first semiconductor element, and the second semiconductor element via the solder material; The solder material is melted by reflow treatment, The step of electrically connecting the first semiconductor element and the second semiconductor element or the first semiconductor element or the second semiconductor element and the first wiring through the second wiring. A method for manufacturing a semiconductor device is provided.

In one embodiment of the present invention, a step of preparing a support substrate in which a plurality of cavities are formed on a main surface, and a plurality of first wirings are selectively arranged on the main surface, and the support substrate is formed. Mounting at least one first semiconductor element in the cavity ; placing a solder material on a part of the first wiring and the electrode of the first semiconductor element; Two wirings are selectively disposed on the main surface, and further, the second semiconductor element electrically connected to the second wiring is mounted on the main surface on the opposite side of the main surface of the wiring support base Are placed on the first wiring and the first semiconductor element via the solder material, and the solder material is melted by a reflow process, so that the first semiconductor element and the first semiconductor element are 2 semiconductor elements, or the first semiconductor element and the first semiconductor element A line, a method of manufacturing a semiconductor device characterized by having a step of electrically connecting through the second wiring is provided.

Furthermore, in one embodiment of the present invention, a step of preparing a support substrate in which a plurality of cavities are formed on a main surface and a plurality of first wirings are selectively arranged on the main surface ; the cavity which is, at least one first semiconductor element, a step of mounting at least one of the second semiconductor element for controlling said first semiconductor device, a portion of the first wiring, the second A step of disposing a solder material on the electrode of one semiconductor element, and a plurality of second wirings are selectively disposed on the main surface, and further, a columnar electrode or via that conducts to the second wiring, or Placing the opposite side of the main surface of the wiring support substrate having the vias and electrode pads on the first wiring and the first semiconductor element via the solder material; reflowing; The solder material is melted by the treatment, and the first The semiconductor element and the first wiring, a method of manufacturing a semiconductor device characterized by having a step of electrically connecting through the second wiring is provided.

  According to the present invention, a highly productive semiconductor device and a method for manufacturing the semiconductor device can be realized. Furthermore, it is possible to realize a semiconductor device having a reduced thickness and size and a method for manufacturing the semiconductor device.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
<First Embodiment>
FIG. 1 is a main part view of the semiconductor device according to the first embodiment. Here, FIG. (A) shows the upper surface of the semiconductor device 1a according to the first embodiment, and FIG. (B) shows the semiconductor device 1a at the ab position in FIG. (A). A cross section is shown.

  As shown in the figure, the semiconductor device 1a uses a rectangular support substrate 10 as a base. Then, at a predetermined position of the support substrate 10, at least one cavity 10a is formed in a substantially parallel shape, and, for example, lead-free solder (tin (Sn) -silver (Ag)) is contained in each cavity 10a. The semiconductor elements 20a, 20b, and 21 are mounted via the (solder) layer 11.

  Here, a so-called printed wiring board (circuit board) in which electrodes, wiring, and resin layers are laminated in a multilayer structure is applied to the support substrate 10. And as the said resin, organic-material insulating resin, such as glass-epoxy resin, glass-bismaleimide triazine, or a polyimide, is mentioned.

Moreover, such a support substrate 10, instead of the printed wiring board, for example, alumina (Al ₂ O _3), aluminum nitride (AlN), silicon oxide (SiO _2), magnesium oxide (MgO), calcium oxide You may use the ceramic wiring board which has (CaO) or a mixture of these as a main component.

  Further, when the semiconductor device 1a is manufactured by a wafer process, a silicon wiring board having a base material of a silicon (Si) wafer as a base material may be used as a support substrate. Or it is good also considering the insulating film coating metal wiring board mentioned later as a support substrate.

Further, as shown in FIG. (B), a metal heat radiating plate (heat spreader) 10h may be fixed below the support substrate 10 as necessary.
In addition, for example, vertical power semiconductor elements are applied to the semiconductor elements (first semiconductor elements) 20a and 20b. Specifically, a main electrode (for example, a source electrode) and a control electrode (gate electrode) are disposed on one main surface (upper surface side), and another main electrode (for example, a lower electrode side) is disposed on the other main surface (lower surface side). This corresponds to a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) element provided with a drain electrode.

Alternatively, an IGBT (Insulated Gate Bipolar Transistor) element may be used as an element instead of the power MOSFET.
A semiconductor element (second semiconductor element) 21 located between the semiconductor elements 20a and 20b is a control IC chip, and the semiconductor element 21 performs switching or the like of at least one of the semiconductor elements 20a and 20b. Control.

  The number of semiconductor elements mounted on the semiconductor device 1a is not particularly limited to the above number. That is, it is only necessary that at least one semiconductor element (for example, a power MOSFET or IGBT element) and at least one control IC chip for controlling the power semiconductor element are arranged on the support substrate 10.

  Further, in the semiconductor device 1a, wiring (wiring) incorporated in the main circuit, signal circuit, power supply circuit, etc. on the main surface (upper surface side) of the support substrate 10 on which the semiconductor elements 20a, 20b, 21 are not mounted. A plurality of patterns) 12 are selectively arranged. These wirings 12 are composed of, for example, copper (Cu) as a main component. Further, a wiring support substrate (base film) 30 processed into a predetermined shape is disposed on the wiring 12.

  Here, the wiring support substrate 30 is made of a resin including at least one of a polyimide resin (PI), a liquid crystal polymer resin (LCP), an epoxy resin (EP), a polyethylene terephthalate resin (PET), and a polyphenylene ether resin (PPE). It is configured.

  Further, in the semiconductor device 1a, a plurality of wirings each including a conductive pattern (conductor connector) 40 constituting a wiring pattern is selectively disposed on the wiring support base 30. Yes. These conductive patterns 40 are composed of, for example, copper as a main component.

  Then, due to the arrangement of these conductive patterns 40, the electrodes provided in the semiconductor elements 20a, 20b, and 21 and the wirings 12 corresponding to the respective elements are electrically connected via the conductive patterns 40. ing. Alternatively, the electrodes between the elements provided in the respective semiconductor elements 20 a, 20 b, 21 are electrically connected via the conductive pattern 40.

Note that a solder layer 13 made of lead-free solder is applied as an adhesive member for ensuring the electrical connection.
Further, in the semiconductor device 1a, at the end of the support substrate 10 in the longitudinal direction, the electrode terminals 12a extend from the respective wirings 12 and are connected to the respective electrode terminals 12a as rod-like input / output terminals 50. A plurality of (the material is copper) is provided.

  Then, the semiconductor elements 20a, 20b, 21, the wiring 12, the wiring support base material 30, the conductive pattern 40, and the like mounted on the support substrate 10 are completely made of the epoxy resin 60 formed by the transfer molding method. It is sealed. In FIG. 1A, the resin 60 is not shown in order to clarify the internal structure of the semiconductor device 1a.

  In addition to the transfer molding method, such a resin 60 may be formed by any one of a potting method, a dipping method, a casting method, and a fluidized immersion method. Further, the resin 60 may be impregnated with an inorganic filler composed of alumina or silicon oxide.

With such a configuration, the semiconductor device 1a can function as a multi-chip power device with a compact shape and low cost.
Next, in order to better understand the structure of the semiconductor device 1a shown in FIG. 1, the structure of the semiconductor device 1a will be described with reference to an enlarged view of the cross section of the semiconductor device 1a.

In all the drawings shown below, the same members as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.
FIG. 2 is a schematic cross-sectional view of an essential part of the semiconductor device according to the first embodiment. In FIG. 2, the resin 60 and the input / output terminal 50 are not particularly shown, and an enlarged view of the characteristic form of the semiconductor device 1a is shown.

As described above, in the semiconductor device 1a, the support substrate 10 is used as a base, and the heat radiating plate 10h is fixed below the support substrate 10.
Further, at least one cavity 10 a is formed at a predetermined position of the support substrate 10. In the support substrate 10, conductor pads are selectively arranged. For example, in the semiconductor device 1a, the main surfaces of the conductor pads 14a and 14b constitute the bottom surfaces of the cavities 10a.

  Such conductor pads 14a and 14b are electrically connected to wirings, vias, and the like (not shown) disposed in the support substrate 10, and further, electrical connection with the input / output terminals 50 and the like is ensured through the wirings and the like. Yes.

The semiconductor elements 20a and 21 are mounted on the conductor pads 14a and 14b via the solder layer 11.
Accordingly, the drain electrode on the lower surface side of the semiconductor element 20a and the conductor pad 14a are electrically connected via the solder layer 11.

  In addition, in the semiconductor element 21 which is a control IC chip, when electrodes are disposed on the upper and lower main surfaces, the electrode on the lower surface side and the conductor pad 14b are interposed via the solder layer 11. Electrically connected. However, in the semiconductor element 21, in the case where electrodes are not disposed on both main surfaces, the conductor pad 14b is not necessarily disposed.

  Further, the conductor pads 14a and 14b are arranged in the support substrate 10 so that the area of the main surface thereof is as large as possible. In order to suppress the influence (interference) of noise between the semiconductor elements 20a and 21, the conductor pads 14a and 14b are separated from each other, and the distance d is set to 0.2 to 3 mm. In this case, if d is extremely small, adjacent cavities 10a may be coupled to each other. Therefore, the lower limit of d is 0.2 mm. In order not to reduce the mounting density, it is desirable to set the upper limit of d to 3 mm. In addition, in order to ensure the insulation between power semiconductor elements between the cavity 10a which accommodates a power semiconductor element, it is desirable to set the minimum of d to 0.5 mm.

  A plurality of wirings 12 are selectively arranged on the upper surface of the support substrate 10 on which the semiconductor elements 20a and 21 are not mounted. A wiring support base 30 processed into a predetermined shape is disposed on the wiring 12.

  Furthermore, in the semiconductor device 1 a, the conductive pattern 40 is disposed on the wiring support base 30. With the arrangement of the conductive pattern 40, the electrode pads 20 ap and 21 p disposed on the upper surfaces of the semiconductor elements 20 a and 21 and the wiring 12 are electrically connected via the conductive pattern 40.

Note that a solder layer 13 is applied as an adhesive member for ensuring the electrical connection.
In the semiconductor device 1a, the depth of the cavity 10a is adjusted so that the upper surfaces of the electrode pads 20ap and 21p and the upper surface of the wiring 12 have substantially the same height.

Next, a characteristic structure of each part constituting the semiconductor device 1a will be described.
First, the conductive pattern 40 selectively disposed on the wiring support base 30 will be described.

  FIG. 3 is a main part view of the conductive pattern selectively disposed on the wiring support base. Here, FIG. 3 shows a state of the wiring support base 30 and the conductive pattern 40 when the semiconductor device 1a shown in FIG. 1A is viewed from above.

  As shown in the drawing, a conductive pattern 40 is selectively placed and supported on an interconnect support base 30 processed into a predetermined shape via an adhesive member (not shown). Here, the conductive pattern 40 has a thickness and a line width of 5 mm or less.

Further, a through hole 30 a is provided in the central portion of the wiring support base 30. The semiconductor element 21 shown in FIGS. 1 and 2 is located below the through hole 30a.
Each conductive pattern 40 includes an extended portion (finger portion) 40 a extending from the main surface of the wiring support base 30 at both ends thereof. And the electrode pad and wiring which are to-be-joined bodies are located below the said extension part 40a (back direction of a figure).

  With such a structure, after the wiring support base material 30 on which the conductive pattern 40 is disposed is placed on the electrode pads 20ap, 21p or the wiring 12, the semiconductor element 20a, The electrodes provided in 20b and 21 and the wiring 12 corresponding to the position of each element, or the electrodes between the elements provided in each semiconductor element 20a, 20b and 21 are connected via the conductive pattern 40. , And can be electrically connected together (described later).

Moreover, the plating part is coat | covered in such an extension part 40a. This state will be described with reference to FIG.
FIG. 4 is a main part view of the conductive pattern selectively disposed on the wiring support base. Here, in FIG. 4, the back view which looked at the wiring support base material 30 shown in FIG. 3 and the electroconductive pattern 40 from the back surface side is shown. Here, FIG. (A) shows an overall view, and FIG. (B) shows a cross-section at the ab position in FIG. (A).

  As illustrated, an extending portion 40 a that is a part of the conductive pattern 40 extends from the main surface of the wiring support base 30. A plating layer 40g coated with nickel (Ni), gold (Au), nickel (Ni), and tin (Sn) in this order from the lower layer is formed on the back surface side of the extended portion 40a.

  By providing such a plating layer 40g, oxidation of the joint surface of the conductive pattern 40 is prevented. Thereby, the state of the joint part after soldering becomes good, and no joint failure or the like occurs.

Next, the structure of the input / output terminal 50 provided at the end of the support substrate 10 will be described.
FIG. 5 is a diagram for explaining the structure of the input / output terminals.
As shown in the drawing, the input / output terminal 50 includes a clip portion 50a that is split into two branches at one end thereof. The clip portion 50 a is sandwiched between the wiring 12 disposed on the upper and lower main surfaces of the support substrate 10 via the plating layer 12 g and the solder layer 51.

  Thus, the input / output terminal 50 is firmly supported by the end of the support substrate 10 by fitting the clip portion 50a to the end of the support substrate 10 and soldering the clip portion 50a and the wiring 12 via the plating layer 12g. Yes.

  Further, the solder layer 51 is not only disposed in the gap between the plating layer 12g and the clip portion 50a, but is formed so as to cover these portions from the end of the clip portion 50a to a part of the wiring 12. Has been. By forming the solder layer 51, the mechanical strength in the sandwiched state is further increased.

  The plating layer 12g is composed of nickel, gold, nickel, or tin as main components from the lower layer according to the material of the solder layer 51. Further, the plating layer 12g may be formed on the input / output terminal 50 side in addition to being formed on the main surface of the wiring 12.

Subsequently, a semiconductor device obtained by modifying the configuration of the semiconductor device 1a according to the present embodiment will be described.
<Variation 1 of the first embodiment>
First, the semiconductor device 1b will be described in which an insulating film is formed on the adjacent wiring 12 disposed on the main surface (upper surface side) of the support substrate 10.

FIG. 6 is a main part view for explaining a semiconductor device in which an insulating film is arranged.
As shown in the drawing, an insulating coating 61 is formed on the main surface of the support substrate 10 located between the adjacent wirings 12 and on a part of the main surface of these wirings 12. However, the insulating coating 61 is formed in a region excluding the joint portion between the solder layer 13 and the wiring 12.

  When such an insulating coating 61 exists, when the solder layer 13 is formed by the reflow process, the outflow of the molten solder material can be suppressed by the dam effect. Thereby, the short circuit between the wiring 12 by a solder material can be prevented reliably.

<Modification 2 of the first embodiment>
Next, the semiconductor device 1c in which the ground layer is embedded in the support substrate 10 will be described.
FIG. 7 is a main part diagram for explaining a semiconductor device having a ground layer.

  As shown in the figure, ground layers 15a, 15b, 15b, and 15b, grounded at positions between the wiring 12 arranged on the main surface (upper surface side) of the support substrate 10 and the conductor pads 14a, 14b arranged in the cavity 10a. A plurality of 15c are selectively provided.

As described above, when the ground layers 15a, 15b, and 15c are arranged at positions between the wiring 12 and the conductor pads 14a and 14b, there is an effect of further noise reduction.
<Modification 3 of the first embodiment>
Next, the semiconductor device 1d using the above-described insulating film-covered metal wiring board will be described.

FIG. 8 is a principal view for explaining a semiconductor device using an insulating film-covered metal wiring board.
As shown in the drawing, in the semiconductor device 1d, instead of the support substrate 10 described above, an insulating film-covered metal including a core substrate 70, a resin layer 71 disposed above and below the core substrate 70, and an insulating film 72 is provided. A wiring board 73 is used.

Here, the core substrate 70 has a thickness of 100 μm to 1 mm, and its material is mainly copper, aluminum, or an alloy thereof.
On the core substrate 70, a resin layer 71 made of the same material as that of the support substrate 10 and having wiring, vias and the like laminated therein is selectively disposed.

  In addition, the semiconductor element 20 a is mounted via the solder layer 11 on the main surface of the core substrate 70 on which the resin layer 71 is not selectively disposed. Further, the resin layer 71 is provided with a cavity 10a, and the semiconductor element 21 is mounted in the cavity 10a via an adhesive member (not shown).

The insulating film 72 disposed under the core substrate 70 is made of the ceramic or resin.
According to such a configuration of the semiconductor device, the heat generated from the semiconductor elements 20 a and 21 can be reliably radiated to the core substrate 70 through the solder layer 11 or the resin layer 71.

  The insulating film-covered metal wiring board 73 described above may be a metal core substrate in which both ends of the core substrate 70 are covered with a resin or the like, or a metal base substrate in which the insulating film 72 is not disposed in the lowermost layer.

<Second Embodiment>
FIG. 9 is a schematic cross-sectional view of the relevant part of a semiconductor device according to the second embodiment. Note that, in all the drawings shown below, the same members shown in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. Further, in FIG. 9, the resin 60 and the input / output terminal 50 are not particularly displayed, and an enlarged view of the characteristic form of the semiconductor device 2 is shown.

In the semiconductor device 2 according to the second embodiment, the support substrate 10 is used as a base, and the heat radiating plate 10 h is fixed below the support substrate 10.
Further, at least one cavity 10 a is formed at a predetermined position of the support substrate 10. Conductor pads 14a and 14b are disposed on the bottom of the cavity 10a as a base. However, in the semiconductor element 21 which is a control IC chip, when the electrodes are not provided on the upper and lower main surfaces, the conductor pad 14b is not necessarily provided.

  A plurality of wirings 12 are selectively arranged on the main surface (upper surface side) of the support substrate 10 on which the semiconductor elements 20a and 21 are not mounted. And on the wiring 12, the wiring support base material 31 by which the conductive metal film (metal film) 41 which comprises a wiring pattern was pattern-formed by the lower surface side is arrange | positioned. The line width of the conductive metal film 41 is 5 mm or less.

  With such an arrangement of the conductive metal film 41, the electrode pads 20ap and 21p disposed on the upper surfaces of the semiconductor elements 20a and 21 and the wiring 12 are electrically connected via the conductive metal film 41. Yes. Alternatively, although not shown in the drawing, the electrodes of the semiconductor element 20 a and the electrodes of the semiconductor element 21 are electrically connected via the conductive metal film 41.

Note that a solder layer 13 is applied as an adhesive member for ensuring the electrical connection.
Next, the configuration of the conductive metal film 41 selectively disposed on the lower surface of the wiring support base 31 will be described in detail.

  FIG. 10 is a main part view of a conductive metal film selectively disposed on a wiring support base. Here, FIG. 10 shows the state of the wiring support base 30 and the conductive metal film 41 when the semiconductor device 2 shown in FIG. 9 is viewed from below. Therefore, in FIG. 10, the back side of the wiring support base 31 is shown.

  As shown in the drawing, a conductive metal film 41 is selectively disposed on the main surface (lower surface side) of the wiring support base 31 processed into a predetermined shape, for example, via an adhesive member (not shown). It is supported. Here, the conductive metal film 41 is made of any metal of copper, silver (Ag), gold, aluminum (Al), or an alloy containing at least one of them. In particular, it is desirable to use a metal material that improves the wettability of the solder material.

  Each conductive metal film 41 has a line width of 5 mm or less. Further, the thickness of the conductive metal film 41mos that conducts to the electrode of the power semiconductor element such as the semiconductor elements 20a and 20b is 25 to 500 μm. In addition, when elements other than the power semiconductor element (described later) are used as the semiconductor elements 20a and 20b, the thickness of the conductive metal film 41mos that conducts to the electrode of the element is configured to be 3 to 500 μm. In addition, the conductive metal film 41ic that is electrically connected to the electrode of the control IC chip such as the semiconductor element 21 has a thickness of 3 to 500 μm.

  Moreover, the selective pattern formation of the conductive metal film 41 as shown in the figure is performed by laminating and bonding an integral metal film made of the above metal material onto the wiring support base material 31 and further to the metal film. It is formed by etching.

Alternatively, after a conductive paste composed of the metal material on the wiring support substrate 31 is selectively positioned by screen printing, it may be formed by drying and hardening the conductive paste.

Or after forming the metal film comprised with the said metal material on the wiring support base material 31 by sputtering or vapor deposition, you may form by etching the said metal film.
Or after forming the plating layer comprised with the said metal material on the wiring support base material 31, you may form by performing the selective etching to the said plating layer.

Alternatively, the surface of the wiring support base 31 may be modified by a chemical or optical method and formed by a selective chemical plating method.
Then, below the end of each conductive metal film 41 (front side in the figure), electrode pads and wirings which are bonded bodies are located.

  With such a structure, after the wiring support base 31 provided with the conductive metal film 41 is placed on the electrode pads 20ap, 21p or the wiring 12, the semiconductor element 20a is subjected to a single reflow process. , 20b, 21 and the wiring 12 corresponding to each element, or the electrodes between the elements provided in each semiconductor element 20a, 20b, 21 are connected via the conductive metal film 41. , And can be electrically connected together (described later).

In the semiconductor device 2 according to the second embodiment, the configurations shown in FIGS. 5 to 8 described in the first embodiment may be diverted.
<Third Embodiment>
FIG. 11 is a main part view of a semiconductor device according to the third embodiment. Here, FIG. (A) shows the top surface of the semiconductor device 3a according to the first embodiment, and FIG. (B) shows the semiconductor device 3a at the ab position in FIG. (A). A cross section is shown.

In all the drawings shown below, the same reference numerals are given to the same members shown in the first and second embodiments, and the detailed description thereof will be omitted.
As shown in the figure, the semiconductor device 3a uses a rectangular support substrate 10 as a base. At least one cavity 10 a is formed on both sides of the support substrate 10, and the semiconductor elements 20 a and 20 b are mounted in the respective cavities 10 a via, for example, the solder layer 11.

Further, as shown in FIG. (B), a heat radiating plate 10h may be fixed below the support substrate 10 as necessary.
In the semiconductor device 3a, a plurality of wirings 12 are selectively arranged on the main surface (upper surface side) of the support substrate 10 on which the semiconductor elements 20a and 20b are not mounted. Further, a wiring support substrate 30 processed into a predetermined shape is disposed on the wiring 12.

In the semiconductor device 3a, a plurality of conductive patterns 40 are selectively disposed on the wiring support base 30.
In the third embodiment, the semiconductor element 21 is mounted on the plurality of conductive patterns 40 located at the center of the support substrate 10.

  Furthermore, by the arrangement of these conductive patterns 40, the electrodes provided on the semiconductor elements 20a, 20b, and 21 and the wirings 12 corresponding to the respective elements are electrically connected via the conductive patterns 40. ing. Alternatively, the electrodes between the elements provided in the respective semiconductor elements 20 a, 20 b, 21 are electrically connected via the conductive pattern 40.

Note that a solder layer 13 is applied as an adhesive member for ensuring the electrical connection.
Further, the number of semiconductor elements mounted on the semiconductor device 3a is not particularly limited to the above number. That is, it is only necessary that at least one semiconductor element (for example, a power MOSFET or IGBT element) and at least one control IC chip for controlling the power semiconductor element are arranged on the support substrate 10.

  Further, in the semiconductor device 3a, at the end in the longitudinal direction of the support substrate 10, the electrode terminal 12a extends from the wiring 12, and a plurality of rod-like input / output terminals 50 that are electrically connected to the respective electrode terminals 12a are provided. Are provided.

  The semiconductor elements 20 a, 20 b, 21 mounted on the support substrate 10, the wiring 12, the wiring support base material 30, the conductive pattern 40, etc. are completely sealed with the resin 60. In FIG. 1A, the resin 60 is not shown in order to clarify the internal structure of the semiconductor device 3a.

With such a configuration, the semiconductor device 3a can function as a multi-chip power device with a compact shape and low cost.
Next, in order to understand the structure of the semiconductor device 3a shown in FIG. 11 in more detail, the structure of the semiconductor device 3a will be described with reference to an enlarged view of the semiconductor device 3a.

  FIG. 12 is a schematic cross-sectional view of an essential part of a semiconductor device according to the third embodiment. In FIG. 12, the resin 60 and the input / output terminal 50 are not particularly shown, and an enlarged view of the characteristic form of the semiconductor device 3a is shown.

As described above, in the semiconductor device 3a, the support substrate 10 is used as a base, and the heat radiating plate 10h is fixed below the support substrate 10.
Further, at least one cavity 10 a is formed at a predetermined position of the support substrate 10. A conductor pad 14a is disposed on the bottom of the cavity 10a as a base.

  Such a conductor pad 14a is electrically connected to a wiring, a via, etc. (not shown) disposed in the support substrate 10, and further, an electrical connection with the input / output terminal 50 or the like is secured through the wiring or the like.

A semiconductor element 20a is mounted on the conductor pad 14a via the solder layer 11.
Accordingly, the drain electrode on the lower surface side of the semiconductor element 20a and the conductor pad 14a are electrically connected via the solder layer 11.

Further, the conductor pad 14a is arranged in the support substrate 10 so that the area of the main surface thereof is as large as possible.
A plurality of wirings 12 are selectively arranged on the main surface (upper surface side) of the support substrate 10 on which the semiconductor element 20a is not mounted. A wiring support base 30 processed into a predetermined shape is disposed on the wiring 12.

Furthermore, in the semiconductor device 3 a, the conductive pattern 40 is disposed on the wiring support base 30.
In the semiconductor element 20a, due to the arrangement of the conductive pattern 40, the electrode pad 20ap disposed on the upper surface of the semiconductor element 20a and the wiring 12 are electrically connected via the conductive pattern 40. ing.

  In the semiconductor element 21, the electrode pad 21 p mounted on the conductive pattern 40 and disposed on the main surface of the semiconductor element 21 and the wiring 12 are electrically connected via the conductive pattern 40. Has been.

Alternatively, although not shown in the drawing, the electrode of the semiconductor element 20 a and the electrode of the semiconductor element 21 are electrically connected via the conductive pattern 40.
In other words, the semiconductor device 3 a has a configuration in which the semiconductor element 21 is mounted on the conductive pattern 40 selectively disposed on the wiring support base 30.

Note that a solder layer 13 is applied as an adhesive member for ensuring the electrical connection.
Further, the semiconductor device 3a is configured such that the upper surface of the electrode pad 20ap and the upper surface of the wiring 12 have substantially the same height by adjusting the depth of the cavity 10a.

Subsequently, a semiconductor device obtained by modifying the configuration of the semiconductor device 3a according to the present embodiment will be described.
<Modification of Third Embodiment>
This modification is characterized in that the semiconductor element 21 and the conductive pattern 40 are electrically connected by wire bonding.

  FIG. 13 is a main part view of a semiconductor device according to a modification of the third embodiment. Here, FIG. (A) shows the top surface of the semiconductor device 3b according to the modification, and FIG. (B) shows a cross section of the semiconductor device 3b at the ab position in FIG. (A). Has been.

  As shown in the figure, the semiconductor device 3b uses a rectangular support substrate 10 as a base. At least one cavity 10 a is formed on both sides of the support substrate 10, and the semiconductor elements 20 a and 20 b are mounted in the respective cavities 10 a via, for example, the solder layer 11.

Further, as shown in FIG. (B), a heat radiating plate 10h may be fixed below the support substrate 10 as necessary.
In the semiconductor device 3b, a plurality of wirings 12 are selectively arranged on the main surface (upper surface side) of the support substrate 10 on which the semiconductor elements 20a and 20b are not mounted. Further, a wiring support substrate 30 processed into a predetermined shape is disposed on the wiring 12.

Further, in the semiconductor device 3b, a plurality of conductive patterns 40 are selectively disposed on the wiring support base 30.
And in the said modification, the semiconductor element 21 is mounted in the position of the center part of the wiring support base material 30 via the adhesive member (not shown). Furthermore, an electrode disposed on the main surface of the semiconductor element 21 and a plurality of conductive patterns 40 positioned around the semiconductor element 21 are electrically connected via bonding wires 22 formed of gold wires. ing.

  Furthermore, by the arrangement of these conductive patterns 40, the electrodes provided on the semiconductor elements 20a, 20b, and 21 and the wirings 12 corresponding to the respective elements are electrically connected via the conductive patterns 40. .

Note that a solder layer 13 or the like is applied as an adhesive member for ensuring the electrical connection.
Further, the number of semiconductor elements mounted on the semiconductor device 3b is not particularly limited to the above number. That is, it is only necessary that at least one semiconductor element (for example, a power MOSFET or IGBT element) and at least one control IC chip for controlling the power semiconductor element are arranged on the support substrate 10.

  Further, in the semiconductor device 3b, at the end portion in the longitudinal direction of the support substrate 10, the electrode terminal 12a extends from the wiring 12, and there are a plurality of rod-like input / output terminals 50 connected to the electrode terminal 12a. , Provided.

  The semiconductor elements 20 a, 20 b, 21 mounted on the support substrate 10, the wiring 12, the wiring support base 30, the conductive pattern 40, the bonding wire 22, etc. are completely sealed with the resin 60. In FIG. 1A, the resin 60 is not shown in order to clarify the internal structure of the semiconductor device 3b.

With such a configuration, the semiconductor device 3b can function as a multi-chip power device with a compact shape and low cost.
Next, in order to understand the structure of the semiconductor device 3b shown in FIG. 13 in more detail, the structure of the semiconductor device 3b will be described with reference to an enlarged view of the cross section of the semiconductor device 3b.

  FIG. 14 is a schematic cross-sectional view of an essential part of a semiconductor device according to a modification of the third embodiment. In FIG. 14, the resin 60 and the input / output terminal 50 are not particularly shown, and an enlarged view of the characteristic form of the semiconductor device 3b is shown.

As described above, in the semiconductor device 3b, the support substrate 10 is used as a base, and the heat radiating plate 10h is fixed below the support substrate 10.
Further, at least one cavity 10 a is formed at a predetermined position of the support substrate 10. A conductor pad 14a is disposed on the bottom of the cavity 10a as a base.

  Such a conductor pad 14a is electrically connected to a wiring, a via, etc. (not shown) disposed in the support substrate 10, and further, an electrical connection with the input / output terminal 50 or the like is secured through the wiring or the like.

A semiconductor element 20a is mounted on the conductor pad 14a via the solder layer 11.
Accordingly, the drain electrode on the lower surface side of the semiconductor element 20a and the conductor pad 14a are electrically connected via the solder layer 11.

Further, the conductor pad 14a is arranged in the support substrate 10 so that the area of the main surface thereof is as large as possible.
A plurality of wirings 12 are selectively arranged on the main surface (upper surface side) of the support substrate 10 on which the semiconductor element 20a is not mounted. A wiring support base 30 processed into a predetermined shape is disposed on the wiring 12.

Furthermore, in the semiconductor device 3 b, the conductive pattern 40 is disposed on the wiring support base 30.
In the semiconductor element 20a, due to the arrangement of the conductive pattern 40, the electrode pad 20ap disposed on the upper surface of the semiconductor element 20a and the wiring 12 are electrically connected via the conductive pattern 40. ing.

  Moreover, in the semiconductor element 21, it mounts on the wiring support base material 30 in which the electroconductive pattern 40 is not arrange | positioned through the adhesive member (not shown). The electrode pad 21 p disposed on the main surface of the semiconductor element 21 and the conductive pattern 40 positioned around the semiconductor element 21 are electrically connected via the bonding wire 22. With such a configuration, the electrode pad 21 p disposed on the main surface of the semiconductor element 21 and the wiring 12 are electrically connected via the conductive pattern 40.

  Further, the semiconductor device 3b is configured such that the upper surface of the electrode pad 20ap and the upper surface of the wiring 12 have substantially the same height by adjusting the depth of the cavity 10a.

  Thus, the electrode pads 21p disposed on the main surface of the semiconductor element 21 and the conductive pattern 40 positioned around the semiconductor element 21 are electrically connected via the bonding wires 22. Thereby, even if the semiconductor element 21 is different in size, it can be easily incorporated into the semiconductor device 3b.

Furthermore, since the bonding wire 22 composed of a gold wire is used, high-speed bonding is possible.
Further, in each of the semiconductor devices 3a and 3b according to the third embodiment, the configurations of FIGS. 5 to 8 described in the first embodiment may be diverted.

<Fourth embodiment>
FIG. 15 is a schematic cross-sectional view of a relevant part of a semiconductor device according to the fourth embodiment. In all the drawings shown below, the same members shown in the first to third embodiments are denoted by the same reference numerals, and detailed description thereof is omitted. In FIG. 15, the resin 60 and the input / output terminal 50 are not particularly shown, and an enlarged view of the characteristic form of the semiconductor device 4 is shown.

In the semiconductor device 4 according to the fourth embodiment, the support substrate 10 is used as a base, and the heat radiating plate 10 h is fixed below the support substrate 10.
Further, at least one cavity 10 a is formed at a predetermined position of the support substrate 10. A conductor pad 14a is disposed on the bottom of the cavity 10a as a base.

  A plurality of wirings 12 are selectively arranged on the main surface (upper surface side) of the support substrate 10 on which the semiconductor element 20a is not mounted. On the wiring 12, a wiring support base 31 having a conductive metal film 42 patterned on the upper surface side is disposed.

  Here, a via 42 v penetrating the wiring support base 31 is provided at a predetermined position of the wiring support base 31. An electrode pad 42p is provided on the lower surface of the wiring support base 31 corresponding to the position of the via 42v.

With this configuration, the conductive metal film 42 patterned on the upper surface side of the wiring support base 31 is electrically connected to the electrode pad 42p disposed on the lower surface side via the via 42v.
Then, each electrode pad 42p is joined to the electrode pads 20ap, 21p disposed on the upper surfaces of the semiconductor elements 20a, 21 so that the electrode pads 20ap, 21p and the wiring 12 are interposed via the conductive metal film 42. Are electrically connected. Alternatively, although not shown in the drawing, the electrode of the semiconductor element 20 a and the electrode of the semiconductor element 21 are electrically connected via the conductive metal film 42.

Note that a solder layer 13 is applied as an adhesive member for ensuring the electrical connection.
Subsequently, the configuration of the conductive metal film 42 selectively disposed on the wiring support base 31 will be described in detail.

  FIG. 16 is a main part view of a conductive metal film selectively disposed on a wiring support base. Here, FIG. 16 shows the state of the wiring support base 30 and the conductive metal film 42 when the semiconductor device 4 shown in FIG. 15 is viewed from above. Therefore, in FIG. 16, the upper surface side of the wiring support base material 31 is shown.

  As shown in the figure, a conductive metal film 42 is selectively disposed and supported on the main surface (upper surface side) of the wiring support base 31 processed into a predetermined shape via, for example, an adhesive member (not shown). Has been. Here, the conductive metal film 42 is made of any metal of copper, silver, gold, aluminum, or an alloy containing at least one of them. In particular, it is desirable to use a metal material that improves the wettability of the solder material.

  Each conductive metal film 42 has a line width of 5 mm or less. Further, the thickness of the conductive metal film 42 mos conducted to the electrode of the power semiconductor element such as the semiconductor elements 20 a and 20 b is set to 25 to 500 μm. In addition, the conductive metal film 42ic that is electrically connected to the electrode of the control IC chip such as the semiconductor element 21 has a thickness of 3 to 500 μm.

  In addition, the selective pattern formation of the conductive metal film 42 as shown in the figure is performed by laminating and bonding the integrated metal film made of the above metal material onto the wiring support base material 31 and further bonding the metal. The film is formed by etching.

Alternatively, after a conductive paste composed of the metal material on the wiring support substrate 31 is selectively positioned by screen printing, it may be formed by drying and hardening the conductive paste.

Alternatively, a pattern of a metal film made of the above metal material may be formed on the wiring support base 31 by facing the mask and by sputtering or vapor deposition.
Or after forming the plating layer comprised with the said metal material on the wiring support base material 31, you may form by performing selective etching.

Alternatively, the surface of the wiring support base 31 may be modified by a chemical or optical method and formed by a selective chemical plating method.
And the electrode pad and wiring which are to-be-joined bodies are located under the via | veer 42v of each electroconductive metal film 42 (back direction of a figure).

  With such a structure, after the wiring support base 31 provided with the conductive metal film 42 is placed on the electrode pads 20ap, 21p or the wiring 12, the semiconductor element 20a is subjected to a single reflow process. , 20b, 21 and the wiring 12 corresponding to each element, or the electrodes between the elements provided in the respective semiconductor elements 20a, 20b, 21 are connected to each other through the conductive metal film 42. , And can be electrically connected together (described later).

In the semiconductor device 4 according to the fourth embodiment, the configurations shown in FIGS. 5 to 8 described in the first embodiment may be diverted.
<Fifth embodiment>
FIG. 17 is a schematic cross-sectional view of an essential part of a semiconductor device according to the fifth embodiment. In all the drawings shown below, the same reference numerals are given to the same members shown in the first to fourth embodiments, and the detailed description thereof will be omitted. In FIG. 17, the resin 60 and the input / output terminal 50 are not particularly shown, and an enlarged view of the characteristic form of the semiconductor device 5a is shown.

In the semiconductor device 5a according to the fifth embodiment, the support substrate 10 is used as a base, and the heat radiating plate 10h is fixed below the support substrate 10.
A plurality of wirings 12 are selectively disposed on the main surface (upper surface side) of the support substrate 10.

  In the semiconductor device 5a, the semiconductor element 20a is mounted on the wiring 12 arranged on the left side of the support substrate 10 shown in this figure via the solder layer 11. Accordingly, the drain electrode on the lower surface side of the semiconductor element 20 a and the wiring 12 are electrically connected via the solder layer 11.

  Further, the semiconductor element 21 is mounted on the main surface (upper surface side) of the support substrate 10 where the wiring 12 is not disposed via an adhesive member (not shown). Further, in the semiconductor element 21, the electrode pad 21 p and the wiring 12 are electrically connected by a bonding wire 22.

Further, an electrode pad 12p made of copper is fixed on the wiring 12 arranged in the center of the support substrate 10 shown in this figure.
And the wiring support base material 30 processed into the predetermined shape is arrange | positioned above the wiring 12 which mounts the semiconductor element 20a.

Furthermore, in the semiconductor device 5 a, the conductive pattern 40 is disposed on the wiring support base 30.
Here, the conductive pattern 40 is disposed in parallel with the main surface of the support substrate 10, and one end thereof is bonded to the electrode pad 20 ap disposed on the upper surface of the semiconductor element 20 a via the solder layer 13. .

  Further, a via 30 v in which a metal layer is embedded is formed in the wiring support base 30. Such a via 30v is formed by plating, for example, and is electrically connected to the conductive pattern 40. Moreover, the material is comprised with the main component of copper.

The other end of the conductive pattern 40 is joined to the electrode pad 12p on the wiring 12 arranged in the center of the support substrate 10 through the via 30v.
Here, the parallel state of the conductive pattern 40 and the main surface of the support substrate 10 is maintained by adjusting the thickness of the wiring support base 30.

  That is, by setting the wiring support base 30 to a predetermined thickness, the step between the electrode pad 20ap disposed on the upper surface of the semiconductor element 20a and the electrode pad 12p on the wiring 12 is corrected, and the conductive pattern 40 Are arranged horizontally.

  As described above, in the semiconductor element 20a, due to the arrangement of the conductive pattern 40, the electrode pad 20ap and the wiring 12 disposed on the upper surface of the semiconductor element 20a are electrically connected via the conductive pattern 40. It is connected.

In addition, a solder layer 13 is applied as an adhesive member that ensures the electrical connection.
Note that a plating layer coated with nickel and gold in that order from the lower layer may be formed on the surface of the electrode pads 20ap and 12p.

Subsequently, a semiconductor device in which the configuration of the semiconductor device 5a according to the present embodiment is modified will be described.
<Modification 1 of Fifth Embodiment>
FIG. 18 is a schematic cross-sectional view of the relevant part of a semiconductor device according to a modification of the fifth embodiment. In FIG. 18, the resin 60 and the input / output terminal 50 are not particularly shown, and an enlarged view of the characteristic form of the semiconductor device 5b is shown.

In the semiconductor device 5b according to the modified example, the support substrate 10 is used as a base, and the heat radiating plate 10h is fixed below the support substrate 10.
A plurality of wirings 12 are selectively disposed on the main surface (upper surface side) of the support substrate 10.

  Further, in the semiconductor device 5b, the semiconductor element 20a is mounted on the wiring 12 arranged on the left side of the support substrate 10 shown in FIG. Accordingly, the drain electrode on the lower surface side of the semiconductor element 20 a and the wiring 12 are electrically connected via the solder layer 11.

  Further, the semiconductor element 21 is mounted on the main surface (upper surface side) of the support substrate 10 where the wiring 12 is not disposed via an adhesive member (not shown). Further, in the semiconductor element 21, the electrode pad 21 p and the wiring 12 are electrically connected by a bonding wire 22.

Further, an electrode pad 12p made of copper is fixed on the wiring 12 arranged in the center of the support substrate 10 shown in this figure.
And the wiring support base material 30 processed into the predetermined shape is arrange | positioned above the wiring 12 which mounts the semiconductor element 20a.

Furthermore, in the semiconductor device 5 b, the conductive pattern 40 is disposed on the wiring support base 30.
Here, the conductive pattern 40 is disposed in parallel with the main surface of the support substrate 10, and one end thereof is bonded to the electrode pad 20 ap disposed on the upper surface of the semiconductor element 20 a via the solder layer 13. .

  Further, at the other end of the conductive pattern 40, for example, a columnar electrode 40s made of copper is formed so as to face the main surface side of the support substrate 10 from the one end. Such a columnar electrode 40s is formed by plating, for example. The other end is joined to the electrode pad 12p on the wiring 12 disposed in the center of the support substrate 10 via the columnar electrode 40s.

Here, the parallel state of the conductive pattern 40 and the main surface of the support substrate 10 is maintained by adjusting the height of the columnar electrode 40s.
That is, by setting the columnar electrode 40s to a predetermined height, the step between the electrode pad 20ap disposed on the upper surface of the semiconductor element 20a and the electrode pad 12p on the wiring 12 is corrected, and the conductive pattern 40 is formed. It is arranged horizontally.

  As described above, in the semiconductor element 20a, due to the arrangement of the conductive pattern 40, the electrode pad 20ap and the wiring 12 disposed on the upper surface of the semiconductor element 20a are electrically connected via the conductive pattern 40. It is connected.

In addition, a solder layer 13 is applied as an adhesive member that ensures the electrical connection.
Note that a plating layer coated with nickel and gold in that order from the lower layer may be formed on the surface of the electrode pads 20ap and 12p.

<Modification 2 of Fifth Embodiment>
FIG. 19 is a schematic cross-sectional view of an essential part of a semiconductor device according to a modification of the fifth embodiment. In FIG. 19, the resin 60 and the input / output terminal 50 are not particularly shown, and an enlarged view of the characteristic form of the semiconductor device 5c is shown.

In the semiconductor device 5c according to the modification, the support substrate 10 is used as a base, and the heat radiating plate 10h is fixed below the support substrate 10.
A plurality of wirings 12 are selectively disposed on the main surface (upper surface side) of the support substrate 10.

Further, in the semiconductor device 5c, the semiconductor element 20a is mounted on the wiring 12 arranged on the left side of the support substrate 10 shown in this figure via the solder layer 11.
Further, the semiconductor element 21 is mounted on the main surface (upper surface side) of the support substrate 10 where the wiring 12 is not disposed via an adhesive member (not shown). Further, in the semiconductor element 21, the electrode pad 21 p and the wiring 12 are electrically connected by a bonding wire 22.

And the wiring support base material 30 processed into the predetermined shape is arrange | positioned above the wiring 12 which mounts the semiconductor element 20a.
Furthermore, in the semiconductor device 5 c, the conductive pattern 40 is disposed on the wiring support base 30.

  Here, the conductive pattern 40 is disposed in parallel with the main surface of the support substrate 10, and one end thereof is bonded to the electrode pad 20 ap disposed on the upper surface of the semiconductor element 20 a via the solder layer 13. .

  Further, at the other end of the conductive pattern 40, for example, a columnar electrode 40s made of copper is formed so as to face the main surface side of the support substrate 10 from the other end. . Such a columnar electrode 40s is formed by plating, for example. The other end is joined to the wiring 12 arranged at the center of the support substrate 10 via the columnar electrode 40s.

  By the way, the height of the columnar electrode 40s is adjusted to a predetermined height, for example, about the thickness of the semiconductor element 20a. Thereby, the step between the electrode pad 20ap disposed on the upper surface of the semiconductor element 20a and the wiring 12 is corrected, and the conductive pattern 40 can be disposed horizontally.

  As described above, in the semiconductor element 20a, due to the arrangement of the conductive pattern 40, the electrode pad 20ap disposed on the upper surface of the semiconductor element 20a and the wiring 12 are electrically connected via the conductive pattern 40. Has been.

In addition, a solder layer 13 is applied as an adhesive member that ensures the electrical connection.
<Modification 3 of Fifth Embodiment>
FIG. 20 is a schematic cross-sectional view of an essential part of a semiconductor device according to a modification of the fifth embodiment. In FIG. 20, the resin 60 and the input / output terminal 50 are not particularly shown, and an enlarged view of the characteristic form of the semiconductor device 5d is shown.

In the semiconductor device 5d according to the modification, the support substrate 10 is used as a base, and the heat radiating plate 10h is fixed below the support substrate 10.
A plurality of wirings 12 are selectively disposed on the main surface (upper surface side) of the support substrate 10.

In the semiconductor device 5d, the semiconductor element 20a is mounted on the wiring 12 arranged on the left side of the support substrate 10 shown in this figure via the solder layer 11.
Further, the semiconductor element 21 is mounted on the main surface (upper surface side) of the support substrate 10 where the wiring 12 is not disposed via an adhesive member (not shown). Further, in the semiconductor element 21, the electrode pad 21 p and the wiring 12 are electrically connected by a bonding wire 22.

  A wiring support base 31 processed into a predetermined shape is disposed above the wiring 12 on which the semiconductor element 20a is mounted. Further, a conductive metal film 41 is patterned on the lower surface of the wiring support base 31.

  Here, the conductive metal film 41 is disposed parallel to the main surface of the support substrate 10, and one end thereof is bonded to the electrode pad 20 ap disposed on the upper surface of the semiconductor element 20 a via the solder layer 13. Yes.

  Further, at the other end of the conductive metal film 41, for example, a columnar electrode 40s made of copper is formed so as to face the main surface side of the support substrate 10 from the other end. . Such a columnar electrode 40s is formed by plating, for example. The other end is joined to the wiring 12 arranged at the center of the support substrate 10 via the columnar electrode 40s.

  By the way, the height of the columnar electrode 40s is adjusted to a predetermined height, for example, about the thickness of the semiconductor element 20a. Thereby, the step between the electrode pad 20ap disposed on the upper surface of the semiconductor element 20a and the wiring 12 is corrected, and the conductive metal film 41 can be disposed horizontally.

  As described above, in the semiconductor element 20a, the electrode pad 20ap and the wiring 12 disposed on the upper surface of the semiconductor element 20a are electrically connected via the conductive metal film 41 due to the arrangement of the conductive metal film 41. It is connected.

In addition, a solder layer 13 is applied as an adhesive member that ensures the electrical connection.
<Modification 4 of Fifth Embodiment>
FIG. 21 is a schematic cross-sectional view of an essential part of a semiconductor device according to a modification of the fifth embodiment. In FIG. 21, the resin 60 and the input / output terminal 50 are not particularly shown, and an enlarged view of the characteristic form of the semiconductor device 5e is shown.

In the semiconductor device 5e according to the modified example, the support substrate 10 is used as a base, and the heat radiating plate 10h is fixed below the support substrate 10.
A plurality of wirings 12 are selectively disposed on the main surface (upper surface side) of the support substrate 10.

Further, in the semiconductor device 5e, the semiconductor element 20a is mounted on the wiring 12 arranged on the left side of the support substrate 10 shown in this figure via the solder layer 11.
Further, the semiconductor element 21 is mounted on the main surface (upper surface side) of the support substrate 10 where the wiring 12 is not disposed via an adhesive member (not shown). Further, in the semiconductor element 21, the electrode pad 21 p and the wiring 12 are electrically connected by a bonding wire 22.

  A wiring support base 31 processed into a predetermined shape is disposed above the wiring 12 on which the semiconductor element 20a is mounted. Further, a conductive metal film 42 is patterned on the upper surface of the wiring support base 31.

  Here, the conductive metal film 42 is disposed in parallel with the main surface of the support substrate 10. A via 42v penetrating the wiring support base 31 is formed at one end thereof. The via 42v is electrically connected to the conductive metal film 42. Further, the via 42 v is electrically connected to the electrode pad 42 p disposed on the lower surface of the support substrate 10. The electrode pad 42p is bonded to the electrode pad 20ap disposed on the upper surface of the semiconductor element 20a via the solder layer 13.

  Further, at the other end of the conductive metal film 42, a via 42v penetrating the wiring support base 31 is formed. The via 42v is electrically connected to the conductive metal film 42. Further, the via 42 v is electrically connected to the electrode pad 42 p disposed on the lower surface of the support substrate 10. And from the said electrode pad 42p, the columnar electrode 40s comprised with copper is formed so that the main surface side of the support substrate 10 may be opposed. Such a columnar electrode 40s is formed by plating, for example. The other end is joined to the wiring 12 arranged at the center of the support substrate 10 via the columnar electrode 40s.

  By the way, the height of the columnar electrode 40s is adjusted to a predetermined height, for example, about the thickness of the semiconductor element 20a. Thereby, the step between the electrode pad 20ap disposed on the upper surface of the semiconductor element 20a and the wiring 12 is corrected, and the conductive metal film 42 can be disposed horizontally.

  As described above, in the semiconductor element 20a, the electrode pad 20ap and the wiring 12 disposed on the upper surface of the semiconductor element 20a are electrically connected via the conductive metal film 41 due to the arrangement of the conductive metal film 41. It is connected.

In addition, a solder layer 13 is applied as an adhesive member that ensures the electrical connection.
In the semiconductor devices 5a to 5e according to the fifth embodiment, the configurations shown in FIGS. 5, 6, and 8 described in the first embodiment may be diverted.

In addition, the first to fifth embodiments described above are not independent embodiments, but may be configured by combining one embodiment with another embodiment.
<Sixth Embodiment>
Finally, a method for manufacturing the semiconductor devices 1a to 1d, 2, 3a, 3b, 4, 5a to 5e will be described with reference to FIGS. Here, as a description of the manufacturing method, the manufacturing method of the semiconductor device 1a will be described as a representative. However, the manufacturing method described here is not limited to the manufacturing method of the semiconductor device 1a, but can be diverted to the manufacture of other semiconductor devices 1b to 1d, 2, 3a, 3b, 4, 5a to 5e.

FIG. 22 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device.
First, the support substrate 10 described above is prepared. At this stage, the wiring 12 has already been selectively disposed on the main surface of the support substrate 10. In addition, at least one cavity 10a is formed on the main surface of the support substrate 10 on which the wiring 12 is not disposed, if necessary.

  In addition, the support substrate 10 prepared at this stage is in a state where the ends of the support substrate 10 on the side where the electrode terminals 12a are not disposed are continuous with each other, thus forming a two-stage structure. Furthermore, the said continuous support substrate 10 exists in the state continued in the horizontal direction in parallel.

  Here, the length which continues in a horizontal direction does not specifically limit the number. Accordingly, the support substrate 10 is arranged in N rows and is continuous in the lateral direction. However, the number of continuous support substrates 10 may be adjusted according to the mold capacity of a transfer mold apparatus described later.

FIG. 23 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device.
Next, a paste-like solder material made of lead-free solder is placed in the cavity 10a by a dispensing method (not shown). Alternatively, a sheet-like solder material may be disposed in the cavity 10a instead of the paste-like solder material.

  Subsequently, the semiconductor elements 20a, 20b, and 21 are placed on the solder material. Further, a paste-like solder material is disposed by a dispensing method (not shown) on the joint portion of the wiring 12 and the electrode pads 20ap, 20bp, 21p of the semiconductor elements 20a, 20b, 21.

  Alternatively, a solder material may be disposed in the cavity 10a, and the semiconductor elements 20a, 20b, and 21 may be bonded to the support substrate 10 by performing a reflow process immediately after placing the semiconductor elements 20a, 20b, and 21. In this embodiment, the reflow process at this stage is not performed.

  Further, if necessary, before placing the semiconductor elements 20a, 20b, 21 on the solder material, the solder material is arranged on the electrode pads 20ap, 20bp, 21p of the semiconductor elements 20a, 20b, 21 in advance. May be.

FIG. 24 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device.
Next, the wiring support base material 30 in which a plurality of conductive patterns 40 are selectively disposed is placed on the wiring 12 and the semiconductor elements 20a, 20b, and 21 via the solder material. Here, the wiring support base material 30 is placed in the direction in which the conductive pattern 40 is exposed on the wiring support base material 30. Further, the wiring support base material 30 at this stage is in a continuous state so as to correspond to the support substrate 10 continuous in the lateral direction. At this stage, the end of the conductive pattern 40 comes into contact with the wiring 12 and the electrodes of the semiconductor elements 20a, 20b, and 21 via the solder material.

In addition, in the wiring support base material 30, you may mount the wiring support base material 30 separated into pieces instead of a continuous body at this stage.
Further, when the semiconductor device according to the third and fourth embodiments is manufactured, the semiconductor element is already formed on the wiring support base materials 30 and 31 before the wiring support base materials 30 and 31 are placed. 21 is mounted on the conductive patterns 40 and 42 (described above). Therefore, when manufacturing the semiconductor device according to the third and fourth embodiments, it is not necessary to place the semiconductor element 21 on the support substrate 10 at the stage shown in FIG.

  When manufacturing the semiconductor device according to the fifth embodiment, vias 30v and 42v and electrode pads 42p are already formed in the wiring support base 30 before the wiring support base 30 is placed. Is formed. In the case where the semiconductor device according to the fifth embodiment is manufactured, the columnar electrodes 40 s are formed on the conductive pattern 40 before the wiring support base 30 is placed.

  Then, in the heating furnace, for example, a reflow process is performed at 260 ° C. for 10 seconds to melt and permeate the solder material. By this processing, the semiconductor elements 20 a and 20 b and the semiconductor element 21 or any one of the semiconductor elements 20 a, 20 b and 21 and the wiring 12 are electrically connected through the conductive pattern 40.

  That is, instead of bonding bonding wires one by one as in wire bonding, any of the semiconductor elements 20a, 20b and the semiconductor element 21 or the semiconductor elements 20a, 20b, 21 is collectively performed by a reflow process. The heel wiring 12 is electrically connected through the conductive pattern 40.

FIG. 25 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device.
Next, after the above electrical connection is completed, the input / output terminal 50 is electrically connected to the electrode terminal 12 a disposed at the end of the main surface of the support substrate 10. That is, after the clip portion 50a of the input / output terminal 50 is fitted to the end portion, the input / output terminal 50 is electrically connected to the electrode terminal 12a by reflow processing.

FIG. 26 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device.
Subsequently, after the input / output terminals 50 are electrically connected, the wiring 12, the semiconductor elements 20a, 20b and 21, the wiring support base 30 and the conductive pattern 40 arranged on the support substrate 10 using a transfer mold apparatus. Are sealed with a resin 60.

  And after sealing with the said resin 60, the support substrate 10, the wiring support base material 30, and the resin 60 are cut | disconnected along the dicing line DL, and are separated into pieces. As a result, an individualized multichip module (semiconductor device 1a) is formed as shown in FIG.

Thus, according to the sixth embodiment, the productivity of a semiconductor device that is a multi-chip power device can be significantly improved.
For example, in the conventional wire bonding method using aluminum wiring, it takes about 1 second to bond one aluminum wiring. Therefore, it takes about 20 seconds to complete the wire bonding in one multichip module on which about 20 bonding wires are mounted.

Thus, when M multichip modules are manufactured, a time of about 20 × M seconds is spent for wire bonding.
However, according to the present embodiment, wire bonding of all M multichip modules can be completed in 10 seconds of reflow processing.

  Therefore, according to the present embodiment, the time required for conventional wire bonding can be reduced to about 10 × 20 × M. In particular, since the time can be shortened to 10 / (20 × M), the larger M, the more remarkable the effect.

  In the semiconductor devices shown in the first to fifth embodiments, the wiring support base materials 30 and 31 in which the conductive pattern 40 or the conductive metal films 41 and 42 are selectively arranged are incorporated in the semiconductor device. . Thereby, the semiconductor device can be reduced in thickness and size.

  Further, the combination of the semiconductor elements (first semiconductor elements) 20a and 20b and the semiconductor element (second semiconductor element) 21 is not limited to the power semiconductor element and the control IC chip described above.

  For example, the first semiconductor element may be a semiconductor memory, and the second semiconductor element may be a CPU (Central Processing Unit), a DSP (Digital Signal Processor), or a semiconductor memory. Good. Further, both the first semiconductor element and the second semiconductor element may be analog IC chips.

1 is a main part view of a semiconductor device according to a first embodiment; It is a principal part cross-sectional schematic diagram of the semiconductor device which concerns on 1st Embodiment. It is a principal part figure of the electroconductive pattern selectively arrange | positioned on a wiring support base material (the 1). It is a principal part figure of the electroconductive pattern selectively arrange | positioned on the wiring support base material (the 2). It is a figure for demonstrating the structure of an input-output terminal. It is a principal part figure for demonstrating the semiconductor device which has arrange | positioned the insulating film. It is a principal part figure for demonstrating the semiconductor device which has a ground layer. It is a principal part figure for demonstrating the semiconductor device using the insulating film covering metal wiring board. It is a principal part cross-sectional schematic diagram of the semiconductor device which concerns on 2nd Embodiment. It is a principal part figure of the electroconductive metal film selectively arrange | positioned on a wiring support base material (the 3). It is a principal part figure of the semiconductor device which concerns on 3rd Embodiment. It is a principal part cross-sectional schematic diagram of the semiconductor device which concerns on 3rd Embodiment. It is a principal part figure of the semiconductor device which concerns on the modification of 3rd Embodiment. It is a principal part cross-sectional schematic diagram of the semiconductor device which concerns on the modification of 3rd Embodiment. It is a principal part cross-sectional view of the semiconductor device which concerns on 4th Embodiment. It is a principal part figure of the electroconductive metal film selectively arrange | positioned on a wiring support base material (the 4). It is a principal part cross-sectional schematic diagram of the semiconductor device which concerns on 5th Embodiment. It is a principal part cross-sectional schematic diagram of the semiconductor device which concerns on the modification of 5th Embodiment (the 1). FIG. 22 is a schematic cross-sectional view of a relevant part of a semiconductor device according to a modification of the fifth embodiment (No. 2). FIG. 10 is a schematic cross-sectional view of a relevant part of a semiconductor device according to a modification of the fifth embodiment (No. 3). FIG. 10 is a schematic cross-sectional view of a relevant part of a semiconductor device according to a modification of the fifth embodiment (No. 4). FIG. 6 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device (part 1); FIG. 7 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device (part 2); FIG. 9 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device (part 3); FIG. 10 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device (part 4); FIG. 10 is a main part diagram for explaining one process of the manufacturing process of the semiconductor device (part 5);

Explanation of symbols

1a, 1b, 1c, 1d, 2, 3a, 3b, 4, 5a, 5b, 5c, 5d, 5e Semiconductor device 10 Support substrate 10a Cavity 10h Heat sink 11, 13, 51 Solder layer 12 Wiring 12a Electrode terminal 12g, 40g Plating layer 12p, 20ap, 20bp, 21p, 42p Electrode pad 14a, 14b Conductor pad 15a, 15b, 15c Ground layer 20a, 20b, 21 Semiconductor element 22 Bonding wire 30, 31 Wiring support base material 30a Through hole 30v, 42v Via 40 Conductive pattern 40a Extension part 40s Columnar electrode 41, 41mos, 41ic, 42, 42mos, 42ic Conductive metal film 50 Input / output terminal 50a Clip part 60 Resin 61 Insulating film 70 Core substrate 71 Resin layer 72 Insulating film 73 Insulating film coating Metal wiring board DL dicing Inn

Claims (39)

A printed wiring board, a ceramic wiring board, a silicon wiring board, or an insulating film-covered metal wiring board, and a support substrate having a plurality of cavities formed on the main surface ;
A plurality of first wires which are selectively arranged on the main surface of said supporting substrate,
At least one first semiconductor element mounted in the cavity formed in the support substrate;
At least one second semiconductor element mounted in the cavity formed in the support substrate and controlling the first semiconductor element;
A wiring support base disposed on the first wiring of the main surface of the support substrate, and a plurality of second wirings selectively disposed on the main surface opposite to the first wiring ;
And the first semiconductor element and the second semiconductor element, or the first semiconductor element or the second semiconductor element and the first wiring are at least one second wiring. A semiconductor device characterized by being electrically connected through a solder layer .   The plurality of conductor pads are selectively disposed in the support substrate, and the first semiconductor element or the second semiconductor element is mounted on the conductor pads. Semiconductor device.   3. The semiconductor device according to claim 2, wherein a main surface of the conductor pad is a bottom surface of the cavity formed on the support substrate.   The semiconductor device according to claim 2, wherein a distance between adjacent conductor pads is 0.2 to 3 mm.   The semiconductor device according to claim 1, wherein a plurality of ground layers are selectively disposed in the support substrate.   The cavity mounted so that the height of the first wiring and the electrode pad disposed in the main surface of the first semiconductor element or the second semiconductor element mounted in the cavity is the same height. 2. The semiconductor device according to claim 1, wherein the depth of the semiconductor device is adjusted.   2. An insulating film is formed on a main surface of the support substrate located between the adjacent first wirings and on a part of the main surface of the adjacent first wirings. The semiconductor device described.   The wiring support base material is a resin containing at least one of polyimide resin (PI), liquid crystal polymer resin (LCP), epoxy resin (EP), polyethylene terephthalate resin (PET), and polyphenylene ether resin (PPE). The semiconductor device according to claim 1.   The second wiring is a conductive pattern formed on a main surface of the wiring support base, and the first semiconductor element and the second semiconductor element, or the first semiconductor element are formed through the conductive pattern. The semiconductor device according to claim 1, wherein the semiconductor element or the second semiconductor element and the first wiring are electrically connected.   The semiconductor device according to claim 9, wherein an end of the conductive pattern extends from a main surface of the wiring support base.   A plating layer made of nickel (Ni) and gold (Au) or nickel (Ni) and tin (Sn) is formed on the surface of the conductive pattern extending from the main surface of the wiring support base. The semiconductor device according to claim 10.   The semiconductor device according to claim 9, wherein the second semiconductor element is mounted on the conductive pattern, and an electrode of the second semiconductor element is bonded to the conductive pattern.   The second semiconductor element is mounted on the wiring support base, and the electrode of the second semiconductor element and the conductive pattern are electrically connected by a bonding wire. Item 10. A semiconductor device according to Item 9.   One end of the conductive pattern is electrically connected to the electrode of the first semiconductor element mounted on the first wiring, and the other end of the conductive pattern penetrates the wiring support base. The semiconductor device according to claim 9, wherein the semiconductor device is electrically connected to an electrode pad formed on another first wiring through a via.   The semiconductor device according to claim 14, wherein the conductive pattern and the main surface of the support substrate are in a parallel state by adjusting the thickness of the wiring support base.   One end of the conductive pattern is electrically connected to the electrode of the first semiconductor element mounted on the first wiring, and the other end of the conductive pattern is formed at the other end. The semiconductor device according to claim 9, wherein the semiconductor device is electrically connected to an electrode pad formed on another first wiring through a columnar electrode.   One end of the conductive pattern is electrically connected to the electrode of the first semiconductor element mounted on the first wiring, and the other end of the conductive pattern is formed at the other end. The semiconductor device according to claim 9, wherein the semiconductor device is electrically connected to another first wiring through a columnar electrode.   18. The semiconductor device according to claim 16, wherein the conductive pattern and a main surface of the support substrate are in a parallel state by adjusting a height of the columnar electrode.   The second wiring is a metal film that is selectively disposed on a main surface of the wiring support base, and the first semiconductor element and the second semiconductor element or the first semiconductor element through the metal film. The semiconductor device according to claim 1, wherein the semiconductor element or the second semiconductor element and the first wiring are electrically connected.   The second wiring is a metal film selectively disposed on the upper surface of the wiring support base, and the metal film is selected on the lower surface of the wiring support base through a via penetrating the wiring support base. The first semiconductor element and the second semiconductor element, or the first semiconductor element or the second semiconductor element are electrically connected to the electrode pad disposed in a row and through the metal film, the via, and the electrode pad. 20. The semiconductor device according to claim 19, wherein a semiconductor element and the first wiring are electrically connected.   One end of the metal film is electrically connected to the electrode of the first semiconductor element mounted on the first wiring, and the other end of the metal film is a columnar electrode formed on the other end. The semiconductor device according to claim 19, wherein the semiconductor device is electrically connected to another first wiring.   The metal film is selectively disposed on the upper surface of the wiring support base, and one end of the metal film is mounted on the first wiring through the via and the electrode pad. It is electrically connected to an electrode, and the other end of the metal film is electrically connected to another first wiring through the via, the electrode pad and the columnar electrode formed at the other end. The semiconductor device according to claim 19.   23. The semiconductor device according to claim 21, wherein the metal film and a main surface of the support substrate are in a parallel state by adjusting a height of the columnar electrode.   The material of the metal film is a metal containing at least one of copper (Cu), silver (Ag), gold (Au), and aluminum (Al). The semiconductor device described.   The metal film is
  A method of forming a metal film having the same component as that of the metal film on the wiring support substrate by laminating and then etching the metal film,
  A method of forming a conductive paste of the same component as that of the metal film on the wiring support base material by selectively arranging the conductive paste by screen printing, and then drying and curing the conductive paste.
  A method of forming the metal film having the same component as the metal film by sputtering or vapor deposition on the wiring support substrate, and then etching the metal film,
  A method of forming a plating layer having the same component as the metal film on the wiring support base material, and then etching the plating layer.
  A method of modifying the surface of the wiring support substrate by a chemical or optical method and forming it by a selective chemical plating method;
  24. The semiconductor device according to claim 19, wherein the semiconductor device is formed by any one of the methods.   24. The semiconductor device according to claim 19, wherein a thickness of the metal film bonded to the electrode of the first semiconductor element is 25 to 500 [mu] m.   24. The semiconductor device according to claim 19, wherein a thickness of the metal film bonded to the electrode of the second semiconductor element is 3 to 500 [mu] m.   A plurality of electrode terminals that are electrically connected to the first wiring are extended to end portions of the main surface of the support substrate, and input / output terminals are electrically connected to the respective electrode terminals. The semiconductor device according to claim 1.   29. The semiconductor device according to claim 28, wherein a clip portion is provided at an end of the input / output terminal, and the end portion is sandwiched by the clip portion.   30. The semiconductor device according to claim 29, wherein the clip terminal and the metal wiring disposed on the main surface opposite to the end where the electrode terminal and the electrode terminal are disposed are solder-bonded. .   31. A plating layer made of nickel (Ni) and gold (Au) or nickel (Ni) and tin (Sn) is formed on the surface of the electrode terminal and the metal wiring. The semiconductor device described.   Preparing a support substrate in which a plurality of cavities are formed on a main surface, and a plurality of first wirings are selectively disposed on the main surface;
  Mounting at least one first semiconductor element and at least one second semiconductor element for controlling the first semiconductor element in the cavity formed in the support substrate;
  Disposing a solder material on a part of the first wiring, the electrode of the first semiconductor element, and the electrode of the second semiconductor element;
  On the opposite side of the main surface of the wiring support substrate on which the plurality of second wirings are selectively disposed on the main surface, the first wiring, the first semiconductor element, and the second semiconductor element are placed on the opposite side of the main surface. In addition, the step of placing via the solder material,
  The solder material is melted by a reflow process, and the first semiconductor element and the second semiconductor element, or the first semiconductor element or the second semiconductor element and the first wiring, Electrically connecting through the second wiring;
  A method for manufacturing a semiconductor device, comprising:   After completing the electrical connection, the input / output terminal is electrically connected to the electrode terminal extending to the end portion of the main surface of the support substrate and conducting to the first wiring. 33. A method of manufacturing a semiconductor device according to claim 32.   After electrically connecting the input / output terminals, the first wiring, the first semiconductor element, the second semiconductor element, the second wiring, and the wiring support base disposed on the support substrate 34. The method of manufacturing a semiconductor device according to claim 33, wherein the material is sealed with a resin.   35. The method of manufacturing a semiconductor device according to claim 34, wherein after sealing with the resin, the support substrate, the wiring support base material, and the resin are separated into individual pieces to form a multichip module.   36. The method of manufacturing a semiconductor device according to claim 35, wherein the supporting substrate is in a continuous state before sealing with the resin.   The end portions of the support substrate on the side where the electrode terminals are not disposed are in a continuous state, and the continuous support substrates are further continued in parallel. Semiconductor device manufacturing method.   Preparing a support substrate in which a plurality of cavities are formed on a main surface, and a plurality of first wirings are selectively disposed on the main surface;
  Mounting at least one first semiconductor element in the cavity formed in the support substrate;
  Disposing a solder material on a part of the first wiring and the electrode of the first semiconductor element;
  The main surface of the wiring support substrate on which a plurality of second wirings are selectively disposed on the main surface, and further, the second semiconductor element electrically connected to the second wiring is mounted on the main surface And placing the opposite side on the first wiring and the first semiconductor element via the solder material;
  The solder material is melted by reflow treatment, and the first semiconductor element and the second semiconductor element, or the first semiconductor element and the first wiring are electrically connected through the second wiring. Connecting to
  A method for manufacturing a semiconductor device, comprising:   Preparing a support substrate in which a plurality of cavities are formed on a main surface, and a plurality of first wirings are selectively disposed on the main surface;
  Mounting at least one first semiconductor element and at least one second semiconductor element for controlling the first semiconductor element in the cavity formed in the support substrate;
  Disposing a solder material on a part of the first wiring and the electrode of the first semiconductor element;
  A plurality of second wirings are selectively disposed on the main surface, and are further opposite to the main surface of the wiring support base member provided with columnar electrodes or vias which are electrically connected to the second wirings, or the vias and electrode pads. Placing the side on the first wiring and the first semiconductor element via the solder material;
  A step of melting the solder material by a reflow process and electrically connecting the first semiconductor element and the first wiring through the second wiring;
  A method for manufacturing a semiconductor device, comprising:

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