JP5229993B2 - 1-chip electronic musical tone generator - Google Patents

Description

  The present invention relates to a one-chip electronic musical tone generator.

In a conventional electronic sound generator, a control means such as a CPU used for a sound source accesses a storage device storing a sound source control program in a predetermined time slot and reads a necessary program. (See Patent Document 1 below).
Japanese Patent Laid-Open No. 02-179699

  However, in the configuration of the above prior art, the use of the time slot by the control means such as the CPU squeezes the time slot to be used by the tone generation means such as the tone generator, resulting in a problem that the number of simultaneous sounds is reduced. It was.

  The present invention has been devised in view of the above problems, and interrupts reading of musical sound waveform data by the musical sound generating means so that a control means such as a CPU can access the storage means while It is an object of the present invention to provide a one-chip electronic musical tone generator that does not affect the generation of a plurality of musical tones performed by division.

The configuration of the one-chip electronic musical tone generator according to the present invention is as follows:
According to the parameter generated based on the program for generating the musical sound, which is read out from the first storage means storing the musical sound waveform data for generating the musical sound, and stored in the second storage means. A musical sound generating means for processing musical sound waveform data to generate a plurality of musical sounds in a time-sharing manner;
The first storage means and the second storage means are accessed in a time-sharing manner via an external bus, and the musical sound waveform data is read out by the musical sound generation means by receiving a cache miss signal. A bus controller that interrupts the reading and sends out the interrupted musical tone waveform data as a missing value;
Control means that operates in accordance with the read program, generates a parameter for generating the musical sound, and supplies the parameter to the musical sound generating means;
Cache means for interposing at least a program interposed between the bus controller and the control means,
When a cache miss hit is detected by the cache means, a cache miss signal is transmitted to the bus controller when a cache miss hit is detected, and when the musical tone waveform data reading by the bus controller is interrupted, the control is performed. Memory management means for permitting access to the second storage means by the means and storing the simultaneously read program in the cache means;
If the bus controller by the musical tone waveform data read is interrupted, the value of the musical tone waveform data read out after the interruption occurs before and generating, possess an interpolation means for repairing interpolating between the missing values,
The interpolation means is basically characterized in that the repair interpolation process is performed using check data added for each fixed amount of read musical sound waveform data .

According to the above configuration, when the memory management means detects a cache miss hit of the cache means, the bus controller interrupts reading of the musical sound waveform data by the musical sound generating means, and the second storage by the control means. Access to the means is permitted and the program read at the same time is stored in the cache means. Further, the musical tone waveform data whose reading has been interrupted is sent to the interpolation means as a missing value by the bus controller. On the other hand, when the reading of the musical sound waveform data is interrupted, the interpolation means restores and interpolates between the missing values by the value of the musical sound waveform data read before and after the interruption. .

That is, when a cache miss in the cache means, by interrupting the reading of the musical tone waveform data, the reading of the program is given priority by the control means, loss of tone waveform data generated at the time of the interruption, Ri by the said interpolation means The read tone waveform data is supplemented by the repair interpolation process using the check data added every fixed amount to be read . Therefore, the reading of the musical sound waveform data by the musical sound generating means is interrupted by the bus controller so that the control means such as the CPU can access the storage means, while the generation of a plurality of musical sounds performed in a time division manner is affected. It becomes possible not to be.

Repair interpolation processing by the interpolation means, when performed using the inserts stored check data to the first storage means every predetermined amount of the musical tone waveform data are read out, immediately that the interruption has been made As well, it is possible to correct and simplify the repair interpolation process. As such check data, parity data as will be described later and other authenticity check data capable of checking its correctness are suitable.

According to the above-described one-chip electronic musical tone generator of the present invention, at the time of a cache miss, reading of musical tone waveform data by the musical tone generating means is interrupted by the bus controller so that a control means such as a CPU can access the storage means. On the other hand, the musical sound waveform data lost due to the interruption is supplemented by the repair interpolation process using the check data added for each read amount of the musical sound waveform data to be read, and thus is performed in a time-sharing manner. It is possible to achieve an excellent effect that it is possible to prevent the generation of a plurality of musical sounds.

  Hereinafter, embodiments of the present invention will be described together with the following illustrated examples.

  FIG. 1 is a circuit diagram showing a configuration of an electronic sound generator including a one-chip electronic musical tone generator and peripheral circuits according to an embodiment of the present invention.

  As shown in the figure, the electronic sound generator of the present invention is composed of a one-chip LSI with a built-in cached core CPU. An interface I / F to the device is connected.

  That is, the one-chip electronic musical tone generator of this embodiment indicated by LSI-CHIP is connected to the CPU, tone generator (TG), memory managing unit (MMU), and data cache (C1) via the internal bus 100. ing.

  The program cache (C0) has two inputs / outputs, ie, dual connection, to the memory managing unit (MMU), and one input / output is connected to the internal bus by the memory managing unit (MMU). The other input / output is connected to an external storage device such as a ROM or a RAM via a bus controller (BC) and an external bus 200. Therefore, the program cache (C0) is configured to cache a program for generating musical sounds between the CPU and these external storage devices.

  The CPU is composed of a microcomputer core in the LSI-CHIP, creates parameters for generating musical sounds in accordance with a program for generating musical sounds, and supplies them to a tone generator (TG). As will be described later, reading of musical sound waveform data is interrupted due to a cache miss, and the CPU goes to the ROM or RAM external storage device via the bus controller (BC) and external bus 200 to read the program. Then, the tone generator (TG), which will be described later, is instructed to interpolate the missing portion of the musical sound waveform data.

  On the other hand, the tone generator (TG) has a sound source configuration for generating 16 sound tone waveform data in a time-division manner with a sample time of 1/50000 sec, for example, a decoder buffer (D / B), the bus controller (BC), an external Similarly, it is connected to an external storage device such as a ROM or a RAM via a bus 200. Here, the musical sound waveform data stored in these external storage devices are read out, and a musical sound is generated based on the parameters supplied from the CPU and output to the outside. The parameter register of the tone generator (TG) is connected to the CPU via the internal bus 100. Therefore, the register is accessed as RAM from the CPU. Further, the tone generator (TG) constitutes an interpolation unit 15 which will be described later, and when the reading of musical sound waveform data is interrupted, the tone data is checked based on the instruction of the CPU and the musical sound waveform data. Perform the necessary interpolation processing.

  The decoder buffer (D / B) is interposed between the external storage device and the tone generator (TG), and reads out, for example, 8 words of musical sound waveform data per channel from the external storage device for buffering. In addition, when the waveform data is compressed like ADPCM, the data processing to the normal PCM is performed, read and expanded one by one, the interpolation processing is performed, and the PCM format To be decoded. That is, interpolation processing (different from the interpolation processing performed by the tone generator) is performed on the read musical sound waveform data. The tone waveform data interpolated by the decoder buffer (D / B) in accordance with the waveform reading of the tone generator (TG) is sent to the tone generator (TG). At that time, the ACC signal output from the tone generator (TG) is not generated by the channel of the tone generator (TG) [the amplitude envelope (EG-2) 1112 or the volume Loudness (LD) 1114 in FIG. Zero]. The REQ signal output from the decoder / buffer (D / B) to the bus controller (BC) indicates that the decoder / buffer (D / B) is requesting buffer data replacement.

  On the other hand, the memory managing unit (MMU) is configured to switch the bus accessed by the CPU between the internal bus 100 and the external bus 200, and when switched to the internal bus 100, the CPU accesses the program cache (C0). In addition, when switching to the external bus 200, the CPU accesses the external storage device via the external bus 200. At this time, the program for generating musical sounds read from the external storage device via the memory managing unit (MMU) is also stored in the program cache (C0).

  The CTR signal issued from the memory managing unit (MMU) to the bus controller (BC) is a signal indicating that the CPU has made a cache miss (cache miss signal defined in the present invention), and The W0 signal output from the memory managing unit (MMU) to the CPU is output when the external bus 200 is in use by the decoder buffer (D / B) via the bus controller (BC) described later [the bus controller ( When a WAIT signal is issued from BC) to the memory managing unit (MMU)], a signal is applied to wait for the CPU accessing the external storage device via the external bus 200.

  Further, the bus controller (BC) has a switching control configuration for switching the connection to the external bus 200 to any one of a program cache (C0), a memory managing unit (MMU), and a decoder buffer (D / B).

  The WAIT signal issued from the bus controller (BC) to the memory managing unit (MMU) is a signal indicating that the external bus 200 is being used by the decoder buffer (D / B). The W0 signal is output from the memory managing unit (MMU) to the CPU, and a wait is applied to the CPU for accessing the external storage device via the external bus 200.

  The ROM is an external storage device that stores a program for CPU and musical tone waveform data for tone generator (TG).

  The RAM is an external storage device that temporarily stores a CPU program and data such as parameters and flags.

  The interface (I / F) is an interface for the CPU to access the keyboard or panel of the electronic musical instrument.

  As shown in FIG. 2, the configuration of the present invention is configured by the following functional blocks configured by the respective units in the previous diagram. That is, in the configuration of this embodiment, the musical sound waveform data is read from the first storage unit 210 in which the musical sound waveform data for generating a musical sound is stored, and the musical sound stored in the second storage unit 211 is generated. The musical sound generator 10 for processing the musical sound waveform data to generate a plurality of musical sounds in a time-sharing manner according to the parameters generated based on the program, and the first storage unit 210 and the second storage unit 211. On the other hand, these storage units are accessed in time division via the external bus 200, and upon receipt of a cache miss signal (CTR signal in the figure), reading of the musical tone waveform data by the musical tone generator 10 is interrupted, And the bus controller 11 that sends out the musical sound waveform data that has been interrupted as a missing value, and operates according to the read program, A control unit 12 that creates and supplies parameters to the musical sound generation unit 10, a cache unit 13 that interposes between the bus controller 11 and the control unit 12, and caches at least a program; When a cache miss hit is detected in the cache unit 13 and a cache miss hit is detected, a cache miss hit signal (same CTR signal) is transmitted to the bus controller 11 and musical tone waveform data reading by the bus controller 11 is interrupted. When this is done, the control unit 12 allows the control unit 12 to access the second storage unit 211 and stores the simultaneously read program in the cache unit 13. When waveform data reading is interrupted, before and after the interruption The musical tone waveform data values to be read has a configuration of an interpolation section 15 for interpolating between the missing values.

  The first storage unit 210 is composed of the ROM for storing musical sound waveform data, and the second storage unit 211 is composed of the ROM and RAM for storing a program for the CPU.

  The tone generator 10 is composed of a tone generator (TG), and the interpolator 15 is also composed of a tone generator (TG).

  The bus controller 11 includes the bus controller (BC). The decoder buffer 16 is interposed between the bus controller 11 and the tone generator 10 and the interpolator 15, and is composed of the decoder buffer (D / B).

  The control unit 12 is composed of a CPU, and the cache unit 13 is composed of the program cache (C0).

  The memory management unit 14 includes a memory managing unit (MMU).

  The musical tone generator 10, the controller 12, and the memory manager 14 are connected via the internal bus 100 and can exchange data and the like.

  In the figure, reference numeral 17 denotes a data cache unit corresponding to (C1) in FIG.

  In the electronic sound generation apparatus, when key depression data or the like is received from the interface (I / F) side, the memory management unit 14 sends the control unit 12 from the second storage unit 211 to the CPU. Program is read. At that time, a part (preferably frequently used) or all of the program is page-loaded and stored in the cache unit 13 by the memory management unit 14.

  On the other hand, musical tone waveform data is read from the first storage unit 210 by the bus controller 11 via the external bus 200 with respect to the musical sound generating unit 10. In the middle, the musical tone waveform data read out to the decoder buffer 16 is temporarily stored, decoded, processed in a time-division manner, and supplied to the musical tone generator 10 for each of the sequences that are simultaneously sounded. .

  Further, a parameter for generating a musical tone is created by the control unit 12 in which the CPU program is executed and supplied to the musical tone generating unit 10 via the internal bus 100.

  The musical tone generator 10 further processes the read musical tone waveform data according to the generated and supplied parameters to generate a plurality of musical tones in a time-division manner and generate musical tones outside.

  In the meantime, when the same program read once and stored in the cache unit 13 is read by the control unit 12, that is, when the cache is hit, the memory management unit 14 causes the internal bus 100 to The address specified by the control unit 12 connected to the unit 13 is automatically replaced with the address of the cache unit 13 by the memory management unit 14, and the program is read from the cache unit 13. At this time, the memory management unit 14 turns off the control signal CTR (cache hit state).

  On the other hand, the bus controller 11 gives priority to the access right to the decoder buffer 16 that is a temporary storage unit of musical sound waveform data read by the musical sound generator 10. If the TG channel of the current time slot in the tone generator 10 is sounding (see FIG. 3 to be described later) and the decoder buffer 16 needs to be updated, REQ = ON is sent. 200 is connected to the decoder buffer 16.

  FIG. 3 shows a time chart of each signal, bus, and TG channel (simultaneous sound generation channel of the tone generator 10) when the cache is hit as described above.

  As shown in the figure, in this apparatus, the sampling time is set to 20 μsec, and the time division channel time is set to 1.25 μsec during that time, and the time-division sound generation channel (TG channel) having the same number of pronunciations 16 within one sampling time. All of these channels are processed in a time-sharing manner, and 16 sounds are simultaneously generated (indicated by 0x0 to 0xF in the figure).

  At this time, the WAIT signal from the bus controller 11 to the memory management unit 14 (the WO signal from the memory management unit 14 to the control unit 12) and the CTR signal from the memory management unit 14 to the bus controller 11 are in an OFF state. Since the REQ signal from the decoder / buffer 16 to the bus controller 11 always reads out plural series of musical sound waveform data, the ON state as shown in the figure is repeated.

  Further, the memory management unit 14 reads the program of the cache unit 13 onto the internal bus 100 (indicated by C0 in the figure), that is, the cache is hit.

  On the other hand, the musical tone waveform data is read from the first storage unit 210 to the external bus 200 by the bus controller 11 that has received the REQ signal, and is temporarily stored in the decoder buffer 16 (D / in the figure). B).

  FIG. 4 shows a time chart when the cache is miss-hit, reading of musical sound waveform data is interrupted, and the program is being updated. FIG. 5 is an explanatory diagram showing functional blocks of the configuration of the present invention in the above case.

  When the cache misses, that is, when the address required by the control unit 12 is specified in the memory management unit 14 and the program is read from the cache unit 13, the cache unit 13 corresponds to the address. These figures show a case where there is no address on the cache to be executed and there is no corresponding program in the cache unit 13.

  In such a case, first, the memory management unit 14 sends a CTR signal to the bus controller 11 (as described above, the control signal CTR detected a cache miss by the access from the control unit 12 by the memory management unit 14. In this case, a signal indicating that a cache miss hit is issued from the memory management unit 14 to the bus controller 11 = cache miss signal) is output.

  At this time, the bus controller 11 receives the CTR signal and blocks the reception of the REQ signal from the decoder buffer 16 as shown in FIG. Interrupt. Then, as shown in the figure, the bus controller 11 sends out the musical sound waveform data whose reading has been interrupted to the musical sound generator 10 as a missing value.

  When the musical tone waveform data reading by the bus controller 11 is interrupted, the memory management unit 14 permits the control unit 12 to access the second storage unit 211 as shown in FIGS. 4 and 5. The control unit 12 attempts to access the external bus 200 by connecting the internal bus 100 to the external bus 200 via the memory management unit 14. Thereby, the control unit 12 loads a necessary program from the second storage unit 211.

  At the same time, the memory management unit 14 causes the cache unit 13 to page load the program to be loaded.

  On the other hand, with respect to the function of the bus controller 11 at the above-mentioned timing, the bus controller 11 itself gives priority to the access right to the decoder / buffer 16, but until the CTR signal is received, While outputting WAIT, the external bus 200 is connected to the decoder / buffer 16 side, and during that time, it is used for reading the musical sound waveform data of each channel. Meanwhile, the WAIT is processed by the memory management unit 14 and is not sent to the control unit 12 (as a WO signal).

  Then, at a timing when the cache miss occurs and the CTR signal is turned ON (when the CTR signal is ON in FIG. 4), the external bus 200 is connected to the internal bus 100 via the memory management unit 14 as shown in FIG. The control unit 12 loads a necessary program from the second storage unit 211. At this time, the memory management unit 14 simultaneously loads the loaded program into the cache unit 13.

  In the above example, whether or not there is an empty channel at the time of a cache miss hit, the reading of the musical sound waveform data to the musical sound generator 10 is forcibly interrupted by the bus controller 11 and the reading is interrupted. The musical tone waveform data is sent to the interpolation unit 15 as a missing value.

  As described above, according to the present embodiment, the memory management unit 14 issues a command to the bus controller 11 to force the bus controller 11 to send a command, whether or not there is an empty channel when a cache miss hits. The reading of the musical sound waveform data to the musical sound generating unit 10 is interrupted, the internal bus 100 is connected to the external bus 200, and a necessary program is loaded from the second storage unit 211 to the control unit 12. At the same time, the memory management unit 14 loads the loaded program into the cache unit 13. In addition, the musical sound waveform data that should be lost in the meantime is determined based on the value of the musical sound waveform data read before and after the interruption of the reading of the musical sound waveform data by the interpolation unit 15 that has received the lost value by the bus controller 11. Interpolated between values. As a result, the musical tone waveform data that is read out is not lost, and the number of pronunciations can be increased as long as the access time permits without reducing the number of simultaneous pronunciations.

  FIG. 5 will be described in further detail. The memory management unit 14 accesses the external bus 200 by taking the access right of the decoder buffer 16 continuously for one sample time after a cache miss hit (after the CTR signal is turned ON) [ Rather than accessing the external memory during a time period when the musical sound generating unit 10 does not occupy the external bus 200, at least n (a number equal to the frequency of parity data to be described later periodically appearing in the musical sound waveform data; in this example) 4) Once every sample, the control unit 12 forcibly deprives the musical tone generation unit 10 of access]. After one sample time (1/44100 seconds), the access right is lost and the WAIT signal becomes active. Since the WAIT signal continues to be active for 3 sample times after the WAIT signal becomes active (in the example shown in the figure), the memory management unit 14 cannot access the external bus 200.

  On the other hand, the WAIT signal is active in the initial state. It has a counter for each sample time and remains active for 3 sample times after it becomes active. After that, at the moment when the CTR signal becomes active, the external bus 200 is released to the memory management unit 14 for one sample time. During this time, the decoder buffer 16 misses the musical sound waveform data, but the data missed by the interpolation unit 15 is reproduced as described above.

  As described above, if attention is paid to a certain pronunciation sequence (TG Channel), even if one sample is dropped out of four consecutive samples, the other three samples can always be read out, and one sample removed Is interpolated by the interpolating unit 15, so that the sound generation is not interrupted and the control unit 12 can continue to operate.

  The interpolation processing by the interpolation unit 15 will be described below.

  As shown in FIG. 6, parity data for checking is added to the read sound waveform data for every certain amount to be read. In other words, in the case shown in the figure, the musical sound waveform data is read out in a time-sharing manner in the order of data n + 3, n + 2, n + 1, and n as the (3 + 1) pronunciation sequence. Here, since the parity data appears once in 4 samples, “n = 4” is obtained, and the memory management unit 14 can access the external memory once in 4 samples. If the parity data appears once in 6 samples, the memory management unit 14 sets the external memory once in 6 samples, and if the parity data appears once in 11 samples, the memory management unit 14 sets the external memory once in 11 samples. It will be accessible.

  While the CTR signal is active (cache miss hit), as shown in FIG. 7, the decoder buffer 16 could not read (indicated by xx in the figure), the missing data flag bf is active (= 1) Make the data that became. This data is ignored by the decoder buffer 16, and the interpolation unit 15 generates the ignored data from other samples and parity data by interpolation. That is, taking the data shown in the figure as an example, the interpolation unit 15 obtains the data to be interpolated by = bp-b0-b2, and the missing data (xx) is repaired and interpolated.

  On the other hand, as shown in FIG. 8, when there is no loss in the musical sound waveform data [the missing data flag bf of that data is inactive (= 0)], or when the data in which the loss occurs is parity data [the loss of the data The data flag bf may be inactive 0 or active 1 (indicated by xx in the figure)], since there is no problem with the extracted musical sound waveform data, it is transferred to the decoder buffer 16 as it is, and interpolation processing is performed. I will not.

  FIG. 9 is a diagram illustrating a main flow of the control unit 12 according to the first embodiment.

  As shown in the figure, the control unit 12 initializes the cache unit 13, the decoder buffer 16, the data cache unit 17, the RAM that constitutes a part of the second storage unit 211, and the like (step S100). .

  Then, it is detected whether or not there is an event (step S102). If there is an event (step S102; Y), the process proceeds to step S106.

  On the contrary, if there is no event (step S102; N), the event is processed (step S104).

  In step S106, processing outside the event (processing with the passage of time) is performed.

  FIG. 10 shows a processing flow of initialization processing by the control unit 12 shown in step S100 of FIG.

  In the initialization process, the interval timer interrupt routine TINT (), external interrupt, etc. are prohibited (step S200).

  Next, variables such as a stack pointer are initialized (step S202).

  Further, device settings such as mute all channels of the musical tone generator 10 are made (step S204).

  Then, the cache unit 13 is loaded with the cache zero page (which stores the mute routine of the tone generator 10 for accessing the external bus 200) (step S206).

  Thereafter, the program constant is loaded from the second storage unit 211 to the data cache unit 17 (C1), and the program constant pointer is set in the data cache unit 17 (C1) area (step S208).

  Further, initial values of program variables are set (step S210).

  Finally, the above-described interval timer interrupt routine TINT (), permission settings enabling external interrupts, etc. are made (step S212). This is the end of the initialization process routine.

  FIG. 11 is a flowchart showing the contents of the interval timer interrupt routine TINT (). In the interval timer interrupt routine TINT (), a process of incrementing the timer counter T (incrementing by 1) is performed (step S300). This completes the interval timer interrupt routine TINT ().

  FIG. 12 shows a process flow of the event process (doEvent) performed in step S104 in the main process flow of the control unit 12 of FIG.

  It is checked whether or not the event is a key event (step S400). If the event is a key event (step S400; Y), sound generation / mute processing is performed in response to a key press / release event from a key scanner (not shown) (step S402).

  If the event is not a key event in step S400 (step S400; N), it is checked whether the event is a panel event (step S404). If the event is a panel event (step S404; Y), a tone generation parameter such as a tone color is changed according to a panel event from a panel scanner (not shown) (step S406).

  If the event is not a panel event in step S404 (step S404; N), it is checked whether the event is a MIDI event (step S408). If the event is a MIDI event (step S408; Y), MIDI processing is performed according to a MIDI input received by an external interrupt (not shown) (step S410).

  If the event is not a MIDI event in step S408 (step S408; N), other event processing is performed (step S412).

  Further, FIG. 13 shows a processing flow of processing (doTVar) based on the timer counter T performed in step S106 in the main processing flow of the control unit 12 of FIG.

  First, the timer counter T is referred to and an automatic performance is executed (step S500).

  Then, an analog input such as an expression pedal is read and processing based on the analog input is executed (step S602).

  Next, the timer counter T is referred to, and the modulation LFO stepping process is performed (step S504).

  Subsequently, after releasing the key or pressing the decay sound, processing is performed by searching for a EG-2 level of zero (step S506).

  FIG. 14 is an explanatory diagram showing a detailed configuration of the tone generator 10 of the first embodiment.

  As shown in the figure, the tone generator 10 includes a parameter register (PR) 1100, a wave address generator (WAG) 1102, an interpolator (IP) 1104, a DCF 1106, and a first envelope generator (EG- 1) 1108, DCA 1110, second envelope generator (EG-2) 1112, loudness circuit (LD) 1114, OR circuit (OR) 1116, pan controller 1118, mixer 1120, and effect applying circuit (EFP) 1122. Although not shown, the CPU, like the wave address generator (WAG) 1102, etc., has a first envelope generator (EG-1) 1108, a second envelope generator (EG-2) 1112, and a loudness circuit (LD). 1114, the effect applying circuit (EFP) 1122, and the like may exchange parameters via the parameter register (PR) 1100.

  Among them, the program register (PR) 1100 receives a waveform read start address, loop start address, loop end address, waveform read rate, DCF offset frequency, EG-1 target value, EG-1 rate, It has a function of receiving parameters such as volume and PAN coefficient, supplying them to each unit, and saving the current value obtained by the calculation of each unit.

  The wave address generator (WAG) 1102 has a function of generating an address for repeatedly reading between the loop start address and the loop end address after reaching the loop end address via the loop start address in order from the waveform read start address. doing. The reading speed is changed according to the waveform reading rate (F number).

  The interpolator (IP) 1104 has a function of receiving the read waveform data and performing interpolation.

  The DCF 1106 is a digitally controlled filter that performs filtering on waveform data.

  The first envelope generator (EG-1) 1108 has a function of giving a time envelope to the cutoff frequency of the DCF 1106.

  The DCA 1110 is a digitally controlled amplifier that controls the amplitude of waveform data.

  The second envelope generator (EG-2) 1112 has a function of providing a time envelope to the amplitude of the DCA 1110 and outputting a zero amplitude detection signal to the OR circuit (OR) 1116.

  The loudness circuit (LD) 1114 has a function of controlling the volume of the waveform data and outputting a volume zero detection signal to the OR circuit (OR) 1116.

  The logical sum circuit (OR) 1116 is a circuit that outputs a logical sum of the zero detection signals of the second envelope generator (EG-2) 1112 and the loudness circuit (LD) 1114.

  The pan controller 1118 has a function of controlling stereo localization of waveform data.

  The mixer 1120 is a mixing circuit that, for example, adds the waveform data of each of the 16 sound generation channels when the number of channels of the apparatus of this embodiment is 16.

  The effect applying circuit (EFP) 1122 has a function of applying an effect to the waveform data added in series.

  FIG. 15 is an explanatory diagram illustrating detailed configurations of the memory management unit 14 and the cache unit (C0) 13 according to the first embodiment.

  As shown in the figure, among these circuit configurations, the cache unit (C0) 13 is assumed to have a 16-line configuration from 0 to F, for example, and the capacity per line is assumed to be 4096 bytes. In this case, the capacity of the cache unit 13 is 65536 bytes.

  The operation of each unit will be described.

  1) An address (for example, 32 bits) to the external memory (first and second storage units 210 and 211) is transmitted from the control unit 12 to the internal bus 100.

  2) The line address selector 1400 (LAS-0 to LAS-F) of each line (CacheLine0 to F) of the cache unit 13 receives this and corresponds to the line that it is registering by looking at the upper (20) bits. Compare with the upper (for example, 20) bits of the address to be processed. For this comparison, the line address selector 1400 includes an upper address register (for example, 20 bits). The contents of the register are rewritten when the line is updated.

  3) The match result is sent to the line selector 1406 (LS) as a HIT signal. When HIT = ON, the lower (for example, 12) bit address is sent to the line memory 1300 (LM-0 to LM-F). When HIT = OFF, no address is sent.

  4) All the HIT signals of each line are collected in the line selector 1406 (LS).

  4-1) If all the HITs are OFF, the line selector 1406 (LS) outputs (0) CTR = ON (a signal output when the control unit 12 has a cache miss hit), and (1) Select an appropriate cache line (for example, the oldest accessed time), and (2) switch the data bus selector 1402 (DBS) of the line to “external-internal direct connection” using the OCT signal. (3) The line memory 1300 (LM) of the line is selected in the write mode using the CCT signal, and (4) the line address selector 1400 (LAS) is forcibly set to the internal bus 100 selected using the ICT signal. 5) Request the preload address generator 1404 (PAG) to clear the start address.

  4-2) If any line indicates HIT = ON and the preload address generator 1404 (PAG) is not updated by the completion of the previous line processing, the line selector 1406 (LS) 0) CTR = OFF is output, (1) The line memory 1300 (LM) of the line where HIT = ON is selected in the read mode using the CCT signal, and (2) the data bus selector 1402 (DBS) of the line ) Is connected only to “inside” using the OCT signal. 4-3) When any line indicates HIT = ON and the preload address generator 1404 (PAG) is updated by the completion of the previous line processing, the line selector 1406 (LS) ) CTR = ON is output, (1) The line memory 1300 (LM) of the line where HIT = ON is selected in the read mode using the CCT signal, and (2) the data bus selector 1402 (DBS) of the line (3) Select an appropriate (for example, the oldest accessed time) cache line, and (4) set the data bus selector 1402 (DBS) of the line Using the OCT signal, only “external” is switched to the connected state. (5) The line memory 1300 (LM) of the line is changed to the CCT signal. (6) The line address selector 1400 (LAS) is forcibly set to the internal bus 100 selection state using the ICT signal, and (7) the preload address generator 1404 (PAG) clears the start address. Request.

  5) Data on the external bus 200 is analyzed by the data analyzer 1408 (DA). If there is a jump or call instruction in the data (program data), the data analyzer 1408 (DA) acquires the upper (for example, 20) bits of the jump destination address and sends it to the preload address generator 1404 (PAG). .

  6) The preload address generator 1404 (PAG) receives the jump address from the data analyzer 1408 (DA) while the line selector 1406 (LS) is executing the rewrite of the line memory 1300 (LM). 12) Add “0” to the bit and register as a preload start address. Thereafter, when the line selector 1406 (LS) finishes transferring the line, the preload address is incremented by 1 in accordance with a clock (not shown) and sent out.

  Here, an example when line 1 is hit will be described.

  The line address selector 1400 (LAS-1) selects an internal address, and the other line address selectors 1400 are set to be disconnected. The line memory 1300 (LM-1) executes read processing according to the lower address from the line address selector 1400 (LAS-1), and the other line memories 1300 are in a non-selected state. Thereafter, the data bus selector 1402 (DBS-1) connects the line memory 1300 (LM-1) to the internal bus 100, and the other line memories 1300 are disconnected.

  On the contrary, a case where the cache misses will be described.

  Once all the line address selectors 1400 output HIT = OFF, the CTR signal is output. When the bus controller 11 (BC) competes with the musical sound generator 10 and the bus timing, the bus controller 11 (BC) connects the external bus 200 to the memory manager 14.

  The bus controller maintains the connection for one sample time by counting a clock (not shown). During this time, while the data is stored in the line from the external memory (second storage unit 211 or the like) connected to the external bus, the control unit 12 also operates. During this time, if there is a jump or call instruction, a preload address is further stored. Is done.

  When the one sample time elapses, the bus controller 11 (BC) outputs a WAIT signal, and the connection of the external bus 200 is returned from the memory management unit 14 to the decoder / buffer 16, and this connection is made for a minimum of, for example, three sample times. To maintain.

  Thereafter, if there is a connection request by the CTR signal from the memory management unit 14, the above processing is repeated until there is no connection request. Here, the time for the bus controller 11 (BC) to maintain the connection back to the decoder / buffer 16 is, for example, a data string (normal waveform data) between check data (parity data) that appears periodically in the waveform data. ).

  When the above line reaches the end, it looks for the next line. If the next is HIT, the control unit 12 reads and operates the cache, and at the same time, the jump destination page is preloaded using the preload address generator 1404 (PAG). If the HIT is not performed, the preload is not executed. A line is read.

  FIG. 16 is a circuit diagram showing a configuration of the decoder buffer (D / B) 16 of the first embodiment.

  The waveform read address generated by the wave address generator (WAG) 1102 (see FIG. 14) of the tone generator 10 is given to the wave data buffers (WDB-0 / 1) 1502a and 1502b through the buffer selector (BS) 1500. The waveform is sent from the wave data buffer (WDB-0 / 1) 1502a or 1502b on the side where the current waveform is not read from the external bus 200 to the interpolator (IP) 1104 (see FIG. 14) of the tone generator 10. .

  In the wave data buffer (WDB-0 / 1) 1502a or 1502b on the side where the waveform is not sent to the musical tone generator 10, the waveform data is read from the external bus 200 through the wave reader register (WRR) 1510.

  The wave reader register (WRR) 1510 reads and stores one block (8 bits × 4 words according to FIG. 6) from the external memory (first storage unit 210) via the bus controller 11. The entity is a memory having 1-bit memory by the bit width × word number. When reading from the external memory, the word address (row) is stored as the upper address and the bit address (column) is stored as the lower address as usual, but when sent to the interpolation unit (IPUnit; IU) 1506, the wave reader register (WRR) is stored. An address R / C exchanger (ARCE) 1508 that controls the exchange of the write / read address 1510 with row and column is read by exchanging the row address and the column address. The address R / C exchanger (ARCE) 1508 reads the stored data as shown in FIG. Further, the interpolation unit (IPUnit; IU) 1506 restores from other data as shown in FIG. 7 described above when there is missing data among the data read from the wave reader register (WRR) 1510. .

  The read data is decoded by a wave decoder (WD) 1504. At this time, the buffer speeds (for example, per channel time) of the wave data buffers (WDB-0 / 1) 1502a and 1502b obtained by the reading speed of the musical sound waveform data (for example, 2 bytes per channel time) and the compression ratio (eg, 1/2) are obtained. If 4 bytes) is equal to or higher than the waveform reading speed of the wave address generator (WAG) 1102 (for example, 2.0 bytes / channel time or less), it becomes a free time after the reading of the sound waveform data for the buffer size is completed. During this time, REQ = OFF, and the control unit 12 can directly access the external bus 200.

  Even when an address is not transmitted from the wave address generator (WAG) 1102, REQ = OFF, and the control unit 12 can directly access the external bus 200.

  FIG. 17 is a circuit diagram showing the configuration of the bus controller (BC) 11, and FIG. 18 is a truth table of the bus select control (BSC) 1600 shown in the figure.

  The bus select control (BSC) 1600 is connected to an external address selector (EAL) 1602, an external data selector (EDL) 1604, and an external control selector (ECL) 1606, and outputs these signals.

  The bus select control (BSC) 1600 receives a CTR signal from the memory management unit 14 and a REQ signal from the decoder buffer 16 and outputs a select signal to each of the above units, as well as a WAIT signal to the memory management unit 14. Output.

  The external address selector (EAL) 1602 receives the signal specifying the memory address from the memory management unit 14 and the memory address from the decoder buffer 16 in addition to the select signal, and receives the first storage unit 210 or the second memory address. A signal designating a predetermined address in the storage unit 211 is transmitted.

  An external data selector (EDL) 1604 transmits / receives data to be exchanged between the memory management unit 14 and the external bus 200, and exchanges data to be exchanged between the decoder buffer 16 and the external bus 200, in addition to the select signal. In addition, these data are transmitted / received to / from the external bus 200.

  In addition to the select signal, the external control selector (ECL) 1606 receives a control (Control) signal from the memory management unit 14 and a control (Control) signal from the decoder buffer 16 to receive the first storage unit 210 or the first control unit. The control (Control) signal for the second storage unit 211 is output.

  FIG. 18 is a truth table of the bus select control (BSC) 1600 as described above.

  According to the figure, when both the CTR signal and the REQ signal are OFF, the bus controller 11 does not connect the external bus 200 to the memory management unit 14 or the decoder / buffer 16, and the WAIT signal is turned ON. Is set.

  When the CTR signal = OFF and the REQ signal = ON, the external bus 200 is connected to the decoder buffer 16 and the WAIT signal is set to the ON state.

  Further, when the CTR signal = ON and the REQ signal = OFF, the external bus 200 is connected to the memory management unit 14 and the WAIT signal is set to the OFF state.

  When both the CTR signal and the REQ signal are ON, the external bus 200 is connected to the memory management unit 14 and the WAIT signal is set to the OFF state. When the WAIT signal is OFF for one sample time (while the control unit 12 operates and the cache unit 13 is updated at the same time), the WAIT signal is turned ON again, and then the minimum, for example, 3 sample time (3ST ), The external bus 200 continues to be connected to the decoder / buffer 16. In the case where both the CTR signal and the REQ signal of FIG. 18 are ON, “3” of “the external bus 200 continues to be connected to the decoder / buffer 16 for 3 sample times (3ST)” is the waveform data of FIG. Is equal to the number of words in the data string between the “parity data” and the next “parity data”. Further, the above processing is repeated while the CTR signal and the REQ signal are competing.

  According to the configuration of the present embodiment, when the memory management unit 14 detects a cache miss hit of the cache unit 13, the bus controller 11 interrupts the musical sound waveform data reading by the musical sound generation unit 10, and the control unit 12. Access to the second storage unit 211 is permitted, and the program read at the same time is stored in the cache unit 13. Further, the musical tone waveform data whose reading has been interrupted is sent to the interpolation unit 15 as a missing value by the bus controller 11. On the other hand, when the reading of the musical sound waveform data is interrupted, the interpolation unit 15 interpolates between the missing values based on the value of the musical sound waveform data read before and after the occurrence of the interruption. .

  That is, at the time of a cache miss hit of the cache unit 13, the bus controller 11 interrupts the reading of the musical sound waveform data, gives priority to the program reading by the control unit 12, and the loss of the musical sound waveform data that occurs at the time of the interruption is This is supplemented by the interpolation processing by the interpolation unit 15. Therefore, the reading of musical sound waveform data by the musical sound generating unit 10 is interrupted by the bus controller 11 so that the control unit 12 can access the second storage unit 211, and the musical sound waveform corresponding to the missing data is lost. Since the data is supplemented by the interpolation unit 15, it is possible to prevent the generation of a plurality of musical sounds performed in time division.

  The interpolation processing by the interpolating unit 15 is performed immediately after the musical tone waveform data to be read is used by using check parity data for every fixed amount to be read. Can be done correctly and easily.

  Note that the one-chip electronic musical tone generator of the present invention is not limited to the above-described illustrated examples, and it is needless to say that various modifications can be made without departing from the gist of the present invention. For example, the cache (C0) and the data cache (C1) may be packaged without being incorporated in the chip. Further, the zero page program may be stored not in the cache (C0) but in the data cache (C1) or other storage means arranged on the internal bus. Of the lines in the cache (C0), line 0 may not be rewritten or paged out. The data cache (C1) may be handled in the same manner as the cache (C0). The data cache (C1) may be eliminated, and the program code and program data may be mixed in the cache (C0). The first storage unit and the second storage unit may be different areas of the same storage unit.

  The configuration of the one-chip electronic musical tone generator according to the present invention can be used for electronic musical instruments and the like, as well as for electronic games and other devices that can generate musical sounds electronically.

1 is a circuit diagram showing a configuration of an electronic sound generator including a one-chip electronic musical tone generator and peripheral circuits according to an embodiment of the present invention. It is a functional block diagram of the electronic-sound-generation generator which has a structure of Example 1 of this invention. It is a time chart of each signal, bus | bath, and TG channel when a cache is hit. It is a time chart when the cache is missed and the program is being updated when the sound channel 0x3 is muted and the others are sounding. It is explanatory drawing which shows a functional block in case a sound channel 0x3 is muted and others are sounding and a cache is missed and a program is being updated. It is explanatory drawing explaining the interpolation process by the interpolation part. FIG. 8 is an explanatory diagram for continuing the description of the interpolation processing by the interpolation unit 15. FIG. 10 is an explanatory diagram for further explaining the interpolation processing by the interpolation unit 15; 3 is a flowchart showing a main flow of a control unit 12. It is a flowchart which shows the processing flow of the initialization process by the control part 12 shown by FIG.9 S100. It is a flowchart which shows the content of the interval timer interruption routine TINT (). 10 is a flowchart showing a process flow of event processing (doEvent) performed in step S104 in the main process flow of the control unit 12 of FIG. 9. 10 is a flowchart showing a processing flow of processing (doTVar) based on the timer counter T performed in step S106 in the main processing flow of the control unit 12 of FIG. 9. 3 is an explanatory diagram showing a detailed configuration of a musical sound generating unit 10. FIG. It is explanatory drawing which shows the detailed structure of the memory management part 14 and the cache part (C0) 13. 3 is a circuit diagram showing a configuration of a decoder buffer (D / B) 16. FIG. 2 is a circuit diagram showing a configuration of a bus controller (BC) 11. FIG. 18 is a truth table of the bus select control (BSC) 1600 of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Music sound generation part 11 Bus controller 12 Control part 13 Cache part 14 Memory management part 15 Interpolation part 16 Decoder buffer 17 Data cache part 100 Internal bus 200 External bus 210 First memory | storage part 211 2nd memory | storage part 1100 Parameter register 1102 Wave address generator 1104 Interpolator 1106 DCF
1108, 1112 Envelope Generator 1110 DCA
1114 Loudness circuit 1116 OR circuit 1118 Pan control 1120 Mixer 1122 Effect applying circuit 1300 Line memory 1400 Line address selector 1402 Data load selector 1404 Preload address generator 1406 Line selector 1408 Data analyzer 1500 Buffer selector 1502a, 1502b Wave data buffer 1504 Wave decoder 1506 Interpolation unit 1508 Address R / C exchanger 1510 Wave reader register 1600 Bus select control 1602 External address selector 1604 External data selector 1606 External control selector

Claims (2)

According to the parameter generated based on the program for generating the musical sound, which is read out from the first storage means storing the musical sound waveform data for generating the musical sound, and stored in the second storage means. A musical sound generating means for processing musical sound waveform data to generate a plurality of musical sounds in a time-sharing manner;
The first storage means and the second storage means are accessed in a time-sharing manner via an external bus, and the musical sound waveform data is read out by the musical sound generation means by receiving a cache miss signal. A bus controller that interrupts the reading and sends out the interrupted musical tone waveform data as a missing value;
Control means that operates in accordance with the read program, generates a parameter for generating the musical sound, and supplies the parameter to the musical sound generating means;
Cache means for interposing at least a program interposed between the bus controller and the control means,
When a cache miss hit is detected by the cache means, a cache miss signal is transmitted to the bus controller when a cache miss hit is detected, and when the musical tone waveform data reading by the bus controller is interrupted, the control is performed. Memory management means for permitting access to the second storage means by the means and storing the simultaneously read program in the cache means;
If the bus controller by the musical tone waveform data read is interrupted, the value of the musical tone waveform data read out after the interruption occurs before and generating, possess an interpolation means for repairing interpolating between the missing values,
The one-chip electronic musical tone generator according to claim 1 , wherein the interpolation means performs the repair interpolation processing using check data added for every fixed amount of read musical sound waveform data . Repair interpolation processing by the interpolation means, according to claim 1, wherein a is performed using an insert stored check data to the first storage means every predetermined amount of the musical tone waveform data are read out 1 chip electronic musical tone generator.

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