JP5217042B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including a transistor having an SOI (silicon on insulator) structure formed on an insulating film as a memory cell transistor. More specifically, the present invention relates to an arrangement of a memory cell array of a semiconductor memory device having an orthogonal transform function for converting the order of arrangement of input data and output data.

In the field of image data processing and the like, a system LSI in which logic such as a processor and a memory device are integrated on the same semiconductor chip is widely used in order to process a large amount of data at high speed. In such a system LSI, since the logic and the memory device are interconnected by wiring on the chip, the following advantages are obtained:
(1) The load of the signal wiring is smaller than the wiring on the board, and data / signal can be transmitted at high speed.
(2) Since there is no restriction on the number of pin terminals, the data bus width can be increased, and the data transfer bandwidth can be increased.
(3) Since each component is integrated on a semiconductor chip, a small and lightweight system can be realized. (4) A library of macros is arranged as a component formed on a semiconductor chip. Design efficiency can be improved.

  For the above reasons, system LSIs have been widely used in various fields. As a memory device to be integrated, a dynamic random access memory (DRAM), a static random access memory (SRAM), and a nonvolatile semiconductor memory device (nonvolatile RAM) such as a flash memory are used. . As the logic, a processor that performs control and data processing, an analog processing circuit such as an analog / digital conversion circuit, and a logic circuit that performs dedicated logic processing are used. In digital signal processing for audio and image data, data processing such as filter processing is performed. In such data processing, there are many arithmetic processes that repeat the product-sum operation. A configuration for executing such operations efficiently and at high speed is disclosed in Japanese Patent Application Laid-Open No. 2006-99232.

  In the configuration disclosed in Patent Document 1, the memory cell array is divided into a plurality of entries. An arithmetic processing unit (ALU) is provided for each entry. Data to be calculated is stored in each entry. In a plurality of entries, arithmetic processing is performed in a bit serial manner in parallel, and the arithmetic result is stored in a predetermined position of the original entry. In this arithmetic processing, data is transferred from the outside in word serial. Therefore, in order to store data in this entry, it is necessary to convert word serial data into a bit serial and word parallel data string and write it into the entry. Here, the bit serial and word parallel data string indicates a mode in which bits at the same position of a plurality of words are transferred in parallel. The word serial indicates a mode in which data is transferred in units of words.

  For this data string conversion, the above-mentioned Patent Document 1 uses a transposition memory using SRAM cells. The word line and bit line of port A are arranged so as to be orthogonal to the bit line and word line of port B, respectively. Bits of the same data are stored in memory cells connected to the port A word line. Data bits at the same bit position of a plurality of data words from port A are stored in memory cells connected to the word line of port B. Data transferred from port A in word serial and stored is read from port B as a word parallel data string. Also, the data transferred from port B and transferred in bit serial and word parallel is read from port A as a word serial data string.

  In general, in image and sound processing, it is required to perform orthogonal transform processing such as DCT transform (discrete cosine transform) at high speed. When executing this orthogonal transformation algorithm, it is necessary to transform the data input / output order. A signal processing apparatus for performing such orthogonal transformation at high speed is disclosed in Patent Document 2 (Japanese Patent Laid-Open No. 10-74141). In the configuration disclosed in Patent Document 2, image data is input in a bit-parallel and word-serial sequence, that is, in units of words (pixel data). This input pixel data string is converted into a word parallel and bit serial data string using a serial / parallel conversion circuit and written into the memory cell array. In the memory cell array, data constituting the same block on the screen is stored aligned in the column direction. That is, in each memory array block, pixel data constituting the corresponding image block is stored in units of words for each row of the memory array. An arithmetic unit is provided for each memory array block.

  In the configuration disclosed in Patent Document 2, data is transferred in units of words (data corresponding to one pixel) between a memory array block and a corresponding arithmetic unit. For each block, the same processing is executed on the words transferred by the corresponding arithmetic unit, and the filtering process by DCT conversion is executed at high speed. The result of the arithmetic processing is written again into the memory cell array. After that, parallel / serial conversion is performed again on the data stored in the memory cell array to convert bit serial and word parallel data into a bit parallel and word serial data string. Pixel data for each line is sequentially output in a word serial sequence. In normal processing, the bit position of data is not converted. In the arithmetic unit, normal arithmetic processing is executed in parallel on a plurality of data.

In mobile terminal devices such as mobile phones, low power consumption and small size and weight are strongly demanded. Non-Patent Literature 1 (F. Morishita et al., “A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI,” Proc. CICC, Sep. 2005, pp.435-438) and Non-Patent Document 2 (K. Arimoto et al., “A Configurable Enhanced T ² RAM Macro for System-Level Power Management Unified Memory,” Proc. VLSI Symp.).

  In the configuration shown in Non-Patent Document 1, the memory cell is composed of two SOI (silicon-on-insulator) transistors connected in series. The body region of one transistor (storage transistor) is used as a storage node, and another transistor is used as an access transistor. The body region is in a floating state. The threshold voltage of the storage transistor changes according to the potential of the body region. The source node of the storage transistor is maintained at the power supply voltage level. At the time of data reading, the current flowing through the memory cell is detected to read the data. At the time of data writing, the voltage in the body region is set to a voltage level corresponding to the write data by using capacitive coupling between the body region of the storage transistor and the control electrode.

In the configuration shown in Non-Patent Document 2, as in Non-Patent Document 1, an access transistor and a data storage transistor constitute one memory cell. The data read operation is the same as that shown in Non-Patent Document 1. At the time of data writing, a GIDL (gate / induct / drain / leak) current is used instead of capacitive coupling between the gate and the body region. By utilizing this GIDL current, the potential of the storage node is increased to almost the power supply voltage level.
JP 2006-99232 A Japanese Patent Laid-Open No. 10-74141 F. Morishita et al., “A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI,” Proc. CICC, Sep. 2005, pp.435-438 K. Arimoto et al., “A Configurable Enhanced T2RAM Macro for System-Level Power Management Unified Memory,” Proc. VLSI Symp.

  As the amount of data processing increases, in order to perform orthogonal transform processing at high speed, the memory for orthogonal transform is also required to have a large capacity. In the transposed memory for orthogonal transformation shown in Patent Document 1, a dual port SRAM cell is used. In the case of this dual port SRAM cell, four transistors for data storage and four transistors for access from two ports and a total of eight transistors are required per bit. Therefore, there is a problem that the size of the memory increases and the chip size increases when the capacity is increased.

  In the configuration disclosed in Patent Document 2, a flip-flop array is used for data array conversion. Therefore, as in Patent Document 1, the layout area of the circuit for data array conversion is large and is not suitable for high integration.

  In Non-Patent Documents 1 and 2, a memory cell is composed of two SOI transistors, a body region is used for charge storage, and a capacitor having a complicated shape such as a DRAM is not used. Therefore, scaling is possible following process miniaturization, and the manufacturing process is also compatible with a standard CMOS logic process. However, in these Non-Patent Documents 1 and 2, only a single-port memory cell configuration is shown, and no consideration is given to a multi-port configuration such as a dual port. In particular, in the memory (TTRAM) shown in Non-Patent Documents 1 and 2, the source node of the storage transistor for storage in the memory cell is fixed at the power supply voltage level, for example. Data is read by detecting a current flowing through the series body of the storage transistor and the access transistor. Therefore, in order to arrange access transistors for different ports with respect to the storage transistors for data storage, the arrangement of the memory cell transistors is devised so that the read current is the same for each port. There is a need to.

  In particular, in the memory cell layout shown in Non-Patent Document 1, in one column, a data storage transistor and an access transistor are arranged in alignment along the column direction. Further, the active region of the access transistor and the bit line are arranged in parallel so as to overlap each other in a planar layout. In this memory cell layout, it is difficult to arrange the access transistors of the two ports symmetrically with respect to the data storage transistors.

  In particular, when performing orthogonal transformation, the row and column for one port corresponds to the column and row for the other port. Therefore, it is necessary to arrange the word lines orthogonally for the two ports, and also to arrange the bit lines for the different ports orthogonally. Therefore, in order to realize a memory for orthogonal transformation, a device for layout is required more than the layout of a simple dual port memory.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor memory device for orthogonal transformation having a memory cell configuration that can be easily scaled following process miniaturization.

  The semiconductor memory device according to the present invention uses a data storage transistor (storage transistor) of a TTRAM cell as a data storage element as a memory cell. In one aspect, an SOI transistor having a double drain structure having two drains is used as a first transistor for storing data in a memory cell. This double drain transistor has a body region and a source region in common for each port, and has a drain for each port. A port access second and third transistor is individually connected to each of these drains. Alternatively, the drain and body regions of the storage transistor are connected to separate access transistors, respectively. In another aspect, the drain and body regions of the first transistor for data storage of the memory cell are connected to separate second and third access transistors, respectively.

  The memory cells are aligned in the first and second directions and arranged in a two-dimensional array. A plurality of first word lines, a plurality of second word lines, a plurality of first bit lines, a plurality of second bit lines, and a plurality of charge lines are provided for port access to the memory cell array. . The plurality of first word lines are arranged corresponding to a plurality of first memory cell groups each having memory cells arranged in alignment along the first direction, and the first word lines corresponding to each of the first word lines are arranged. The control electrode of the second transistor of the memory cell group is connected. The plurality of second word lines are arranged corresponding to a plurality of second memory cell groups each having a memory cell arranged in alignment along the second direction, and the second word line corresponding to each of the plurality of second word lines is arranged. The control electrode of the third transistor of the memory cell group is connected. The plurality of first bit lines are arranged corresponding to the second memory cell group, and a conduction node of the second transistor of the corresponding second memory cell group is connected to each of the plurality of first bit lines. The plurality of second bit lines are arranged corresponding to the first memory cell group, and are connected to the conduction node of the third transistor of the corresponding first memory cell group. The plurality of charge lines are arranged corresponding to the respective second memory cell groups, and the control electrodes of the first transistors of the corresponding second memory cell groups are connected to the respective charge lines.

  In the semiconductor memory device according to the present invention, a dual port RAM is configured using TTRAM cells as a base. Therefore, since the individual capacitor element is not used for data storage, the memory cell can be scaled following the miniaturization of the manufacturing process. Further, data reading is non-destructive reading, which eliminates the time required for rewriting the charge to the memory cell capacitor, thereby realizing high-speed access.

  Further, the number of transistors is smaller than that of the SRAM cell, and the cell occupation area can be reduced.

[System configuration]
FIG. 1 schematically shows an overall configuration of a signal processing system to which an orthogonal transformation semiconductor memory device according to the present invention is applied. The use of the semiconductor memory device for orthogonal transform is not limited to the signal processing system shown in FIG. 1, but here, in order to clearly show the use of orthogonal transform, a signal processing system that performs parallel arithmetic processing is used in the application example. As an example.

  In FIG. 1, the signal processing system 1 includes a system LSI 2 that realizes an arithmetic function for executing various processes, and an external memory connected to the system LSI 2 via an external system bus 3. The external memory includes a large-capacity memory 4, a high-speed memory 5, and a read-only memory (read-only memory: ROM) that stores fixed information such as an instruction at the time of system startup. The large-capacity memory 4 is composed of, for example, a clock synchronous dynamic random access memory (SDRAM), and the high-speed memory 5 is composed of, for example, a static random access memory (SRAM).

  The system LSI 2 includes basic operation blocks FB1 to FBh coupled in parallel to the internal system bus 7, a host CPU 8 that controls processing operations of these basic operation blocks FB1 to FBh, and input signals from the outside of the signal processing system 1. It includes an input port 9 that converts IN to internal processing data, and an output port 10 that receives output data provided from the internal system bus 7 and generates an output signal OUT that is transferred to the outside of the system. The host CPU 8 controls processing operations of the basic arithmetic blocks FB1 to FBh via the internal system bus 7.

  The input port 9 and the output port 10 are composed of, for example, library IP (integral property) blocks, and realize functions necessary for data / signal input / output.

  The system LSI 2 further includes an interrupt controller 11, a CPU peripheral 12, a DMA (direct memory access) controller 13, an external bus controller 14, and dedicated logic 15 coupled in parallel to the internal system bus 7.

  The interrupt controller 11 receives an interrupt signal from the basic operation blocks FB1 to FBh and notifies the host CPU 8 of the interrupt. The CPU peripheral 12 executes a control operation necessary for each type of the host CPU 8. The DMA controller 13 executes data transfer to the external memory in accordance with a transfer request from the basic operation blocks FB1 to FBh. The external bus controller 14 controls access to the memory 4-6 connected to the external system bus 3 in accordance with an instruction from the host CPU 8 or the DMA controller 13.

  To the DMA controller 13, a DMA request signal is given as a transfer request from the basic operation blocks FB1-FBh.

  Since basic operation blocks FB1-FBh have the same configuration, FIG. 1 representatively shows the configuration of basic operation block FB1.

  The basic operation block FB1 includes a main operation circuit 20, a microinstruction memory 21, a controller 22, a work data memory 23, and a system bus interface (I / F) 24. The main arithmetic circuit 20 executes actual data arithmetic processing. The microinstruction memory 21 stores microinstructions that specify arithmetic processing in the main arithmetic circuit 20. The controller 22 controls the arithmetic processing of the main arithmetic circuit 20 in accordance with the microinstruction from the microinstruction memory 21. The work data memory 23 stores intermediate processing data or work data of the controller 22. The system bus interface 24 transfers data / signals between the basic operation block FB1 and the internal system bus 7.

  The main arithmetic circuit 20 includes a memory cell mat 40 in which a plurality of memory cells are arranged in a matrix, and a plurality of arithmetic units (ALUs) arranged in parallel that perform operations in a bit serial manner on data stored in the memory cell mat 40. 41) and an inter-ALU switch circuit 42 for setting a data transfer path between the arithmetic units 41.

  Memory cell mat 40 is divided into a plurality of entries. This entry is constituted by each memory cell column of the memory cell mat 40, and each bit of multi-bit data is stored in one entry.

  The arithmetic unit 41 is provided corresponding to each entry of the memory cell mat 40, receives the data from the corresponding entry bit-serially, performs arithmetic processing, and outputs the processing result to the designated entry ( For example, it is stored in a predetermined position of the corresponding entry).

  The inter-ALU interconnection switch circuit 42 switches the connection path of the arithmetic unit 41 and enables calculation of data of different entries.

  The controller 22 performs an operation in accordance with the microprogram method in accordance with the microinstruction stored in the microinstruction memory 21. Work data necessary for this microprogram operation is stored in the work data memory 23. The system bus I / F 24 allows the host CPU 8 or the DMA controller 13 to access the memory cell mat 30, the control register in the controller 22, the microinstruction memory 21 and the work data memory 23.

  A switching circuit (MUX) 26 is provided between the system bus I / F 24 and the main arithmetic circuit 20. The switching circuit 26 connects between the main arithmetic circuit 20 and one of the system bus I / F 24 and the orthogonal transform circuit 30. The orthogonal transform circuit 30 includes an orthogonal transform storage device configured according to the present invention, and executes rearrangement of a given data string.

  That is, the orthogonal transformation circuit 30 receives data transferred in a bit parallel and word serial manner from the system bus I / F 24, transfers the data in a word parallel and bit serial manner, and differs in the entry of the memory cell mat 40. Write bits in the same position of the data word in parallel. Further, the orthogonal transform circuit 30 transposes a data string transferred in word parallel and bit serial from the memory cell mat 40 of the main arithmetic circuit 20 and transfers it in a bit parallel and word serial manner. Thereby, the consistency of data transfer between the system bus I / F 24 and the memory cell mat 30 is established.

  Here, as described above, the bit serial indicates a mode in which the bits constituting one data word are sequentially transferred or processed, and the bit parallel indicates the bits constituting one data word are transferred in parallel. Indicates a process or embodiment. In addition, entry (or word) parallel indicates a mode in which a plurality of entries (or words) are transferred or processed in parallel, and in entry (or word) serial, data of a plurality of entries (or words) is sequentially transferred. Or the aspect processed is shown.

  In this specification, conversion between a bit-serial and word-parallel data sequence and a bit-parallel and word-serial data sequence is defined as “orthogonal transformation”.

  The switching circuit 26 may be configured to select work data from the controller 22 and transfer it to the main arithmetic circuit 20. In this case, the work data memory 23 becomes unnecessary. When it is not necessary to transpose the operation target data string by orthogonal transformation, the switching circuit 26 selects the system bus I / F 24 and connects it to the main arithmetic circuit 20.

  Although the processing operation of the entire signal processing system and the configuration and processing operation of the main arithmetic circuit 20 have already been described in detail in Patent Document 1 by the same applicant, the operation of the orthogonal transformation circuit according to the present invention will be described below. In order to fully understand the effect, the configuration and operation of the main arithmetic circuit 20 will be briefly described.

  FIG. 2 schematically shows an arrangement of memory cell mat 40 and arithmetic unit (ALU) 41 of main arithmetic circuit 20 shown in FIG. In memory cell mat 40, memory cells MC are arranged in a matrix and are divided into M entries ERY. The entry ERY has a bit width of N bits. In memory cell mat 40, word line WL is arranged in common for M entries ERY, and bit line pair BLP is arranged for one entry ERY. Bit lines BL and / BL of bit line pair BLP are used as data transfer lines.

  The arithmetic unit 41 is provided corresponding to each entry ERY and constitutes an arithmetic processing unit 45. The computing unit 41 can perform operations such as addition, logical product, coincidence detection (EXOR), and inversion (NOT). Data is loaded and stored between each entry ERY and the corresponding arithmetic unit 41 to execute arithmetic processing. The calculation contents of the calculator 41 are set by the controller 22 shown in FIG.

  Each entry ERY stores data to be subjected to arithmetic processing, and the arithmetic unit 41 executes arithmetic processing in a bit serial manner. Accordingly, the arithmetic processing unit 45 executes data arithmetic processing in a bit serial and entry parallel manner.

  By performing the arithmetic processing in the bit serial manner in the arithmetic processing unit 45, the following advantages are obtained. That is, even when the bit width of the data to be calculated varies depending on the application, the number of operation cycles is simply changed according to the bit width of the data word. The processing content is not changed, and it is possible to easily cope with data processing with different word configurations. Further, the data of a plurality of entries ERY can be processed in parallel in the arithmetic processing unit 45. Therefore, by increasing the number of entries M, a large amount of data can be collectively processed.

  Memory cell MC is formed of, for example, an SRAM cell, and can perform high-speed access to transfer data.

  When the main arithmetic circuit 20 performs an operation, first, operation target data is stored in each entry ERY. Next, a certain digit of the stored data is read in parallel for all the entries ERY and transferred (loaded) to the corresponding computing unit 41. That is, by driving the word line WL to the selected state, the data of the memory cell MC connected to the selected word line is read onto the corresponding bit line pair BLP. The read data is transferred to the corresponding computing unit 41.

  When performing a binary operation, data of a set of binary operations is stored in each entry ERY. After the bits of one data word are transferred, the same transfer operation is performed on the bits of another data word. Thereafter, each computing unit 41 performs a binary operation, and the computation processing result is rewritten (stored) from the computing unit 41 into a predetermined area in the corresponding entry ERY.

  FIG. 3 is a diagram showing an example of the arithmetic operation in the main arithmetic circuit 20 shown in FIG. In FIG. 3, data words PXa and PXb having a 2-bit width are added to generate data word PXc. In each entry ERY, data words PXa and PXb forming a set to be operated are stored. In FIG. 3, 10B + 01B is added in the calculator 31 for the entry ERY in the first row, and 00B + 11B is calculated in the calculator 41 for the entry ERY in the second row. Here, “B” indicates a binary number. The calculator 41 for the entry ERY in the third row adds 11B + 10B. Thereafter, similarly, an addition operation of the data words PXa and PXb stored in each entry ERY is executed.

  The calculation is performed in a bit serial manner in order from the lower bit. In each entry ERY, the lower bit PXa [0] of the data word PXa is transferred to the corresponding arithmetic unit (ALU) 41. Next, the lower bit PXb [0] of the data word PXb is transferred to the corresponding computing unit 41. Each of the arithmetic units 41 performs an addition operation using the given 2-bit data. This addition operation result PXa [0] + PXb [0] is written (stored) at the position of the lower bit PXc [0] of the data word PXc. For example, in the entry ERY in the first row, the bit “1” is written at the position of PXc [0].

  This addition process is also performed for the upper bits PXa [1] and PXb [1], and the addition result PXa [1] + PXb [1] is written at the position of the bit PXc [1].

  A carry may occur depending on the addition operation. The carry value is written at the position of bit PXc [2]. Thereby, the addition of the data words PXa and PXb is completed in all the entries ERY, and the result is stored as data PXc in each entry ERY. When 1024 entries are provided, the addition of 1024 sets of data can be performed in parallel.

  As shown in FIG. 3, when the operation is performed in the bit serial mode, one machine cycle is required for each data bit transfer between the memory cell mat 40 and the arithmetic unit 41. Let us consider a configuration in which one machine cycle is required. In this case, 4 machine cycles are required to add 2-bit data and store the addition result. That is, 4 machine cycles are required for each digit of the arithmetic processing data. However, by dividing the memory cell mat 40 into a plurality of entries ERY, storing a set of data to be calculated in each entry ERY, and using a configuration in which a corresponding arithmetic unit 41 performs arithmetic processing in a bit serial manner, The following features are realized. In other words, each data operation requires a relatively large machine cycle, but if the amount of data to be processed is very large, high-speed data processing is achieved by increasing the parallelism of the operation. Can be realized. Further, by performing the arithmetic processing in the bit serial mode, the bit width of the data to be processed is not fixed, and can be easily adapted to applications having various data configurations.

  FIG. 4 is a diagram illustrating an example of a specific configuration of the main arithmetic circuit 20. In main arithmetic circuit 20, memory cells MC arranged in memory cell mat 40 are single port SRAM cells. A word line WL is arranged corresponding to each memory cell group aligned in the vertical direction in the figure, and a bit line pair BLP is arranged corresponding to each entry. Memory cell MC is arranged corresponding to the intersection of bit line pair BLP and word line WL. One word line WL is connected to memory cells MC arranged at the same position in entries ERY0 to ERY (M−1). In bit line pairs BLP0-BLP (M-1) arranged corresponding to entries ERY0-ERY (M-1), the memory cells of the corresponding entries are connected.

  A row decoder 54 provided for the word line WL of the memory cell mat 40 drives the word line WL to which the operation target data bit is connected to a selected state in accordance with an address signal from the controller 22 or the orthogonal transform circuit 30. The row decoder 54 can select data bits at the same position in parallel in the entries ERY0 to ERY (M−1).

  In the arithmetic processing unit 45, an arithmetic unit (ALU) 41 is arranged corresponding to the bit line pair BLP0-BLP (M-1). A read / write circuit 48 for loading / storing data is provided between the arithmetic processing unit 45 and the memory cell mat 40. Read / write circuit 48 includes a sense amplifier group 50 that amplifies transfer data from memory cell mat 40, and a write driver group 52 that transfers write data to memory cell mat 40. Sense amplifier group 50 and write driver group 52 include sense amplifiers and write drivers provided corresponding to bit line pairs BLP0 to BLP (M-1), respectively.

  An input / output circuit 56 for transferring data to / from the read / write circuit 48 via the orthogonal transformation circuit 30 and the internal memory bus 57 is provided. Data is transferred between memory cell mat 40 and internal memory bus 57 by input / output circuit 56. The input / output bit width of data of the input / output circuit 56 is set to a value equal to or larger than the bit width of data transferred by the system bus I / F 24.

  In order to adjust the data bit width in input / output circuit 56 and the bit width (M) of an entry connected to one word line WL, a column decoder 58 is provided. A number of bit line pairs (sense amplifiers or write drivers) corresponding to the transfer data bit width of the orthogonal transformation circuit 30 are selected in parallel by the column selection line CL from the column decoder 58. The column decoder 58 is given an entry address from the controller 22 or the orthogonal transformation circuit 30. The number of bits of the address given to the column decoder 58 is appropriately determined according to the bit width of data transferred to the orthogonal transform circuit 30.

  An entry selected by column selection line CL is connected to input / output circuit 56, and data is transferred to / from orthogonal transformation circuit 30 or system bus via internal memory bus 57.

  As shown in FIG. 4, the entries ERY0-ERY (M-1) are selected by the row decoder 54, and data is written in parallel to a predetermined number of selected entries. Therefore, the input / output circuit 56 needs to transfer data stored in different entries. On the other hand, data transferred via the system bus I / F 24 is data in units of data words, and is data included in one entry ERY. Therefore, the word serial and bit parallel transfer data (transfer data on the internal system bus 7) of the system bus I / F 24 is converted into bit serial and word parallel data suitable for writing to the memory cell mat 40. There is a need. In addition, reverse array conversion is also required. As described above, this function is called an orthogonal transform function, and the orthogonal transform circuit 30 performs data array conversion.

  FIG. 5 is a diagram schematically showing the flow of data by the data array conversion operation in the orthogonal transform circuit 30 shown in FIG. In FIG. 5, the operation when 4-bit data is transferred from an external large-capacity memory (SDRAM) 4 and the 4-bit data is transferred from the orthogonal transformation circuit 30 to the memory cell mat 40 in the main arithmetic circuit 20. Is shown as an example.

  The SDRAM 4 stores 4-bit data a (bits a0 to a3) to i (bits i3 to i0). Each bit of 4-bit data DTE (data i: bits i3-i0) is transferred in parallel from the SDRAM 4 via the internal system bus (7). The data DTE from the SDRAM 4 is entry unit data stored in the same entry ERY of the memory cell mat. In the memory 30a of the orthogonal transformation circuit 30, each bit of the transferred 4-bit data is stored aligned in the Y direction. In the memory 30a of the orthogonal transformation circuit 30, the transfer data is sequentially stored in the X direction.

  At the time of data transfer from the orthogonal transform circuit 30 to the memory cell mat 40, the bits aligned in the X direction are read in parallel in the memory 30a, and the selected bit position is sequentially updated along the Y direction for data transfer. Is done. Therefore, data DTA composed of bits e 1, f 1, g 1 and h 1 is stored in parallel in 4 entries of memory cell mat 40. This address unit data DTA is data stored when one address is designated in the memory cell mat, and is stored at a position indicated by entry position information and write bit position information of the memory cell mat 40. By sequentially repeating this operation for all transfer data, a plurality of data bits are written in parallel to a plurality of entries (4 entry units) in the memory cell mat 40. In each entry ERY, entry-unit data DTE is stored.

  When data is transferred from the memory cell mat 40 to the outside via the internal system bus (7), data flows in the opposite direction as shown by a broken line in FIG. 5, and the address unit data DTA is converted into the orthogonal transform circuit 30. Are sequentially stored along the Y direction. In this case, the orthogonal transform circuit 30 stores the read data in another memory (not shown) (the data storage mode is the same as in the memory 30a). In this orthogonal transform circuit 30, only one memory may be provided, but the reason why two memories are arranged as one embodiment is as follows. That is, as will be described in detail later, if each port has a complete IO port configuration as a memory, a problem may occur from the viewpoint of current consumption. Two ports are used as a read port and a write port, respectively. This is because the direction of the transfer data is fixed in each memory.

  Data DTE in entry units aligned in the X direction is read from another memory of the orthogonal transformation circuit 30 and transferred via the system bus I / F (24). Therefore, when data is transferred from the memory cell mat 40 to the SDRAM 4 via the system bus, only the flow of the write data shown in FIG. 5 is reversed, and the same conversion operation is performed by the orthogonal conversion circuit 30. It is executed in another memory.

  Even if two orthogonal transformation memories are used, data is basically transferred in bit parallel and word serial between the internal system bus and the orthogonal transformation circuit 30, and between the orthogonal transformation circuit 30 and the memory cell mat 40. Then, data is transferred in bit serial and word parallel.

  FIG. 6 schematically shows a cross-sectional structure of a single port TTRAM cell used as a base of the present invention. In FIG. 6, the TTRAM cell is formed on the SOI substrate 60. The SIO substrate 60 includes a silicon substrate 62, a buried insulating layer 63 formed on the silicon substrate 62, and a silicon layer (active layer) 64 formed on the buried insulating layer 63. Here, the active layer or active region indicates a region into which impurity ions are implanted, and is used as including a body region below the gate electrode.

  Silicon layer 64 includes N-type impurity regions 70, 72 and 74 formed at a distance from each other, P-type impurity region 71 formed between N-type impurity regions 70 and 72, N-type impurity region 72 and 74 and a P-type impurity region 73 formed between them. In the silicon layer 64, one TTRAM cell is formed.

  Adjacent memory cells are separated from each other by a full trench isolation region 75 having a substantially shallow trench isolation (STI) structure. A gate insulating film 76 and a gate electrode 77 are sequentially stacked on the P-type impurity region 71. Gate electrode 77 is connected to word line WL. On the other hand, the gate insulating film 78 and the gate electrode 17 are sequentially stacked on the P-type impurity region 73. Gate electrode 79 is coupled to charge line CL.

  Impurity region 70-72, gate insulating film 76 and gate electrode 77 constitute access transistor AT. The impurity regions 72-74, the gate insulating film 78, and the gate electrode 79 constitute a charge storage transistor ST that stores information. The body region of the storage transistor ST is formed by a P-type impurity region 73. The P-type impurity region 73 includes a channel formation region 73a where a channel is formed and a charge accumulation node 73b for accumulating charges. The impurity region 73 has a buried insulating layer 3 formed below, and is in a floating state. This storage transistor ST for charge accumulation is constituted by an SOI transistor, and charges are accumulated using its floating body (a body region in a floating state).

  FIG. 7 is a diagram showing an electrical equivalent circuit of the TTRAM cell shown in FIG. As shown in FIG. 7, in the TTRAM cell, an access transistor AT and a storage transistor ST are connected in series between a bit line BL and a source line SL. The charge storage node 73b of the floating body of the storage transistor ST is used as a storage node SN for storing information. The potential of the node (precharge node) PN between the transistors AT and ST is adjusted according to the write data, and by selective capacitive coupling between the charge line CL and the storage node SN and the precharge node PN, Accumulate charge.

  The storage transistor ST has a low threshold voltage when holes are stored in the storage node SN (charge storage node 73b). On the other hand, when no hole is accumulated in storage node SN, the threshold voltage of storage transistor ST increases. Data “0” and “1” are stored depending on the threshold voltage. At the time of data reading, a current is supplied from the source line SL to the bit line BL, and the current flowing through the bit line is detected.

  FIG. 8 is a timing diagram showing data write and read operations of the TTRAM cell shown in FIGS. Hereinafter, referring to FIG. 8, data writing and reading operations of the TTRAM cell shown in FIGS. 6 and 7 will be described in order. Note that the power supply voltage VDD is constantly supplied to the source line SL.

(1) Write operation of data “0” (0 W):
Bit line BL is set to the ground voltage (GND) level during precharge and standby. In this state, the word line WL is raised from the ground voltage GND to the high level of the intermediate voltage (VDD / 2). At the same time, the charge line CL is lowered from the H level (power supply voltage VDD level) to the ground voltage GND level.

  In this state, access transistor AT is rendered conductive, and bit line BL and precharge node PN are electrically coupled. Accordingly, the voltage level of precharge node PN decreases from power supply voltage VDD to the ground voltage level (bit line precharge voltage level) (as will be described later, precharge node PN is at the H level during standby). .

  Further, due to the voltage drop of the charge line CL, in the storage transistor ST, the voltage level of the storage node SN (floating body region 73b) is lowered from the H level to the L level due to the capacitive coupling between the gate and the body region (storage). It is assumed that data “1” is written in the node SN). As a result, a state in which no holes are accumulated is formed in the storage node SN (data “0” is stored).

  Next, the charge line CL is raised from the L level to the H level while the bit line BL is maintained at the L level according to the write data. At this time, the word line WL is at a high level (intermediate voltage level), and the bit line BL is at an L level. Access transistor AT is in a conductive state, and precharge node PN is maintained at the L level. When the voltage of the charge line CL rises and a channel is formed in the channel formation region 73a of the body region 73 of the storage transistor ST, this channel functions as a shield layer. As a result, even if the voltage of the charge storage node 73b (storage node SN) rises slightly, it is maintained at the slightly raised voltage level, and further voltage rise is suppressed. That is, even if the holes injected from the source line SL flow into the precharge node PN (impurity region 72) via the channel formed in the storage transistor ST, the access transistor AT is in a conductive state, and the ground voltage The level bit line BL is discharged. Therefore, the storage node SN is maintained in a state where no holes are accumulated, and data “0” is stored.

  Thereafter, word line WL is lowered to the ground voltage level, and access transistor AT is set in a non-conductive state. At this time, the charge line CL is at the H level, and the voltage level of the precharge node PN rises to the power supply voltage VDD level due to the inflow hole from the source line SL.

(2) Reading operation of data “0” (0R):
Bit line BL is set to L level. The word line WL is driven to a high level (intermediate voltage level), and the access transistor AT is turned on. In this state, the charge line CL is maintained at the H level. The threshold voltage of the storage transistor ST is high because no holes are accumulated in the storage node SN. Therefore, the amount of current flowing from the source line SL to the bit line BL via the storage transistor ST and the access transistor AT is small.

  When access transistor AT becomes conductive, the voltage level of precharge node PN slightly decreases due to coupling with bit line BL (the amount of voltage decrease is determined by the threshold voltage of word transistor AT and the word line voltage). In addition, the voltage drop is suppressed by the hole injection from the source line SL).

  After completion of reading, word line WL is driven to the ground voltage level, and access transistor AT is set to a non-conductive state. A hole flows into the precharge node PN from the source line SL, and its voltage level returns to the H level (power supply voltage VDD level).

(3) Data “0” holding operation (0H):
In the data holding operation, the levels of the bit line BL and the word line WL are held at the L level. Precharge node PN is at an H level higher than the voltage level of bit line BL. Therefore, also in the memory cell of the selected row and the non-selected column, the access transistor AT has a conduction node (impurity region) connected to the bit line BL as a source, its gate-source voltage is 0 V, and is in a non-conduction state. To maintain.

  At this time, as shown in FIG. 8, when the charge line CL is lowered to L level for data writing to another selected memory cell, the voltage levels of the precharge node PN and the storage node SN are changed to the gate cup. Reduced by the ring. However, by driving charge line CL to H level again, the voltage levels of precharge node PN and storage node SN are restored to the original voltage levels.

  This holding operation of data “0” indicates that data “0” is reliably held even in the memory cell of the selected row and the non-selected column. The non-selected bit line is set to the high level of the intermediate voltage level according to the change of the word line voltage.

(4) Write operation of data “1” (1W):
At the time of data writing, first, bit line BL is precharged to the level of ground voltage GND as in the case of writing data “0”. Subsequently, the word line WL is driven to a high level, and in parallel, the charge line CL is driven to an L level. Access transistor AT is turned on, and the voltage level of precharge node PN is lowered to L level due to hole emission to bit line BL. In addition, the voltage level of storage node SN (charge storage node 73b) decreases due to gate coupling with charge line CL.

  Subsequently, the bit line BL is driven to the high level of the intermediate voltage level. As a result, the potentials of word line WL and bit line BL become equal, and access transistor AT is rendered non-conductive. Even when the precharge node PN is the source node of the access transistor AT, the voltage level of the precharge node PN is lower than the voltage level of the word line WL by the threshold voltage of the access transistor AT. The rise is suppressed.

  In this state, the voltage level of the charge line CL is raised. As the voltage of charge line CL rises, the voltage level of precharge node PN rises, and access transistor AT becomes completely non-conductive (the voltages of bit line BL and word line WL are equal and the gate-source voltage is the same). 0V). Accordingly, precharge node PN (impurity region 12) enters a floating state, and the voltage level rises to the H level of power supply voltage VDD level due to gate coupling. At this time, the voltage level of storage node SN, that is, storage transistor ST is in a state where the voltage level of its body region is the ground voltage level and the threshold voltage is high. Therefore, even if the voltage level of the charge line CL rises, both the precharge node PN and the source line SL become H level, the storage transistor ST has almost no channel, and there is no shield layer for capacitive coupling. . Therefore, channel blocking is not performed, and the voltage level of storage node SN rises as the voltage level of charge line CL rises due to this capacitive coupling.

  That is, the holes supplied from the source line SL to the storage node SN are not emitted to the bit line BL but are accumulated in the storage node SN. As a result, a state of storing data “1” is formed.

(5) Reading operation of data “1” (1R):
At the time of data reading, bit line BL is set to L level and word line WL is set to high level for the selected memory cell. In response, access transistor AT is rendered conductive. Charge line CL is at H level. Holes are accumulated in storage node SN, and the threshold voltage of storage transistor ST is in a low state. Therefore, a channel is formed in channel forming region 73a shown in FIG. 6 below charge line CL, and a large current flows from source line SL to bit line BL via storage transistor ST and access transistor AT. The amount of current flowing to the bit line BL is suppressed to a relatively small value because the voltage level of the word line WL is an intermediate voltage level, and a large current is prevented from flowing. By detecting this current, data “1” can be read.

(6) Data “1” holding operation (1H):
In this holding operation, the levels of the bit line BL and the word line WL are held at the L level. In this state, access transistor AT is non-conductive (precharge node PN is at H level). Therefore, no current flows from the source line SL to the bit line BL, and data “1” is retained. At this time, even if the charge line CL is driven to the ground voltage level, even if the voltage level of the precharge node PN and the storage node SN is lowered due to capacitive coupling, the capacitance is increased again due to the rise of the voltage of the charge line CL. The original voltage level is restored by coupling.

  For the memory cells in the selected row and non-selected column, the corresponding word line is driven to a high level. At this time, the corresponding non-selected bit line BL is maintained at the high level in synchronization with the word line drive during the word line drive. As a result, the access transistor can be maintained in the OFF state, and the stored data can be reliably held.

  In the TTRAM cell, charges are accumulated in the floating body region. The time required for the stored charge to disappear due to leakage is sufficiently long and is considered to be almost refresh-free (based on DRAM). However, when performing the refresh operation, the stored data is read, and the potential of the bit line BL is changed in accordance with the read data, so that the stored data is rewritten and refresh is executed.

  As is apparent from the timing chart shown in FIG. 8, at the time of data reading, the stored data in the TTRAM cell is prevented from being destroyed, and a so-called rewrite period (restore period) in the DRAM cell is unnecessary. That is, even if the word line WL is driven to a non-selected state immediately after the sensing operation is completed, the stored data is not destroyed. In the present invention, the characteristics of the TTRAM cell are utilized to shorten the access time from each port in a dual port configuration in which orthogonal transformation is performed. In order to hold data, the body region of the SOI transistor is used, and a capacitor having a complicated shape is not used. Therefore, a memory cell can be formed using a standard CMOS process, and the memory cell can be miniaturized following the miniaturization of the process.

[Embodiment 1]
FIG. 9 is a diagram showing an electrical equivalent circuit of the orthogonal transformation memory cell MC used in the first embodiment of the present invention. In FIG. 9, memory cell MC includes a double drain storage transistor DDST for storing data, an access transistor ATA for port A, and an access transistor ATB for port B. The word line WLA and the bit line BLA of the port A are arranged orthogonal to the word line WLB and the bit line BLB of the port B, respectively. Therefore, the row and column of the access data string from one of port A and port B and the access data string of the other port are transposed.

  Double drain storage transistor DDST includes gate electrode G coupled to charge line CL, one conduction node (first conduction node) S coupled to source line SL, and drain coupled to access transistors ATA and ATB, respectively. Nodes (second and third conduction nodes) DNA and DNB. By configuring the data storage transistor with a double drain storage transistor DDST, one storage transistor can be provided in common for port A and port B and accessed in parallel from port A and port B. .

  Access transistor ATA for port A conducts in response to a signal potential on word line WLA (first word line), and electrically couples drain node DNA to bit line (first bit line) BLA. . The access transistor (third transistor) ATB for port B electrically connects the drain node DNB to the bit line (second bit line) BLB in response to the signal potential on the word line (second word line) WLB. Join. Connection nodes of these drain nodes DNA and DNB and access transistors ATA and ATB are precharge nodes PNA and PNB, respectively.

  As shown in FIG. 9, the memory cell MC is composed of three transistors, and its layout area can be reduced as compared with the SRAM cell. The basic configuration of memory cell MC is the same as that of the TTRAM cell shown in FIGS. 6 and 7 (for one port).

  FIG. 10 schematically shows a planar layout of double drain storage transistor DDST shown in FIG. Double drain storage transistor DDST is formed of a double drain SOI transistor. This double drain SOI transistor (double drain storage transistor) DDST includes N-type impurity regions (first and second impurity regions) 100a and 100b arranged opposite to each other with respect to the gate electrode 102, and a short side of the gate electrode 102. Includes an N-type impurity region (third impurity region) 101 arranged separately from these impurity regions 100a and 100b. These N-type impurity regions 100 a, 100 b and 101 are formed in a self-aligned manner with respect to gate electrode 102. A P-type impurity region is disposed under the gate electrode 102, and a body region 103 is formed. Body region 103 is arranged to be connected to N-type impurity regions 100a, 100b and 101.

  In FIG. 10, impurity regions 100a and 100b may correspond to either drain node DNA or DNB shown in FIG. In FIG. 10, as an example, N-type impurity regions 100a and 100b are shown corresponding to drain nodes DNA and DNB, respectively.

  As shown in FIG. 10, the drain nodes 100 a and 100 b of the double drain storage transistor DDST are arranged facing each other with respect to the gate electrode 102. N-type impurity region 101 forms source node S and is connected to source line SL. Impurity regions 100a and 100b are coupled to corresponding access transistors ATA and ATB via precharge nodes PNA and PNB shown in FIG. Therefore, the length from the source node (impurity region 101) of double drain storage transistor DDST to one conduction node (node connected to the precharge node) of access transistors ATA and ATB can be made equal to each other. Thus, the wiring resistance / capacitance (channel resistance / channel capacity) can be made equal. Thus, data can be written / read accurately with the same operating characteristics when accessing port A and port B.

  FIG. 11 schematically shows a cross-sectional structure along line L11-L11 shown in FIG. In FIG. 11, N-type impurity region 101 and P-type body region 103 are formed on buried insulating film 104. An element isolation layer 105 is provided adjacent to the N-type impurity region 101, and an element isolation region 105 is provided adjacent to the body region (P-type impurity region) 103. The element isolation region 105 has, for example, a shallow trench isolation structure, and is completely isolated from adjacent cells (using a full trench isolation structure). The buried insulating film 104 is formed on the semiconductor substrate 106.

  A gate electrode 102 is formed on body region 103 via a gate insulating film (not shown). When gate electrode 102 is maintained at the H level, a channel is selectively formed on the surface (channel formation region) depending on whether holes are accumulated in charge accumulation region (not shown) of body region 103. .

  12 schematically shows a cross-sectional structure taken along line L12-L12 shown in FIG. In FIG. 12, N-type impurity regions 100 a and 100 b are arranged on both sides of body region 103. An element isolation region 105 is provided outside these N-type impurity regions 100a and 100b. A gate electrode 102 is disposed on body region 103 via a gate insulating film (not shown). Element isolation layer 105 is formed outside N-type impurity regions 100a and 100b.

  When a voltage is applied to gate electrode 102 and a channel is formed on the surface of body region 103, N-type impurity regions 100a and 100b are electrically coupled to have the same potential. Impurity regions 100a and 100b are precharge nodes, and are maintained at the power supply voltage level by a current from source line SL during standby.

  As shown in FIGS. 10 to 12, the double drain storage transistor DDST is formed of an SOI transistor, like the storage transistor of the single port TTRAM cell. Therefore, charges can be stored in body region 103, and data can be stored by setting the threshold voltage of double drain storage transistor DDST in accordance with stored data. The applied voltage sequence of each signal line at the time of data writing and reading is the same as the applied voltage sequence at the time of accessing the single-port TTRAM cell shown in FIGS. 6 and 7 for each port.

  FIG. 13 is a signal waveform diagram showing an operation during read access from port A and port B to one memory cell. A read access operation for memory cell MC shown in FIG. 9 will be briefly described below with reference to FIG.

  Storage node SN is maintained at the H level or the L level according to the stored data, and the threshold voltage of double drain storage transistor DDST is in a low state or a high state according to the stored data.

  At the time of data reading, bit line BL is maintained at L level (ground voltage level). In this state, the word line WLA of the port A is driven to the selected state. Accordingly, the voltage level of precharge node PN (PNA, PNB) decreases. Charge line CL is maintained at the H level. The voltage level of storage node SN is H level or L level according to the stored data and does not change.

  The current flowing through the bit line BLA is sensed by a sense amplifier (read circuit) not shown. In this case, sense amplifier activation signal SENA is activated, and internal read data Dout is determined as internal data QA at time ta. When internal data QA is determined at time ta, word line WLA can be driven to a non-selected state. That is, since no capacitor is used in the memory cell MC, a restore operation for rewriting the charge flowing out from the capacitor into the capacitor is unnecessary. Therefore, word line WLA can be driven to a non-selected state immediately after data reading.

  When the word line WLA is driven to a non-selected state, the precharge node PNA (PNB) also returns to the original voltage level (H level). Since precharge nodes PNA and PNB are connected to bit line BL (BLA, BLB) at the ground voltage level at the time of data reading, the voltage levels thereof are lowered. Therefore, the word line WLB of the port B can be driven to the selected state at time tb without waiting for the precharge node PNA to return to the original voltage level. Usually, in the orthogonal transform operation, reading is performed after all the target data is stored in the memory. However, each access cycle can be shortened, and data for orthogonal transformation can be stored and read at a high speed. Accordingly, an orthogonal transformation operation can be performed at a high speed.

  FIG. 14 schematically shows a planar layout in the case where memory cells according to the first embodiment of the present invention are arranged in 2 rows and 2 columns. In FIG. 14, active layers 110 a and 110 b are provided at intervals with a continuous extension along the X direction. Active layers 110a and 110b include both an impurity region constituting a source and a drain and an impurity region constituting a body region. Active regions 111a, 111b, 111c and 111d extending in the Y direction are provided for this active layer 110a. These active regions 111a to 111d are electrically connected to the active layer 110 through body regions, respectively. Therefore, these active regions 110a to 111d include both the impurity region and the body region, and are connected to the active layer 110a.

  Similarly, active regions 111e, 111f, 111g, and 111h extending in the Y direction are provided for the active layer 110b. These active regions 111e-111h are similarly connected to the active layer 110b. The active layer 110a, the active regions 111a to 111d, the active layer 110b, and the active regions 111e to 111h are arranged in mirror symmetry with respect to their central axes.

  A gate electrode wiring 112a partially extending in the X direction is provided so as to cross the active region 111a. Further, the gate electrode wiring 112b is arranged adjacent to the active layer 110a so as to cross the active region 111d along the X direction so as to cross the active region 111d along the X direction. Similarly, a gate electrode wiring 112c is provided so as to cross the active region 111e along the X direction and adjacent to the active layer 110b. A gate electrode wiring 112d is provided adjacent to the active layer 110b so as to cross the active region 111h along the X direction.

  First-layer metal wirings (conductive layers) 114a to 114f are provided extending continuously along the X direction and spaced from each other. First layer metal interconnection 114a is electrically coupled to active regions 111b and 111c via contacts 120a and 120b. This first layer metal interconnection 114a forms source line SL and transmits a fixed voltage (power supply voltage). First layer metal interconnection 114b is electrically connected to gate electrode interconnections 112a and 112b via contacts 120c and 120d, respectively. This first layer metal interconnection 114b forms a word line WL1A for transmitting a word line selection signal. Therefore, although gate electrode wirings 112a and 112b are arranged along the X direction and separated from each other, they are electrically coupled to each other by first layer metal wiring 114b.

  First layer metal interconnection 114c is electrically connected to active layer 110a (active region AR3) through contact 120e. This first layer metal interconnection 114c constitutes bit line BL1B. The first layer metal wiring 114d is electrically connected to the active layer 110b via a contact 120f at the center along the X direction in the figure. This first layer metal interconnection 114d constitutes bit line BL2B.

  First layer metal interconnection 114e is electrically connected to gate electrode interconnections 112c and 112d through contacts 120g and 120h, respectively. This first layer metal interconnection 114e constitutes word line WL2A. First layer metal interconnection 114f is electrically connected to active regions 111f and 111g via contacts 120i and 120j. This first layer metal interconnection 114f forms source line SL and transmits a fixed voltage (power supply voltage).

  Gate electrode interconnections 116a and 116b are arranged along the Y direction so as to cross active layers 110a and 110b. These gate electrode wirings 116a and 116b are arranged to extend between first-layer metal wirings 114a and 114f constituting source line SL. Between these gate electrode wirings 116a and 116b, gate electrode wirings 116b and 116c are arranged extending continuously in the Y direction.

  Further, second layer metal interconnections 118a-118f are arranged extending continuously along the Y direction and spaced from each other. Second-layer metal interconnection 118a is electrically connected to active region 111a through via / contact 122a, and electrically connected to active region 111e through via / contact 122e. This second layer metal interconnection 118a constitutes bit line BL1A.

  Second layer metal interconnection 118b is arranged in alignment with gate electrode interconnection 116a, and is electrically connected to gate electrode interconnection 116a through via / contact 122c. This second layer metal interconnection 118b constitutes charge line CL1, and transmits a charge line drive signal to the gate of the storage transistor constituted by gate electrode interconnection 116a.

  Second-layer metal interconnection 118c is arranged in parallel with gate electrode interconnection 116b, and is electrically contacted between them in a region not shown. Similarly, the second layer metal wiring 118d is arranged in parallel with the gate electrode wiring 116c, and is electrically connected to the gate electrode wiring 116c in a region not shown. These second layer metal interconnections 118c and 118d constitute word lines WL1B and WL2B, respectively. A so-called word line shunt structure is realized by these gate electrode wiring and second layer metal wiring.

  Second-layer metal interconnection 118e is arranged in alignment with gate electrode interconnection 116b in plan view, and is electrically connected to gate electrode interconnection 116b through via / contact 122d. Second-layer metal interconnection 118e forms charge line CL2 and transmits a charge line drive signal. Second-layer metal interconnection 118f is electrically connected to active regions 111d and 122f through a via / contact. Second-layer metal interconnection 118f forms bit line BL2A.

  The word lines WL1A and WL2A and the bit lines BL1A and BL2A are used when accessing from the port A. On the other hand, the word lines WL1B and WL2B and the bit lines BL1B and BL2B are used when accessing from the port B.

  Memory cell MC is provided by a rectangular region defined by contacts 120a and 120e and via / contacts 111a and 116a, as indicated by a broken line region in FIG. The double drain storage transistor is formed by active regions (first and second active regions) AR1 and AR2 in the active layer 110a, a gate electrode wiring 116a, and an active region 111b. The active region 111b is a source region, and the active regions AR1 and AR2 are drain regions. An access transistor for port A is formed by active region AR1, active region 121a, gate electrode interconnection 112a, and first layer metal interconnection 114b. The access transistor for port B is formed by active region AR2, gate electrode interconnection 116b, second layer metal interconnection 118c, and active region AR3 of active layer 110a electrically connected to contact 120a.

  The gate electrode of the port A access transistor is formed of a separate gate electrode layer. On the other hand, the gate electrode of the access transistor for port B is formed by a gate electrode wiring 116c extending continuously along the Y direction. However, this gate electrode wiring is electrically connected to the upper metal wiring at a predetermined interval to form a shunt structure, and a word line selection signal at the time of access from port A and at the time of access from port B The propagation speeds of these are similar, and there is no particular difference in operating characteristics.

  The layout of the memory cell MC shown in FIG. 14 is arranged in mirror symmetry along the Y direction, and is repeatedly arranged in mirror symmetry along the X direction.

  By arranging the word lines WL1A and WL2A for the port A and the bit lines BL1B and BL2B for accessing the port B on both sides of the active layers 110a and 110b, respectively, the port without changing the pitch of the first layer metal wiring A metal wiring for B access and a metal wiring for port B access can be arranged.

  Further, a charge line CL1 is arranged between the port A access bit line BL1A and the port B access word line WL1B, and this arrangement is mirror-symmetrically repeated along the X direction, thereby allowing the port A access. The bit line and the word line for port B access can be realized by the second layer metal wiring at substantially the same pitch.

  Further, by forming the gate electrode of the port A access transistor with the gate electrode wirings that are individually separated, the collision between the gate electrode of the charge transistor and the gate electrode of the port A access transistor is prevented, The bit line for port A access and the bit line for port B access can be arranged orthogonally.

  FIG. 15 is a diagram showing an electrical equivalent circuit of the planar layout of the memory cell shown in FIG. In FIG. 15, memory cells MCa-MCd are arranged in 2 rows and 2 columns aligned in the X direction and the Y direction. Each of memory cells MCa-MCd includes a double drain storage transistor DDST, an access transistor ATA for port A access, and an access transistor ATB for port B access.

  Drain nodes DNA and DNB of double drain storage transistor DDST are connected to precharge nodes PNA and PNB, respectively. Source lines SL extending in the X direction are connected to the source nodes of the double drain storage transistors DDST of the corresponding memory cells, respectively. Word line WL1A is connected to the control electrode (gate) of access transistor ATA of memory cells MCa and MCb aligned in the X direction, and word line WL2A is connected to the gate of access transistor ATA of memory cells MCc and MCd aligned in the X direction. Connected. Bit line BL1B is connected via a contact common to access transistors ATB of memory cells MCa and MCb, and bit line BL2B is connected via a contact common to access transistors ATB of memory cells MCc and MCd.

  Word line WL1B is commonly connected to the gates of access transistors ATB of memory cells MCa and MCc aligned in the Y direction, and word line WL2B is commonly connected to the gates of access transistors ATB of memory cells MCb and MCd aligned in the Y direction. Connected to.

  Bit line BL1A is electrically connected to the conduction node of access transistor ATA of memory cells MCa and MCc aligned in the Y direction, and bit line BL2A is electrically connected to the conduction node of access transistor ATA of memory cells MCb and MCd. Connected.

  Charge line CL1 is connected to the gates of double storage transistors DDST of memory cells MCa and MCc aligned in the Y direction, and charge line CL2 is connected to the gates of double storage transistors DDST of memory cells MCb and MCd aligned in the Y direction. Is done.

  When accessing from port A, the word line of port A, for example, word line WL1A is selected, and access transistor ATA is rendered conductive in memory cells MCa and MCb. Accordingly, bit lines BL1A and BL2A are coupled to precharge node PNA of corresponding double drain storage transistor DDST, respectively.

  On the other hand, when accessing from port B, the word line of port B, for example, word line WL1B is driven to the selected state. In this case, access transistor ATB is rendered conductive in memory cells MCa and MCc. Therefore, bit lines BL1B and BL2B are connected to precharge nodes PNB of the corresponding memory cells, respectively.

  Bit lines BL1 and BL2B and bit lines BL1A and BL2A are arranged in the orthogonal direction. Data transmitted along bit lines BL1B and BL2B is read along bit lines BL1A and BL2A. That is, the data word transmitted along the X direction is converted into a data word aligned along the Y direction and transferred. Therefore, the Y direction and the X direction are transposed by the port A and the port B, and orthogonal transformation can be realized.

  As shown in FIG. 15, charge line CL is arranged in parallel with B port word line WLiB. Therefore, when the B port word line WLiB (i = 1, 2,...) Is selected at the time of data writing, the corresponding charge line CLiB is selected, and the potential is determined at the timing shown in FIG. By changing, data can be written in parallel to the memory cells connected to the word line WLiB (the bit line potential is set according to the logical value of the write data).

  However, when the word line WLiA of the A port is selected, in order to write data in parallel to the memory cells connected to the word line WLiA, a plurality of bits corresponding to the number of bits of the write data are used. It is necessary to change the potential of the charge line CL in parallel. For example, when 32-bit data is written from the A port, the data bits are transferred to the 32 A port bit lines BLA, so that the potentials of the 32 charge lines need to be changed accordingly. At the time of writing from the A port, it is possible to write data by selecting the charge line CL according to the address of the selected A port bit line and changing its potential. The reduction of the peak current when driving the charge line can be dealt with by shifting the drive timing of the charge line CL.

  However, in this case, there may be a problem that the write access cycle of data from the A port becomes long, and a problem that the current consumption during the write access from the A port becomes high. When such a problem does not particularly affect the performance of the system, each of port A and port B is used as a port for writing / reading, and an orthogonal transformation circuit is formed by one orthogonal transformation memory. Can be realized.

  However, in the first embodiment, port A is used as a read-only port, and port B is used as a write-only port. This avoids the problem of a reduction in access time and an increase in current consumption during data writing.

  FIG. 16 schematically shows a configuration of orthogonal transform circuit 30 including the semiconductor memory device according to the first embodiment of the present invention. In FIG. 16, an orthogonal transformation circuit 30 (see FIG. 1) is connected to the system bus 7 via two orthogonal transformation memories 130a and 130b and the system bus I / F (interface) 24 shown in FIG. Memory cell mat / orthogonal memory interface (I / F) 132 coupled to the input / output interface (I / F) 56 of the memory cell mat 40 via the multiplexer (MUX) 26 shown in FIG. I / F) 134.

  Each of orthogonal transform memories 130a and 130b includes an orthogonal memory array in which the memory cells shown in FIGS. 14 and 15 are arranged in a matrix. The data bit width of the orthogonal transformation memories 130a and 130b is L bits in both the X direction and the Y direction. System bus / orthogonal memory I / F 132 is coupled to port B of orthogonal transformation memory 130a and to port A of orthogonal transformation memory 130b. A switching circuit (not shown) is provided between the orthogonal transformation memories 130a and 130b and the system bus / orthogonal memory I / F 132, and the connection path is switched according to the data transfer direction. That is, the system bus orthogonal memory I / F 132 sends L-bit width write data DTE in units of entries transferred from the processor or external memory (not shown) via the system bus to the port B of the orthogonal transformation memory 130a. And L-bit data DTE read from the port A of the orthogonal transformation memory 130b is transferred to the processor or the external memory via the system bus.

  Memory cell mat / orthogonal memory I / F 134 is coupled to port A of orthogonal transformation memory 130a and to port B of orthogonal transformation memory 130b. Memory cell mat / orthogonal memory I / F 134 transfers L-bit width data DTA read from port A of orthogonal transformation memory 130a to memory cell mat 40, and the memory cell mat transferred from the memory cell mat. Data DTA in address units is transferred to port B of the orthogonal transformation memory 130b. Therefore, port A and port B of orthogonal transformation memories 130a and 130b are used as a read port and a write port, respectively, and the data transfer direction of the ports in each of memories 130a and 130b is one direction.

  A main control circuit 136 is provided to control data input / output in the orthogonal transform circuit 30. The main control circuit 136 transfers the data DTE of entry unit of L bit width in accordance with an address signal and an access request signal supplied via the system bus / orthogonal memory I / F 132, and the system bus / orthogonal memory I / F 132, The switching circuit (not shown) and the operations of the orthogonal transformation memories 130a and 130b are controlled. That is, the main control circuit 136 couples the port A of the orthogonal transformation memory 130b to the system bus I / F 24 when transferring data to the processing device or the external memory via the system bus. The connection paths of these orthogonal memory I / Fs 132 and 134 are set so that the port B of 130b is coupled to the memory cell mat via the MUX 26. Therefore, when data is transferred from the memory cell mat to the processing device (processor) or the external memory via the system bus, the orthogonal transformation memory 130b is used.

  When transferring data from a processing device (processor) or an external memory to a memory cell mat in the arithmetic device, port B of the orthogonal transformation memory 130a is coupled to the system bus via the orthogonal memory I / F 132, and The port A of the orthogonal transformation memory 130a is coupled to the memory cell mat via the orthogonal memory I / F 134. Therefore, when data is written to the memory cell mat, data is transferred using the orthogonal transformation memory 130a.

  The main control circuit 136 performs the following operation control when data is written, that is, when data from an external device is transferred via the system bus 7 and then transferred to the memory cell mat 40. . In the orthogonal transformation memory 130a, when transfer data is stored in all memory cells via the port B, the memory cell mat / orthogonal memory I / F 134 is controlled, and data DTA in units of addresses is sent from the port A of the orthogonal transformation memory 130a. Are sequentially transferred.

  Conversely, when data is transferred from the memory cell mat 40 to the external device via the system bus 7, the main control circuit 136 follows the transfer request from the memory cell mat / orthogonal memory I / F 134 from the memory cell mat 40. The L-bit width data DTA transferred via the multiplexer (MUX) 26 is sequentially written to the orthogonal transformation memory 130b via the port B. When the writing of data to the orthogonal transformation memory 130b via the port B is completed (when the orthogonal transformation memory 130 is full), the main control circuit 136 sets the system bus / orthogonal memory I / F 132 to The data DTE for each entry is sequentially read from the port A of the orthogonal transformation memory 130b and transferred onto the system bus 7 via the system bus I / F 24.

  Therefore, even when ports A and B are used as read-only ports and write-only ports in orthogonal transform memories 130a and 130b, orthogonal transform is performed between the external device and the memory cell mat. Data transfer. Although two memories are used in the orthogonal transformation circuit 30, the memory cells of these memories 130a and 130b are composed of three transistors, and the increase in the occupied area of the orthogonal transformation circuit 30 is sufficiently suppressed. Is done.

  In the above description, the switching between the ports of the orthogonal transformation memories 130a and 130b is switched using the switching circuit. However, the connection between the ports A and B of the memories 130a and 130b may be set by giving a port enable signal to the orthogonal transform memories 130a and 130b.

  FIG. 17 is a diagram more specifically showing the internal configuration of orthogonal transform memories 130a and 130b shown in FIG. In FIG. 17, each of orthogonal transform memories 130a and 130b performs read access from port A with orthogonal memory array 140 in which memory cells MC are arranged in a two-dimensional array aligned in the X and Y directions. Port AX decoder 142A and port A sense amplifier circuit 144A, and a port BX decoder 142B and a port B write drive circuit 144B for write access via port B. As shown in parentheses in FIG. 17, a write drive circuit is further provided in port A sense amplifier circuit 144A according to the contents of bad sew allowed for port A and port B, and port B write drive circuit In 144B, a sense amplifier circuit is provided (this configuration will be described later).

  The port AX decoder 142A drives the addressed word line WLA to the selected state according to the address signal AXA when the port A access enable signal ENA is activated. At the time of data reading, this port AX decoder 142A drives the addressed word line WLA to the selected state while maintaining all the charge lines CL at the H level. Port A is a read-only port, and write access from port A is not performed.

  When accessing from port B, access enable signal ENB for port B is activated. This access from port B is a write access, and port BX decoder 142B drives word line WLiB and charge line CLi of the corresponding row in accordance with address signal AXB. At this time, the voltage level of the B port bit line is driven by the port B write drive circuit 144B in accordance with the write data. Thereby, data is written to the memory cell connected to the selected word line WLiB.

  Here, it is assumed that the bit width of the data is equal to the memory cell connected to one word line. When the bit width of data is smaller than the number of memory cells connected to one word line, the bit line is selected by the Y decoder and coupled to the port A sense amplifier circuit 144A or the port B write drive circuit 144B.

  In the configuration shown in FIG. 17, write access from port A is prohibited. In the case of permitting data writing from port A when accessing from port A, the following configuration is used. As shown in parentheses in FIG. 17, a write drive circuit is also provided for port A. When the access enable signal ENA for the port A is activated, and the access to the port A is a write access, the port BX decoder 142B operates in accordance with the port A write access enable signal (for example, WENA; not shown). In synchronization with the word line selection of the AX decoder 142A, all the charge lines CL are driven in one shot in parallel (when the data bit width is equal to the memory cell connected to one word line). In accordance with activation of access enable signal ENA from port A, port AX decoder 142A drives corresponding word line WLA of orthogonal memory array 140 to a selected state in accordance with address signal AXA. As a result, the voltage of the charge line CL is changed for the memory cells connected to the word line WLiA, and the voltage of the selected bit line is changed via the port A write drive circuit (not shown) in parallel to the memory cells. Set and write data. At this time, the peak current can be reduced by shifting the voltage drive timing of all the charge lines CL.

  If read access from port B is also allowed, a sense amplifier circuit is provided for port B as shown in parentheses in FIG. At the time of reading, all the potentials of charge lines CL are at H level, a word line is selected by port BX decoder 142B, and data of bit line BLB is read by a port B sense amplifier circuit.

  Port A sense amplifier circuit 144A reads and transfers data of L-bit width in parallel with data of bit line BLA of orthogonal memory array 140 at the time of read access of port A. The port B write drive circuit 144B transfers L-bit data to the bit line BLB of the orthogonal memory array 140 during data transfer via the port B.

  When memory cells MC are arranged in L rows × L columns in orthogonal memory array 140, port A sense amplifier circuit 144A and port B write drive circuit 144B do not perform bit line selection and are parallel to the corresponding bit lines. Then, data transfer (write / read) is executed. However, if the input / output data bit width and the number of bit lines of the orthogonal memory array 140 are different, column selection circuits may be provided for port A and port B. In place of this, a circuit for converting the bus width may be provided at port A or port B (data transfer is performed by converting the bus width using a buffer memory). Therefore, a bit line selection circuit (Y decoder or the like) is provided as appropriate according to the transfer data bit width.

  FIG. 18 is a diagram more specifically showing the arrangement of the X decoder and sense amplifier / write drive circuit of orthogonal transform memory 130 shown in FIG. FIG. 18 representatively shows memory cells MC arranged in 2 rows and 2 columns. In FIG. 18, port AX decoder 142A includes word line drivers (WL drivers) WDA1 and WDA2 provided corresponding to word lines WL1A and WL2A, respectively. These WL drivers WDA1 and WDA2 drive corresponding word lines WL1A and WL2A to a selected state in accordance with port A address signals (or decode signals) AXA1 and AXA2, respectively. Port A sense amplifier circuit 144A includes sense amplifiers SWA1 and SWA2 provided corresponding to bit lines BL1A and BL2A, respectively. Sense amplifiers SWA1 and SWA2 read data by detecting currents flowing through corresponding bit lines BL1A and BL2A when activated.

  The port BX decoder 142B includes word line drivers (WL drivers) WDB1 and WDB2 provided corresponding to the word lines WL1B and WL2B, and charge line drivers (CL drivers) CLD1 provided corresponding to the charge lines CL1 and CL2, respectively. And CLD2. When accessing from port B, word line drivers WDB1 and WDB2 drive corresponding word lines WL1B and WL2B to a selected state in accordance with address signals (or decode signals) AXB1 and AXB2. Charge line drivers CLD1 and CLD2 perform one-shot drive on the charge lines (CL1, CL2) corresponding to the addressed word line in accordance with port B address signals AXB1 and AXB2 during write access from port B. In read access from port A, charge line drivers CLD1 and CLD2 maintain charge lines CL1 and CL2 at H level, respectively.

  In the case where write access is permitted also for port A, the following configuration is used. That is, like the port B, a write driver is provided for the port A bit line BLA. When the port A write activation signal (WENA) is activated, the charge line drivers CLD1 and CLD2 drive the charge lines CLD1 and CLD2 in parallel by one-shot regardless of the port B address signals AXB1 and AXB2. . In this case, for example, when the word line WL1A is driven to the selected state by the word line driver WDA1, the charge lines CL1 and CL2 are driven one-shot (the drive timing may be shifted), and the bit lines BL1A and BL2A are connected to the port. In accordance with the write data transferred from the A write driver, data is written in parallel to the memory cells MC connected to the word line WL1A.

  During the write operation from port A, all other word lines WL2A, WL1B and WL2B are not selected even if charge lines CL1 and CL2 are all driven by one shot. Therefore, parallel data writing to the memory cell group connected to word line WL1A is executed, and the remaining non-selected memory cells simply hold data, and the destruction of stored data is prevented. Thereby, even when the charge line CL is arranged in parallel with the word lines WLB (WB1B, WL2B), the data arrangement can be reliably transposed at the port A and the port B.

  In the orthogonal transform memory 130 shown in FIG. 17, port A and port B are used as a data read port and a data write port, respectively. However, as described above, the port B may be used as a port for writing and reading. When read access is permitted for port B, as with port A, sense amplifiers are provided for port B bit lines BL1B and BL2B.

  As described above, according to the first embodiment of the present invention, a memory cell for orthogonal transformation is configured by three transistors based on a TTRAM cell. Therefore, the area occupied by the memory cell can be reduced, and the storage capacity can be increased without increasing the chip size. Further, following the miniaturization of the process, the scaling of the memory cell is easy, the size of the memory cell can be further reduced, and an orthogonal transformation memory that operates at high speed with low power consumption can be realized. Further, the data in the memory cell is nondestructive reading, and each access cycle can be shortened. Accordingly, high-speed writing / reading can be performed, and orthogonal transformation operation can be performed at high speed.

[Embodiment 2]
FIG. 19 schematically shows a planar layout of the memory cell according to the second embodiment of the present invention. In FIG. 19, the memory cell MC is formed in a rectangular active region AR. This active region AR is divided into three sub-active regions ARa, ARb and ARc by a gate electrode GTd extending in the Y direction and a gate electrode GTc extending in the X direction. In the sub active region ARa, a bowl-shaped gate electrode GTa is disposed. The gate electrode GTb is formed in a bowl shape symmetrically with respect to the gate electrode GTa and the gate electrode GTc. The gate electrodes GTc and GTd continuously extend and are arranged in a T shape, and the gate electrode GTd at the base and the gate electrode GTc at the leg constitute a gate electrode of the storage transistor. Gate electrodes GTa and GTb each constitute a gate electrode of an access transistor. In the planar layout shown in FIG. 19, in active regions ARa and ARb, regions between gate electrodes GTc and GTd and gate electrodes GTa and GTb constitute precharge nodes, respectively. Therefore, a double drain storage transistor can be realized even using a planar layout as shown in FIG.

  Further, the gate width (channel width) of the access transistor and the storage transistor can be increased, and a transistor having a sufficiently large current driving capability can be formed even when the transistor is miniaturized.

  FIG. 20 is a diagram showing an electrical equivalent circuit of memory cell MC shown in FIG. In FIG. 20, a memory cell MC has a first drain node electrically connected to source line SL, and a double drain storage having second and third conduction regions forming two precharge nodes PN1 and PN2. Transistor DDST and access transistors ATA and ATB connected to precharge nodes PN1 and PN2 respectively are included.

  Access transistor ATA couples precharge node PN1 to bit line BLA according to the signal potential on word line WLA. Access transistor ATB electrically connects precharge node PN2 to bit line BLB in accordance with the signal potential on word line WLB. The word lines WLA and WLB are orthogonal to each other, and the bit lines BLA and BLB are orthogonal to each other. A port word line WLA and B port bit line BLB are arranged in parallel, and B port word line WLB and A port bit line BLA are arranged in parallel. When accessing from port A, word line WLA and bit line BLA are used, and when accessing from port B, word line WLB and bit line BLB are used. Thereby, orthogonal transformation of the data array can be performed at the time of access from port A and port B.

  FIG. 21 shows a planar layout of the memory cell array according to the second embodiment of the present invention. In FIG. 21, the active regions AR10, AR11, and AR12 are arranged along the Y direction and spaced apart from each other. In addition, the active regions AR13 and AR14 are arranged with an interval in alignment along the Y direction. Active regions AR10-AR12 and active regions AR13 and AR14 are arranged with their positions shifted along the Y direction so that access transistors for the same port are aligned along the Y direction.

  In each active region, gate electrode wirings GTa, GTb and GTc are arranged. The gate electrode GTd constituting the pedestal shown in FIG. 19 is formed by polysilicon wirings 148a and 148a extending continuously along the Y direction, respectively. By continuously disposing the base portion in the T-shaped gate electrode structure, the source line SL and the charge line CL can be disposed in parallel to the gate of the storage transistor along the Y direction. As a result, even if the source line SL for the source region and the charge line CL for the gate that are commonly arranged in the drain of the double drain storage transistor are arranged using the wiring of the same wiring layer, the layout is surely complicated. The source contact and the gate contact can be arranged without any problem.

  The first layer metal wirings 150a to 150d and the first layer metal wirings 152a and 152b are arranged spaced apart from each other and extend continuously along the X direction. First-layer metal interconnection 150a forms bit line BL2B and is electrically connected to sub-active region ARb of lower-layer active region AR13 via contact CT5. First-layer metal interconnection 150b forms bit line BL1B and is electrically connected to a sub-active region (ARb) of active region AR10 via contact CT1.

  First-layer metal interconnection 150c forms bit line BL4B, and is electrically connected to sub-active region ARb of active region AR14 through contact CT6. First-layer metal interconnection 150d forms bit line BL3B, and is electrically connected to sub-active region ARb of active region AR11 through contact CT2.

  First-layer metal interconnection 152a constitutes word line WL2A, and is commonly connected to gate electrodes (wiring) GTa arranged in active regions AR11 and AR13 through contact CT3 arranged in the inter-cell isolation region. The

  First metal interconnection 152b constitutes word line WL3A and is connected in common to gate electrodes (wiring) GTa arranged in active regions AR12 and AR14 via contact CT4 arranged in the inter-cell isolation region. .

  Second-layer metal interconnections 162a and 162b are arranged so as to be parallel to and partially overlap with polysilicon gate electrode interconnections 148a and 148b, respectively, along the Y direction. These second layer metal interconnections 162a and 162b constitute charge lines CL1 and CL2, respectively, and are electrically connected to polysilicon gate electrode interconnections 148a and 148b arranged in the lower layer by contacts in regions not shown. The

  Second layer metal interconnections 164a and 164b are arranged outside the second layer metal interconnections 162a and 162b constituting charge lines CL1 and CL2, respectively, along the X direction. Second-layer metal interconnection 164a forms source line SL, and is electrically connected to sub-active regions ARc of active regions AR10, AR11, and AR12 through via / contacts CV1, CV2, CV3, and CV4, respectively.

  Second-layer metal interconnection 164b also constitutes source line SL and is electrically connected to sub-active regions ARc of active regions AR13 and AR14 through via / contacts CV11, CV12, CV13, and CV14, respectively.

  Between the second layer metal interconnections 162a and 162b, second layer metal interconnections 166a, 168a and 166b are arranged extending continuously along the Y direction and spaced from each other. Second-layer metal interconnection 166a forms bit line BL3A, and is electrically connected to lower-layer active regions AR11 and sub-active regions (ARa) of AR11 via via / contacts CV5 and CV6. Second-layer metal interconnection 166b forms bit line BL2A and is electrically connected to sub-active regions (ARa) of active regions AR13 and AR14 through via / contacts CV9 and CV10, respectively.

  Second-layer metal interconnection 168a constitutes word line WL2B, and is electrically connected to gate electrode (wiring) GTb in sub-active regions (ARb) of active regions AR10-AR14 through via / contact CV7.

  Via / contacts CV7 and CV8 of word line WL2B and contacts CT3 and CT4 of word lines WL2A and WL3A are alternately arranged in the Y direction. Thereby, two access transistors formed in each of active regions AR10-AR14 are electrically coupled to word lines WLA and WLB alternately in the Y direction. By shifting the position of the active region and aligning the transistors of the same port along the X direction, the layout of the port A word line WLA and the port B word line WLB arranged orthogonally can be reduced. The contact can be formed without adversely affecting the bit line arrangement. Further, the word line contact is arranged on the memory cell isolation region, and an increase in the layout area of the memory cell is suppressed.

  The planar layout shown in FIG. 21 is repeatedly arranged along the X direction and the Y direction. That is, the planar layout of the memory cells MC is repeatedly arranged in mirror symmetry along the X direction, and the same layout is repeatedly arranged as the layout of the memory cells along the Y direction. The wiring patterns of this wiring layout are all linear patterns, can be formed accurately during patterning, can reliably draw a memory cell pattern even when a process cell is miniaturized, and process fineness The memory cell can be miniaturized following the miniaturization. The same applies to the memory cell arrangement of the first embodiment.

  FIG. 22 is a diagram showing an electrical equivalent circuit of the planar layout of the memory cell array shown in FIG. In FIG. 22, memory cells MC10-MC14 are arranged in active regions AR10-AR14, respectively. The access transistors ATB for the port B are arranged in alignment along the X direction, and the access transistors ATA for the port A are arranged in alignment. In the Y direction, access transistors ATB and ATA are alternately arranged. Therefore, the planar layout of the memory cells MC is arranged in mirror symmetry along the X direction, and the same pattern is repeatedly arranged along the Y direction.

  The gate of access transistor ATB of memory cells MC11, MC12, MC13 and MC14 is connected to word line WL2B. On the other hand, gates of access transistors ATA of memory cells MC11 and MC13 are connected to word line WL2A, and gates of access transistors ATA of memory cells MC12 and MC14 are connected to word line WL3A. Therefore, when accessing from port B, memory cells arranged in two rows along the Y direction are selected in parallel, and when accessing from port A, they are arranged in one row along the X direction. Memory cells to be selected are selected in parallel.

  That is, when accessing from port B, for example, when word line WL2B is driven to the selected state, access transistor ATB is rendered conductive in each of memory cells MC10-MC14, and data is transmitted via bit lines BL1B, BL2B, BL3B, BL4B. Is written. On the other hand, when accessing from port A, for example, when word line WL2A is selected, access transistor ATA is rendered conductive in memory cells MC11 and MC13, and data reading is executed via bit lines BL3A and BL2A. Here, as an example, as in the first embodiment, port A is used as a read-only port, and port B is used as a write-only port.

  Therefore, the memory cell array selected differs between when accessing from port A and when accessing from port B. When accessing from port A, data is written / read through access transistors ATA of memory cells arranged in a line along the X direction. On the other hand, when accessing from port B, access transistors ATB of memory cells arranged in two rows along the Y direction are turned on.

  In this case, when port A is used as an IO port for writing and reading, all charge lines CL are driven to a selected state at the time of write access from port A. In this case, the selection timing of each charge line may be shifted. At the time of write access from port B, regardless of the configuration of port A, the two charge lines corresponding to the selected word line are driven to the selected state. Therefore, the configurations of the port A and the port B are determined according to the access contents permitted for the ports A and B.

  FIG. 23 shows an arrangement of data bits in the memory cell array shown in FIGS. 21 and 22. In FIG. As shown in FIG. 23, when B port word line WLB is selected, memory cells arranged in two columns corresponding to word line WLB are selected. The data bit groups include an odd bit group WPBO in which data is written through odd bit lines BL1B and BL3B, and an even bit group WPBE in which data is written through even bit lines BL2B and BL4B. Composed. On the other hand, when word line WLA is selected, all data bit groups WPA arranged in alignment along word line WLA are selected in parallel and read.

  For example, when word line WLA is selected and data read access is performed in units of word addresses (external device or memory cell mat address), data bits of one word address are stored in all data bit groups WPA. In this case, when data read access is performed via word line WLA, adjacent bits 2i and 2i + 1 of all data bit groups WPA are accessed in parallel. Therefore, adjacent bit data of the same word is accessed. In the orthogonal transformation operation, it is necessary to convert a word serial and bit parallel data string into a bit serial and word parallel data string. For this purpose, the following configuration is used. That is, at the time of write access from the B port, bits of different data words are stored in the odd bit group WPBO and the even bit group WPBE. It is assumed that adjacent two bits of all word bit groups WPA of an access unit via port A store data of two word addresses. Thereby, the parallel storage of the bit parallel data of the word address and the transfer of the word parallel and bit serial data string can be performed, and the orthogonal transformation can be accurately performed. In this case, the word address of the B port designates the word line WLB and the odd / even bit line. The address of the A port designates the word line WLA.

  Alternatively, data of the same B port word address is stored in the odd bit group WPBO and the even bit group WPBE, and when accessing from the port A, the data bit is determined by the word line address and the odd / even bit line address. (Memory cell) is selected to perform read access.

  Further, in both port A and port B, even if the memory cell is first selected by the even bit line address and the address update is set so that the odd bit line address is accessed after all the even bit line addresses are accessed. Good. In this case, data word addressing is performed using the word line address and the bit line lower address bits.

  Charge lines CL1 and CL2 are arranged in parallel with word line WL2B. Therefore, as shown in FIG. 22, the selection mode during writing of charge lines CL1 and CL2 is set in accordance with the mode of the selected bit line. For example, when the word line WL2B is selected at the time of write access from the port B and the memory cell connected to the word line WLB is write-accessed, the charge lines CL1 and CL2 are driven in parallel.

  In the above description, port A is used as a read-only port. However, if data write access is permitted also at port A, a write driver is provided for the port A bit line. Further, the selection mode of the charge line is determined according to the bit line selection mode. For example, when the word line WL2A is selected, when writing is performed on the memory cell connected to the word line WL2A, all the charge lines are driven to the selected state, and writing is performed via a write driver (not shown). Perform access. In read access from port A and port B, charge line CL is fixed at the H level. Port B may be configured to perform both write and read access (providing read access to port B by providing a port B sense amplifier for each port B bit line). be able to).

  Therefore, as the overall configuration of the semiconductor memory device in the second embodiment, the configuration shown in the first embodiment with reference to FIGS. 17 and 18 can be used. Two charge lines are provided for one word line of port B, and when the corresponding port B word line is selected, the corresponding charge line is driven to a selected state according to the bit line access mode (write access) Time). Even when write access and read access are permitted for port A and port B, the configuration described above with reference to FIGS. 17 and 18 can be used.

  As described above, according to the second embodiment of the present invention, the memory cell is arranged in the rectangular active region, and the gate of the storage transistor has a T-shaped structure. Therefore, a sufficient channel width can be provided to the storage transistor and the access transistor even when the memory cell size is reduced, and a sufficiently large current can be driven even when the element is miniaturized. Thereby, the scaling of the memory cell can be easily performed following the miniaturization of the process. Further, as in the first embodiment, the access time can be shortened.

[Embodiment 3]
FIG. 24 schematically shows a planar layout of the memory cell array of the semiconductor memory device according to the third embodiment of the present invention. The active layer is arranged in a zigzag shape in which concave and convex portions are repeatedly arranged along the X direction. In the active layer, P-type impurity regions 192a and 192b in which P-channel MOS transistors are arranged are arranged in alignment along the X direction as active regions of the recesses, and P-type active regions 192c and 192d are arranged along the X direction They are arranged side by side. These P-type impurities 192a, 192b and 192c, 192d are connected to P-type body regions formed in the active regions 190a and 190b of the convex portions arranged adjacent to each other. A P-channel SOI transistor formed in these regions is used as a writing transistor, and charges are injected into the body region of the storage transistor. The arrangement of the other active regions is the same as the arrangement of the active regions of the memory cell shown in the first embodiment with reference to FIG. The only difference is that P-type impurity regions 192a and 192b are arranged to be displaced and connected to active regions 190a and 190b including N-type impurity regions.

  First layer metal interconnections 175a-175d are arranged extending continuously along the X direction and spaced apart from each other. First layer metal interconnection 175a constitutes bit line BL1B, and first layer metal interconnection 175b constitutes word line WL1A. First layer metal interconnection 175c constitutes bit line BL2B, and first layer metal interconnection 175d constitutes word line WL2A.

  Polysilicon gate wirings 170a-170d are arranged so as to cross each of P-type impurity regions 192a-192d along the Y direction. These polysilicon gate wirings 170a-170d are arranged so as to extend only in the region where the memory cells are formed. Polysilicon gate interconnections 170a and 170b are electrically connected to first layer metal interconnection 175b constituting word line WL1A via contacts 176a and 176b, respectively. Polysilicon gate electrode interconnections 170c and 170d are electrically coupled to second layer metal interconnection 175d constituting word line WL2A via contacts 176c and 176d, respectively. First-layer metal interconnections 175a and 175c constituting bit lines BL1B and BL2B are electrically connected to active regions 190a and 190b through contacts 196a and 196B, respectively. With the arrangement of the gate electrode for each memory cell, the memory cells aligned in the Y direction can be selected in parallel by the word line WLA.

  Polysilicon gate wirings 184a to 184d are arranged extending continuously from each other along the Y direction. Polysilicon gate interconnections 184a-184d are arranged extending continuously so as to cross active regions 190a and 190b, respectively.

  Second-layer metal interconnection 180a is arranged extending continuously along the Y direction so as to cross P-type impurity regions 192a and 192c. Second-layer metal interconnection 180a forms bit line BL1A and is electrically connected to P-type impurity regions 192a and 192c through via / contacts 197a and 197c, respectively.

  Second-layer metal interconnection 180b is arranged extending continuously along the Y direction so as to cross P-type impurity regions 192b and 192d. Second-layer metal interconnection 180b forms bit line BL2A and is electrically connected to lower P-type impurity regions 192b and 192d through via / contacts 197b and 197d, respectively.

  Second-layer metal interconnection 181a is arranged extending continuously in the Y direction so as to cross active region 190a, P-type impurity region 192a, active region 195c, and P-type impurity region 192c, and active region 190a , 190b and P-type impurity regions 192b and 192d, second-layer metal interconnection 181b is arranged extending continuously along the Y direction. These second layer metal interconnections 181a and 181b constitute source line SL. Second-layer metal interconnection 181a is electrically connected to regions adjacent to P-type impurity regions 192a and 192c of active regions 190a and 190b through via / contacts 195a and 195c, respectively. Second-layer metal interconnection 181b is electrically connected to regions adjacent to P-type impurity regions 192b and 192d of active regions 190a and 190b through via / contacts 195b and 195d.

  Second-layer metal wirings 182a, 183a, 183b and 182b are arranged in parallel with polysilicon gate wirings 184a-194d. These gate electrode wirings 184a-184d and second layer metal wirings 182a, 183a, 183b and 182b are electrically coupled in a region not shown, thereby forming a so-called “shunt structure”. Second layer metal interconnection 182a constitutes charge line CL1, and second layer metal interconnection 183a constitutes word line WL1B. Second layer metal interconnection 183b constitutes word line WL2B, and second layer metal interconnection 182b constitutes charge line CL2. These second layer metal wirings are continuously extended along the Y direction, and the source line SL and the charge line CL are arranged adjacent to each other, whereby a P channel SOI transistor for writing and a N line for reading are arranged. The channel SOI transistor can be operated with electrical isolation.

  In the arrangement of the memory cell array shown in FIG. 24, port A (word lines WL1A and WL2A and bit lines BL1A and BL2A) is used as a write-only port, and port B (word lines WL1B and WL2B, bit lines BL1B and BL2B). Is used as a read port (or read / write port). That is, the read port and the write port are individually provided in a fixed manner, and the direction in which data flows is constant.

  FIG. 25 schematically shows an arrangement of impurity regions of one memory cell in the arrangement of the memory cell array shown in FIG. In FIG. 25, P-type impurity region 192b includes high-concentration P-type regions 202a and 202b, and N-type region 204 arranged between P-type regions 202a and 202b. N-type region 204 forms the body region of the P-channel SOI transistor. A polysilicon gate wiring 170b is arranged across the N-type region 204. The polysilicon gate wiring 170b forms a word line WL1A.

  The active region 190a includes the high-concentration N-type regions 206, 207a, and 207b, the P-type region 203 disposed between the N-type regions 206 and 207a, and the P-type region disposed between the N-type regions 207a and 207b. 208 is included. P-type region 203 includes a region arranged adjacent to and in communication with P-type region 202b of P-type impurity region 192b. By disposing this P-type region with respect to both active region 190a and P-type impurity region 192b, the P-type transistor can be coupled to the body region of the storage transistor. Further, by disposing P-type region 202b adjacent to N-type region 206 constituting the source node of the storage transistor, even if source line SL is maintained at the power supply voltage level, this source line SL becomes P-type region 202b. To prevent the power supply voltage from being transmitted to the P-type region 202b. A second layer metal interconnection 182b constituting charge line CL2 is arranged to cross P type region 203. A polysilicon gate wiring 184c (second-layer metal wiring 183b) constituting the word line WL2B is disposed so as to cross the P-type region 208. N-type region 207b is electrically coupled to bit line BL1B, and P-type region 202a is electrically connected to bit line BL2A.

  FIG. 26 shows an electrically equivalent circuit of memory cell MC shown in FIG. In FIG. 26, memory cell MC includes two access transistors ATAP and ATB and a storage transistor STB that accumulates charges in the body region. Access transistor ATB is coupled between one conduction node (drain node) of storage transistor STB and bit line BL1B, and has its gate (control electrode) connected to word line WL2B. Access transistor ATAP is a P-channel SOI transistor, connected between the body region (storage node SN) of storage transistor STB and bit line BL2A, and its gate (control electrode) is connected to word line WL1A. The other conduction node of storage transistor STB is connected to source line SL.

  FIG. 27 shows signal waveforms at the time of data writing in memory cell MC shown in FIG. 25 and FIG. The data write operation shown in FIGS. 25 and 26 will be described below with reference to FIG.

  In the standby state, port A word line WL1A is at the power supply voltage level, and port A bit line BL2A is at the ground voltage level. Now, assume that the storage node SN (P-type region 203) is at the H level.

  Port B word line WL2B is at L level, and charge line CL2 is at H level. Therefore, no channel is formed in P type region 208 (body region) of access transistor ATB, and N type regions 207a and 207b are in an isolated state.

  Charge line CL2 is at the power supply voltage level, and P-type region 203 is maintained at a potential corresponding to the stored data. In this state, even when storage transistor STB is in the low threshold voltage state and turned on, the voltage levels of impurity regions 207a and 206 become the same voltage as the gate, and storage transistor STB is turned off. . Therefore, no channel is formed between the source line SL and the N-type region 207a, and the access transistor ATB is in an off state, and the source line SL and the port B bit line BL1B are in an isolated state.

  In the standby state, port A bit line BL2A is at the L level or a lower LL level, and is at a voltage level lower than the voltage level of word line WL1A. Therefore, no channel is formed in N type region 204 (access transistor ATAP is in an off state), and P type regions 202a and 202b are also in an isolated state.

  At the time of writing L data, first, the port A bit line BL2A is set to L level, and then the port A word line WL1A is driven to L level lower than the potential of the bit line BL2A. The L level of the port A word line WL1A may be the same as the voltage level of the port A bit line BL2A, or may be a lower voltage level. That is, the L level of the word line WL1A may be a ground voltage level or a negative voltage level. The L level of the bit line BL2A is preferably a ground voltage level, and the LL level is a negative voltage.

  In this state, the access transistor ATAP is turned on, and an inversion layer (channel) is formed in the N-type region 104 in FIG. Accordingly, the L level voltage of bit line BL2A is transmitted to P type region 203 via P type region 102b, the voltage level of P type region 203 (storage node SN) is set to L level, and L level data is stored. Written. After data writing is completed, the port A word line WL1A is driven to the H level and the port A bit line BL2A is driven to the LL level in the standby state.

  In writing H data, first, the bit line BL2A is driven from the LL level in the standby state to the H level. In this state, word line WL 1 A is at the H level, access transistor ATAP is off, and no channel is formed in N-type region 204. Next, the word line WL1A is driven to the L level. Accordingly, an inversion layer is formed in N type region 104 (access transistor ATAP is turned on), and the H level voltage on port A bit line BL2A is transmitted to P type region 203 via access transistor ATAP, and P The voltage level of mold region 203 (storage node SN) increases.

  After completion of writing, word line WL1A is again driven to H level (for example, power supply voltage level). Further, the bit line BL2A is set to an LL level lower than the L level of the word line WL1A, and the access transistor ATAP is set to a non-conductive state.

  Therefore, it is possible to set the voltage level of storage node SN by directly injecting charges from bit line BL2A to the body region (storage node SN) of storage transistor STB via access transistor ATAP. By this direct writing, the voltage of the body region (storage node SN) of storage transistor STB can be set reliably. In addition, after the word line WL1A is driven to the selected state, data can be written at high speed by charge injection from the bit line, and high speed writing is realized.

  FIG. 28 schematically shows signal waveforms at the time of data reading of the memory cells shown in FIGS. 25 and 26. In FIG. When data is read, access is performed via port B, so word line WL1A and bit line BL2A are maintained at the H level and the LL level, respectively. In this state, access transistor ATAP is nonconductive, and no channel is formed in N type region 204. Therefore, the body region of storage transistor STB (storage node SN of P-type region 203) and bit line BL2A are reliably separated.

  At the time of data reading, word line WL2B is driven to the H level. Bit line BL1B is precharged to L level. Accordingly, a channel is formed in P type region 208, and N type regions 207a and 207b are electrically connected (access transistor ATB is turned on). Charge line CL2 is maintained at the H level during data reading. Accordingly, also in P-type region 203, a channel is selectively formed according to the potential of the body region (storage node SN). Thereby, the storage transistor STB is selectively turned on, and a current corresponding to the stored data flows between the source line SL and the bit line BL1B. Data can be read by detecting the current of bit line BL1B. FIG. 28 shows that the potential of bit line BL1B rises when H data is read. This is because a sense amplifier that reads data includes a transistor whose gate is coupled to bit line BL1B and that compares the potential of bit line BL1B with a reference potential. A current comparison / detection type sense amplifier may be used.

  FIG. 29 schematically shows an electrically equivalent circuit of the arrangement of the memory cells in the memory cell array shown in FIG. In FIG. 29, memory cells MC11, MC12, MC21 and MC22 are arranged in 2 rows and 2 columns. Bit lines BL1B and word lines WL1A are provided for memory cells MC11 and MC21 arranged in alignment along the X direction, and bit lines are provided for memory cells MC12 and MC22 aligned in the X direction. BL2B and word line WL2A are provided. A source line SL, a charge line CL1, and a word line WL1B are provided for memory cells MC11 and MC12 aligned in the Y direction. Similarly, word line WL2B, charge line CL2, and source line SL are arranged for memory cells MC21 and MC22 aligned along the Y direction. For memory cells aligned in the X direction, bit lines BLA (BL1A, BL2A, BL3A) are individually arranged.

  FIG. 29 shows access transistors ATAP of memory cells MC31 and MC32. With this arrangement, when the word line WL1A is selected, data can be accessed via the bit lines BL1A, BL2A, and BL3A to the memory cells aligned along the X direction.

  On the other hand, for the bit lines BLB (BL1B, BL2B), the contacts are shared by adjacent memory cells along the X direction. The bit lines BLB (BL1B, BL2B...) Are arranged to be orthogonal to the word lines WLB (WL1B, WL2B). When the word lines WLB are selected, the bit lines BLB (BL1B, BL2B. Data can be accessed through line BLB.

  Port A access transistor ATAP is formed of a P-channel SOI transistor. Word lines WL1A and WL2A are changed between H level (power supply voltage) and L level (ground voltage or negative voltage), and the voltage difference between H level and L level of storage node SN is set to the power supply voltage level.

  Port A bit lines BL1A, BL2A and BL3A are set to L level during standby, L level during L level data writing, and H level during H data writing. By setting the bit lines BL1A to BL3A of the port A to the LL level and a voltage level lower than the L level during standby or non-selection, the following effects can be obtained. That is, even when the word line WL1A is driven to the L level in the selected state, the access transistors ATAP in the selected row and the non-selected column can be reliably maintained in the off state. In the memory cell of the non-selected row and the non-selected column, the access transistor ATAP is in a non-conductive state because the bit line BLA (BL1A, BL2A) is L level and the word line WLA (WL1A, WL2A) is H level. maintain. For a memory cell in a non-selected row and a selected column, even if the bit line potential is set to H level or L level according to the write data, the word line potential is at a voltage level higher than the bit line potential. Yes, the access transistor ATAP is kept off. Therefore, even when the bit width of data is smaller than the total number of bit lines, erroneous writing is prevented from occurring in a half-selected memory cell in which one of the word line and the bit line is selected. be able to.

  Charge line CL is not required to be one-shot driven at the time of data writing, and is always maintained at the H level (because gate coupling is not used). Therefore, as with the source line, the charge line CL only needs to be maintained at the power supply voltage level at all times. No charge line driver is required, and the circuit configuration is simplified.

  FIG. 30 schematically shows a whole structure of the semiconductor memory device according to the third embodiment of the present invention. 30, the semiconductor memory device includes a memory cell array 210 in which memory cells MC are arranged in a two-dimensional array aligned in the X direction and the Y direction. In the memory cell array 210, the word line WLA of port A and the bit line BLA of port A are arranged orthogonally, and the word line WLB of port B and the bit line BLB of port B are arranged orthogonally.

  In order to perform write access via port A, port A cell selection drive circuit 212, port A write circuit 214, and port A control circuit 216 are provided. The port A cell selection drive circuit 212 includes a circuit that selects the word line WLA. Port A write circuit 214 includes a write driver arranged corresponding to each bit line, and transmits a write voltage to bit line BLA of port A in accordance with external write data. The port A control circuit 216 controls the operations of the port A column selection drive circuit 212 and the port A write circuit 214 when accessing from the port A.

  In order to perform access from port B, port B cell selection drive circuit 218, port B read / write circuit 220, and port B control circuit 222 are provided. Here, a configuration in which port B is used as a port for performing write and read access is shown. The port B selection drive circuit 218 selects the word line WLB of the port B when accessing from the port B. Port B read / write circuit 220 includes a sense amplifier and a write driver provided corresponding to each bit line BLB. When data is written, internal write data is applied to bit line BLB according to write data D. Transmit and read data Q through a sense amplifier at the time of reading. Port B control circuit 222 drives port B cell selection drive circuit 218 and port B read / write circuit 220 when accessing from port B. The port A control circuit 216 and the port B control circuit 222 exchange signals indicating access states with each other. As a result, at the time of access from port A, after all necessary data is written in memory cell array 210, port B control circuit 222 reads the data. Conversely, data writing is executed from port A after access from port B is completed.

  Charge line CL and source line SL are maintained at the power supply voltage level. Therefore, it is not necessary to provide a charge line drive circuit in the port B cell selection drive circuit 218, control of charge line drive is simplified, and the layout area of the cell selection drive circuit 218 can be reduced.

  In the configuration shown in FIG. 30, port B is used for writing and reading data. However, the port B may be used as a read-only port that performs only data reading. One port is configured to be a write-only port (port A). Therefore, in order to configure the orthogonal transform circuit in the arithmetic processing system, it is necessary to use two memories as described in the first and second embodiments.

  FIG. 31 schematically shows a configuration of an orthogonal transform circuit using a memory cell according to the third embodiment of the present invention. In FIG. 31, the orthogonal transformation circuit 30 includes two orthogonal transformation memories 250 and 252. These orthogonal transformation memories 250 and 252 each have the configuration shown in FIG. 30, and port A and port B are used as write-only port W and read-only port R, respectively.

  For orthogonal transformation memories 250 and 252, switching circuits (MUX) 254 and 256 are provided for memory switching. In switching circuit 256, port S1 is coupled to memory cell mat orthogonal memory I / F 134, port S2 is coupled to read port R (port B) of orthogonal transform memory 252, and port S3 is written to orthogonal transform memory 250. Coupled to port W (port A).

  In switching circuit 254, port S4 is coupled to system bus orthogonal memory I / F 132, port S5 is coupled to write port W (port A) of orthogonal transformation memory 252, and port S6 is read from orthogonal transformation memory 250. Coupled to port R (port B).

  Memory cell mat orthogonal memory I / F 132 is coupled to memory cell mat 40 shown in FIG. 1 and the like, and system bus orthogonal memory I / F 134 is coupled to the system bus via the system bus interface shown in FIG.

  As described above, in orthogonal transform memories 250 and 252 shown in the third embodiment, port A is a write port and port B is a read port. Therefore, the data flow in each of these orthogonal transform memories 250 and 252 is unidirectional. Therefore, switching circuits 254 and 256 are used to switch the data transfer path between the external processor and the data transfer path between the memory cell mats of the internal arithmetic circuit. Access control including port switching in the orthogonal transform circuit 30 is performed by the main control circuit 240.

  When data is transferred from the system to the memory cell mat, switching circuit 254 connects port S4 to port S5 and couples port A for writing in orthogonal transform memory 252 to the system bus. Switching circuit 256 couples port S2 to port S1, and couples read port B of orthogonal transform memory 252 to the memory cell mat via orthogonal memory I / F 134. Therefore, in this state, transfer data from an external device such as a processor on the system side is orthogonally transformed by the orthogonal transformation memory 252 and transferred to the memory cell mat.

  At the time of data transfer from the memory cell mat to the system processor, the switching circuits 254 and 256 switch the connection path. That is, in switching circuit 256, port S1 is coupled to port S3, and in switching circuit 254, port S4 is coupled to port S6. In this state, in orthogonal transformation memory 250, port A for writing is coupled to the memory cell mat, and port B for reading is coupled to the processor via the system bus. Therefore, the data transferred from the memory cell mat is orthogonally transformed by the orthogonal transformation memory 250 and transferred to an external device such as a processor on the system side.

  Therefore, as described above, even if the memory cell of the orthogonal transformation memory has a write-only port, the two orthogonal transformation memories 235A and 235B are arranged in the orthogonal transformation circuit 30, By using as a memory for data transfer from the processor to the memory cell mat and a memory for data transfer from the memory cell mat to the processor, data can be transferred between the memory cell mat and the processor by performing orthogonal transformation. it can.

  The configuration of the orthogonal transform circuit shown in FIG. 31 can be used similarly when the orthogonal transform memory shown in the first and second embodiments is used.

  As described above, according to the third embodiment of the present invention, a P-type impurity region is provided in an active region for forming a memory cell, and a P-channel SOI transistor is used as a write-only access transistor. Therefore, a desired potential change can be reliably generated in the body region of the storage transistor during data writing. Further, similarly to the first and second embodiments, the capacitor-less memory cell structure can follow the scalability of the memory cell in accordance with the miniaturization of the process. Further, like the first and second embodiments, the wiring pattern is linear, and the wiring and the active region can be accurately patterned even when the process is miniaturized.

  Further, in the configuration in which two memory devices are provided in the orthogonal transformation circuit and the data transfer direction of these memories is fixed, and the write-only port is provided in the memory, the transfer data between the processor and the memory cell mat is also transferred. Orthogonal transformation can be performed.

[Embodiment 4]
FIG. 32 schematically shows a configuration of a processing system using the orthogonal transformation memory according to the present invention. A processing system 300 shown in FIG. 32 is provided outside the parallel processing unit 320 and includes two orthogonal transformation memories 302 and 304. An image processing device 306 that processes image data is provided between the orthogonal transformation memories 302 and 304. The read port (R) of the orthogonal transform memory 302 is coupled to the input port of the image processing device 306, and the write port (W) of the direct transform memory 304 is coupled to the output port of the image processing device 306.

  Write / read ports of orthogonal transform memories 302 and 304 are coupled to ports S11 and S12 of switching circuit 310, respectively. In this switching circuit 310, port S 1 is coupled to a memory cell mat in parallel processing unit 320 via memory cell mat / orthogonal memory I / F 134. The bit widths of the transfer data in the parallel processing unit 320 are all equal L bits. The bit width of the transfer data between the orthogonal memories 302 and 306 in the external processing system is set to an appropriate bit width according to the bit width of the processing data of the image processing apparatus 306.

  In this processing system, the memory cell mat in the parallel processing unit 320 is used as a buffer memory as an example. For example, scanned image data input from an external imaging device is temporarily stored in the memory cell mat in the scanning order. Next, the image data R, G, and B of the region to be processed are read from the image data stored in the memory cell mat via the orthogonal memory I / F 134 and the switching circuit 310, and the port W / R is read to the orthogonal transformation memory 302. Are sequentially stored along the X direction. For example, after image data of a necessary area to be filtered is stored in the orthogonal transformation memory 302, the image data is read along the Y direction via the readout port R of the orthogonal transformation memory 302, and the image processing apparatus 306 performs necessary image processing. Execute. In this process, the same color image data R, G, or B is read in parallel, and the image processing apparatus 306 executes the process. Pixel data R ′, G ′, B ′ after processing in the image processing device 306 is written in the orthogonal transformation memory 304 along the Y direction via the write port W. Thereafter, the pixel data R ′, G ′, and B ′ are read from the orthogonal transformation memory 304 along the X direction via the write / read port W / R, and then passed through the switching circuit 310 and the orthogonal memory I / F 134. Store in memory cell mat. Therefore, in the memory cell mat, the processed pixel data is stored in the scanning order.

  In the case of the system configuration shown in FIG. 32, image data processing is executed outside the parallel processing unit 320. Therefore, for example, by processing image data using the memory cell mat in the parallel processing unit as a buffer area (working area) in parallel with the storage of the processing data in the external memory shown in FIG. In the processing system, a plurality of processes can be executed in parallel, and the system performance can be improved.

  The image processing device 306 may be a device dedicated to image processing, such as a DSP (digital signal processing device), or may be a general-purpose processor.

  As the orthogonal transformation memory, in the orthogonal transformation memory shown in the first and second embodiments, the port B is used as the write / read port W / R and the port A is used as the read port W. In the orthogonal transformation memory according to the third embodiment, port A is used as write port W, and port B is used as write / read port W / R. Therefore, the orthogonal transformation memory 302 shown in the first and second embodiments is used, and the orthogonal transformation memory shown in the third embodiment is used as the orthogonal transformation memory 304.

  In the case where the ports A and B of the orthogonal transformation memory shown in the first and second embodiments can be used as write / read ports, the orthogonal transformation memories 302 and 304 are referred to as the first embodiment. And the orthogonal transformation memory shown in FIG.

  In the configuration shown in FIG. 32, both orthogonal transformation memories 302 and 304 have write / read ports W / R coupled to a memory cell mat via switching circuit 310. Therefore, data can be transferred bi-directionally between the memory cell mat and the orthogonal transform memories 302 and 304. In this case, when processing is executed in the parallel processing unit 320, the processing is executed using the orthogonal transformation memory 302 or 304 as a work area. For example, in image processing, coefficient data at the time of filter processing is stored in these orthogonal transformation memories 302 or 304, and processing is executed in the parallel processing unit. In this case, the orthogonal transformation of the pixel data from the outside is performed using one orthogonal transformation memory 304/302 and stored in the memory cell mat.

  In the case of this configuration, for example, in image conversion processing or the like, simple processing such as product-sum operation is performed in the memory cell mat (40), and other processing such as edge extraction, color conversion, and complicated filter processing is performed. This is done with an external processing device. As a result, in the memory cell mat, processing inside the main arithmetic circuit and processing in the external processing device can be realized in an interleaved manner, and processing according to the characteristics of each arithmetic processing device can be performed individually and in parallel. Can be executed.

  In the configuration shown in FIG. 31, when the orthogonal transform memories 250 and 252 are configured to transfer data to and from the switching circuit 256, the following system can be realized.

  That is, as noted in FIG. 31, in the configuration shown in FIG. 31, the write port W and the read port R of each of the orthogonal transformation memories 250 and 252 can bidirectionally transfer data to and from the memory cell mat. In this case, the memory cell mat (40) can bidirectionally transfer data to / from each of the orthogonal transformation memories 250 and 252. The orthogonal transform memory 250 also transfers the stored data to a processing device coupled to the system bus, while the orthogonal transform memory 252 stores data from the processing device coupled to the system bus or an external memory. .

  Therefore, in the case of this orthogonal transformation circuit configuration, processing and data transfer can be executed in parallel between the external device and the memory cell mat 40 (main arithmetic circuit 20), and further the following operations are realized. Can do. For example, the processed image data is stored in the orthogonal memory 252, and the data value of a part of the area of the image data is changed by the data from the external device (for example, paint processing). The changed image data is transferred again to the memory cell mat, and a predetermined calculation process is executed.

  In the configuration shown in FIGS. 31 and 32, one port of the orthogonal transformation memory is set as a port dedicated for writing or reading. However, both ports are set to write and read, and these orthogonal transform memories are used in an interleaved manner, and the other orthogonal transform memory is used for data transfer between one orthogonal transform memory and the memory cell mat. It may be configured to transfer data or load / store processing data from / to a memory between the computer and an external processing device.

  In the configurations shown in FIGS. 31 and 32, the connection between the system bus and the memory cell mat may be reversed.

[Example of change]
FIG. 33 shows a configuration of a modified example of the processing system according to the fourth embodiment of the present invention. In FIG. 33, the straight navigation conversion memory 52 is disposed between the processor 350 and the buffer memory 354. This orthogonal transformation memory 352 may be any of the orthogonal transformation memories of the first to third embodiments. Orthogonal transformation memory 352 has its write port W coupled to processor 350 and its read port R coupled to buffer memory 354. A coprocessor 356 is coupled to the buffer memory 352. The coprocessor 356 can transfer data with the buffer memory 354 and the processor. This orthogonal transformation memory 352 may be any of the orthogonal transformation memories of the first to third embodiments.

  In this processing system, the processor 350 performs predetermined processing on image data and the like arranged in the scanning order, for example, and stores the processing result data in the orthogonal transformation memory 352 via the write port W. The data stored in the orthogonal transform memory 352 is read from the read port R and stored in the buffer memory 354 under the control of a memory controller (not shown). The buffer memory 354 is a memory that does not have an orthogonal transformation function, and stores data that has been orthogonally transformed by the orthogonal transformation memory 352. The coprocessor 356 reads the data after orthogonal transformation stored in the buffer memory 354, performs processing such as filter processing, and transfers the processed data to the processor 350.

  In the configuration of this processing system, the orthogonal transformation memory 352 is only used for one orthogonal transformation. In general, orthogonal transformation processing such as transposition operation used in matrix operation or the like can be performed using a memory with a small occupation area and low current consumption.

  As described above, according to the fourth embodiment of the present invention, data is orthogonally transformed with a processing apparatus and transferred, and even in a general processing system, a small occupied area and low consumption A current processing system can be constructed.

  In the configuration shown in FIG. 33, data transfer between the processor 350, the orthogonal transform memory 352, the buffer memory 354, and the coprocessor 356 may be performed in both directions. The system shown in FIG. 33 may be integrated on the same semiconductor chip, or may be individually arranged on a boat. The system configuration may be any system that requires an orthogonal transform operation, and the system configuration using the orthogonal transform memory according to the present invention is not limited to the system configurations shown in FIGS. 1, 32, and 33.

  In addition, the orthogonal transform circuit according to the first to fourth embodiments of the present invention may be provided in the system LSI on the same chip as the parallel processing unit, and a digital signal may be used as a single dedicated orthogonal transform circuit. You may use for orthogonal transformation processes, such as a discrete cosine transformation in a process.

  The semiconductor memory device according to the present invention follows process miniaturization by applying a data array to a circuit that converts between a bit serial and word parallel data string and a word serial and bit parallel data string. Thus, the memory cell can be miniaturized, and a high-speed orthogonal transformation circuit with a small occupation area can be realized.

1 schematically shows a configuration of a system LSI to which a semiconductor memory device according to the present invention is applied. FIG. FIG. 2 schematically shows a configuration of a main part of the main arithmetic circuit shown in FIG. 1. FIG. 3 is a diagram schematically showing a calculation operation of the main calculation circuit shown in FIG. 2. It is a figure which shows more specifically the structure of the principal part of the main arithmetic circuit shown in FIG. FIG. 2 is a diagram showing a data transfer sequence between a system bus of the system LSI shown in FIG. 1 and a memory cell mat. It is a figure which shows roughly the cross-sectional structure of the TTRAM cell utilized in this invention. It is a figure which shows the electrical equivalent circuit of the TTRAM cell shown in FIG. FIG. 8 is a timing diagram showing a write / read operation of the TTRAM cell shown in FIGS. 6 and 7; FIG. 5 shows an electrically equivalent circuit of a memory cell used in the semiconductor memory device according to the first embodiment of the present invention. FIG. 10 schematically shows a planar layout of the double drain storage transistor shown in FIG. 9. It is a figure which shows roughly the cross-sectional structure along line L11-L11 shown in FIG. It is a figure which shows roughly the cross-sectional structure along line L12-L12 shown in FIG. FIG. 10 is a signal waveform diagram representing an operation of the memory cell shown in FIG. 9. FIG. 4 schematically shows a planar layout of a memory cell array of the semiconductor memory device according to the first embodiment of the present invention. FIG. 15 is a diagram showing an electrical equivalent circuit of the layout of the memory cell array shown in FIG. 14. 1 schematically shows a configuration of an orthogonal transform circuit using a semiconductor memory device according to a first embodiment of the present invention. FIG. FIG. 17 schematically shows a configuration of the orthogonal memory shown in FIG. 16. FIG. 18 specifically shows a configuration of a main part of the memory cell shown in FIG. 17. FIG. 14 schematically shows a planar layout of a memory cell in a semiconductor memory device according to a second embodiment of the present invention. FIG. 20 is a diagram showing an electrical equivalent circuit of the memory cell shown in FIG. 19. FIG. 11 schematically shows a planar layout of a memory cell array according to the second embodiment of the present invention. FIG. 22 is a diagram showing an electrical equivalent circuit of the memory cell array shown in FIG. 21. It is a figure which shows roughly arrangement | positioning of the selection memory cell at the time of orthogonal transformation operation in Embodiment 2 of this invention. FIG. 14 schematically shows a planar layout of a memory cell array of a semiconductor memory device according to a third embodiment of the present invention. FIG. 25 schematically shows an arrangement of impurity regions of memory cells in the planar layout shown in FIG. 24. FIG. 26 is a diagram showing an electrical equivalent circuit of the memory cell shown in FIG. 25. FIG. 27 is a signal waveform diagram representing an operation in data writing of the memory cell shown in FIGS. 25 and 26. FIG. 27 is a signal waveform diagram representing an operation in data reading of the memory cells shown in FIGS. 25 and 26. FIG. 25 is a diagram showing an electrical equivalent circuit of the memory cell array shown in FIG. 24. FIG. 11 schematically shows an entire configuration of a semiconductor memory device according to a third embodiment of the present invention. It is a figure which shows an example of a structure of the orthogonal transformation circuit using the orthogonal transformation memory (semiconductor memory device) according to Embodiment 3 of this invention. It is a figure which shows an example of the system configuration | structure using the semiconductor memory device according to this invention. It is a figure which shows the example of a change of the system configuration | structure using the semiconductor memory device (orthogonal transformation memory) according to this invention.

Explanation of symbols

  1 system LSI, 20 main arithmetic circuit, 24 system bus I / F, 26 multiplexer (MUX), 30 orthogonal transform circuit, 40 memory cell mat, ATA, ATAP, ATB access transistor, DDST double drain storage transistor, PNA, PNB, PN1, PN2 precharge node, 101 N-type impurity region (third impurity region), 100a, 100b N-type impurity region (first and second impurity regions), 102 gate electrode, 103 P-type body region, 110a, 110b active region, AR1-AR3 sub-active region, 111a-111h active region, 112a-112d gate electrode wiring, 116a-116d polysilicon gate electrode wiring, 114a-114f first layer metal wiring, 118a-118f second layer metal wiring Line, 130 orthogonal memory, 132 system bus / orthogonal memory I / F, 134 memory cell mat / orthogonal memory I / F, 140 orthogonal memory array, 142A port AX decoder, 142B port BX decoder, 144A port A sense amplifier / write drive Circuit, 144B port B sense amplifier / write drive circuit, AR active region, ARa-ARc sub-active region, GTa-GTd gate electrode wiring, 150a-150c, 152a-152b first layer metal wiring, 148a, 148b polysilicon gate electrode Wiring, 162a, 162b, 164a, 164b, 166a, 166b, 168a Second layer metal wiring, 170a-170d Gate electrode wiring, 175a, 175b First layer metal wiring, 180a, 180b, 181a, 181b 182a, 182b, 183a Second layer metal wiring, 184a-184d polysilicon gate electrode wiring, 190a, 190b active region, 192a-192d P-type impurity region, 202a, 202b high-concentration P-type region, 203 P-type region, 206 high Concentration N type region, 207a, 207b High concentration N type region, 208 P type region, STB storage transistor, 250, 252, 302, 304 Orthogonal transformation memory, 300 processing system, 320 parallel processing unit, 350 processor, 352 orthogonal transformation Memory, 354 buffer memory, 356 coprocessor.

Claims (21)

A plurality of memory cells arranged in an array in alignment along the first and second directions, each formed on an insulating film, each memory cell storing information according to a voltage of a body region; A first transistor having a first conduction node receiving a fixed voltage and second and third conduction nodes arranged separately from the first conduction node by the body region; and a first transistor of the first transistor A second transistor having a fourth conduction node connected to two conduction nodes, and a third transistor having a fifth conduction node connected to a third conduction node of the first transistor. ,
The second and third conductive nodes are separated from each other by the body region;
Each of the memory cells of the first memory cell group corresponding to each of the plurality of first memory cell groups is arranged corresponding to a plurality of first memory cell groups each having a memory cell arranged in alignment along the first direction. A plurality of first word lines to which the control electrodes of the two transistors are connected;
Each of the memory cells of the second memory cell group corresponding to each of the plurality of second memory cell groups is arranged corresponding to a plurality of second memory cell groups each having a memory cell arranged in alignment along the second direction. A plurality of second word lines to which the control electrodes of the three transistors are connected;
A plurality of first bit lines arranged corresponding to each of the second memory cell groups and connected to the sixth conduction node of the second transistor of the second memory cell group corresponding to each of the second memory cell groups;
A plurality of second bit lines arranged corresponding to each of the first memory cell groups, each connected to a seventh conduction node of a third transistor of the corresponding first memory cell group;
A semiconductor memory device comprising a plurality of charge lines arranged corresponding to each of the second memory cell groups and connected to the control electrode of the first transistor of the corresponding second memory cell group. A plurality of memory cells arranged in an array in alignment along the first and second directions, each formed on an insulating film, each memory cell storing information according to a voltage of a body region; A first transistor having a first conduction node receiving a fixed voltage and second and third conduction nodes arranged separately from the first conduction node by the body region; and a first transistor of the first transistor A second transistor having a fourth conduction node connected to two conduction nodes, and a third transistor having a fifth conduction node connected to a third conduction node of the first transistor. ,
Each of the memory cells of the first memory cell group corresponding to each of the plurality of first memory cell groups is arranged corresponding to a plurality of first memory cell groups each having a memory cell arranged in alignment along the first direction. A plurality of first word lines to which the control electrodes of the two transistors are connected;
Each of the memory cells of the second memory cell group corresponding to each of the plurality of second memory cell groups is arranged corresponding to a plurality of second memory cell groups each having a memory cell arranged in alignment along the second direction. A plurality of second word lines to which the control electrodes of the three transistors are connected;
A plurality of first bit lines arranged corresponding to each of the second memory cell groups and connected to the sixth conduction node of the second transistor of the second memory cell group corresponding to each of the second memory cell groups;
A plurality of second bit lines arranged corresponding to each of the first memory cell groups, each connected to a seventh conduction node of a third transistor of the corresponding first memory cell group;
A plurality of charge lines arranged corresponding to each of the second memory cell groups, each of which is connected to the control electrode of the first transistor of the corresponding second memory cell group;
Each of the first transistors is formed below the control electrode, and is formed adjacent to the first impurity region of the first conductivity type that forms the body region, and the second impurity region. A second impurity region of a second conductivity type that forms a second conduction node connected to the transistor; and the third transistor is disposed opposite to the second impurity region with respect to the first impurity region. A third impurity region of a second conductivity type forming a third conduction node connected to the first impurity region, and a region of the first impurity region different from a side opposite to the second and third impurity regions. disposed adjacent to the first impurity region, and a fourth impurity region of the second conductivity type constituting the first conduction node, semiconductors memory device. A plurality of memory cells arranged in an array in alignment along the first and second directions, each formed on an insulating film, each memory cell storing information according to a voltage of a body region; A first transistor having a first conduction node receiving a fixed voltage and second and third conduction nodes arranged separately from the first conduction node by the body region; and a first transistor of the first transistor A second transistor having a fourth conduction node connected to two conduction nodes, and a third transistor having a fifth conduction node connected to a third conduction node of the first transistor. ,
Each of the memory cells of the first memory cell group corresponding to each of the plurality of first memory cell groups is arranged corresponding to a plurality of first memory cell groups each having a memory cell arranged in alignment along the first direction. A plurality of first word lines to which the control electrodes of the two transistors are connected;
Each of the memory cells of the second memory cell group corresponding to each of the plurality of second memory cell groups is arranged corresponding to a plurality of second memory cell groups each having a memory cell arranged in alignment along the second direction. A plurality of second word lines to which the control electrodes of the three transistors are connected;
A plurality of first bit lines arranged corresponding to each of the second memory cell groups and connected to the sixth conduction node of the second transistor of the second memory cell group corresponding to each of the second memory cell groups;
A plurality of second bit lines arranged corresponding to each of the first memory cell groups, each connected to a seventh conduction node of a third transistor of the corresponding first memory cell group;
A plurality of charge lines arranged corresponding to each of the second memory cell groups, each of which is connected to the control electrode of the first transistor of the corresponding second memory cell group;
In each memory cell of the first memory cell group,
The second transistor is connected to the first active region extending in the first direction and electrically connected to the second conduction node of the first transistor, and the first active region, A second active region extending into the corresponding memory cell along the second direction and electrically coupled to the corresponding first bit line; and on the second active region in the first direction. A first control electrode formed along and electrically connected to the first word line;
The third transistor is arranged in alignment with the first active region along the first direction and is electrically coupled to a third conduction node of the first transistor. And a second control electrode disposed across the third active region and electrically connected to a corresponding second word line, the second control electrode being the second control electrode along the direction is continuously formed, semi-conductor memory device.   4. The semiconductor memory device according to claim 2, wherein a corresponding charge line is arranged between the second word line and the first bit line in each of the memory cells. A plurality of source lines arranged corresponding to each of the first memory cell groups, each transmitting the fixed voltage;
In each memory cell, a corresponding first word line is disposed between a corresponding source line and a corresponding second bit line, and a region between the corresponding source line and the corresponding first word line 3. The semiconductor memory device according to claim 2, wherein said sixth conduction node is connected to a corresponding first bit line. A plurality of memory cells arranged in an array in alignment along the first and second directions, each formed on an insulating film, each memory cell storing information according to a voltage of a body region; A first transistor having a first conduction node receiving a fixed voltage and second and third conduction nodes arranged separately from the first conduction node by the body region; and a first transistor of the first transistor A second transistor having a fourth conduction node connected to two conduction nodes, and a third transistor having a fifth conduction node connected to a third conduction node of the first transistor. ,
Each of the memory cells of the first memory cell group corresponding to each of the plurality of first memory cell groups is arranged corresponding to a plurality of first memory cell groups each having a memory cell arranged in alignment along the first direction. A plurality of first word lines to which the control electrodes of the two transistors are connected;
Each of the memory cells of the second memory cell group corresponding to each of the plurality of second memory cell groups is arranged corresponding to a plurality of second memory cell groups each having a memory cell arranged in alignment along the second direction. A plurality of second word lines to which the control electrodes of the three transistors are connected;
A plurality of first bit lines arranged corresponding to each of the second memory cell groups and connected to the sixth conduction node of the second transistor of the second memory cell group corresponding to each of the second memory cell groups;
A plurality of second bit lines arranged corresponding to each of the first memory cell groups, each connected to a seventh conduction node of a third transistor of the corresponding first memory cell group;
A plurality of charge lines arranged corresponding to each of the second memory cell groups, each of which is connected to the control electrode of the first transistor of the corresponding second memory cell group;
Each of the memory cells is formed in a rectangular active region,
In the first transistor, the control electrode is formed in a T shape having a leg portion and a base portion,
The second and third transistors are arranged oppositely with respect to the leg;
It said second and control electrodes of the third transistor, wherein are formed in mirror-symmetrical L-shaped configuration with respect to the legs, semiconductors memory device. The control electrodes of the second and third transistors extend to an isolation region between active regions of adjacent memory cells in the first direction;
Each of the first word lines is electrically connected to the control electrode of the second transistor of the memory cell of the corresponding first memory cell group on the isolation region;
Each of the second word lines is electrically connected to the control electrode of the third transistor of the corresponding second memory cell group on the isolation region,
The semiconductor memory device according to claim 6, wherein contacts of the first word line and contacts of the second word line are alternately arranged in the second direction.   Each of the first word lines and each of the second word lines are connected to control electrodes of second and third transistors of two memory cells adjacent in the first direction by one contact, respectively. Item 8. The semiconductor memory device according to Item 7.   The active regions of the plurality of memory cells are arranged with their positions shifted in a first direction, the second transistors are aligned in the first direction, and the third transistors are aligned. The semiconductor memory device according to claim 6, wherein the semiconductor memory device is arranged. Each of the charge lines is arranged in parallel to and electrically connected to the base portion of the control electrode of the first transistor of the memory cell of the corresponding second memory cell group,
The semiconductor memory device according to claim 9, wherein the base portion of the control electrode of the first transistor extends continuously along the second direction.   The semiconductor according to claim 6, further comprising a plurality of source lines arranged corresponding to each of the second memory cell groups, each transmitting the fixed voltage to a memory cell of the corresponding second memory cell group. Storage device. A plurality of memory cells arranged in an array in alignment along the first and second directions, each formed on an insulating film, each memory cell storing information according to a voltage of a body region; A first transistor of a first conductivity type having a first conduction node receiving a fixed voltage and a second conduction node arranged separately from the first conduction node by the body region; and the first transistor A second conduction type second transistor having a third conduction node connected to the body region of the first transistor and a first conduction having a fourth conduction node connected to the second conduction node of the first transistor. A third transistor of the type,
Each of the memory cells of the first memory cell group corresponding to each of the plurality of first memory cell groups is arranged corresponding to a plurality of first memory cell groups each having a memory cell arranged in alignment along the first direction. A plurality of first word lines to which the control electrodes of the two transistors are connected;
Each of the memory cells of the second memory cell group corresponding to each of the plurality of second memory cell groups is arranged corresponding to a plurality of second memory cell groups each having a memory cell arranged in alignment along the second direction. A plurality of second word lines to which the control electrodes of the three transistors are connected;
A plurality of first bit lines arranged corresponding to each of the second memory cell groups, each connected to a fifth conduction node of a second transistor of the corresponding second memory cell group;
A plurality of second bit lines arranged corresponding to each of the first memory cell groups, each connected to a sixth conduction node of a third transistor of the corresponding first memory cell group;
A plurality of charge lines arranged corresponding to each of the second memory cell groups, each of which is connected to a control electrode of a first transistor of the corresponding second memory cell group and transmits a predetermined voltage; Semiconductor memory device.   Each of the memory cells is formed in first and second active regions that are shifted and adjacent to each other in the first direction, and the second transistor is formed in the first active region. 13. The semiconductor memory device according to claim 12, wherein the first and third transistors are formed in the second active region. The control electrode of each of the first transistors is composed of a conductive layer that continuously extends along the second direction,
The control electrode of each third transistor is formed of a conductive layer that continuously extends along the second direction,
The control electrode of each said 2nd transistor is comprised with the conductive layer arrange | positioned along the said 2nd direction formed so that a said 1st active region may be crossed in a corresponding memory cell area | region. 14. The semiconductor memory device according to 13.   13. The apparatus according to claim 12, further comprising a plurality of source lines arranged corresponding to each of the second memory cell groups, each transmitting the fixed voltage to the memory cells of the corresponding second memory cell group. Semiconductor memory device. The addressed first word line of the plurality of first word lines and the addressed first bit line of the plurality of first bit lines are selected according to a first address signal. A first port access circuit;
According to a second address signal, an addressed second word line of the plurality of second word lines and an addressed second bit line of the plurality of second bit lines are selected. The semiconductor memory device according to claim 12 , further comprising a second port access circuit. The first port access circuit selects the plurality of first bit lines in parallel when selected,
17. The semiconductor memory device according to claim 16, wherein when activated, said second port access circuit selects said plurality of second bit lines in parallel. When reading data, an addressed first word line of the plurality of first word lines and an addressed first bit of the plurality of first bit lines according to a first address signal A first port access circuit that selects a line and maintains the potential of the charge line at a fixed value;
At the time of data writing, an addressed second word line of the plurality of second word lines and a second addressed address of the plurality of second bit lines according to a second address signal The semiconductor memory device according to claim 1, further comprising a second port access circuit that selects a bit line and an addressed charge line among the plurality of charge lines. At the time of data writing, an addressed first word line of the plurality of first word lines and a plurality of first bit lines addressed according to a first address signal A first port access circuit for selecting a bit line and maintaining the potential of the charge line at a fixed value;
At the time of data reading, the addressed second word line of the plurality of second word lines and the addressed second bit of the plurality of second bit lines in accordance with a second address signal 13. The semiconductor memory device according to claim 12, further comprising a second port access circuit that selects a line and maintains the potentials of the plurality of charge lines at the fixed value. A plurality of memory cells arranged in an array in alignment along the first and second directions, each formed on an insulating film, each memory cell storing information according to a voltage of a body region; A first transistor having a first conduction node receiving a fixed voltage and second and third conduction nodes arranged separately from the first conduction node by the body region; and a first transistor of the first transistor A second transistor having a fourth conduction node connected to two conduction nodes, and a third transistor having a fifth conduction node connected to a third conduction node of the first transistor. ,
Each of the memory cells of the first memory cell group corresponding to each of the plurality of first memory cell groups is arranged corresponding to a plurality of first memory cell groups each having a memory cell arranged in alignment along the first direction. A plurality of first word lines to which the control electrodes of the two transistors are connected;
Each of the memory cells of the second memory cell group corresponding to each of the plurality of second memory cell groups is arranged corresponding to a plurality of second memory cell groups each having a memory cell arranged in alignment along the second direction. A plurality of second word lines to which the control electrodes of the three transistors are connected;
A plurality of first bit lines arranged corresponding to each of the second memory cell groups and connected to the sixth conduction node of the second transistor of the second memory cell group corresponding to each of the second memory cell groups;
A plurality of second bit lines arranged corresponding to each of the first memory cell groups, each connected to a seventh conduction node of a third transistor of the corresponding first memory cell group;
A plurality of charge lines arranged corresponding to each of the second memory cell groups, each of which is connected to the control electrode of the first transistor of the corresponding second memory cell group;
The addressed first word line of the plurality of first word lines and the addressed first bit line of the plurality of first bit lines are selected according to a first address signal. A first port access circuit;
According to a second address signal, an addressed second word line of the plurality of second word lines and an addressed second bit line of the plurality of second bit lines are selected. A semiconductor memory device comprising: a second port access circuit. The first port access circuit selects the plurality of first bit lines in parallel when selected,
21. The semiconductor memory device according to claim 20, wherein when activated, said second port access circuit selects said plurality of second bit lines in parallel.

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