JP5173962B2 - Resolver / digital conversion apparatus and resolver / digital conversion method - Google Patents

Description

  The present invention relates to a resolver / digital conversion device and a resolver / digital conversion method for converting an output signal of a resolver that detects a rotation angle of a rotating device such as a rotating electrical machine or an internal combustion engine into a digital rotation angle signal of the resolver.

  Conventionally, various rotary machines have been used for power steering of automobiles, servo motors for machine tools, and the like, but a rotation angle sensor is used to detect the rotation angle of the rotor in the rotary machine. As a sensor for detecting the rotation angle, a two-phase resolver using AC excitation, or a rotation angle sensor composed of a sine wave magnetized rotor and two semiconductor magnetic sensors is used. In the resolver, the reactance between the rotor and the stator changes depending on the position of the rotor, and an AC signal corresponding to the change is output. Specifically, a control transformer having two-phase windings orthogonal to the stator and a single-phase winding or two-phase windings orthogonal to the rotor is configured, and one-phase excitation / 2-phase There are output types and 2-phase excitation / 1-phase output types. The angle detection signal obtained from the resolver is a two-phase analog signal of a cosine wave and a sine wave whose phases are different by 90 °. The detection signal is a resolver / digital converter (RDC: Resolver Digital Converter, hereinafter abbreviated as RDC). It is processed by using.

  The RDC converts the rotation angle position of the rotor into angle information data, which is digital data, based on the angle detection signal from the resolver and outputs it. As RDC, the angle information data is calculated by the arithmetic circuit based on the one that obtains the angle information data by an analog electric circuit and the digital data obtained by converting the angle detection signal by an A / D (Analog / Digital) converter. There is something to do. Various errors occur when the rotor angle is detected by the combination of the resolver and the RDC. For example, a difference in amplitude occurs due to a difference in sensitivity of the resolver or an amplification degree in the RDC, an offset error due to an amplifier circuit or an A / D converter, or a sampling timing error due to a period variation or impedance variation due to change over time. Etc. are added.

  In order to correct such a detection error and improve detection accuracy, various ideas have been made. For example, as a countermeasure against offset error, as disclosed in Patent Document 1, a DC component is removed by subtracting data of two consecutive samples from digital data obtained by conversion by an A / D converter. There is something like that. Further, as disclosed in Patent Document 2, based on the zero-cross position of the reference excitation signal, the time difference from the zero-cross position of the previous cycle is calculated, and the sampling timing for A / D conversion of the resolver signal is calculated. Some have been corrected.

JP 2002-162255 A JP 2007-315856 A

  However, in the configuration described in Patent Document 1 described above, the offset component included in the data is removed by subtracting the data twice consecutively sampled by the A / D converter. In this example, The output signal of the resolver is captured by an A / D converter. For errors in digital values, including DC component errors that occur during A / D conversion and errors that are A / D converted, including amplifier offset components, It is valid. However, the impedance of the signal line changes due to the temperature rise or aging of the resolver operating in the rotating machine, and it is not possible to cope with fluctuations in the transmission delay time of the resolver signal generated as a result. In other words, there is a problem that it is not possible to deal with errors in the sampling timing itself.

  In the configuration described in Patent Document 2, the A / D conversion sampling timing is determined based on the zero crossing of the reference AC signal for excitation, but the reference AC signal of the oscillation circuit is set as the correct timing. Since it is used, the impedance of the signal line and the like change due to the temperature rise and change over time of the resolver operating in the rotating machine, and it is impossible to cope with fluctuations in the transmission delay time of the resolver signal generated as a result. That is, although it corresponds to the fluctuation of the reference AC signal for resolver input, there is a problem that it is not possible to remove the temporal error component included in the voltage signal induced in the resolver that is expected to occur thereafter. .

  The present invention has been made to solve the above-described problems, and is a resolver / digital conversion that can cope with a change in a resolver signal transmission delay time with respect to a temperature rise of a resolver and a change in impedance of a signal line. An object is to provide an apparatus and a resolver / digital conversion method.

According to a first aspect of the present invention, there is provided a resolver / digital conversion device including an excitation signal generation circuit for generating an excitation signal for exciting a resolver attached to a rotating device at a predetermined frequency, and a voltage signal output from the resolver at a predetermined frequency. An analog / digital converter that performs sampling at the sampling timing and converts it into a digital signal, and a phase correction circuit that corrects the sampling timing based on the digital signal are provided,
The phase correction circuit samples the digital signal output by the analog / digital converter obtained at the sampling timing four times in one cycle of the frequency of the excitation signal, and data at the timing when it becomes zero The phase of the sampling timing is discriminated based on the amplitude level of the signal to correct the phase, and the sampling timing is corrected by correcting the phase. The analog / digital converter inputs the corrected sampling timing. Thus, the resolver voltage signal is sampled.

A resolver / digital conversion method according to a second invention excites a resolver attached to a rotating device at a predetermined frequency, samples a voltage signal output from the resolver at a sampling timing at a predetermined frequency, and converts it into a digital signal. The digital signal obtained by the conversion at the sampling timing is sampled four times in one period of the excitation signal frequency, and the phase of the sampling timing is based on the amplitude level of the data at the timing when it becomes zero. The phase is corrected by discriminating the deviation, and the voltage signal of the resolver is sampled at the sampling timing after the correction.

Since the resolver / digital conversion apparatus according to the first aspect of the present invention has the above-described configuration, even if the sampling timing is shifted due to a rise in the temperature of the resolver, a change in impedance of the signal line, a change with time, or the like. Therefore, it is possible to always perform sampling with an accurate phase and to obtain accurate angle information.
Also in the resolver / digital conversion method according to the second invention, the same effect as the first invention can be obtained.

1 is a block diagram illustrating a configuration of a resolver / digital conversion device according to a first embodiment. 3 is a time chart showing sampling timing according to the first embodiment. 3 is a time chart showing sampling timing according to the first embodiment. 3 is a time chart showing sampling timing according to the first embodiment. FIG. 2 is a detailed block diagram illustrating a configuration of a phase correction circuit 5 in FIG. 1. It is a detailed block diagram which shows the structure of the angle calculation circuit 4 in FIG. FIG. 6 is a block diagram illustrating a configuration of a resolver / digital conversion device according to a second embodiment. FIG. 10 is a block diagram illustrating a configuration of a resolver / digital conversion device according to a third embodiment. 10 is a flowchart illustrating a resolver / digital conversion method according to a fourth embodiment.

Embodiment 1 FIG.
Embodiment 1 of the present invention will be described below with reference to the drawings.
There are various types of resolvers attached to rotating equipment, depending on the winding method, such as those in which a slip ring and brush are connected to the rotor winding, and those in which a rotating transformer is connected. . The resolver which is the subject of the present invention can be applied to any configuration as long as it is a one-phase excitation / two-phase or more output type resolver.
FIG. 1 is a block diagram showing a configuration of a resolver / digital conversion apparatus 100 according to the first embodiment. In FIG. 1, a resolver 1 attached to a rotating machine (not shown) outputs a two-phase voltage signal induced according to the rotational position of the rotor as a resolver signal. The two-phase voltage signals induced in the resolver 1 are converted into digital data by analog / digital converters (hereinafter referred to as AD converters) 2 and 3, respectively. At that time, excitation frequency (reference sine wave described later) The discretization process is performed at a frequency that is an integer multiple of 4. The angle calculation circuit 4 calculates the angle information of the rotor by calculating the data sampled by the AD converters 2 and 3. The phase correction circuit 5 calculates the sampling timing of the AD converters 2 and 3 by calculating the data sampled by the AD converters 2 and 3, and outputs a sampling pulse to the AD converters 2 and 3.
The reference counter 6 operates with a reference clock serving as a reference for the entire system. The excitation signal generation circuit 7 outputs a reference sine wave for exciting the resolver 1 as an excitation signal based on the reference clock output from the reference counter 6. The amplifier circuit 8 amplifies a reference sine wave that excites the resolver 1. The output terminal 9 outputs a digital value of rotor angle information obtained by the angle calculation circuit 4.

となる。レゾルバ／デジタル変換装置１００は、この回転子の角度Ｎθをデジタル値として求める機能を有するものであり、式（１）、式（２）を変形して、

として求めることができる。なお、正確に角度Ｎθを計算して求めるためには、ｓｉｎωＴ＝１、あるいはｓｉｎωＴ＝−１となる位相でサンプリングする必要がある。レゾルバ１の出力するこの電圧信号Ｖｓｉｎ、およびＶｃｏｓが、ＡＤ変換器２、３に入力されている。
角度演算回路４は、ＡＤ変換器２、３の出力に対して、上記（３）式のような演算を行うことによりＮθを求める。なお、レゾルバ１からの電圧信号は、回転子の角度に基づく正弦波を励磁信号で振幅変調された波形と見ることができるので、例えば同期検波による復調を行うことによってｓｉｎωＴによる変調成分を除去することも可能である。ｓｉｎωＴを除けば、（３）式によりＮθを求めることができる。 Next, the operation will be described.
In the resolver 1, a reference sine wave (excitation signal) having a constant frequency for excitation is applied to the rotor and excited. As a result, a voltage is induced in two windings provided in the stator and orthogonal to each other, and the value of the voltage is output while changing depending on the angle of the rotor. That is, the angular velocity of the excitation signal is ω [rad / s], the angle of the excitation signal is ωT [rad], the angle of the rotor is Nθ [rad], and the amplitude ratio of the induced voltage obtained from the applied AC voltage is K. Then, if the two-phase voltage signals induced in the resolver 1 are Vsin and Vcos, respectively,

It becomes. The resolver / digital conversion device 100 has a function of obtaining the angle Nθ of the rotor as a digital value. The equation (1) and the equation (2) are modified,

Can be obtained as In order to accurately calculate and obtain the angle Nθ, it is necessary to sample at a phase where sin ωT = 1 or sin ωT = −1. The voltage signals Vsin and Vcos output from the resolver 1 are input to the AD converters 2 and 3.
The angle calculation circuit 4 calculates Nθ by performing a calculation such as the above equation (3) on the outputs of the AD converters 2 and 3. Since the voltage signal from the resolver 1 can be regarded as a waveform in which a sine wave based on the rotor angle is amplitude-modulated by the excitation signal, the modulation component due to sin ωT is removed by performing demodulation by synchronous detection, for example. It is also possible. If sin ωT is excluded, Nθ can be obtained by equation (3).

  The phase correction circuit 5 corrects the phase so that the sampling timing of the AD converters 2 and 3 becomes a timing at which sin ωT = 1 and sin ωT = −1. When sampling is performed at a frequency four times the excitation frequency, it is necessary to perform sampling at four points ωT = 0, π / 2, π, and 3π / 2. In that case, as shown in FIG. 2A, phase data of a1, b1, a2, and b2 can be obtained. If there is no deviation in the sampling phase, data with a1 = 0 and a2 = 0 is obtained. It is done. The values of b1 and b2 are used for calculating the angle. Here, as shown in FIG. 2B, when the sampling phase is shifted in the direction of delay, a1 takes a positive value instead of zero, and a2 takes a negative value. On the other hand, b1 and b2 are also sampled at timings shifted from the correct phases of π / 2 and 3π / 2. Therefore, the deviation before and after the sampling phase can be determined by examining the signs of a1 and a2, and the amount of phase deviation can be known by calculating from the amplitude value. FIG. 3A shows three examples of a normal operation case, FIG. 3B shows a case where the sampling phase is delayed, and FIG. 3C shows a case where the sampling phase is advanced. Here, when the sampling phase of FIG. 3B is delayed, it is the same as the case shown in FIG. 2B, and a1 is positive data and a2 is negative data. Conversely, when the sampling phase is advanced, as shown in FIG. 3C, a1 is negative data and a2 is positive data.

  In the present invention, since a signal having a phase of ωT = 0 and π is necessary for adjusting the sampling phase, sampling is performed at a frequency that is an integral multiple of 4 of the excitation frequency, such as 4 times, 8 times, or 12 times. It has a function that makes it possible to adjust the sampling phase as described above.

Here, in order to correct the sampling phase as accurately as possible, it is necessary to use a clock having a frequency much higher than the excitation frequency as a reference clock. On the other hand, in the resolver / digital conversion process, the angle is often calculated using one period of the excitation frequency as a basic unit. Therefore, in the circuit configuration, a high frequency system clock is used for internal signal processing, and only the angle calculation result is output at the frequency of the excitation signal. The AD conversion sampling phase is corrected based on this system clock.
The reference counter 6 in FIG. 1 is a reference counter that operates in units of the system clock described above. The system clock generally has a frequency of several MHz to several tens of MHz. Especially when the frequency is high, it may exceed 100 MHz.
The excitation signal generation circuit 7 is a circuit that generates a sine wave for exciting the resolver 1. In general, a sine wave is often generated digitally using a ROM (Read Only Memory), and the output digital data is converted into an analog waveform by a digital / analog converter (DA converter). It is also possible to output a rectangular wave from a microcomputer or the like and shape the waveform into a sine wave using an external filter.
The amplifier circuit 8 serves as a sine wave drive circuit for exciting the resolver 1. The output terminal 9 outputs a digital value of angle information calculated by the angle calculation circuit 4 and outputs it at least once in one cycle of the excitation frequency.

  FIG. 4 is a diagram showing an example of timing for correcting the sampling phase of the AD converters 2 and 3. This figure shows an example in which correction for three system clocks is performed. Before the correction, when the reference counter 6 outputs an n + 8 value, an AD conversion sampling pulse is output. As a result of correcting for three clocks, the reference counter 6 value becomes an n + 3 value. It is controlled to output a sampling pulse when it is output. The amount of clock correction is also related to the AD conversion dynamic range. Next, an example of converting the amplitude value obtained specifically into the amount of phase shift will be described.

の近似が成り立つので、位相のずれ量は、約２０／２０４８［ｒａｄ］となる。この位相のずれ量は、以下のように３クロック分に相当する。

従って、振幅レベルで±２０の誤差があったケースでは、基準カウンタ６において３クロック分の補正を前後に行うことによりタイミングを調整することが可能となる。なお、このような近似を用いた計算方法はあくまで一例であり、他の計算方法を用いて位相のずれ量を求めても良い。
また、レゾルバ１の励磁周波数に対して４倍の周波数でサンプリングを行う場合、励磁周波数の１周期のうちに４回のパルスを出力することになるので、各パルス出力のタイミングがそれぞれ３クロック分補正される。例えば、上記の例では、１周期２０００のカウンタとなるので、補正なしの状態では０、５００、１０００、１５００の位置で立ち上がりが得られるように制御されたとすると、３クロック分の補正の結果、４９７、９９７、１４９７、１９９７の位置で立ち上がりが得られるように制御される。なお、タイミングの補正処理は、励磁信号の一周期と同期するので、サンプリングの４回目のパルスが出力された後に補正値を出力してタイミングの更新を行い、次の励磁の周期でその値が反映されたサンプリングパルスが出力されるよう制御される。
励磁信号の周波数と基準カウンタ６のクロック周波数の関係で位相の誤差を完全にゼロとすることは出来ないが、最終的には０度と１８０度の位相におけるレゾルバ信号の振幅がある一定の値χ以下となる基準として、
Ｓｉｎ（０＋α）＜χ
Ｓｉｎ（π＋α）＜χ
となるように位相量α［ｒａｄ］による補正を行う。 For example, it is assumed that the excitation frequency is 10 kHz, the system clock is 20 MHz, the number of AD conversion bits is 12 bits (4096: -2048 to +2047), and the maximum voltage value matches the full scale of AD conversion. At this time, one cycle of the excitation frequency is
20MHz / 10KHz = 2000
Thus, the system clock 2000 count is one cycle. In the sampled data, if the output value is a value of +20 at the timing of ωT = π / 2 where the output is originally zero, the angle is close to zero.

Therefore, the phase shift amount is approximately 20/2048 [rad]. This phase shift amount corresponds to three clocks as follows.

Therefore, in the case where there is an error of ± 20 in the amplitude level, the timing can be adjusted by performing correction for three clocks before and after in the reference counter 6. Note that the calculation method using such approximation is merely an example, and the phase shift amount may be obtained using another calculation method.
In addition, when sampling is performed at a frequency four times the excitation frequency of the resolver 1, four pulses are output in one cycle of the excitation frequency, so each pulse output timing is equivalent to 3 clocks. It is corrected. For example, in the above example, since it is a counter of 2000 in one cycle, if it is controlled so that a rise is obtained at positions 0, 500, 1000, 1500 in the state without correction, the result of correction for 3 clocks is as follows: Control is performed so that rising edges are obtained at positions 497, 997, 1497, and 1997. Since the timing correction process is synchronized with one cycle of the excitation signal, the correction value is output after the fourth pulse of sampling is output, the timing is updated, and the value is updated at the next excitation cycle. The reflected sampling pulse is controlled to be output.
Although the phase error cannot be made completely zero due to the relationship between the excitation signal frequency and the reference counter 6 clock frequency, the resolver signal amplitude at a phase of 0 degrees and 180 degrees eventually has a certain value. As a standard of χ or less,
Sin (0 + α) <χ
Sin (π + α) <χ
Correction by the phase amount α [rad] is performed so that

Next, the operation of the phase correction circuit 5 will be described.
FIG. 5 is a detailed block diagram of the phase correction circuit 5 in FIG. A counter output value from the reference counter 6 is input to the input terminal 10. The digital values of the two-phase voltage signals of the resolver 1 are input to the input terminals 11 and 12, respectively. The output terminal 13 outputs a sampling pulse for the AD converters 2 and 3. The delay circuits 14 and 15 are delay circuits for delaying two sampling pulses based on the sampling pulses of the AD converters 2 and 3, and the correction amount calculation circuit 16 receives an input from the input terminal 10 and an input The correct output timing of the sampling pulse is calculated from the inputs of the terminals 11 and 12 and the outputs of the delay circuits 14 and 15, and the correction amount is output. The comparison circuit 17 compares the counter value of the reference counter 6 with the output of the correction amount calculation circuit 16.

  Next, the operation of the correction amount calculation circuit 16 will be described. The correction amount calculation circuit 16 calculates a phase correction amount from the sampled amplitude value based on the calculation as described above. The value of the reference counter 6 input from the input terminal 10 is used to distinguish the timing of ωT = π / 2, 3π / 2, and the delay circuits 14 and 15 are positive and negative at ωT = π / 2, 3π / 2. Is used to process the values of In other words, the outputs of the delay circuits 14 and 15 are data whose phases are exactly delayed by π, which makes it possible to simultaneously process the values of b1 and b2. In this example, positive and negative values and the voltage signal of the resolver 1 are input for two phases, but this is configured to calculate a correction amount from data for two phases in order to obtain an accurate result. Because. For the purpose of simplifying the circuit, the correction amount may be calculated from the result of only one phase. In addition, a low-pass filter or the like can be inserted into the data signal for the purpose of removing error components due to noise or the like.

In the first embodiment, the correction amount of the sampling timing with respect to the reference counter 6 is configured to be constantly constant and corrected in the next excitation cycle. However, the correction amount is periodically changed. Correspondence is also possible. For example, if the sampling timing is periodically shifted or varies depending on the mechanical angle position of the rotor, the mechanical angle position or cycle is stored in advance, and the correction amount is set according to the mechanical angle position. It can also be adjusted. In other words, the correction amount can be calculated from the amplitude of the resolver signal, and at the same time, the correction amount corresponding to the mechanical angle position and cycle can be stored and output.
It is also possible to switch the correction amount of the sampling timing according to the rotation frequency and the rate of change of the rotation frequency. When the correction amount of the sampling phase depends on the rotation frequency, it can be corrected in combination with the value. In addition, when the rotation frequency changes rapidly, such as acceleration / deceleration, a configuration in which the correction amount is adjusted according to the change amount is also conceivable. The degree of correction required according to the amount of change is integrated and stored, and the sampling timing is corrected according to the amount of change in acceleration / deceleration.

  FIG. 6 is an example of a detailed block diagram of the angle calculation circuit 4 in FIG. Here, an example is shown in which the angle is obtained by performing AM demodulation processing using synchronous detection. Input terminals 18 and 19 receive a digital value of a two-phase resolver signal. The counter value of the reference counter 6 is input to the input terminal 20. The output terminal 21 outputs a digital value of the calculated angle information. The modulation wave generation circuit 22 generates a sine wave having the same frequency and the same phase as the modulation wave for AM demodulation. The multiplier circuits 23 and 24 multiply the sine wave output from the modulated wave generation circuit 22 and the resolver signal. The outputs of the multiplication circuits 23 and 24 are input to a function circuit 27 that performs an arc tangent (arcTan) operation via low-pass filters 25 and 26. In AM demodulation by synchronous detection, the original signal is obtained by multiplying the same sine wave as the modulation wave and removing the harmonic component from the result. Since the outputs of the low-pass filters 25 and 26 have values of sin Nθ and cos Nθ, Nθ is obtained by performing an arctangent (arcTan) operation on the resultant ratio (sinNθ / cosNθ). The angle information that is output from the angle calculation circuit 4 is output for each period of the excitation frequency. Note that the calculation method of the angle calculation is not limited to this method, and other calculation methods may be applied.

As described above, according to the first embodiment, the resolver signal is sampled four times in one period of the frequency of the excitation signal, and the amplitude level of the data at the timing when it becomes zero is used. Therefore, even if the sampling timing is shifted due to temperature or changes over time, it is possible to always perform sampling with an accurate phase, enabling long-term use and accurate. Angle information can be obtained.
Further, even when the sampling timing is shifted due to variations in the mechanical angle position or rotation frequency, it is possible to always perform sampling with an accurate phase, and as a result, it is possible to calculate accurate angle information.

Embodiment 2. FIG.
Next, the second embodiment will be described with reference to the drawings.
FIG. 7 is a block diagram showing a resolver / digital conversion apparatus 100 according to the second embodiment. The difference between the second embodiment and the first embodiment described above is that the sampling phase of AD conversion is not controlled in common for both phases but can be controlled individually. 7, components that perform the same operations as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted, and the other portions will be described. The phase correction circuit 28 that outputs two phases of sampling pulses calculates the correction amount of the phase of the sampling pulse of one of the two phases based on the output of the reference counter 6 and the output of the AD converter 2, and the reference counter 6 And the output of the AD converter 3 calculate the phase correction amount of the sampling pulse of the other of the two phases. In the second embodiment, the AD converter 2 and the AD converter 3 are configured so as to be able to cope with the case where the sampling timing correction amount is different. The correction amount is determined based on the calculation method described above, and the timing is independently determined. Is corrected.
As described above, in the second embodiment, even in the case where the sampling timing of the analog / digital converters 2 and 3 is shifted due to temperature and changes over time in the two-phase resolver, the output timing of the excitation signal output to the resolver 1 It is possible to adjust the sampling phase relatively by adjusting and to always perform sampling with an accurate phase and to calculate accurate angle information as a result.

Embodiment 3 FIG.
Next, Embodiment 3 will be described with reference to the drawings.
FIG. 8 is a block diagram showing a resolver / digital conversion apparatus 100 according to the third embodiment. The difference between the third embodiment and the first embodiment is that the output timing of the excitation signal is controlled instead of controlling the sampling phase of the AD converters 2 and 3. 8, components that perform the same operations as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted, and the other portions will be described. The output of the phase correction circuit 29 that outputs the sampling pulse and the phase control signal of the excitation signal is input to the excitation signal generation circuit 30. The phase correction circuit 29 calculates a timing correction amount from the output from the reference counter 6 and the outputs from the AD converters 2 and 3. In the first embodiment, control is performed so as to correct the sampling timing. However, in the third embodiment, the output timing of the excitation signal is adjusted so as to match the sampling timing. The method for calculating the amount of phase shift is the same as in the first embodiment. The excitation signal generation circuit 30 adjusts and outputs the timing for outputting the excitation signal based on the input from the phase correction circuit 29.
As described above, in the third embodiment, even if the propagation delay times of the signals of the two phases vary in the two-phase resolver, the sampling can always be performed with an accurate phase. As a result, accurate angle information can be calculated.

Embodiment 4 FIG.
Next, a fourth embodiment will be described.
FIG. 9 is a flowchart showing a resolver / digital conversion method according to Embodiment 4 of the present invention. The difference between the fourth embodiment and the first embodiment is that processing is performed by software. When performing the resolver / digital conversion process, a microcomputer, a DSP (Digital Signal Processor), or the like can be used. FIG. 9 shows a control flowchart in that case. In FIG. 9, S1 is an input step for inputting the digital value of the AD-converted two-phase resolver signal, S2 is a reset operation step for setting the output of the reference counter operating at the system clock to zero, and S3 is the system clock. An incrementing step of adding +1 to the operating reference counter, S4 is a step of calculating a sampling timing correction amount, S5 and S6 are sinusoidal waves and cosine waves based on angles from a two-phase resolver signal by synchronous detection processing or the like. A step of AM demodulation for extracting S, a step of comparing with a counter value in order to determine a sampling output timing, a step of performing a function calculation of arc tangent (arcTan), and a step S9 of exciting signal to the resolver Output step, S10 is a sampling pulse to AD converters 2 and Output steps, S11 is a step of outputting the digital angle information.

Next, the operation will be described.
When processing is performed by software such as a microcomputer, the basic unit of calculation processing is performed based on a high-speed clock such as a system clock. FIG. 9 is a flowchart for converting the resolver signal into angle information and outputting it, but the execution periods of step S9 for exciting sine wave output, step S10 for sampling pulse output, and step S11 for angle information output are different. Yes. The angle information output step S11 is executed for each excitation frequency cycle to output angle information, and the sampling pulse output step S10 is executed four times within one excitation frequency cycle to output a sampling pulse. Is done. Step S9 of the excitation sine wave output is executed every certain period with the system clock as a reference.

In step S1, a two-phase resolver signal digitized by AD conversion is captured four times in one cycle of the excitation signal. Since the basic cycle of the process of this flowchart assumes one cycle of the excitation signal, step S2 is first performed as a reset of the reference counter, and each process is performed until the reference counter advances to the value of one cycle of the excitation signal. Execute. Note that step S2 is not necessary in a configuration in which reset is automatically performed in hardware. Step S3 is a step of incrementing the reference counter. If the counter is automatically advanced, this step is also unnecessary. In step S4, a sampling timing correction amount is calculated from the input resolver data. The calculation method is the same as the method described above. If the timing to be corrected is obtained in step S4, the correction value is passed to step S7. In step S7, the value passed from step S4 is held, and the output timing of the sampling pulse is controlled by reflecting the value from the execution of the next cycle. Step S7 operates so as to output a sampling pulse to Step S10 when the reference counter 6 reaches a desired value, and when AD conversion is performed at a frequency four times the excitation frequency, A pulse is output four times in one cycle.
Steps S5 and S6 are AM demodulation steps by synchronous detection. Step S8 is a step of obtaining Nθ based on the function calculation of arc tangent (arcTan) using the results obtained in steps S5 and S6. Step S9 is a step of outputting an excitation signal, and generally it is often converted into a sine wave waveform using a ROM. The output timing depends on the processable speed. In particular, when the processing speed is fast, it can be output in synchronization with the system clock, but it can operate as an excitation signal output even at a low speed such as one-half or one-fourth of the system clock. Step S10 is a step of outputting a sampling pulse, outputting a pulse for AD conversion, and step S11 outputting the calculated digital angle information.

  As described above, the resolver / digital conversion method according to the fourth embodiment has the same effects as those of the first embodiment.

  In the first to fourth embodiments, the resolver outputs an example of a two-phase resolver signal. However, the present invention is not limited to this and may be a case of outputting two or more phases.

1 resolver, 2, 3 AD converter, 4 angle calculation circuit, 5 phase correction circuit,
6 reference counter, 7 excitation signal generation circuit, 100 resolver / digital converter.

Claims (7)

An excitation signal generation circuit for generating an excitation signal for exciting a resolver attached to a rotating device at a predetermined frequency, and a voltage signal output from the resolver are sampled at a sampling timing at a predetermined frequency and converted into a digital signal. In a resolver / digital conversion apparatus provided with an analog / digital converter and a phase correction circuit for correcting the sampling timing based on the digital signal,
The phase correction circuit samples the digital signal output from the analog / digital converter obtained at the sampling timing four times in one cycle of the frequency of the excitation signal, and at a timing when it becomes zero. The phase of the sampling timing is discriminated based on the amplitude level of the data to correct the phase, the sampling timing is corrected by correcting the phase, and the analog / digital converter performs the sampling after the correction. A resolver / digital conversion apparatus characterized by sampling timing and a voltage signal of the resolver. An excitation signal generation circuit for generating an excitation signal for exciting a resolver attached to a rotating device at a predetermined frequency, and a voltage signal output from the resolver are sampled at a sampling timing at a predetermined frequency and converted into a digital signal. A resolver / digital conversion apparatus provided with an analog / digital converter, a reference counter that operates with a reference clock, and a phase correction circuit that corrects the sampling timing based on the digital signal and the output of the reference counter In
The phase correction circuit samples the digital signal output from the analog / digital converter obtained at the sampling timing four times in one cycle of the frequency of the excitation signal, and at a timing when it becomes zero. The phase of the sampling timing is corrected based on the amplitude level of the data and the output of the reference counter, the sampling timing is corrected by correcting the phase, and the excitation signal generation circuit sets the sampling timing after the correction. A resolver / digital conversion device, wherein the output timing of the excitation signal is controlled so as to match. The phase correction circuit samples the digital signal for each phase output from the analog / digital converter four times in one cycle of the frequency of the excitation signal, and the data at the timing when it becomes zero The resolver / digital conversion device according to claim 1, wherein a phase shift of the sampling timing is determined based on each amplitude level, and the phase of each sampling timing is corrected. 3. The resolver / digital conversion device according to claim 1, wherein the voltage signal output from the resolver is a signal having two or more phases. 4. 3. The resolver / digital conversion device according to claim 1, wherein the predetermined frequency of the sampling timing is an integer multiple of 4 of a frequency for exciting the resolver. 4. The digital signal obtained by exciting the resolver attached to the rotating device at a predetermined frequency, sampling the voltage signal output from the resolver at a sampling timing at a predetermined frequency, and converting it to a digital signal. On the other hand, sampling is performed four times in one cycle of the frequency of the excitation signal, and the phase is corrected by determining the phase shift of the sampling timing based on the amplitude level of the data at the timing when it becomes zero. The resolver / digital conversion method characterized in that the voltage signal of the resolver is sampled at the corrected sampling timing. The resolver / digital conversion method according to claim 6, wherein the resolver voltage signal output from the resolver is a signal of two or more phases.

Images