JP5166211B2 - Device using non-volatile memory as main memory - Google Patents

Description

  The present invention relates to an embedded device such as a mobile phone, a car navigation system, and a TV, and a system using them.

  2. Description of the Related Art In recent years, with increasing performance and capacity of non-volatile memories and lowering of the unit price of bits, non-volatility of cache memories of main storage units and storage (HDD, etc.) composed of volatile memories has been progressing. . The nonvolatile memory can hold the stored contents even when power is not supplied, and thus is very effective for developing a device with low power consumption. In particular, development aimed at mounting on a portable terminal is progressing.

  In the future, it is said that a single nonvolatile memory called universal memory with low cost and high performance that can be applied to all of cache memory, main memory, and storage will be realized and installed in various devices. Yes.

  Under such circumstances, a study of a system composed only of a non-volatile memory is also proceeding, a system in which a main memory is configured using a flash memory (see, for example, Patent Document 1), a ROM area, a random access area, In addition, there is a system (for example, see Patent Document 2) that uses a ferromagnetic memory divided into three areas of a storage area.

In addition, the main storage area of the system is composed of a volatile part and a non-volatile part. Information necessary to continue the process when the power is shut off is stored in the non-volatile part. There has also been proposed a system that realizes quick recovery by transferring to a volatile unit (for example, Patent Document 3).
JP-A-5-334168 US Pat. No. 6,449,683 B1 JP 2004-36246 A

  However, in the above-described prior art, even if the memory is composed only of a nonvolatile memory, if a sudden power interruption occurs, data being written to the memory element, I / O access processing, a register in the processor, or the like The system will not operate properly when the power is restored.

  Further, in the above-described conventional technology, when a mixed memory composed of a volatile memory and a nonvolatile memory is used as a main storage unit, it takes time to save data for suspending the system.

  A typical example of the present invention is as follows. That is, a device using a nonvolatile memory including a processor, one or more nonvolatile memories, and a peripheral circuit as a main memory, and the device detects whether or not the power supply of the device is abnormally cut off. And a power supply abnormal end notification register for storing information indicating that the power supply of the device has been cut off abnormally, the peripheral circuit includes a power supply circuit, and the non-volatile memory is an operating system. A system, software, and a device driver are stored, and the operating system includes the power supply abnormality interruption determination unit, and the power supply abnormality interruption determination unit refers to the power supply abnormality end notification register when the apparatus is turned on. The power failure end notification register stores information indicating that the power supply of the device is abnormally shut down, and the processor is If the processor is not a compatible processor, restart the process that was being executed before the device was turned off, check the device driver, and the power failure termination notification register was turned off abnormally. If the processor is a non-volatile processor, the process executed before the power of the device is shut down is restarted from the process where the process was interrupted, It is characterized by checking a device driver.

  ADVANTAGE OF THE INVENTION According to this invention, the process in the recovery | restoration from a sudden power shutdown and a system stop can be performed at high speed and reliably.

[Embodiment]
First, the outline | summary of embodiment of this invention is demonstrated.

  First, in hardware including a processor, a volatile memory, a nonvolatile memory, and a peripheral circuit, at least one of the power supply circuit, the processor, or the nonvolatile memory includes a power supply interruption determination function and a power supply interruption notification register. Prepare.

  As a result, when the power is turned on to the hardware, the OS determines whether or not the power supply interruption notification register is set. If the power supply is set, the OS determines that the power supply is recovered from the power supply interruption. Execute. In the recovery process, the OS determines whether or not the processor is volatile. If the processor is volatile, the OS restarts the process that was being executed before the power was shut down. If the processor is non-volatile, the OS resumes processing based on information about the process held by the processor. Next, the OS determines the state of each device driver, determines whether or not the process can be restarted. If the process cannot be restarted, the OS notifies the caller process and executes error processing.

  Secondly, in hardware in which the main storage area is composed of a plurality of volatile memories and nonvolatile memories, virtual memory consisting of logical addresses and physical addresses is supported, and each memory space is managed by pages of a certain size. System.

  When switching from a user interface process to a background process, or when logical-physical address conversion occurs, the OS determines the priority of a page on a low-speed nonvolatile memory or volatile memory, and the priority Based on the above, the replacement flag is set, and the replacement is executed when the system is idle.

  Furthermore, when the code area and constants of processes that are not updated are allocated in the volatile memory, and the data to be updated is preferentially allocated in the nonvolatile memory, the system power supply is suddenly shut down. Even if the data in the volatile memory is lost, the OS reads the code part or constant part of the process from the storage, and executes the recovery process using the data held in the nonvolatile memory.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram illustrating the configuration of an embedded device according to an embodiment of the present invention.

  This embedded device includes a processor 104, a nonvolatile memory 101, and a peripheral circuit 102, which are connected to each other by a bus.

  The processor 104 includes a register, an instruction execution unit, and the like. In the present embodiment, the processor 104 includes an instantaneous interruption determination register A121.

  The instantaneous interruption determination register A121 stores information indicating whether or not the power supply is suddenly cut off, and is set when the voltage in the processor 104 becomes unstable. Further, the OS 107 clears the instantaneous interruption determination register A121.

  The nonvolatile memory 101 includes an instantaneous interruption determination register B116, a remaining write check counter 117, a normal end register 124, and a data recording unit 123.

  The instantaneous interruption determination register B116 stores information indicating whether or not the power supply is suddenly cut off. For example, when the voltage of the nonvolatile memory 101 becomes unstable, when power is turned on to the nonvolatile memory 101, or when the normal end register 124 is not set, the instantaneous interruption determination register B116 is set. .

  The remaining write check counter 117 stores information indicating the number of areas in the data received by the nonvolatile memory 101 that have not been written to the memory. As the region, for example, a memory cell unit, a bit unit, a byte unit, or a block unit can be considered. Depending on the non-volatile memory 101, it takes time until the writing to the memory cell is completed after receiving the write data. Therefore, when the power is shut off during the writing process, the data that could not be written to the memory cell is lost. The remaining write check counter 117 is for detecting that the above-described abnormality has occurred.

  The normal end register 124 stores information indicating whether the power supply is suddenly shut down (instantaneous power interruption) or a recovery after the power supply is normally shut down. The normal end register 124 is set by the processor 104 or the OS 107 when the system ends normally. When the nonvolatile memory 101 is activated, the internal control circuit (labor saving in the figure) checks the normal end register 124. If the normal end register 124 is set, the instantaneous interruption determination register B116 is set, and the normal end register 124 is set. If not, the instantaneous interruption determination register B116 is set.

  The data recording unit 123 indicates an area of the nonvolatile memory 101 in which data is actually stored. For example, it is composed of memory cells or the like. In the present embodiment, the data recording unit 123 is divided into a ROM (Read Only Memory) area 119, a main storage area 113, and a storage area 114.

  The ROM area 119 is an area used as a ROM, and is an area for storing data such as the OS 107, execution program code, etc. that do not update during normal operation. In the example illustrated in FIG. 1, the OS 107 and the basic application group 108 are stored.

  An OS 107 indicates the OS main body, and stores data such as an execution code that does not occur during normal operation. In the present embodiment, the OS 107 includes a device driver 126 that is a program group that controls hardware such as the peripheral circuit 102, and a power recovery processing function 111 that is a function of executing power recovery processing.

  When the system is activated, the power recovery processing function 111 reads the instantaneous interruption determination register (A121, B116, C122), and executes a determination process of whether to restart or to recover from the power interruption.

  The basic application group 108 stores the OS 107 and a software group that is constantly used by the device. For example, a device driver, a GUI program, a web browser, and the like.

  The main storage area 113 stores data updated during normal operation. In the present embodiment, the main storage area 113 stores the OS management information 103 and the process 115.

  The OS management information 103 stores various types of management information of the OS 107 that is updated. Specifically, the power-off detection destination designation data 120, the activation identification flag 112, the process management table 106, the logical physical conversion table 105, the file system. / Database management 110 and process 115.

  The power-off detection destination designation data 120 stores data for designating means for detecting the cause of power-off. That is, data indicating which of the registers (instant interruption determination register or the like) or data provided in the system is to be read is stored. As a result, a flag for designating the data reading destination for instantaneous interruption determination is set. The power-off detection destination designation data 120 is a value set in the system from the beginning. The power-off detection destination designation data 120 may be designated by the user.

  The activation identification flag 112 stores information indicating whether it is a restart or a recovery from a power failure, and is referred to by the power recovery processing function 111 in order for the OS 107 to determine the reason for the operation resumption when the operation is resumed. Specifically, when the activation identification flag 112 is “0”, a restart flag is set, and when the activation identification flag 112 is “1”, a power-off recovery flag is set.

  The process management table 106 stores information for managing all processes existing on the system.

  The logical-physical conversion table 105 stores information for managing the correspondence when the system uses a logical address and a physical address.

  The file system / database management 110 stores management information of files or databases (DB) stored in the storage area 114.

  The process 115 stores individual programs executed by the OS 107. For example, an application or communication middleware.

  The storage area 114 stores file format data and various saved data. In the example shown in FIG. 1, various files 125 that are data groups of file formats such as programs, moving images, still images, and music, temporary information generated during the execution of the process, page data with low execution priority, and the like The save data 109 is stored.

  The peripheral circuit 102 includes various peripheral functions such as a key, a touch panel, a display, a microphone, a speaker, and a network connection function, and a power supply circuit 118.

  The power supply circuit 118 manages the power supply of each device, and includes an instantaneous interruption determination register C122 in this embodiment.

  The instantaneous interruption determination register C122 stores information indicating whether or not the power supply is suddenly cut off. The instantaneous interruption determination register C122 is set when an abnormality is detected by the power supply circuit 118, and the OS 107 is cleared.

  In the present embodiment, it is assumed that the embedded device includes all instantaneous interruption registers (A121, B116, C122). In addition, the form provided only with one of the instantaneous interruption registers | resistors (A121, B116, C122) may be sufficient.

  FIG. 2A is a diagram illustrating an example of basic data 206 included in the process management table 106 according to the embodiment of this invention. The basic data 206 manages basic attributes of each process.

  The basic data 206 includes a process ID 201, a segment 202, and a state 205.

  The process ID 201 stores an identifier for identifying a process.

  The segment 202 stores information for specifying an area on a memory in which a process corresponding to the process ID 201 is stored, and further includes a code area 203 and a data area 204.

  The code area 203 stores information indicating the storage location of the execution code of the process corresponding to the process ID 201.

  The data area 204 stores information indicating a location where a process corresponding to the process ID 201 is stored.

  The state 205 stores information indicating the process state. For example, “in execution” is stored when the processor 104 is executing a process corresponding to the process ID 201, and “waiting” is stored when the processor 104 is waiting to execute a process corresponding to the process ID 201. If the process 104 is waiting for a response corresponding to the process ID 201 to another process or I / O, “wait for response” is stored.

  FIG. 2B is a diagram showing an example of the process type definition table 218 according to the embodiment of this invention.

  The process type definition table 218 defines process types and process execution priorities, and is used when calculating the overall priority 209 of the extended data 207 included in the process management table 106.

  The process type definition table 218 includes a process type 227 and a priority 228.

  The process type 227 stores information indicating the type of process. For example, in the case of a user interface system process, “UI” is stored, in the case of a process providing a server function that operates in the background, “service” is stored, and in the case of other processes, “normal” is stored. .

  The priority 228 stores the priority of the process corresponding to the process type 227. The priority value is executed preferentially from a large process.

  FIG. 2C is a diagram illustrating an example of the extended data 207 included in the process management table 106 according to the embodiment of this invention. The extended data 207 manages information necessary for determining the execution priority of the process.

  The extended data 207 includes a process ID 208, an overall priority 209, a process type 210, and a usage frequency 211.

  The process ID 208 is the same as the process ID 201.

  The overall priority 209 stores the priority of the process actually handled by the OS 107. Processes with a higher overall priority 209 are executed preferentially. The general priority 209 is calculated from the process type 210 and the usage frequency 211. For example, a process corresponding to the process type 210 is searched from the process type definition table 218, and an average value, a maximum value, a minimum value, or the like is calculated by using the searched priority 228 and usage frequency 211 values. The

  Further, when a plurality of processes access the same page, the total priority 209 is calculated, for example, by obtaining an average value, a maximum value, a minimum value, or the like of each priority 228 of the plurality of processes. The overall priority 209 is reflected in the overall priority 813 of the extension data (see FIG. 8B) included in the logical-physical conversion table 105.

  The usage frequency 211 stores the usage frequency of each state of the system. Specifically, the usage frequency 211 includes three types: immediately after startup 212, immediately after return 213, and during normal operation 214.

  Immediately after the activation 212 stores the number of times the process has been activated immediately after the activation of the system. Immediately after starting 212, a value of “1” is added when a process is started immediately after starting the system. The determination immediately after the system is started can be made, for example, by defining the time from when the system is started to when the screen for user operation is displayed as immediately after the system is started.

  Immediately after recovery 213 stores the number of times the process has been started immediately after the system has recovered from a power interruption. Immediately after the return 213, a value of “1” is added when the process is started immediately after the system recovers from a power interruption. The determination as to whether or not it is immediately after return is the same as that immediately after startup 212.

  In the normal operation 214, the number of times the process has been started is stored in addition to the above two states. During normal operation 214, a value of “1” is added when a process is started in addition to the two states described above.

  In addition to the items described above, various determination criteria such as process execution time, process scale, or user-specified priority can be considered for the priority setting items.

  FIG. 2D is a diagram illustrating an example of the storage location management data 215 included in the process management table 106 according to the embodiment of this invention. The storage location management data 215 manages in which area of which memory a process is stored when an embedded device is configured using a plurality of types of memory.

  The storage destination management data 215 is referred to when the OS 107 executes data saving or replacement.

  The storage location management data 215 includes a process ID 216 and a segment 219.

  The process ID 216 is the same as the process ID 201.

  The segment 219 stores information indicating in which area on the memory the execution code of the process corresponding to the process ID 216 is stored. The segment 219 further includes a code area 229 and a data area 220.

  The code area 229 stores information indicating the memory in which the execution code of the process corresponding to the process ID 216 is stored.

  The data area 220 stores information indicating in which memory the process corresponding to the process ID 216 is stored. The data area 220 further includes a constant 221 and an update generation unit 222.

  The constant 221 is a basic parameter embedded in the process from the beginning. In the example shown in FIG. 2D, the constant 221 stores the memory type ID 223 (see FIG. 2E).

  The update generation unit 222 stores information for specifying the memory in which the process to be updated is stored. In the example shown in FIG. 2D, the update generation unit 222 stores a memory type ID 223 (see FIG. 2E).

  FIG. 2E is a diagram showing an example of the memory type definition table 217 in the embodiment of the present invention. The memory type definition table 217 defines the attributes of each memory constituting this embedded device.

  The memory type definition table 217 includes a memory type ID 223, a type 224, a read speed 225, and a write speed 226.

  The memory type ID 223 stores an identifier for identifying the memory.

  The type 224 stores a memory type corresponding to the memory type ID 223. Specifically, information indicating whether the memory is volatile or nonvolatile is stored.

  The Read speed 225 indicates the unit reading time of the memory corresponding to the memory type ID 223, and indicates that the smaller the value, the faster.

  The write speed 226 indicates the unit writing time of the memory, and indicates that the smaller the value, the faster.

  The Read speed 225 and the Write speed 226 are values determined when the memory is installed.

  FIG. 3 is a flowchart illustrating the setting process of the activation identification flag 112 according to the embodiment of this invention.

  This process is executed when the system is booted, and is a process for setting the boot identification flag 112 that the OS 107 uses for boot reason determination. Note that reasons for hardware activation include system restart, recovery from power failure, and return from sleep state.

  First, power is turned on to the system, and power supply to the processor 104, peripheral circuits, and nonvolatile memory 101 is started (step 301).

  The OS 107 determines whether or not the power-off detection destination designation data 120 is “0” (step 302).

  When it is determined that the power-off detection destination designation data 120 is “0”, the OS 107 reads the instantaneous interruption determination register C122 included in the power supply circuit 118, and the read instantaneous interruption determination register C122 is used as the activation identification flag 112. Setting is made (step 303), and the process is terminated.

  When it is determined that the power-off detection destination designation data 120 is not “0”, the OS 107 determines whether or not the power-off detection destination designation data 120 is “1” (step 304).

  When it is determined that the power-off detection destination designation data 120 is “1”, the OS 107 reads the instantaneous interruption determination register B116 included in the nonvolatile memory 101, and uses the read instantaneous interruption determination register B116 as the activation identification flag 112. (Step 305), and the process ends.

  When it is determined that the power-off detection destination designation data 120 is not “1”, the OS 107 determines whether the power-off detection destination designation data 120 is “2” (step 306).

  When it is determined that the power-off detection destination designation data 120 is “2”, the OS 107 reads the instantaneous interruption determination register A121 included in the processor 104 and sets the read instantaneous interruption determination register A121 in the activation identification flag 112. (Step 307), and the process ends.

  If it is determined that the power-off detection destination designation data 120 is not “2”, the OS 107 determines whether the power-off detection destination designation data 120 is “3” (step 308).

  When it is determined that the power-off detection destination designation data 120 is not “3”, the OS 107 ends the process.

  When it is determined that the power-off detection destination designation data 120 is “3”, the OS 107 reads the remaining write check counter 117 (step 309).

  Next, the OS 107 determines whether or not the remaining write check counter 117 is “0” (step 310).

  When it is determined that the remaining write check counter 117 is not “0”, the OS 107 sets “1” in the activation identification flag 112 (step 311) and ends the process.

  When it is determined that the remaining write check counter 117 is “0”, the OS 107 sets “0” in the activation identification flag 112 (step 312), and ends the process.

  The data stored in the power-off detection destination designation data 120 may be any data as long as it specifies the information reading destination (for example, the instantaneous interruption determination register A121). In this embodiment, values “0” to “3” are stored, and the OS 107 acquires information from a read destination corresponding to the value.

  FIG. 4 is a flowchart for explaining the flow from the start of the OS 107 to the start of processing in the embodiment of the present invention.

  In this process, the power recovery processing function 111 that is executed when the OS 107 is activated refers to the activation identification flag 112, determines the reason for activation, and resumes the process based on the determination result.

  The power recovery processing function 111 confirms the activation identification flag 112 (step 401).

  Next, the power recovery processing function 111 determines whether or not the activation identification flag 112 is “1” (step 402).

  When it is determined that the activation identification flag 112 is “1”, the power recovery processing function 111 determines whether or not the processor 104 is nonvolatile (step 403).

  Here, the non-volatile processor 104 means the processor 104 in which a register is configured with non-volatile elements. Therefore, the nonvolatile processor 104 can retain the register even after the power is turned off.

  In step 403, if the processor 104 is volatile, the register held by the processor 104 is cleared before the power is turned off. Therefore, in order for the OS 107 to restart the process, it is necessary to acquire information held in the register before the power is turned off. On the other hand, in the case of the nonvolatile processor 104, the register before the power is turned off is held. Therefore, in order for the OS 107 to restart the process, it is not necessary to acquire a register before the power is turned off.

  For the reasons described above, in step 403, it is determined whether the processor 104 is volatile. Whether or not the processor 104 is nonvolatile is determined by referring to the identification information of the processor held by the processor 104 by the OS 107.

  If it is determined that the processor 104 is non-volatile, the power recovery processing function 111 proceeds to step 405.

  When it is determined that the processor 104 is not nonvolatile, the power recovery processing function 111 refers to the process management table 106 and restarts the process whose state 205 is “executing” (step 404).

  Next, the power recovery processing function 111 determines whether or not the states of all device drivers 126 have been confirmed (step 405).

  When it is determined that the states of all the device drivers 126 have been confirmed, the power recovery processing function 111 ends the processing.

  When it is determined that the states of all device drivers 126 have not been confirmed, the power recovery processing function 111 confirms the states of the device drivers 126 (step 406). The content to be confirmed is, for example, whether the hardware and data exchange have not been interrupted or destroyed.

  The power recovery processing function 111 determines whether or not the interrupted processing can be resumed (step 407). For example, if the power is shut off during the issuance of commands and data that should be issued to the hardware in a batch, it is determined that the interruption process cannot be resumed.

  When it is determined that the interruption process cannot be resumed, the power recovery processing function 111 transmits an abnormal termination notification to the calling process (step 408). For the notified process, an error recovery process such as retry of the process is executed.

  When it is determined that the interruption process can be resumed, the power recovery processing function 111 returns to step 405.

  If it is determined in step 402 that the activation identification flag 112 is not “1”, the power recovery processing function 111 initializes the system (step 409).

  The power recovery processing function 111 sets “1” in the activation identification flag 112 and ends the processing (410).

  As described above, when the system power is turned on by the processing of FIGS. 3 and 4, it can be determined whether the OS 107 is normally turned on or has returned from an abnormality such as an instantaneous power interruption. Error recovery processing can be executed quickly and system operation can be resumed.

  FIG. 5 is a flowchart for explaining the update processing of the usage frequency 211 in the embodiment of the present invention.

  This process is executed by the OS 107 when the process is activated.

  First, the process is started (step 501).

  The OS 107 determines whether or not the process activation timing is immediately after the system activation (step 502). In the determination, for example, it is determined whether or not a process has been started from when the system is started to when a screen for a user to operate is displayed.

  If it is determined that the process activation timing is immediately after system activation, the OS 107 adds “1” to the value immediately after activation of the entry that matches the process ID 208 of the activated process (step 503), and ends the process. To do.

  If it is determined that the process activation timing is not immediately after system startup, the OS 107 determines whether or not the process activation timing is immediately after system recovery (step 504). In this determination, as in step 502, it is determined whether or not the process has been started at a certain timing.

  If it is determined that the process activation timing is immediately after the system is restored, the OS 107 adds “1” to the value 213 immediately after the restoration of the entry that matches the process ID 208 of the activated process (step 505), and ends the process. To do.

  When it is determined that the process activation timing is not immediately after the system recovery, the OS 107 determines whether or not the process activation timing is the system normal operation time (step 506).

  When it is determined that the process activation timing is during the normal system operation, the OS 107 adds “1” to the normal operation 214 value of the entry that matches the process ID 208 of the activated process (step 507). Exit.

  If it is determined that the process activation timing is not during normal system operation, the OS 107 ends the process.

  As described above, the system in the embedded device according to the present invention designates the instantaneous interruption determination register (A121, B116, C122) to be confirmed when the system is activated in advance as shown in FIG. The read instantaneous interruption determination register (A121, B116, C122) is read, and the read instantaneous interruption determination register is set in the activation identification flag 112. With this process, the OS 107 can determine whether or not the power supply is restored from a power interruption. Further, the OS 107 refers to the activation identification flag 112 when the system is activated, and executes a recovery process in the case of an instantaneous power interruption.

  As a result, the system can operate normally when power is restored.

  Next, processing for dynamically changing the storage location of data stored in the memory based on the process management table (206, 207, 215) will be described.

  This process is not limited to the embedded device having the single nonvolatile memory shown in FIG. 1, but in particular, the embedded device having a plurality of types of nonvolatile memories as shown in FIG. 6, or the nonvolatile device as shown in FIG. It is most suitable for embedded devices equipped with volatile memory and volatile memory. First, the system configuration of the embedded device shown in FIGS. 6 and 7 will be described.

  FIG. 6 is a block diagram illustrating an example of the configuration of the embedded device according to the embodiment of this invention.

  Compared with the configuration of the embedded device shown in FIG. 1, the configuration of the embedded device shown in FIG. 6 includes a plurality of types of nonvolatile memories having different characteristics. The characteristics of the nonvolatile memory are, for example, a high-performance memory that reads and writes at high speed, or a low-performance memory that reads at high speed and writes slowly. Hereinafter, the difference from FIG. 1 will be mainly described.

  The processor 104 newly includes a memory management unit 607.

  The memory management unit 607 includes a TLB (Table Lookup Buffer) 614. The memory management unit 607 uses the TLB 614 to perform conversion between the logical address space 628 and the physical address space 627 as indicated by the range 626.

  The TLB 614 holds correspondence information between logical addresses and physical addresses having a high use frequency as shown in the range 626 in the logical-physical conversion table 105. Normally, when an address that is not held by the TLB 614 is accessed, it is necessary to access the logical-physical translation table 105, and it takes time for the address translation processing. However, the TLB 614 holds the address information of the access destination, The conversion process of the management unit 607 can be speeded up.

  A case where an address not held by the TLB 614 is accessed is called a TLB miss.

  Further, the logical address space 628 and the physical address space 627 are associated with each page, which is an area unit of a certain size. In general, the page size is often about 4 kbytes. Hereinafter, a page in the logical address space 628 is referred to as a logical page 623, and a page in the physical address space 627 is referred to as a physical page 621. However, there are as many logical pages 623 as 1 to n, and there are as many physical pages 621 as 1 to m.

  The configuration of the embedded device shown in FIG. 6 includes a nonvolatile memory A 601, a nonvolatile memory B 630, a nonvolatile memory C 616, and a storage 602.

  The ROM area 119 is configured in the nonvolatile memory A601. As the non-volatile memory A601, for example, a ROM or a NOR type memory can be considered.

  The main storage area 113 is configured by a nonvolatile memory B630 and a nonvolatile memory C616. As the nonvolatile memory B630, for example, a memory capable of high-speed random access such as SP-RAM can be considered. Further, the non-volatile memory C616 may be a memory that is slower in writing speed than the non-volatile memory B630 such as a NOR type memory and can perform random reading.

  The nonvolatile memory B 630 includes a logical / physical conversion table 105. The logical-physical translation table 105 manages the correspondence between logical addresses and physical addresses in a system that supports virtual addresses, and page attributes in each address space (physical address space 627 and logical address space 628).

  In this embodiment, process codes and data are stored in a distributed manner in accordance with memory characteristics. For example, a data area in which a process update with a high priority occurs is stored in the nonvolatile memory B 630, and a data area of a process with a low priority, a code part of the process, and a constant part in the data area are stored in the nonvolatile memory C616. Can be stored in That is, data with a high update frequency is stored in a non-volatile memory (in this case, the non-volatile memory B 630) that is written and read at high speed, and data with a low update frequency is read at a high speed and written at a low speed. It is stored in a nonvolatile memory (in this case, the nonvolatile memory C616).

  In general, a high-performance memory such as the non-volatile memory B630 is expensive, and a low-performance memory such as the non-volatile memory C616 is low in price. Manufacturing cost can be reduced.

  Data stored in the storage 602 is the same as the storage area 114 in FIG. Further, the storage 602 in the present embodiment may be an HDD, a flash memory, or the like.

  The combination of the nonvolatile memory and the storage is an example, and other combinations may be used.

  FIG. 7 is a block diagram illustrating an example of the configuration of the embedded device according to the embodiment of this invention.

  Compared to FIG. 6, the system of the embedded device of FIG. 7 includes a volatile memory 701 instead of the nonvolatile memory C616. The data stored in the volatile memory 701 is the same as that of the nonvolatile memory C616.

  Data stored in the volatile memory 701 is lost when the system is powered off, but can be restored by reading the data stored in the storage 602.

  Hereinafter, specific processing will be described with reference to FIGS. 6 and 7 as an example. Also in FIG. 1, when the processor 104 includes the memory management unit 607 logical-physical conversion table, the same processing can be performed.

  FIG. 8A is a diagram illustrating an example of basic data 801 included in the logical-physical conversion table 105 according to the embodiment of this invention.

  The basic data 801 manages basic information of each page (physical page 621 and logical page 623).

  The basic data 801 includes a page ID 803, a logical address 804, a physical address 805, and an attribute 811.

  The page ID 803 stores an identifier for identifying each page (physical page 621 and logical page 623).

  The logical address 804 stores a logical address corresponding to each page (physical page 621 and logical page 623).

  The physical address 805 stores a physical address corresponding to each page (physical page 621 and logical page 623). If there is no corresponding data on the memory, “0xffffff” is stored in the physical address 805. However, any value may be used as long as it is an invalid value as a real address.

  The attribute 811 stores the attribute of each page (physical page 621 and logical page 623). The attribute 811 further includes a write permission 806, an accessible process 807, a memory ID 808, and a save to storage 809.

  The write permission 806 stores a value indicating whether or not writing is permitted to the page (physical page 621 and logical page 623) corresponding to the page ID 803. For example, when writing is permitted for each page (physical page 621 and logical page 623), “y” is stored, and when writing is not permitted for each page (physical page 621 and logical page 623), “ n "is stored.

  The accessible process 807 stores a list of processes that can access the page (physical page 621 and logical page 623) corresponding to the page ID 803.

  The memory ID 808 stores an identifier for identifying a memory in which a page (physical page 621 and logical page 623) corresponding to the page ID 803 exists. The memory ID 808 is the same as the memory type ID 223.

  The save to storage 809 stores information indicating whether the information stored in the page (physical page 621 and logical page 623) corresponding to the page ID 803 has been saved to the storage 602. For example, when information stored in the page corresponding to the page ID 803 (physical page 621 and logical page 623) is saved in the storage 602, “y” is stored and the page corresponding to the page ID 803 (physical page 621). When the information stored in the logical page 623) is not saved in the storage 602, “n” is stored.

  FIG. 8B is a diagram illustrating an example of the extended data 802 included in the logical-physical conversion table 105 according to the embodiment of this invention.

  The extended data 802 manages information that is referred to in the process of replacing each page (physical page 621 and logical page 623).

  The extended data 802 includes a page ID 812, a general priority 813, and a replacement flag 810.

  The page ID 812 is the same as the page ID 803.

  The general priority 813 is the same as the general priority 209. The overall priority 813 of the page (physical page 621 and logical page 623) is determined by the mutual priority 209 of the process. That is, the page corresponding to the page ID 812 indicates that the process corresponding to the general priority 813 is stored.

  The replacement flag 810 stores a value indicating whether to replace pages and a value for identifying a pair of pages to be replaced. Specifically, when the page is replaced, a value of “0” or more is stored, and when the page is not replaced, “−1” is stored. Further, the replacement flag 810 of the page to be replaced stores the same value in the replacement source page and the replacement destination page. The replacement flag 810 is assigned by the OS 107.

  FIG. 9A, FIG. 9B, and FIG. 9C are flowcharts for explaining the flow of system activation and process restart according to the present invention.

  The power recovery processing function 111 confirms the activation identification flag (step 901).

  The power recovery processing function 111 determines whether or not the activation identification flag 112 is “1” (step 902).

  When it is determined that the activation identification flag 112 is “1”, the power recovery processing function 111 refers to the extended data 207 included in the process management table 106 and sets the values in the process management table 106 in descending order of the value 212 immediately after activation. The entries are rearranged (step 903).

  The power recovery processing function 111 determines whether the processor 104 is non-volatile (step 904).

  When it is determined that the processor 104 is not nonvolatile, the power recovery processing function 111 refers to each data in the process management table 106 and determines whether or not processing has been completed for all entries (step 905).

  When it is determined that the processing has been completed for all entries, the power recovery processing function 111 proceeds to step 916.

  When it is determined that the processing has not been completed for all entries, the power recovery processing function 111 reads one entry from the process management table 106, and the process information corresponding to the process ID 201 of the entry is all non-volatile. It is determined whether it is stored in the memory (step 906).

  When it is determined that all the process information corresponding to the process ID 201 is stored in the nonvolatile memory, the power recovery processing function 111 corresponds to the process ID 201 based on the information stored in the nonvolatile memory. A process whose process state 205 is “executing” is restarted (step 907), and the process returns to step 905.

  When it is determined that the process information corresponding to the process ID 201 is stored in addition to the nonvolatile memory, the power recovery processing function 111 stores part of the information corresponding to the process ID 201 in the nonvolatile memory. It is determined whether it has been performed (step 908).

  When it is determined that a part of the process information corresponding to the process ID 201 is stored in the nonvolatile memory, the power recovery processing function 111 is stored in the nonvolatile memory among the process information corresponding to the process ID 201. Information is read from the storage 602, the process is restarted based on the information stored in the nonvolatile memory and the read information (step 909), and the process returns to step 905.

  When it is determined that not all the information of the process corresponding to the process ID 201 is stored in the nonvolatile memory, the power recovery processing function 111 reads all the information of the process corresponding to the process ID 201 from the storage 602 and reads The process is restarted based on the information (step 921), and the process returns to step 905.

  If it is determined in step 904 that the processor 104 is non-volatile, the power recovery processing function 111 refers to each data in the process management table 106 and determines whether or not processing has been completed for all entries ( Step 910). When the processor 104 is nonvolatile, the processor 104 can recover the stored information. Therefore, in the processing from step 910 onward, the necessary information from the storage 602 is newly obtained for the portion where the abnormality of the information stored in the memory has occurred. A reading process is executed.

  When it is determined that the processing has been completed for all entries, the power recovery processing function 111 proceeds to step 916.

  When it is determined that the processing has not been completed for all entries, the power recovery processing function 111 reads one entry from the process management table 106, and the process information corresponding to the process ID 201 of the entry is all non-volatile. It is determined whether it is stored in the memory (step 911).

  When it is determined that all the process information corresponding to the process ID 201 is stored in the nonvolatile memory, the power recovery processing function 111 performs the process corresponding to the process ID 201 based on the information stored in the nonvolatile memory. Is resumed (step 912), and the process returns to step 910.

  When it is determined that the process information corresponding to the process ID 201 is stored in a memory other than the nonvolatile memory, the power recovery processing function 111 stores only information on the update unit of the data area 220 of the process corresponding to the process ID 201 in the memory. (Step 913).

  When it is determined that the information of only the update part of the data area 220 of the process corresponding to the process ID 201 is stored in the memory, the power recovery processing function 111 stores the code part of the process corresponding to the process ID 201 and the constant 221. Based on the information read from 602 and stored in the memory and the read information, the suspended process is resumed (step 914), and the process returns to step 910.

  When it is determined that information other than the update part of the data area 220 of the process corresponding to the process ID 201 is stored in the memory, all information of the process corresponding to the process ID 201 is read from the storage 602, and the read information And restart the process (step 915) and return to step 910.

  When it is determined in step 902 that the confirmed activation identification flag 112 is not “1”, the power recovery processing function 111 initializes the system (step 919) and sets “1” in the activation identification flag (step 919). 920), the process proceeds to step 916.

  The power recovery processing function 111 checks the status of all device drivers (step 916), and determines whether the interruption processing can be resumed (step 917). Steps 916 and 917 are the same processing as steps 406 and 407.

  When it is determined that the interruption process cannot be resumed, the power recovery processing function 111 transmits an abnormal termination notification to the calling process (step 918) and ends the process.

  When it is determined that the interruption process can be resumed, the power recovery processing function 111 ends the process.

  FIG. 10A, FIG. 10B, and FIG. 10C are flowcharts for explaining a process and a page replacement process in the configuration of an embedded device having a plurality of memories in the embodiment of the present invention.

  The timing at which the process is executed may be when a TLB miss occurs or when the process is switched from the UI process to the background process. In the following description, a process that triggers processing is referred to as “process A”.

  The OS 107 determines whether or not the system is in an idle state (step 1001).

  When it is determined that the system is in an idle state, the OS 107 acquires a page list from the logical-physical conversion table 105, and arranges the acquired page list entries in descending order of memory performance to which the acquired page is allocated. In addition, the entries in the page list stored in the memory are rearranged in the order of decreasing overall priority 813 of the pages stored in each memory (step 1002). Note that the performance of the memory is determined with reference to the memory type definition table 217 based on the memory ID 808.

  The OS 107 determines whether or not processing has been completed for all entries in the acquired page list (step 1003).

  When it is determined that the processing has been completed for all entries in the acquired page list, the OS 107 ends the processing.

  If it is determined that the processing has not been completed for all entries in the acquired page list, the OS 107 reads the entries rearranged in step 1002 in order from the top, and combines the read page and other pages. The priority levels 813 are compared, and it is determined whether a page with a low overall priority level 813 is stored in the high performance memory and a page with a high overall priority level 813 is stored in the low performance memory (step 1004).

  If it is determined that a page with a low overall priority 813 is stored in the high performance memory and a page with a high overall priority 813 is not stored in the low performance memory, the OS 107 returns to step 1003.

  If it is determined that a page with a low overall priority 813 is stored in the high performance memory and a page with a high overall priority 813 is stored in the low performance memory, the OS 107 determines that the page with the low overall priority 813 and the overall priority are stored. The same value is set in the replacement flag 810 of the large page having the degree 813 (step 1005), and the process returns to step 1003. When there are a plurality of page pairs, a method may be considered in which the value of the replacement flag 810 is set to a value obtained by adding 1 each time the page pair increases. However, any value may be used as long as the page to be replaced can be identified.

  When it is determined in step 1001 that the system is not in the idle state, the OS 107 determines whether or not a TLB miss has occurred in access to the process A (step 1006).

  When it is determined that a TLB miss has occurred in the access to the process A, the OS 107 acquires information regarding the page to be accessed by the process A from the logical-physical conversion table 105, and stores the acquired information in the TLB 714. (Step 1007).

  The OS 107 acquires a page having a general priority 813 lower than the general priority 813 of the process A from the logical physical conversion table 105 as a replacement target page list (step 1008).

  The OS 107 determines whether or not a replacement target page exists (step 1009).

  When it is determined that there is a replacement target page, the OS 107 rearranges the acquired replacement target page list entries in descending order of the performance of the memory to which the acquired replacement target page is allocated, and further stores each page in each memory. The entries of the acquired replacement target page list are rearranged in the order of the total priority 813 of the stored pages (step 1010).

  The OS 107 searches for free areas in the memory in descending order of performance (step 1011).

  The OS 107 determines whether a free area exists as a result of the search in step 1011 (step 1012).

  If it is determined that there is no free area, the OS 107 saves the top page of the rearranged result to the storage 602, secures a free area (step 1014), and proceeds to step 1015.

  If it is determined that there is a free area, or if a free area is secured in step 1014, the OS 107 stores the page to be accessed by process A in the free area (step 1015), and ends the process.

  If it is determined in step 1009 that there is no replacement target page, the OS 107 acquires a page with the overall priority 813 that is the next higher than the overall priority 813 of the process A from the logical-physical conversion table 105 (step 1016).

  The OS 107 saves the acquired page in the storage 602 and secures a free area (step 1017).

  The OS 107 stores the page to be accessed by the process A in the reserved free space (step 1018).

  If it is determined in step 1006 that a TLB miss has not occurred in access to the process A, the OS 107 determines whether or not the UI process is switched to the background process (step 1019).

  If it is determined that switching from the UI process to the background process is not performed, the OS 107 ends the process.

  When it is determined that the switching is from the UI process to the background process, the OS 107 refers to each replacement flag 810 of the logical-physical conversion table 105, and replacement processing is executed for all pages for which the replacement flag 810 is set. It is determined whether or not (step 1020).

  When it is determined that the replacement process has been executed for all pages for which the replacement flag 810 is set, the OS 107 ends the process.

  If it is determined that the replacement process has not been executed for all the pages for which the replacement flag 810 is set, the OS 107 executes the replacement process for the page for which the replacement flag 810 is set (1021), and returns to Step 1020. .

  Note that when the processor 104 operates in multitasking and the load of processing to be executed in parallel increases, the OS 107 interrupts the processing of step 1020 and step 1021.

  Conventionally, since page replacement is performed even during a user operation, the moving image display such as moving an icon may freeze during the user operation. In the present invention, when switching from the UI process to the background process by the above process, the page replacement process is executed. Therefore, the nonvolatile memory is frequently and frequently updated at a timing that does not affect the user operation. The data to be processed can be arranged sequentially with priority. Therefore, since the amount of important data existing in the volatile area can be reduced, it is possible to reduce the data save processing time when the system is paused.

It is a block diagram explaining the structure of the embedded device of embodiment of this invention. It is a figure which shows an example of the basic data which the process management table | surface in embodiment of this invention contains. It is a figure which shows an example of the process type definition table | surface in embodiment of this invention. It is a figure which shows an example of the extension data which the process management table | surface in embodiment of this invention contains. It is a figure which shows an example of the storage location management data which the process management table | surface in embodiment of this invention contains. It is a figure which shows an example of the memory type definition table | surface in embodiment of this invention. It is a flowchart explaining the setting process of the starting identification flag in embodiment of this invention. It is a flowchart explaining the flow until OS starts in the embodiment of this invention until it starts a process. It is a flowchart explaining the update process of the usage frequency in embodiment of this invention. It is a block diagram explaining an example of a structure of the embedded apparatus of embodiment of this invention. It is a block diagram explaining an example of a structure of the embedded apparatus of embodiment of this invention. It is a figure which shows an example of the basic data which the logical physical conversion table in embodiment of this invention contains. It is a figure which shows an example of the extension data which the logical physical conversion table in embodiment of this invention contains. It is a flowchart explaining the flow of the system starting of this invention, and the restart of a process. It is a flowchart explaining the flow of the system starting of this invention, and the restart of a process. It is a flowchart explaining the flow of the system starting of this invention, and the restart of a process. In the embodiment of the present invention, it is a flowchart for explaining a process in the configuration of an embedded device having a plurality of memories, and a page replacement process. In the embodiment of the present invention, it is a flowchart for explaining a process in the configuration of an embedded device having a plurality of memories, and a page replacement process. In the embodiment of the present invention, it is a flowchart for explaining a process in the configuration of an embedded device having a plurality of memories, and a page replacement process.

Explanation of symbols

101 Non-volatile memory 102 Peripheral circuit 103 OS management information 104 Processor 105 Logical physical conversion table 106 Process management table 107 OS
108 Basic application group 109 Anti-save data 110 File system / database management 111 Power recovery processing function 112 Start identification flag 113 Main storage area 114 Storage area 115 Process 116 Instantaneous interruption determination register B
117 Remaining write check counter 118 Power supply circuit 119 ROM area 120 Power interruption detection destination designation data 121 Instantaneous interruption determination register A
122 Instantaneous interruption judgment register C
123 Data recording unit 124 Normal end register 125 Various files 126 Device driver 601 Non-volatile memory A
602 Storage 607 Memory management unit 614 TLB
616 Nonvolatile memory C
621 Physical page 623 Logical page 624 Range 626 Range 627 Physical address space 628 Logical address space 630 Non-volatile memory B
701 Volatile memory 714 TLB

Claims (13)

A device using a nonvolatile memory including a processor, one or more nonvolatile memories, and a peripheral circuit as a main memory,
The apparatus includes a power supply abnormality interruption determination unit that detects whether or not the power supply of the apparatus is abnormally interrupted, and a power supply abnormality end notification register that stores information indicating that the power supply of the apparatus is abnormally interrupted. ,
The peripheral circuit includes a power supply circuit,
The non-volatile memory stores an operating system, software, and device drivers;
The operating system includes the power supply abnormality interruption determination unit,
The power supply abnormality interruption determination unit
When powering on the device, refer to the power supply abnormal end notification register,
The power supply abnormal end notification register stores information indicating that the power supply of the apparatus is abnormally cut off. If the processor is not a non-volatile processor, it is executed before the power supply of the apparatus is cut off. Restart the process, check the device driver,
If the power supply abnormal end notification register stores information indicating that the power supply of the apparatus is abnormally shut down, and the processor is a non-volatile processor, it is executed before the power supply of the apparatus is shut down. An apparatus using a non-volatile memory as a main memory, wherein a process that has been interrupted is resumed from a process in which the process is interrupted, and the device driver is confirmed.   The data received by the device is written into the non-volatile memory every predetermined unit,
  The device is
  Write the received data to the non-volatile memory for each predetermined unit,
  It comprises write remaining information indicating the presence or absence of a unit of data that has not been written to the nonvolatile memory among the data received by the device,
  The power supply abnormality interruption determination unit
  Refer to the remaining write information when the device is turned on,
  When the remaining write information indicates that there is a unit of unwritten data, it is determined that the power supply of the device is abnormally cut off, and information indicating that the power supply of the device is abnormally cut off, The device using the nonvolatile memory according to claim 1, wherein the device is stored in the power supply abnormal end notification register.   Each of the processor, the nonvolatile memory, and the peripheral circuit includes the power supply abnormal end notification register,
  The power supply abnormality interruption determination unit sequentially refers to each of the power supply abnormality end notification registers included in the processor, the nonvolatile memory, and the peripheral circuit when the apparatus is turned on. A device using the nonvolatile memory described in 2 as main memory.   The apparatus retains power-off detection destination designation information for designating a reading destination of a power supply abnormal end notification register included in the processor, nonvolatile memory, and peripheral circuit,
  The said power supply abnormality interruption | blocking determination part refers to the said power supply abnormality completion notification register of the designated reading destination based on the said power supply detection destination information at the time of power activation of the said apparatus. A device that uses a non-volatile memory as its main memory.   The device is
  Furthermore, it comprises one or more volatile memories and a non-volatile storage medium,
  Information for managing the operating system and a main storage unit for managing information related to the process are composed of the nonvolatile memory and the volatile memory,
  Of the information related to the process, information with high update frequency is stored in the nonvolatile memory, information with low update frequency is stored in the volatile memory,
  The nonvolatile storage medium stores information regarding the process,
  The power supply abnormality interruption determination unit
  When the device is turned on, information related to the process stored in the volatile memory is read from the nonvolatile storage medium,
  Based on the information on the read process and the information stored in the nonvolatile memory, the process executed before the power of the device is shut down is restarted from the process at which the process was interrupted. An apparatus using the nonvolatile memory according to at least one of claims 1 to 4 as a main memory.   The device is
  Furthermore, it comprises one or more volatile memories and a non-volatile storage medium,
  Information for managing the operating system and a main storage unit for managing information related to the process are composed of the nonvolatile memory and the volatile memory,
  A logical storage area is created in a physical storage area of the nonvolatile memory or the volatile memory,
  The physical storage area is divided into a plurality of physical unit storage areas,
  The logical storage area is divided into a plurality of logical unit storage areas,
  Of the information related to the process, information with high update frequency is stored in the nonvolatile memory, information with low update frequency is stored in the volatile memory,
  The nonvolatile storage medium stores information regarding the process,
  The nonvolatile memory manages a process management table for managing the process and a priority of the process indicating the order of execution of the process, and a correspondence between the physical unit storage area and the logical unit storage area Logical to physical conversion table
  The logical-physical conversion table includes an address of the logical unit storage area and an address of the physical unit storage area in the nonvolatile memory or the volatile memory, a priority of the logical storage area, and the Including memory performance information indicating the performance of the non-volatile memory and the volatile memory,
  The operating system is
  When the process to be executed is switched, refer to the priority of the logical unit storage area and the memory performance information,
  A first process is stored in a first logical unit storage area having a high priority of the logical unit storage area of the nonvolatile memory or the volatile memory in which the memory performance information is low performance, When the second process is stored in a second logical unit storage area having a low priority of the logical unit storage area of the nonvolatile memory or the volatile memory having high memory performance information, 6. The nonvolatile memory according to claim 1, wherein the first logical unit storage area and the second logical unit storage area are interchanged. Equipment used for.   The priority of the logical unit storage area is:
  When the priority of the process is large, it is set large,
  The apparatus using the nonvolatile memory according to claim 6, wherein the non-volatile memory is set to be small when the priority of the process is low.   The process management table includes an attribute of the process indicating whether the process is related to a user operation or the process executed in the background, and a usage frequency indicating a frequency at which the process is executed at a specific timing.
  The apparatus using the nonvolatile memory according to claim 6 or 7, wherein the priority of the process is calculated based on an attribute of the process and the use frequency.   When the operating system is switched from the process related to the user operation to the process executed in the background, the first logical unit storage area in which the first process is stored, and the second 9. The apparatus using the nonvolatile memory as at least one of claims 6 to 8, wherein the second logical unit storage area in which the process is stored is replaced.   The processor caches information on the logical unit storage area in which the processes with high usage frequency are stored in the logical-physical conversion table,
  When the operating system accesses an area other than the logical unit storage area cached by the processor, the operating system includes the first logical unit storage area, the second logical unit storage area, 10. A device using the non-volatile memory according to claim 6 as main memory.   The apparatus using the nonvolatile memory according to claim 1 or 2, wherein the processor includes the power supply abnormal end notification register.   12. The apparatus using the nonvolatile memory according to claim 1, 2 or 11, wherein the nonvolatile memory includes the power supply abnormal end notification register.   The apparatus using the nonvolatile memory according to at least one of claims 1, 2, 11, and 12, wherein the power supply circuit includes the power supply abnormal end notification register. .

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