JP5163184B2 - Data scanning circuit, solid-state imaging device, and camera system - Google Patents

Description

  The present invention relates to a data scanning circuit, a solid-state imaging device represented by a CMOS image sensor, and a camera system.

In recent years, CMOS image sensors have attracted attention as solid-state imaging devices (image sensors) that replace CCDs.
This requires a dedicated process for manufacturing the CCD pixel, requires a plurality of power supply voltages for its operation, and further requires a combination of a plurality of peripheral ICs to operate, resulting in a very complicated system. This is because the CMOS image sensor overcomes various problems such as.

  The CMOS image sensor can be manufactured by using a manufacturing process similar to that of a general CMOS integrated circuit, can be driven by a single power source, and further, an analog circuit or a logic circuit using the CMOS process. Can be mixed in the same chip, so that it has a plurality of great merits such as reducing the number of peripheral ICs.

The output circuit of a CCD is mainly a 1-channel (ch) output using an FD amplifier having a floating diffusion layer (FD).
In contrast, a CMOS image sensor has an FD amplifier for each pixel, and its output is a column parallel output type in which one row in the pixel array is selected and read out in the column direction at the same time. Mainstream.
This is because it is difficult to obtain a sufficient driving capability with an FD amplifier arranged in a pixel, and therefore it is necessary to lower the data rate, and parallel processing is advantageous.

  Various signal output circuits of this column parallel output type CMOS image sensor have been proposed, and one of the most advanced forms is an analog-to-digital converter (hereinafter referred to as ADC (Analog digital converter)) for each column. And a pixel signal is extracted as a digital signal.

  A CMOS image sensor equipped with such a column parallel ADC is disclosed in Non-Patent Document 1 and Patent Document 1, for example.

  FIG. 1 is a block diagram illustrating a configuration example of a solid-state imaging device (CMOS image sensor) equipped with a column parallel ADC.

  The solid-state imaging device 1 includes a pixel array unit 2 as an imaging unit, an ADC group 3, a vertical (row) scanning circuit 4, a horizontal (column) scanning circuit 5, a timing control circuit 6, and a sense amplifier (S / A) group 7. And a data processing circuit 8.

  The pixel array unit 2 is configured by unit pixels 2-1 including photodiodes and in-pixel amplifiers arranged in a matrix (matrix).

The ADC group 3 includes ADC0 to ADCn (n = 15 in the example of FIG. 1) arranged corresponding to each column of the pixel matrix array.
Each ADC0 to ADC15 includes a ramp waveform RAMP in which a reference voltage generated by a digital-analog converter (DAC) (not shown) is changed stepwise, and a unit pixel 2 for each row line H0, H1,. -1 to the analog signal obtained through the column lines V0, V1,..., A counter for counting the comparison time, and a memory device for holding the count result of the counter.
Assuming that the data after AD conversion is n bits, ADC0 to ADC15 in each column each have an n-bit memory device.

  In the solid-state imaging device 1, as a control circuit for sequentially reading out signals from the pixel array unit 2, a timing control circuit 6 that generates an internal clock, a row scanning circuit 4 that controls a row address and vertical (row) scanning, A horizontal scanning circuit 5 for controlling column addresses and horizontal (column) scanning is arranged.

The H scanner 5A of the horizontal scanning circuit 5 has a plurality of data flip-flop circuits FF0, FF1, FF2,... FFx (x = 3 in the example of FIG. 1) that sequentially read out output signals in synchronization with the clock φCK from the timing control circuit 6. ).
Here, the output signals of the data flip-flop circuits FF0, FF1, FF2, and FF3 are denoted as HSEL10, HSEL11, HSEL12, and HSEL13.
As data reading circuits, data transfer lines 5-0, 5-1, 5-2, and 5-3 and sense amplifiers 7-0, 7-1, 7-2, and 7 corresponding to the output lines are provided. Switching transistors NT0 to NT15 comprising n-channel MOS transistors are arranged between the data transfer lines 5-0, 5-1, 5-2, and 5-3 and the data output portions of the ADC0 to ADC15. It is connected.

Specifically, switching transistors NT0, NT4, NT8, and NT12 are connected between the data transfer line 5-0 and the data output units of ADC0, ADC4, ADC8, and ADC12, respectively.
Switching transistors NT1, NT5, NT9, and NT13 are connected between the data transfer line 5-1 and the data output portions of the ADC1, ADC5, ADC9, and ADC13, respectively.
Switching transistors NT2, NT6, NT10, NT14 are connected between the data transfer line 5-2 and the data output portions of the ADC2, ADC6, ADC10, ADC14, respectively.
Switching transistors NT3, NT7, NT10, and NT15 are connected between the data transfer line 5-3 and the data output portions of the ADCs 3, ADC7, ADC11, and ADC15, respectively.

The output signal HSEL10 of the data flip-flop circuit FF0 is supplied to the gates of the switching transistors NT0 to NT3.
The output signal HSEL1 of the data flip-flop circuit FF1 is supplied to the gates of the switching transistors NT4 to NT7.
The output signal HSEL2 of the data flip-flop circuit FF2 is supplied to the gates of the switching transistors NT8 to NT11.
The output signal HSEL3 of the data flip-flop circuit FF3 is supplied to the gates of the switching transistors NT12 to NT15.

In the horizontal scan for data reading, since it is necessary to read all the data for one row within 1H (one horizontal scan period), a very high-speed operation is required.
In particular, CMOS image sensors have recently increased in pixel count and frame rate, and the output data rate has reached several hundred MHz. Therefore, a sense amplifier that reads data in the horizontal direction is particularly required to operate at high speed.
However, since the operation of the sense amplifier is difficult to drive at several hundred MHz, it is connected in parallel to guarantee the data rate.
In the example of FIG. 1, four sense amplifiers 7-0 to 7-3 connected in parallel are shown, and 4n sense amplifiers and data transfer lines are arranged.

With this configuration, 4n-bit data stored in the memory of the four columns is transferred through the 4n-bit data transfer line and input to the data processing circuit 8.
With this configuration, the data rate of the sense amplifier is 1/4 of the actual data rate.

  The details of the above-described operation for reading data in parallel in the horizontal direction will be described.

First, a read start pulse φST is issued from the timing control circuit 6. Then, in the H scanner 5A, the data flip-flop circuits FF0, FF1, FF2, and FF3 sequentially transfer the output signal pulses HSEL10, HSEL11, HSEL12, and HSEL13 in synchronization with the clock φCK.
When the output signal pulses HSEL10, HSEL11, HSEL12, and HSEL13 are active (high level in the example of FIG. 1), the data flip-flop circuits FF0, FF1, FF2, and FF3 sense the data of the column to which the output signal is connected. It is output via the amplifiers 7-0 to 7-3.

For example, when the signal pulse HSEL10 is active, the reading switching transistors NT0 to NT3 in the 0th to 3rd columns are turned on, and the digital data by the ADC0, ADC1, ADC2, ADC3 of the ADC group 3 is transferred to the data transfer line 5. It is output from the sense amplifiers 7-0 to 7-3 via -0 to 5-3.
Subsequently, HSEL1 becomes active at the next clock, and the data in the fourth, fifth, sixth and seventh columns are output from the sense amplifiers 7-0, 7-1, 7-2 and 7-3.
In this way, data reading is executed.
W. Yang et al. (W. Yang et. Al., “An Integrated 800x600 CMOS Image System,” ISSCC Digest of Technical Papers, pp. 304-305, Feb., 1999) JP 2005-323331 A Japanese Patent Laid-Open No. 5-167988 JP 2003-31935 A

  In the data reading described above, if the thinning-out reading is executed, the following problems occur.

For example, when 2/4 decimation is desired, the data in the column column to be read is data by ADC0, ADC1, ADC4, and ADC5.
That is, in this case, the data from ADC2, ADC3, ADC6, and ADC7 is to be skipped, but in the configuration of FIG. 1, the output signals HSEL10 to HSEL13 of the data flip-flop circuits FF0 to FF3 of the H scanner 5A are to be read out. Since it is connected to both the column to be skipped, redundant data is read out.
Since redundant data is read out in this way, it is necessary to sample only necessary data outside after reading out all the data once (see, for example, Patent Document 2).

When 2/4 decimation is performed, the required data is half that of normal times, so we want to double the frame rate. However, the current configuration reads redundant data, so the data bus is effective. It is not used and the frame rate cannot be increased.
As a method for realizing the thinning-out operation, a method for realizing a thinning-out circuit by skipping the data flip-flop circuit of the H scanner (for example, see Patent Document 3) is known.
However, in the case of parallel reading as in the configuration of FIG. 1, each data flip-flop circuit is connected to both the column to be read at the time of thinning and the column to be skipped. It is not possible to realize a thinning-out operation such as reading out only valid data by skipping the data.

  It is an object of the present invention to provide a data scanning circuit, a solid-state imaging device, and a camera system that can realize arbitrary thinning-out readout that reads out only valid data without reading out redundant data.

A data scanning circuit according to a first aspect of the present invention holds a plurality of transfer lines for transferring data and data corresponding to an input level, and transfers the data to the corresponding transfer line in response to a selection signal. A plurality of holding units arranged in parallel, and a scanning unit that generates the selection signal in synchronization with a clock and outputs the selection signal to the holding unit, and the transfer line is arranged in the parallel arrangement direction of the holding units The scanning unit is arranged corresponding to the parallel arrangement of the holding units, outputs the selection signal to the corresponding holding unit in synchronization with the supplied clock, and the output line of the selection signal is thinned out. A plurality of selection signal generators alternately and individually connected to an array holding unit to be read at the time of reading and an array holding unit to be skipped, and at the time of normal reading, the plurality of selection signal generation units are sequentially scanned. And select the above When the thinning-out reading is performed, the selection signal generation unit in which the selection signal supply line is connected to the holding unit of the array to be skipped at the time of the thinning-out reading is bypassed, and the array from which data is to be read out by the thinning-out reading is retained. A selector unit that sequentially scans the selection signal generation unit connected to the unit, and the plurality of selection signal generation units are connected to a holding unit of an array to be read out, which is a target to be read out during decimation readout A plurality of first selection signal generation units and a plurality of second selection signal generation units connected to the holding unit of the array to be skipped, and the selection signal on the previous stage side in synchronization with the clock signal The selector unit supplies the selection signal supplied by the generation unit to the selection signal generation unit on its own stage and outputs it to the selection signal generation unit on the rear stage side. In this case, the plurality of selection signal generation units of the first and second selection signal generation units are sequentially scanned to generate the selection signal. The selection signal of the selection signal generation unit is supplied to the first selection signal generation unit next to the bypassed second selection signal generation unit, and the first selection signal generation unit is connected to the first selection signal generation unit. The supply of the selection signal of one selection signal generation unit is stopped, the generation of the selection signal of the second selection signal generation unit is stopped, and the scanning unit is configured to select the plurality of selection signal generation units during normal reading. was output sequentially scanned to Kiten feed line on the corresponding data of the plurality of holding portions, when the thinning-out reading is to change the order of the scanning, the holding portion of the array from which data is to be read at a thinning read out of the valid data of only in Kiten transmission line on the corresponding To help.

A solid-state imaging device according to a second aspect of the present invention includes an imaging unit in which a plurality of pixels that perform photoelectric conversion are arranged in a matrix, a plurality of transfer lines that transfer data, and pixels in each column of the imaging unit. Holds data corresponding to the input level of the output data, and transfers the data to the corresponding transfer line in response to a selection signal. And a scanning unit that generates the selection signal in synchronization with the clock and outputs the selection signal to the holding unit, and the transfer line is wired in the parallel arrangement direction of the holding unit, A holding unit of an arrangement that is arranged corresponding to the parallel arrangement of the holding units, outputs the selection signal to the corresponding holding unit in synchronization with a supplied clock, and an output line of the selection signal is to be read at the time of thinning-out reading Alternately in the holding part of the array to be skipped A plurality of selection signal generating unit that is connected separately, when the normal read, by sequentially scanning the plurality of selection signal generating unit to generate the selection signal, when the thinning-out reading, when the thinning readout The selection signal generator connected to the selection signal supply line to the holding unit of the array to be skipped is bypassed, and the selection signal generator connected to the holding unit of the array from which data is to be read out by decimation readout is sequentially A plurality of selection signal generation units that skip scanning with a plurality of first selection signal generation units connected to a holding unit of an array to be read out that is a target for thinning out reading And a plurality of second selection signal generation units connected to the array holding unit, and provided by the selection signal generation unit on the preceding stage in synchronization with the clock signal. The selection signal includes a function to output the selection signal to the selection signal generation unit on the rear stage side, and the selector unit is configured to output the first and second selection signal generation units during normal reading. The plurality of selection signal generation units are sequentially scanned to generate the selection signal, and at the time of thinning-out reading, the selection signal of the first selection signal generation unit on the previous stage is bypassed to the second selection Supply to the first selection signal generation unit at the next stage of the signal generation unit, stop supplying the selection signal of the first selection signal generation unit on the previous stage side to the second selection signal generation unit, The generation of the selection signal of the second selection signal generation unit is stopped, and the scanning unit sequentially scans the plurality of selection signal generation units during normal reading, and corresponds to the data of the plurality of holding units. Kiten is output to the transmission line, when the thinning-out reading Changes the order of the scanning, at a thinning readout is output to Kiten feed line on which corresponding only valid data holding portion of the array from which data is to be read.

A camera system according to a third aspect of the present invention includes a solid-state imaging device and an optical system that forms a subject image on the imaging device, and the solid-state imaging device includes a plurality of pixels that perform photoelectric conversion in a matrix. The image pickup unit arranged in a line, a plurality of transfer lines for transferring data, and data corresponding to the input level of the output data of the pixels of each column of the image pickup unit are held, and the data is received in response to a selection signal. A plurality of holding units arranged in parallel corresponding to each column of the plurality of pixels to be transferred to the corresponding transfer line, and a scan that generates the selection signal in synchronization with a clock and outputs the selection signal to the holding unit The transfer line is wired in the parallel arrangement direction of the holding units, and the scanning unit is arranged corresponding to the parallel arrangement of the holding units, and is synchronized with a supplied clock. The selection signal is output to the corresponding holding unit, and the selection signal A plurality of selection signal generating unit force lines are alternately and individually connected to the holding portion of the holding portion and the reading skips sequence of SEQ be read out during thinning readout, when the normal read, the plurality of selection signal generator Are sequentially scanned to generate the selection signal, and in the case of decimation readout, the selection signal generation unit in which the selection signal supply line is connected to the holding unit of the array to be skipped during the decimation readout is bypassed, and decimation is performed. A selector unit that sequentially scans the selection signal generation unit connected to a holding unit of an array from which data is to be read out, and the plurality of selection signal generation units are targets for decimation readout at the time of decimation readout A plurality of first selection signal generators connected to the holding unit of the array to be read and a plurality of second selection signals connected to the holding unit of the array to be skipped. The selection signal supplied from the selection signal generation unit on the preceding stage in synchronization with the clock signal is used as the selection signal for the own stage and is output to the selection signal generation unit on the subsequent stage. The selector unit includes a function, and at the time of normal reading, the plurality of selection signal generation units of the first and second selection signal generation units are sequentially scanned to generate the selection signal, and the thinning readout is performed. The first selection signal generation unit on the preceding stage side is supplied to the first selection signal generation unit on the next stage of the bypassed second selection signal generation unit, and the second selection signal is supplied. The supply of the selection signal of the first selection signal generation unit on the upstream side to the signal generation unit is stopped, the generation of the selection signal of the second selection signal generation unit is stopped, and the scanning unit When the plurality of selection signal generators Is output sequentially scanned in Kiten feed line on the corresponding data of the plurality of holding portions, when the thinning-out reading is to change the order of the scanning, the holder of the array from which data is to be read at a thinning read is output to Kiten feed line on the corresponding valid data only.

  Preferably, a data sort circuit is provided that rearranges the read data in a special order corresponding to the connection of the output of the selection signal generation unit during normal reading.

According to the present invention, at the time of normal reading, the scanning unit sequentially scans the plurality of selection signal generation units. Thereby, the data of the plurality of holding units are output to the corresponding data transfer lines.
At the time of thinning-out reading, the scanning order is changed, and only valid data in the holding unit of the array from which data is to be read out by thinning-out reading is output to the corresponding data transfer line.

  According to the present invention, it is possible to realize arbitrary thinning-out reading that reads only valid data without reading redundant data.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
FIG. 2 is a block diagram showing a configuration example of a solid-state image pickup device (CMOS image sensor) equipped with a column parallel ADC including the data transfer circuit according to the first embodiment of the present invention.

As shown in FIG. 2, the solid-state imaging device 10 includes a pixel array unit 11 as an imaging unit, an ADC group 12, a vertical (row) scanning circuit 13, a horizontal (column) scanning circuit 14, a timing control circuit 15, and a sense amplifier. (S / A) group 16, data processing circuit 17, and data sort circuit 18.
The solid-state imaging device 10 is configured to be capable of 2/4 decimation readout.

  The pixel array unit 11 includes unit pixels 111 including photodiodes and in-pixel amplifiers arranged in a matrix (matrix).

The ADC group 12 is configured by ADC10 to ADC1n (n = 15 in the example of FIG. 1) arranged corresponding to each column of the pixel matrix arrangement.
Each of the ADCs 10 to 115 can be obtained from a ramp waveform RAMP in which a reference voltage generated by a DAC (not shown) is changed stepwise, and from the unit pixel 111 to the column lines V10, V11... For each row line H10, H11. The comparator includes a comparator that compares the analog signal, a counter that counts the comparison time, and a memory device that holds a count result of the counter.
Assuming that the data after AD conversion is n bits, ADC10 to ADC115 in each column have an n-bit memory device.

  In the solid-state imaging device 10, as a control circuit for sequentially reading out signals from the pixel array unit 11, a timing control circuit 15 that generates an internal clock, a vertical scanning circuit 13 that controls a row address and vertical (row) scanning, A horizontal scanning circuit 14 for controlling column addresses and horizontal (column) scanning is disposed.

The H scanner 140 of the horizontal scanning circuit 14 basically shifts the start pulse φST from the timing control circuit 15 sequentially or one by one in synchronism with the clock φCK from the timing control circuit 15 and outputs an output signal. FF1x (x = 3 in the example of FIG. 1) as a plurality of selection signal generation units that sequentially read out and selectors SL10, SL11, SL12,. In the example of FIG. 1, x = 3).
Here, output signals of the data flip-flop circuits FF10, FF11, FF12, and FF13 are referred to as selection signals HSEL10, HSEL11, HSEL12, and HSEL13.

The selector SL10 has two inputs I0 and I1, and these two inputs I0 and I1 are connected in common to the supply line of the start pulse φST, and the output is connected to the data input of the data flip-flop circuit FF10. Yes.
The selector SL10 selects and outputs the input I0 when the switching signal SW10 is at the low level “0”, and selects the input I1 when the switching signal SW10 is at the high level “1”. Output.
That is, the selector SL10 selects the start pulse φST and outputs data regardless of whether the switching signal SW10 is “0” or “1” because the input portions I0 and I1 are commonly connected to the supply line of the start pulse φST. This is supplied to the flip-flop circuit FF10.

The selector SL11 has two inputs I0 and I1, the input unit I0 is connected to the output line of the selection signal HSEL10 of the data flip-flop circuit FF10, and the input unit I1 is connected to a fixed potential.
The selector SL11 selects and outputs the input I0 when the switching signal SW11 is at the low level “0”, and selects the input I1 when the switching signal SW11 is at the high level “1”. Output.
That is, when the switching signal SW11 is “0”, the selector SL11 supplies the selection signal HSEL10, which is the output of the previous data flip-flop circuit FF10, to the data input section of the next data flip-flop circuit FF11.
On the other hand, when the switching signal SW11 is “1”, the selector SL11 does not supply any signal to the next data flip-flop circuit FF11. Thereby, the data flip-flop circuit FF11 is bypassed in the shift operation of the start pulse φST.

The selector SL12 has two inputs I0 and I1, the input unit I0 is connected to the output line of the selection signal HSEL11 of the preceding data flip-flop circuit FF11, and the input unit I1 is connected to the two-stage previous data flip-flop circuit FF10. It is connected to the output line of the selection signal HSEL10.
The selector SL12 selects and outputs the input I0 when the switching signal SW12 is at the low level “0”, and selects the input I1 when the switching signal SW12 is at the high level “1”. Output.
That is, when the switching signal SW11 is “0”, the selector SL12 supplies the selection signal HSEL11, which is the output of the preceding data flip-flop circuit FF11, to the data input section of the data flip-flop circuit FF12.
On the other hand, when the switching signal SW11 is “1”, the selector SL12 supplies the selection signal HSEL10, which is the output of the data flip-flop circuit FF10 two stages before, to the data input section of the data flip-flop circuit FF12.

The selector SL13 has two inputs I0 and I1, the input unit I0 is connected to the output line of the selection signal HSEL12 of the data flip-flop circuit FF12, and the input unit I1 is connected to a fixed potential.
The selector SL13 selects and outputs the input I0 when the switching signal SW13 is at the low level “0”, and selects the input I1 when the switching signal SW13 is at the high level “1”. Output.
That is, when the switching signal SW13 is “0”, the selector SL13 supplies the selection signal HSEL12, which is the output of the previous data flip-flop circuit FF12, to the data input section of the next data flip-flop circuit FF13.
On the other hand, when the switching signal SW13 is “1”, the selector SL13 does not supply any signal to the next data flip-flop circuit FF13. Thereby, the data flip-flop circuit FF13 is bypassed in the shift operation of the start pulse φST.

Then, the circuit 141 Shi read out actual data, the sense amplifier and the data transfer line 14-0,14-1,14-2,14-3, corresponding to the output line 16-0,16-1,16- 2 and 16-3, and a switching transistor NT10 composed of an n-channel MOS transistor between each data transfer line 14-0, 14-1, 14-2, 14-3 and the data output section of each ADC10 to ADC115. -NT115 is connected.

Specifically, switching transistors NT10, NT12, NT18, and NT110 are connected between the data transfer line 14-0 and the data output units of the ADC10, ADC12, ADC18, and ADC110, respectively.
Switching transistors NT11, NT13, NT19, NT111 are connected between the data transfer line 14-1 and the data output sections of the ADC11, ADC13, ADC19, ADC111, respectively.
Switching transistors NT14, NT16, NT112, and NT114 are connected between the data transfer line 14-2 and the data output portions of the ADC 14, ADC16, ADC112, and ADC114, respectively.
Switching transistors NT15, NT17, NT113, and NT115 are connected between the data transfer line 14-3 and the data output sections of the ADC15, ADC17, ADC113, and ADC115, respectively.

The selection signal HSEL10 output from the data flip-flop circuit FF10 is supplied to the gates of the switching transistors NT10, NT11, NT14, and NT15 connected to the outputs of the ADC10, ADC11, ADC14, and ADC15.
The selection signal HSEL11 output from the data flip-flop circuit FF11 is supplied to the gates of the switching transistors NT12, NT13, NT16, NT17 connected to the outputs of the ADC12, ADC13, ADC16, ADC17.
ADC18, ADC19, ADC112, ADC1 1 3 switching transistor connected to the output of the NT18, NT19, NT112, selection signal HSEL12 to the gate of the NT113 is output from the data flip-flop circuit FF12 is supplied.
The selection signal HSEL13 output from the data flip-flop circuit FF13 is supplied to the gates of the switching transistors NT110, NT111, NT114, NT115 connected to the outputs of the ADC 110, ADC 111, ADC 114, ADC 15.

In the horizontal scan for data reading, since it is necessary to read all the data for one row within 1H (one horizontal scan period), a very high-speed operation is required.
In particular, CMOS image sensors have recently increased in pixel count and frame rate, and the output data rate has reached several hundred MHz. Therefore, a sense amplifier that reads data in the horizontal direction is particularly required to operate at high speed.
However, since the operation of the sense amplifier is difficult to drive at several hundred MHz, it is connected in parallel to guarantee the data rate.
In the example of FIG. 2, four sense amplifiers 16-0 to 16-3 connected in parallel are shown, and 4n sense amplifiers and data transfer lines are arranged.

With this configuration, 4n-bit data stored in the memory of the four columns is transferred through the 4n-bit data transfer line and input to the data sort circuit 18.
With this configuration, the data rate of the sense amplifier is 1/4 of the actual data rate.

In the present embodiment, instead of sequentially selecting the column selection order indicated by each data flip-flop circuit of the H scanner 140, a configuration in which columns that are read out when performing thinning processing and columns that are not read out are collected separately By changing the selection order and reading out, it is possible to realize horizontal 2/4 thinning-out reading that doubles the frame rate.
In this embodiment, random access is performed during normal reading. However, by installing a data storage memory in the output data processing circuit 17 and a data sorting circuit 18 having a rearranging function, random access is performed. It is possible to sort the data output in step S3, and as a result, sequentially process the data.
The data sort circuit 18 will be described in detail later.

As described above, in this embodiment, the selection signal HSEL10 that is the output of the first stage data flip-flop circuit FF10 of the H scanner 140 is the switching transistors NT10, NT11, It is supplied to the gates of NT14 and NT15.
HSEL11 which is the output of the second-stage data flip-flop circuit FF11 is supplied to the gates of the switching transistors NT12, NT13, NT16 and NT17 in the second and third columns and the sixth and seventh columns.
That is, the selection signal HSEL10 that is the output of the first-stage data flip-flop circuit FF10 is supplied to the column column that is read out during 2/4 decimation, and the selection signal HSEL11 that is the output of the second-stage data flip-flop circuit FF11 is It is supplied to a column row that is skipped during 2/4 thinning.

As described above, in this embodiment, a configuration is employed in which the columns for reading out the outputs of the data flip-flop circuits FF10 to FF1x of the H scanner 140 are alternately connected to the columns to be skipped.
In addition, two-input selectors SL10 to SL1x are arranged for input signals of the data flip-flop circuits FF10 to FF1x.

  In this embodiment, one of the input signals of the selectors SL11 to SL1x arranged at the inputs of the data flip-flop circuits FF11 to FF1x is the selection signal HSEL1 (x−1) of the previous stage, but another input signal. Is the output signal HSEL1 (x-2) of the preceding stage for the data flip-flop circuits FF10, FF12,. It is said.

In the above configuration, when normal reading is executed, the selector switching signals SW10 to SW1x are set to “0”. By setting in this way, the inputs of all the data flip-flop circuits FF11 to FF1x become the previous stage output, and all the data flip-flop circuits FF10 to FF1x are scanned.
In this state, when the start pulse φST is input to the H scanner 140, the 0th column, the 1st column, the 4th column, the 5th column, and the 5th column are synchronized with the selection signal HSEL10 output from the first-stage data flip-flop circuit FF10 in synchronization with the clock φCK. The column is selected, and data AD0, AD1, AD4, and AD5 are read out.
At the next clock, the data AD2, AD3, AD6, AD7 of the second, third, sixth and seventh columns selected by the selection signal HSEL11 are read.

When performing the thinning operation, the switching signals SW10 to SW1x are set to “1”, and the inputs of the selectors SL10 to SL1x are set to I1.
With this setting, every other data flip-flop circuit scans in the H scanner 140.
In this state, when the start pulse φST is input to the H scanner 140, the 0th column, the 1st column, the 4th column, the 5th column, and the 5th column are synchronized with the selection signal HSEL10 output from the first-stage data flip-flop circuit FF10 in synchronization with the clock φCK. The column is selected and the data AD0, AD1, AD4, AD5 are read out.
At the next clock, the selection signal HSEL11 by the second-stage data flip-flop circuit FF11 is skipped, the selection signal HSEL12 that is the output of the third-stage data flip-flop circuit FF12 becomes active, and is selected by the selection signal HSEL12. , 9, 12, and 13th column data AD8, AD9, AD12, and AD13 are read out, and 2/4 decimation readout is realized while skipping unnecessary data.

As described above, the H scanner 140 does not sequentially select the column selection order indicated by each data flip-flop circuit, but separately collects columns that are read out when performing thinning processing and columns that are not read out. By changing the selection order and reading, it is possible to realize horizontal 2/4 decimation readout that doubles the frame rate.
Normally, random access is performed at the time of reading, but in this embodiment, as described above, a data storage memory is mounted in the output data processing circuit 17 and a data sorting circuit 18 having a rearranging function is mounted. Thus, it is possible to sort the data output by random access and, as a result, sequentially process it as data.

  FIG. 3 is a diagram showing a configuration example of a data sort circuit corresponding to 2/4 decimation according to the present embodiment.

4 channels of n-bit (nbit) data output from the sense amplifiers 16-0 to 16-3 in FIG. 2 are sequentially input to the data sort circuit 18 in synchronization with the clock clkt.
The data sort circuit 18 in FIG. 3 has two stages of flip-flop circuits for the 0 channel and the 1 channel.
In FIG. 3, the first-stage flip-flop circuit of channel 0 is indicated by sort_indat0, and the second-stage flip-flop circuit is indicated by indat0_dly1.
Similarly, two-stage flip-flop circuits of one channel are indicated by sort_indat1 and indat1_dly1 in order from the first stage.
The 2 and 3 channels have a 3-stage flip-flop circuit, and the 2-channel 3-stage flip-flop circuit is indicated by sort_indat2, indat2_dly1, and indat2_dly2 in order from the first stage. Similarly, the three-channel three-stage flip-flop circuits are indicated by sort_indat3, indat3_dly1, and indat3_dly2 in order from the first stage.

  Further, the data sort circuit 18 has multiplexers 180 to 184.

The multiplexer 180 selects and outputs either the output of the 0-channel second-stage flip-flop circuit indat0_dly1 or the output of the 2-channel third-stage flip-flop circuit indat2_dly2.
The multiplexer 180 selects the output of the second-stage flip-flop circuit indat1_dly1 of 1 channel when the 1-bit signal sort_cnt is “0”, and the output of the third-stage flip-flop circuit indat3_dly2 of 3 channels when “1”. Select.

The multiplexer 181 selects and outputs either the output of the 1-channel second-stage flip-flop circuit indat1_dly1 or the 3-channel third-stage flip-flop circuit indat3_dly2.
The multiplexer 181 selects the output of the second-stage flip-flop circuit indat1_dly1 of 1 channel when the 1-bit signal sort_cnt is “0”, and the output of the third-stage flip-flop circuit indat3_dly2 of 3 channels when “1”. Select.

The multiplexer 182 selects and outputs either the output of the 2-channel second stage flip-flop circuit indat2_dly1 or the output of the 0-channel first stage flip-flop circuit sort_indat0.
The multiplexer 182 selects the output of the 2-channel second stage flip-flop circuit indat2_dly1 when the 1-bit signal sort_cnt is “0”, and the output of the first-stage flip-flop circuit sort_indat0 of 0 channel when the signal is “1”. Select.

The multiplexer 183 selects and outputs either the output of the first-stage flip-flop circuit sort_indat1 of one channel or the output of the second-stage flip-flop circuit indat3_dly1 of three channels.
The multiplexer 183 selects the output of the first-stage flip-flop circuit sort_indat1 of 1 channel when the 1-bit signal sort_cnt is “0”, and the output of the second-stage flip-flop circuit indat3_dly1 of 3 channels when “1”. Select.

The multiplexer 184 is a 4-channel data (4ch × nbit) output from the 0 to 3 channel second stage flip-flop circuits indat0_dly1, indat1_dly1, indat2_dly1, indat3_dly1, and 4 channels selected and output by the multiplexers 180 to 183. Either data (4ch × nbit) is selected and output.
The multiplexer 184 selects the 4-channel data (4ch × nbit) selected and output by the multiplexers 180 to 183 as the normal reading mode when the mode switching signal hsdcmt for separating the normal reading and the 2/4 decimation reading is “0”. To do.
When the mode switching signal hsdcmt is “1”, the multiplexer 184 operates as the 2/4 thinning-out read mode, and outputs 4-channel data (4 ch × 4) of the output of the second to third flip-flop circuits indat0_dly1, indat1_dly1, indat2_dly1, indat3_dly1. nbit).

  That is, in the present embodiment, the normal read mode is set when the mode switching signal hsdcmt is “0”, and the 2/4 thinning mode is set when it is “1”.

  FIG. 4 is a diagram for explaining a normal read operation and a 2/4 thinning operation of the data sort circuit of FIG.

  Here, the operation of the data sort circuit 18 in the normal reading will be described.

The data AD0, AD1, AD4, and AD5 are stored in the first stage flip-flop circuits sort_indat0 to sort_indat3 of each channel ch0 to ch3 in synchronization with the clock clkgt, and the second stage flip-flop in the second clock. Stored in the in-circuits indat0_dly1-indat3_dly1.
Here, the data AD0 from the second flip-flop circuit indat0_dly1 of the channel CH0, the data AD1 from the second flip-flop circuit indat1_dly1 of the channel ch1, the data AD2 from the first flip-flop circuit sort_indat0 of the channel ch0, the channel ch1 The data AD3 is output from the first-stage flip-flop circuit sort_indat1.
When these are connected to the output, the sorted data is output as a result, such as AD0 to AD3.

At the third clock, data AD4 from the third stage flip-flop circuit indat2_dly2 of channel ch2, data AD5 from the third stage flip-flop circuit indat3_dly2 of channel ch3, and data from the second stage flip-flop circuit indat2_dly1 of channel ch2 Data AD7 is output from the flip-flop circuit indat3_dly1 at the second stage of AD6 and channel ch3.
When these are connected to the output, the sorted data is output as AD4 to AD7 as a result.
In the fourth clock, data AD8 to AD11 are output by the same output connection as in the second clock, and in the fifth clock, data AD12 to AD15 are output from the same output connection as in the third clock.

  From the above, by switching the output of each flip-flop circuit to the above two connections in synchronization with the clock, the sorted data can be output as a result. Here, a 1-bit signal sort_cnt is prepared as a pulse indicating output switching.

In the case of the thinning-out operation, the outputs of the second-stage flip-flop circuits indat0_dly1 to indat3_dly1 after the second clock are output as they are in synchronization with the clock clkrt.
With the circuit configuration described above, it becomes possible to read out only valid data during the 2/4 decimation operation, and as a result, it is possible to operate at a frame rate twice that of normal reading.

  In addition, until now, 2/4 decimation can be realized by skipping one data flip-flop circuit of the H scanner, but if it is configured to skip every third, 2/8 decimation is possible. It is possible to operate at a frame rate four times that of normal operation.

Second Embodiment
FIG. 5 is a block diagram showing a configuration example of a solid-state image pickup device (CMOS image sensor) equipped with a column parallel ADC including a data transfer circuit according to the second embodiment of the present invention.

  The second embodiment is another embodiment of the 2/4 thinning-out operation, and is different from the first embodiment described above in that the odd-numbered columns and the even-numbered columns are read out by different systems (see FIG. 5). Correspondingly, it is a vertical reading structure), and two output signal lines connected to the ADC groups 12A and 12B from each data flip-flop circuit of the H scanners 140A and 140B are connected every four columns. is there.

  The odd column reading side (upper side in FIG. 5) is the ADC group 12A, the H scanner 140A, the data transfer lines 14A-0 and 14A-1, the switching transistors NT11, NT13, NT15, NT17, NT19, NT111, NT113, NT115, and Sense amplifiers 16A-1 and 16A-2 are arranged.

  The ADC group 12A includes ADC11, ADC13, ADC15, ADC17, ADC19, ADC111, ADC113, and ADC115 connected to odd-numbered column lines.

The H scanner 140A basically has the same configuration and functions as the H scanner 140 of the first embodiment, and includes data flip-flop circuits FFA10, FFA11, FFA12, FFA13, and selectors SLA10, SLA11, SLA12, SLA13. It is comprised including.
The selector SLA10 is supplied with a switching signal SWA10, the selector SLA11 is supplied with a switching signal SWA11, the selector SLA12 is supplied with a switching signal SWA12, and the selector SLA13 is supplied with a switching signal SWA13.

Switching transistors NT11, NT13, NT19, NT111 are connected between the data transfer line 14A-0 and the data output sections of the ADC11, ADC13, ADC19, ADC111, respectively.
Switching transistors NT15, NT17, NT113, and NT115 are connected between the data transfer line 14A- 1 and the data output units of the ADC15, ADC17, ADC113, and ADC115, respectively.

Then, a selection signal HSELA10 that is an output of the data flip-flop circuit FFA10 of the H scanner 140A is supplied to the gates of the switching transistors NT11 and NT15.
A selection signal HSELA11, which is the output of the data flip-flop circuit FFA11, is supplied to the gates of the switching transistors NT13 and NT17.
A selection signal HSELA12, which is the output of the data flip-flop circuit FFA12, is supplied to the gates of the switching transistors NT19 and NT113.
A selection signal HSELA13, which is the output of the flip-flop circuit FFA13, is supplied to the gates of the switching transistors NT111 and NT115.

  The even column readout side (lower side in FIG. 5) is the ADC group 12B, the H scanner 140B, the data transfer lines 14B-0 and 14B-1, the switching transistors NT10, NT12, NT14, NT16, NT18, NT110, NT112, NT114, In addition, sense amplifiers 16B-1 and 16B-2 are arranged.

  The ADC group 12B includes ADC10, ADC12, ADC14, ADC16, ADC18, ADC110, ADC112, and ADC114 connected to odd-numbered column lines.

The H scanner 140B basically has the same configuration and function as the H scanner 140 of the first embodiment, and includes data flip-flop circuits FFB10, FFB11, FFB12, and FFB13, and selectors SLB10, SLB11, SLB12, and SLB13. It is comprised including.
The selector SLB10 is supplied with a switching signal SWB10, the selector SLB11 is supplied with a switching signal SWB11, the selector SLB12 is supplied with a switching signal SWB12, and the selector SLB13 is supplied with a switching signal SWB13.

Switching transistors NT14, NT16, NT112, and NT114 are connected between the data transfer line 14B-0 and the data output portions of the ADCs 14, ADC16, ADC112, and ADC114, respectively.
Switching transistors NT10, NT12, NT18, NT110 are connected between the data transfer line 14B-1 and the data output sections of the ADC10, ADC12, ADC18, ADC110, respectively.

Then, the selection signal HSELB10 that is the output of the data flip-flop circuit FFB10 of the H scanner 140B is supplied to the gates of the switching transistors NT10 and NT14.
A selection signal HSELB11, which is the output of the flip-flop circuit FFB11, is supplied to the gates of the switching transistors NT12 and NT16.
A selection signal HSELB12 that is the output of the flip-flop circuit FFB12 is supplied to the gates of the switching transistors NT18 and NT112.
A selection signal HSELB13, which is the output of the flip-flop circuit FFB13, is supplied to the gates of the switching transistors NT110 and NT114.

In the solid-state imaging device 10A according to the second embodiment, the selection signal HSELA10 that is the output of the first-stage data flip-flop circuit FFA10 of the odd-numbered (upper) H scanner 140A is the first and fifth columns. The selection signal HSELB10 that is supplied to the gates of the switching transistors NT11 and NT15 and is the output of the first stage data flip-flop circuit FFB10 of the even-numbered (lower) H scanner 140B is connected to the 0th and 4th columns. Has been.
The selection signal HSELA11, which is the output of the second-stage data flip-flop circuit FFA11 of the odd-numbered (upper) H scanner 140A, is supplied to the gates of the switching transistors NT13 and NT17 in the third and seventh columns. The selection signal HSELB11, which is the output of the second-stage data flip-flop circuit FFB11 of the even-numbered (lower) H scanner 140B, is supplied to the gates of the switching transistors NT12 and NT16 in the second and sixth columns.

  That is, in the second embodiment, the selection signals HSELA10 and HSELB10, which are the outputs of the first-stage data flip-flop circuits FFA10 and FFB10, are supplied to the column column to be read at the time of 2/4 thinning, and the second-stage data The selection signals HSELA11 and HSELB11, which are the outputs of the flip-flop circuits FFA11 and FFB11, are supplied to a column row that is skipped during 2/4 decimation.

As described above, the second embodiment also adopts a configuration in which the column for reading out the output of the data flip-flop circuit of the H scanners 140A and 140B is alternately connected to the column to be skipped.
Two-input selectors SLA10 to SLA13 and SLB10 to SLB13 are arranged on the input side of each data flip-flop circuit.

  As in the case of the first embodiment, one of the selector input signals arranged at the input of the data flip-flop circuit FFA1x is the selection signal HSELAx-1 which is the output of the previous flip-flop circuit. One input signal is a selection signal HSELx-2 that is the output of the preceding flip-flop circuit for the data flip-flop circuit that is read at the time of thinning, and is a fixed potential for the data flip-flop circuit that is skipped at the time of thinning.

In the above configuration, when normal reading is performed, the switching signals SWA10 to SWA13 and SWB10 to SWB13 of the selectors SLA10 to SLA13 and SLB10 to SLB13 are set to “0”.
By setting in this way, the inputs of all the data flip-flop circuits FFA11 to FFA13 and FFB11 to FFB13 become the previous stage output, and all the data flip-flop circuits are scanned.
When the start pulse φST is input to the H scanners 140A and 140B in this state, the 0th column and the 1st column are selected by the selection signals HSELA10 and HSELB10 which are the outputs of the first data flip-flop circuits FFA10 and FFB10 in synchronization with the clock φCK. The fourth, fifth, and fifth columns are selected, and data AD0, AD1, AD4, and AD5 are read.
At the next clock φCK, the data AD2, AD3, AD6, AD7 in the second, third, sixth and seventh columns selected by the selection signals HSELA11, HSELB11 are read.

When executing the thinning operation, the switching signals SWA10 to SWA13 and SWB10 to SWB13 of the selectors SLA10 to SLA13 and SLB10 to SLB13 are set to “1”.
With this setting, every other data flip-flop circuit scans.
In this state, when the start pulse φST is input to the H scanners 140A and 140B, the selection signals HSELA10 and HSELB10, which are outputs of the first-stage data flip-flop circuits FFA10, FFB10 /, FFA10, and FFB10, synchronize with the clock φCK. The first column, the first column, the fourth column, and the fifth column are selected, and the data AD0, AD1, AD4, and AD5 are read out.
At the next clock φCK, the selection signals HSELA11 and HSELB11 by the second-stage data flip-flop circuits FFA11 and FFB11 are skipped, the selection signals HSELA12 and HSELB12 by the third-stage data flip-flop circuits FFA12 and FFB12 become active, and the selection signal The eighth, ninth, twelfth, and thirteenth columns selected by HSELA 12 and HSELB 12 are read, and 2/4 decimation reading is realized while skipping unnecessary data.

  In the second embodiment, the configuration is such that the selection method of the H scanner at the time of 2/4 decimation is changed. However, the configuration is not limited to 2/4 decimation, and a configuration for realizing horizontal reading of arbitrary l / m decimation is possible. is there. The column position indicated by another selector, the data flip-flop circuit to be skipped, and the output of the data flip-flop circuit may be anywhere.

<Third Embodiment>
FIG. 6 is a block diagram illustrating a configuration example of a main part of a solid-state image pickup device (CMOS image sensor) equipped with a column parallel ADC including a data transfer circuit according to the third embodiment of the present invention.

The third embodiment shows a configuration that realizes 2-channel parallel reading and 1/3 decimation reading.
In FIG. 6, the same components and functional parts as those in FIG. 2 for easy understanding are represented by the same reference numerals.

The H scanner 140C basically shifts the start pulse φST from the timing control circuit 15 sequentially or one by one in synchronism with the clock φCK from the timing control circuit 15, and sequentially reads output signals. The data flip-flop circuits FF10 to FF15 and selectors SL10 to SL15 are included.
Here, the output signals of the data flip-flop circuits FF10, FF11, FF12, FF13, FF14, and FF15 are referred to as selection signals HSEL10, HSEL11, HSEL12, HSEL13, HSEL14, and HSEL15.

The selector SL10 has two inputs I0 and I1, and these two inputs I0 and I1 are connected in common to the supply line of the start pulse φST, and the output is connected to the data input of the data flip-flop circuit FF10. Yes.
The selector SL10 selects and outputs the input I0 when the switching signal SW10 is at the low level “0”, and selects the input I1 when the switching signal SW10 is at the high level “1”. Output.
That is, the selector SL10 selects the start pulse φST and outputs data regardless of whether the switching signal SW10 is “0” or “1” because the input portions I0 and I1 are commonly connected to the supply line of the start pulse φST. This is supplied to the flip-flop circuit FF10.

The selector SL11 has two inputs I0 and I1, the input unit I0 is connected to the output line of the selection signal HSEL10 of the data flip-flop circuit FF10, and the input unit I1 is connected to a fixed potential.
The selector SL11 selects and outputs the input I0 when the switching signal SW11 is at the low level “0”, and selects the input I1 when the switching signal SW11 is at the high level “1”. Output.
That is, when the switching signal SW11 is “0”, the selector SL11 supplies the selection signal HSEL10, which is the output of the previous data flip-flop circuit FF10, to the data input section of the next data flip-flop circuit FF11.
On the other hand, when the switching signal SW11 is “1”, the selector SL11 does not supply any signal to the next data flip-flop circuit FF11. Thereby, the data flip-flop circuit FF11 is bypassed in the shift operation of the start pulse φST.

The selector SL12 has two inputs I0 and I1, the input unit I0 is connected to the output line of the selection signal HSEL11 of the data flip-flop circuit FF11, and the input unit I1 is connected to a fixed potential.
The selector SL12 selects and outputs the input I0 when the switching signal SW12 is at the low level “0”, and selects the input I1 when the switching signal SW12 is at the high level “1”. Output.
That is, when the switching signal SW12 is “0”, the selector SL12 supplies the selection signal HSEL11, which is the output of the previous data flip-flop circuit FF11, to the data input section of the next data flip-flop circuit FF12.
On the other hand, the selector SL12 does not supply any signal to the data flip-flop circuit FF12 at the next stage when the switching signal SW12 is “1”. Thereby, the data flip-flop circuit FF12 is bypassed in the shift operation of the start pulse φST.

The selector SL13 has two inputs I0 and I1, the input unit I0 is connected to the output line of the selection signal HSEL12 of the preceding data flip-flop circuit FF12, and the input unit I1 is the three-stage previous data flip-flop circuit FF10. It is connected to the output line of the selection signal HSEL10.
The selector SL13 selects and outputs the input I0 when the switching signal SW13 is at the low level “0”, and selects the input I1 when the switching signal SW13 is at the high level “1”. Output.
That is, when the switching signal SW13 is “0”, the selector SL13 supplies the selection signal HSEL12 that is the output of the previous data flip-flop circuit FF12 to the data input unit of the data flip-flop circuit FF13.
On the other hand, when the switching signal SW13 is “1”, the selector SL13 supplies the selection signal HSEL10, which is the output of the data flip-flop circuit FF10 two stages before, to the data input section of the data flip-flop circuit FF13.

The selector SL14 has two inputs I0 and I1, the input unit I0 is connected to the output line of the selection signal HSEL13 of the data flip-flop circuit FF13, and the input unit I1 is connected to a fixed potential.
The selector SL14 selects and outputs the input I0 when the switching signal SW14 is at the low level “0”, and selects the input I1 when the switching signal SW14 is at the high level “1”. Output.
That is, when the switching signal SW14 is “0”, the selector SL14 supplies the selection signal HSEL13, which is the output of the previous data flip-flop circuit FF13, to the data input section of the next data flip-flop circuit FF14.
On the other hand, the selector SL14 does not supply any signal to the data flip-flop circuit FF14 at the next stage when the switching signal SW14 is “1”. Thereby, the data flip-flop circuit FF14 is bypassed in the shift operation of the start pulse φST.

The selector SL15 has two inputs I0 and I1, the input unit I0 is connected to the output line of the selection signal HSEL14 of the data flip-flop circuit FF14, and the input unit I1 is connected to a fixed potential.
The selector SL15 selects and outputs the input I0 when the switching signal SW15 is at the low level “0”, and selects the input I1 when the switching signal SW15 is at the high level “1”. Output.
That is, when the switching signal SW14 is “0”, the selector SL15 supplies the selection signal HSEL14, which is the output of the previous data flip-flop circuit FF14, to the data input section of the next data flip-flop circuit FF15.
On the other hand, the selector SL15 does not supply any signal to the data flip-flop circuit FF15 at the next stage when the switching signal SW15 is “1”. Thereby, the data flip-flop circuit FF15 is bypassed in the shift operation of the start pulse φST.

  As a circuit 141B for actually reading data, data transfer lines 14-0 and 14-1 and sense amplifiers 16-0 and 16-1 corresponding to the output lines are arranged, and the data transfer lines 14-0 and 14-1 are arranged. The switching transistors NT10 to NT111, which are n-channel MOS transistors, are connected between the -1 and the data output sections of the ADC10 to ADC111.

Specifically, switching transistors NT10, NT12, NT14, NT16, NT18, and NT110 are connected between the data transfer line 14-0 and the data output units of the ADC10, ADC12, ADC14, ADC16, ADC18, and ADC110, respectively. Yes.
Switching transistors NT11, NT13, NT15, NT17, NT19, and NT111 are connected between the data transfer line 14-1 and the data output sections of the ADC11, ADC13, ADC15, ADC17, ADC19, and ADC111, respectively.
Switching transistors NT14, NT16, NT112, and NT114 are connected between the data transfer line 14-2 and the data output portions of the ADC 14, ADC16, ADC112, and ADC114, respectively.

The selection signal HSEL10 output from the data flip-flop circuit FF10 is supplied to the gates of the switching transistors NT10 and NT13 connected to the outputs of the ADC10 and ADC13.
The selection signal HSEL11 output from the data flip-flop circuit FF11 is supplied to the gates of the switching transistors NT11 and NT12 connected to the outputs of the ADC11 and ADC12.
The selection signal HSEL12 output from the data flip-flop circuit FF12 is supplied to the gates of the switching transistors NT14 and NT15 connected to the outputs of the ADC 14 and ADC15.
The selection signal HSEL13 output from the data flip-flop circuit FF13 is supplied to the gates of the switching transistors NT16 and NT19 connected to the outputs of the ADC16 and ADC19.
The selection signal HSEL14 output from the data flip-flop circuit FF14 is supplied to the gates of the switching transistors NT17 and NT18 connected to the outputs of the ADC17 and ADC18.
The selection signal HSEL15 output from the data flip-flop circuit FF15 is supplied to the gates of the switching transistors NT110 and NT111 connected to the outputs of the ADC 110 and ADC 111.

As described above, in the solid-state imaging device 10B of the third embodiment, the selection signal HSEL10 that is the output of the first-stage data flip-flop circuit FF10 is supplied to the 0th column and the 3rd column.
The selection signal HSEL11 that is the output of the second-stage data flip-flop circuit FF11 is supplied to the first and second columns, and the selection signal HSEL12 that is the output of the third-stage data flip-flop circuit FF12 is the fourth column. The fifth column is supplied.
That is, the selection signal HSEL10 that is the output of the first-stage data flip-flop circuit FF10 is supplied to the column column that is read out during 1/3 decimation, and the outputs of the second-stage and third-stage data flip-flop circuits FF11 and FF12. Is connected to a column that skips readings during 1/3 decimation.
The outputs of the selectors SL10 to SL15 arranged at the input stage of each data flip-flop circuit are all selected when the switching signals SW10 to SW15 input to the selectors SL10 to SL15 are “0”. It is like that.
When the switching signals SW10 to SW15 input to the selectors SL10 to SL15 are “1”, the selector SL13 selects and outputs the selection signal HSEL10. The selectors SL11 and SL12 in the previous stage are fixed voltages. Is output.

In the above configuration, when normal reading is performed, the switching signals SW10 to SW15 of the selectors SL10 to SL15 are set to “0”. By setting in this way, the input of all the data flip-flop circuits FF10 to FF15 becomes the output of the previous stage, and all the data flip-flop circuits FF10 to FF15 are scanned.
In this state, when the start pulse φST is input to the H scanner 140C, the 0th column and the 3rd column are selected by the selection signal HSEL10 output from the first data flip-flop circuit FF10 in synchronization with the clock φCK, and the data AD0 , AD3 are read out.
At the next clock φCK, the data AD1 and AD2 in the first and second columns selected by the selection signal HSEL11 are read.

Further, when executing the thinning-out operation, the switching signals SW10 to SW15 are set to “1”. With this setting, every third data flip-flop circuit scans.
When the start pulse φST is input to the H scanner 140C in this state, the 0th column and the 3rd column are selected by the selection signal HSEL10 output from the first stage data flip-flop circuit FF10 in synchronization with the clock φCK, and the data AD0 and AD3 are read.
At the next clock φCK, the data flip-flop circuits FF11 and FF12 are skipped, so that the selection signal HSEL13, which is the output of the third-stage data flip-flop circuit FF13, becomes active, and the sixth and ninth columns selected by the selection signal HSEL13 Data is read out.
As a result, 1/3 decimation reading is realized while skipping unnecessary data, and reading at a frame rate three times that of normal reading becomes possible.

FIG. 7 is a diagram illustrating a configuration example of a data sort circuit corresponding to 1/3 decimation according to the present embodiment.
In FIG. 7, for ease of understanding, portions having the same configuration and function as those of the data sort circuit of FIG. 3 are denoted by the same reference numerals.

Two-channel n-bit data output from the sense amplifiers 16-1 and 16-2 in FIG. 6 is sequentially input to the data sort circuit 18B in synchronization with the clock clkt.
In the data sort circuit 18A in FIG. 7, the 0 channel has a two-stage flip-flop circuit.
In FIG. 7, the first-stage flip-flop circuit is indicated by sort_indat0, and the second-stage flip-flop circuit is indicated by indat0_dly1.
One channel has a three-stage flip-flop circuit, and the three-stage flip-flop circuits are indicated by sort_indat1, indat1_dly1, and indat1_dly2 in order from the first stage.

  Further, the data sort circuit 18B has multiplexers 185 and 186.

The multiplexer 185 selects one of the output of the first-stage flip-flop circuit sort_indat1 of the first channel, the output of the second-stage flip-flop circuit indat0_dly1, and the output of the third-stage flip-flop circuit indat1_dly2.
The multiplexer 185 selects the output of the first-stage flip-flop circuit sort_indat1 of 1 channel when the 2-bit signal sort_cnt is “0”, and selects the output of the second-stage flip-flop circuit indat0_dly1 when “2”. When “2”, the output of the third-stage flip-flop circuit indat1_dly2 is selected.

The multiplexer 186 includes two-channel data (2ch × nbit) output from the second stage flip-flop circuits indat0_dly1 and indat1_dly1 of 0 and 1 channel, n-bit output from the second stage flip-flop circuit indat0_dly1 of 0 channel, and One of 2-channel data (2ch × nbit) consisting of n-bit data selected by the multiplexer 185 is selected and output.
The multiplexer 186 selects the normal reading mode when the mode switching signal hsdcmt for separating normal reading and 1/3 decimation reading is “0”, and the n-bit output of the second-stage flip-flop circuit indat0_dly1 of the 0 channel and the multiplexer 185 2-channel data (2ch × nbit) consisting of n-bit data is selected.
The multiplexer 186 selects two-channel data (2ch × nbit) as the 1/3 decimation mode when the mode switching signal hsdcmt is “1” and the output of the first-stage flip-flop circuits indat0_dly1 and indat1_dly1. .

  That is, in the third embodiment, when the mode switching signal hsdcmt is “0”, normal reading is performed, and when it is “1”, the 1/3 thinning mode is set.

  FIG. 8 is a diagram for explaining a normal read operation and a 1/3 thinning operation of the data sort circuit of FIG.

  Here, the operation in the case of normal reading of the data 18B will be described.

Data AD0 and AD3 are stored in the first stage flip-flop circuits sort_indat0 and sort_indat1, respectively, in the first first clock in synchronization with the clock clkgt, and are stored in the second stage flip-flop circuits indat0_dly1 and indat1_dly1 in the second clock. .
Here, the data AD0 is output from the second-stage flip-flop circuit indat0_dly1 of the channel ch0, and the data AD1 is output from the first-stage flip-flop circuit sort_indat1 of the channel ch1.
When these are connected to the output, AD0 and AD1 and sorted data are output as a result.

At the third clock, the data AD2 is output from the second-stage flip-flop circuit indat0_dly1 of the channel ch0, and the data AD3 is output from the third-stage flip-flop circuit indat1_dly2 of the channel ch1.
When these are connected to the output, AD2 and AD3 and the sorted data are output as a result.

At the fourth clock, data AD4 is output from the first-stage flip-flop circuit indat0_dly1 of channel ch0, and data AD5 is output from the second-stage flip-flop circuit indat1_dly1 of channel ch1.
When these are connected to the output, AD4 and AD5 and the sorted data are output as a result.
In the fifth lock, data AD6 and AD7 are output by taking the same output connection as in the second clock, and in the sixth clock, data AD7 and AD8 are output by taking the same output connection as in the third clock. Is done.

From the above, the output of the channel ch0 is the output of the second-stage flip-flop circuit indat0_dly1, the output of the channel ch1 is synchronized with the clock, the output of the first-stage flip-flop circuit sort_indat1, and the output of the third-stage flip-flop circuit indat1_dly2 By switching the output to the output of the second-stage flip-flop circuit indat1_dly1, sorted data can be output as a result.
In the third embodiment, a 2-bit signal sort_cnt is used as a pulse indicating switching of three patterns of outputs.

  In the case of the thinning-out operation, the outputs of the second-stage flip-flop circuits indat0_dly1, indat1_dly1 after the second clock are output as they are in synchronization with the clock.

  As described above, in the H scanner, the column selection order indicated by each data flip-flop circuit is not sequentially selected, but the columns that are read when performing the thinning process and the columns that are not read are configured separately. By changing the selection order and performing readout, 1 / m thinning readout can be realized in parallel readout of k columns in the horizontal direction.

  As described above, according to the present embodiment, the pixel array unit 11 as an imaging unit in which a plurality of pixels that perform photoelectric conversion are arranged in a matrix, and a plurality of data transfer lines 14-0 that transfer digital data. 14-3 and data corresponding to the input level of the output data of the pixels of each column of the imaging unit, and the data of the plurality of pixels are transferred to the corresponding transfer line in response to a selection signal ADC group 12 including ADC 10 to ADC 115 as a plurality of holding units arranged in parallel corresponding to each column, and H scanner 140 that generates a selection signal in synchronization with the clock and outputs the selection signal to the output unit of ADC 10 to ADC 115. The H scanner 140 is arranged corresponding to the parallel arrangement of ADC10 to ADC115, and outputs a selection signal to the corresponding ADC in synchronization with the supplied clock. Including output flip-flop circuits FF10 to FF13 as a plurality of selection signal generation units connected alternately and individually to the output unit of the ADC of the array to be read at the time of decimation reading and the ADC of the array to be skipped In normal reading, a plurality of data flip-flop circuits FF10 to FF13 are sequentially scanned to output a plurality of ADC data to corresponding data transfer lines. In thinning-out reading, the scanning order is changed. Since only the effective data of the ADC of the array from which data is to be read by thinning readout is output to the corresponding data transfer line, the following effects can be obtained.

That is, according to the present embodiment, in a system that horizontally transfers the data of the imaging unit by thinning processing, the bus can be effectively used by thinning processing effectively, and a double data rate can be realized. , Can contribute to higher frame rate.
Further, when it is not necessary to reduce the frame rate in the thinning-out process, it is possible to take measures such as slowing down the clock, which can contribute to reduction in power consumption.
In addition, redundant processing such as discarding data on the DPU side, which was necessary in a general configuration, is no longer necessary, and the DPU can be configured in a simple manner, facilitating design and reducing design time and man-hours. Can also contribute.

  A solid-state imaging device having such an effect can be applied as an imaging device for a digital camera or a video camera.

  FIG. 9 is a diagram illustrating an example of a configuration of a camera system to which the solid-state imaging device according to the embodiment of the present invention is applied.

  As shown in FIG. 9, the camera system 20 guides incident light to the imaging device 21 to which the solid-state imaging device 10 according to the present embodiment can be applied and the pixel region of the imaging device 21 (forms a subject image). ) Optical system, for example, a lens 22 that forms incident light (image light) on the imaging surface, a drive circuit (DRV) 23 that drives the imaging device 21, and a signal processing circuit that processes the output signal of the imaging device 21 ( PRC) 24.

  The drive circuit 23 includes a timing generator (not shown) that generates various timing signals including a start pulse and a clock pulse that drive a circuit in the imaging device 21, and drives the imaging device 21 with a predetermined timing signal. .

The signal processing circuit 24 performs signal processing such as CDS (Correlated Double Sampling) on the output signal of the imaging device 21.
The image signal processed by the signal processing circuit 24 is recorded on a recording medium such as a memory. The image information recorded on the recording medium is hard copied by a printer or the like. The image signal processed by the signal processing circuit 24 is displayed as a moving image on a monitor including a liquid crystal display.

  As described above, a high-precision camera can be realized by mounting the above-described imaging element 10 as the imaging device 21 in an imaging apparatus such as a digital still camera.

It is a block diagram which shows the structural example of a column parallel ADC mounting solid-state image sensor (CMOS image sensor). It is a block diagram which shows the structural example of the solid-state image sensor (CMOS image sensor) mounted with column parallel ADC which concerns on one Embodiment of this invention. It is a figure which shows the structural example of the data sort circuit corresponding to 2/4 thinning-out concerning this embodiment. It is a figure for demonstrating normal read-out operation | movement and 2/4 thinning-out operation | movement of the data sort circuit of FIG. It is a block diagram which shows the structural example of the column parallel ADC mounting solid-state image sensor (CMOS image sensor) containing the data transfer circuit which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the structural example of the principal part of the column parallel ADC mounting solid-state image sensor (CMOS image sensor) containing the data transfer circuit which concerns on the 3rd Embodiment of this invention. It is a figure which shows the structural example of the data sort circuit corresponding to 1/3 thinning-out concerning this embodiment. It is a figure for demonstrating the normal read-out operation | movement and 1/3 thinning-out operation | movement of the data sort circuit of FIG. It is a figure which shows an example of a structure of the camera system with which the solid-state image sensor which concerns on embodiment of this invention is applied.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10, 10A, 10B ... Solid-state image sensor, 11 ... Pixel array part, 12 ... ADC group 12, 13 ... Vertical (row) scanning circuit, 14 ... Horizontal (column) scanning circuit, 14-0 to 14-3, 14A-0, 14A-1, 14B-0, 14B-1 ... data transfer line, 15 ... timing control circuit, 16 ... sense amplifier (S / A) group 16-0 to 16-3, 16A-0, 16A-1, 16B-0, 16B-1... Sense amplifier, 17... Data processing circuit, 18, 18B. FF15, FFA10 to FFA13, FFB10 to FFB13, data flip-flop circuit, 20 ... camera system, 21 ... imaging device, 22 ... drive circuit, 23 ... lens, 24 ... signal processing circuit.

Claims (6)

A plurality of transfer lines for transferring data;
A plurality of holding units arranged in parallel holding data corresponding to the input level and transferring the data to the corresponding transfer line in response to a selection signal;
A scanning unit that generates the selection signal in synchronization with a clock and outputs the selection signal to the holding unit;
The transfer line is
Wired in the parallel arrangement direction of the holding parts,
The scanning unit is
A holding unit of an arrangement that is arranged corresponding to the parallel arrangement of the holding units, outputs the selection signal to the corresponding holding unit in synchronization with a supplied clock, and an output line of the selection signal is to be read at the time of thinning-out reading A plurality of selection signal generation units alternately and individually connected to the holding unit of the array to be skipped ; and
During normal reading, the plurality of selection signal generation units are sequentially scanned to generate the selection signal, and during thinning reading, a selection signal supply line is connected to a holding unit of an array that is skipped during the thinning reading. Including a selector unit that sequentially scans the selection signal generation unit connected to a holding unit of an array that reads out data by thinning-out readout, bypassing the selection signal generation unit,
The plurality of selection signal generators are
A plurality of first selection signal generators connected to a holding unit of an array to be read, which is a target for thinning-out reading, and a plurality of second selection signal generators connected to a holding unit of an array to be skipped , And
The selection signal supplied by the selection signal generation unit on the front stage side in synchronization with the clock signal is used as a selection signal for the own stage, and includes a function of outputting to the selection signal generation unit on the rear stage side,
The selector part
During normal reading, the plurality of selection signal generation units of the first and second selection signal generation units are sequentially scanned to generate the selection signal,
At the time of thinning-out reading, the selection signal of the first selection signal generation unit on the preceding stage side is supplied to the first selection signal generation unit on the next stage of the bypassed second selection signal generation unit, and the first selection signal generation unit Stop supplying the selection signal of the first selection signal generation unit on the preceding stage to the second selection signal generation unit, stop generating the selection signal of the second selection signal generation unit,
The scanning unit is
During normal read, is output to Kiten feed line on the corresponding data of the plurality of holding portions are sequentially scanning the plurality of selection signal generator,
When thinning readout, data scanning circuit for outputting change the order of the scanning, the Kiten feed line on which corresponding only valid data holding portion of the array from which data is to be read in thinning readout. The data scanning circuit according to claim 1, further comprising a data sorting circuit that rearranges the read data in a special order corresponding to the connection of the output of the selection signal generation unit during normal reading. An imaging unit in which a plurality of pixels that perform photoelectric conversion are arranged in a matrix;
A plurality of transfer lines for transferring data;
Corresponding to each column of the plurality of pixels, holding data corresponding to the input level of the output data of the pixels of each column of the imaging unit, and transferring the data to the corresponding transfer line in response to a selection signal A plurality of holding portions arranged in parallel,
A scanning unit that generates the selection signal in synchronization with a clock and outputs the selection signal to the holding unit;
The transfer line is
Wired in the parallel arrangement direction of the holding parts,
The scanning unit is
A holding unit of an arrangement that is arranged corresponding to the parallel arrangement of the holding units, outputs the selection signal to the corresponding holding unit in synchronization with a supplied clock, and an output line of the selection signal is to be read at the time of thinning-out reading A plurality of selection signal generation units alternately and individually connected to the holding unit of the array to be skipped ; and
During normal reading, the plurality of selection signal generation units are sequentially scanned to generate the selection signal, and during thinning reading, a selection signal supply line is connected to a holding unit of an array that is skipped during the thinning reading. Including a selector unit that sequentially scans the selection signal generation unit connected to a holding unit of an array that reads out data by thinning-out readout, bypassing the selection signal generation unit,
The plurality of selection signal generators are
A plurality of first selection signal generators connected to a holding unit of an array to be read, which is a target for thinning-out reading, and a plurality of second selection signal generators connected to a holding unit of an array to be skipped , And
The selection signal supplied by the selection signal generation unit on the front stage side in synchronization with the clock signal is used as a selection signal for the own stage, and includes a function of outputting to the selection signal generation unit on the rear stage side,
The selector part
During normal reading, the plurality of selection signal generation units of the first and second selection signal generation units are sequentially scanned to generate the selection signal,
At the time of thinning-out reading, the selection signal of the first selection signal generation unit on the preceding stage side is supplied to the first selection signal generation unit on the next stage of the bypassed second selection signal generation unit, and the first selection signal generation unit Stop supplying the selection signal of the first selection signal generation unit on the preceding stage to the second selection signal generation unit, stop generating the selection signal of the second selection signal generation unit,
The scanning unit is
During normal read, is output to Kiten feed line on the corresponding data of the plurality of holding portions are sequentially scanning the plurality of selection signal generator,
When thinning readout is to change the order of the scanning, the solid-state imaging device to output the Kiten feed line on which corresponding only valid data holding portion of the array from which data is to be read in thinning readout. The solid-state imaging device according to claim 3, further comprising a data sort circuit that rearranges the read data in a special order corresponding to the connection of the output of the selection signal generation unit during normal reading. A solid-state image sensor;
An optical system for forming a subject image on the image sensor,
The solid-state imaging device is
An imaging unit in which a plurality of pixels that perform photoelectric conversion are arranged in a matrix;
A plurality of transfer lines for transferring data;
Corresponding to each column of the plurality of pixels, holding data corresponding to the input level of the output data of the pixels of each column of the imaging unit, and transferring the data to the corresponding transfer line in response to a selection signal A plurality of holding portions arranged in parallel,
A scanning unit that generates the selection signal in synchronization with a clock and outputs the selection signal to the holding unit;
The transfer line is
Wired in the parallel arrangement direction of the holding parts,
The scanning unit is
A holding unit of an arrangement that is arranged corresponding to the parallel arrangement of the holding units, outputs the selection signal to the corresponding holding unit in synchronization with a supplied clock, and an output line of the selection signal is to be read at the time of thinning-out reading A plurality of selection signal generation units alternately and individually connected to the holding unit of the array to be skipped ; and
During normal reading, the plurality of selection signal generation units are sequentially scanned to generate the selection signal, and during thinning reading, a selection signal supply line is connected to a holding unit of an array that is skipped during the thinning reading. Including a selector unit that sequentially scans the selection signal generation unit connected to a holding unit of an array that reads out data by thinning-out readout, bypassing the selection signal generation unit,
The plurality of selection signal generators are
A plurality of first selection signal generators connected to a holding unit of an array to be read, which is a target for thinning-out reading, and a plurality of second selection signal generators connected to a holding unit of an array to be skipped , And
The selection signal supplied by the selection signal generation unit on the front stage side in synchronization with the clock signal is used as a selection signal for the own stage, and includes a function of outputting to the selection signal generation unit on the rear stage side,
The selector part
During normal reading, the plurality of selection signal generation units of the first and second selection signal generation units are sequentially scanned to generate the selection signal,
At the time of thinning-out reading, the selection signal of the first selection signal generation unit on the preceding stage side is supplied to the first selection signal generation unit on the next stage of the bypassed second selection signal generation unit, and the first selection signal generation unit Stop supplying the selection signal of the first selection signal generation unit on the preceding stage to the second selection signal generation unit, stop generating the selection signal of the second selection signal generation unit,
The scanning unit is
During normal read, is output to Kiten feed line on the corresponding data of the plurality of holding portions are sequentially scanning the plurality of selection signal generator,
When thinning reading, a camera system to output by changing the order of the scanning, the Kiten feed line on which corresponding only valid data holding portion of the array from which data is to be read in thinning readout. The camera system according to claim 5, further comprising a data sorting circuit that rearranges the read data in a special order corresponding to the connection of the output of the selection signal generation unit during normal reading.

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