JP5154605B2 - Ferroelectric material layer manufacturing method, thin film transistor, and piezoelectric ink jet head - Google Patents

Description

  The present invention relates to a method for manufacturing a ferroelectric material layer, a thin film transistor, and a piezoelectric ink jet head.

FIG. 25 is a diagram for explaining a conventional thin film transistor 900.
As shown in FIG. 25, a conventional thin film transistor 900 includes a source electrode 950 and a drain electrode 960, a channel layer 940 positioned between the source electrode 950 and the drain electrode 960, and a gate that controls a conduction state of the channel layer 940. The electrode 920 includes a gate insulating layer 930 formed between the gate electrode 920 and the channel layer 940 and made of a ferroelectric material layer. In FIG. 25, reference numeral 910 denotes an insulating substrate.

In the conventional thin film transistor 900, as a material constituting the gate insulating layer 930, a ferroelectric material (for example, BLT (Bi _4-x La _x Ti ₃ O ₁₂ ), PZT (Pb (Zr _x , Ti _1-x )) is used. O ₃ )) is used, and an oxide conductive material (for example, indium tin oxide (ITO)) is used as a material constituting the channel layer 940.

  According to the conventional thin film transistor 900, since an oxide conductive material is used as a material constituting the channel layer, the carrier concentration can be increased, and a ferroelectric material is used as the material constituting the gate insulating layer. Therefore, it is possible to perform high-speed switching with a low driving voltage, and as a result, it becomes possible to control a large current at high speed with a low driving voltage.

  A conventional thin film transistor can be manufactured by a conventional thin film transistor manufacturing method shown in FIG. FIG. 26 is a diagram for explaining a conventional method of manufacturing a thin film transistor. FIG. 26A to FIG. 26E are process diagrams, and FIG. 26F is a plan view of the thin film transistor 900.

First, as shown in FIG. 26A, a laminated film of Ti (10 nm) and Pt (40 nm) is formed on an insulating substrate 910 made of an Si substrate having a SiO ₂ layer formed on the surface by an electron beam evaporation method. A gate electrode 920 is formed.
Next, as shown in FIG. 26B, a ferroelectric material layer (for example, BLT (Bi _3.25 La _0.75 Ti ₃ O ₁₂ ) or PZT (PZT) is formed from above the gate electrode 920 by a sol-gel method. A gate insulating layer 930 (200 nm) made of Pb (Zr _0.4 Ti _0.6 ) O ₃ ).) Is formed.
Next, as shown in FIG. 26C, a channel layer 940 (5 nm to 15 nm) made of ITO is formed on the gate insulating layer 930 by RF sputtering.
Next, as shown in FIG. 26D, Ti (30 nm) and Pt (30 nm) are vacuum-deposited on the channel layer 940 by electron beam evaporation to form a source electrode 950 and a drain electrode 960.
Next, the element region is separated from other element regions by the RIE method and the wet etching method (HF: HCl mixed solution).
Thereby, a thin film transistor 900 as shown in FIGS. 26E and 26F can be manufactured.

FIG. 27 is a diagram for explaining the electrical characteristics of the conventional thin film transistor 900. In FIG. 27, reference numeral 940a indicates a channel, and reference numeral 940b indicates a depletion layer.
In the conventional thin film transistor 900, as shown in FIG. 27, when the gate voltage is 3 V (VG = 3 V), the on-current is about 10 ⁻⁴ A, the on / off ratio is 1 × 10 ⁴ , the field-effect mobility μ A value of 10 cm ² / Vs for _{FE and} about 2 V for the memory window are obtained.

JP 2006-121029 A

  However, since the ferroelectric material layer is formed by the sol-gel method in the above-described thin film transistor, the case where the ferroelectric material layer is formed by a vapor phase method (evaporation method, sputtering method, CVD method, etc.) In comparison, it is not easy to improve the quality of the ferroelectric material layer (crystallinity, uniformity, surface roughness, etc.). As a result, the electrical characteristics of the ferroelectric material layer (for example, high remanent polarization characteristics, Low leakage current characteristics etc.) As a result, there is a problem that it is not easy to improve the performance of the thin film transistor.

  Such a requirement is not a requirement that exists only in the above-described thin film transistor, but a requirement that exists in general applications that utilize the electrical characteristics of the ferroelectric material layer, such as piezoelectric inkjet heads, capacitors, and the like.

  Therefore, the present invention has been made to solve the above problems, and can further improve the electrical characteristics (for example, high remanent polarization characteristics, low leakage current characteristics, etc.) of the ferroelectric material layer. An object of the present invention is to provide a method for manufacturing a ferroelectric material layer. Another object of the present invention is to provide a high-performance thin film transistor including a gate insulating layer formed using such a method for manufacturing a ferroelectric material layer. Still another object of the present invention is to provide a high-performance piezoelectric inkjet head including a piezoelectric layer formed by using such a method for manufacturing a ferroelectric material layer.

[1] The method for producing a ferroelectric material layer according to the present invention includes a first step of preparing a sol-gel solution to be a ferroelectric material by heat treatment, and applying the sol-gel solution on a base material. A second step of forming a precursor composition layer of a ferroelectric material, a third step of drying the precursor composition layer at a first temperature within a range of 120 ° C. to 300 ° C., and the precursor composition A fourth step of embossing the precursor composition layer in a state where the physical layer is heated to a second temperature that is higher than the first temperature and within a range of 150 ° C. to 300 ° C .; And a fifth step of forming a ferroelectric material layer from the precursor composition layer by heat-treating the precursor composition layer at a third temperature higher than the second temperature in this order. And

  According to the method for producing a ferroelectric material layer of the present invention, the precursor composition layer is dried at a first temperature in the range of 120 ° C. to 300 ° C., and the precursor composition layer is made to be at a temperature higher than the first temperature. Since it is supposed that the precursor composition layer is embossed in a state of being heated to a second temperature that is high and within a range of 150 ° C. to 300 ° C., it will be understood from Example 1 described later. In addition, the remanent polarization of the ferroelectric material layer can be further increased.

  Here, the reason why the first temperature is “within a range of 120 ° C. to 300 ° C.” is that when the first temperature is less than 120 ° C., the precursor composition layer cannot be sufficiently dried. This is because it is difficult to uniformly emboss the precursor composition layer in the fourth step. When the first temperature exceeds 300 ° C., the solidification reaction of the precursor composition layer Since the process proceeds too much, the precursor composition layer cannot be sufficiently softened (the plastic deformation ability of the precursor composition layer can be sufficiently increased) in the fourth step, and as a result, sufficient embossing can be performed. This is because it is difficult to obtain an effect. From the above viewpoint, it is more preferable that the first temperature is in the range of 120 ° C to 250 ° C.

  In addition, the second temperature is “higher than the first temperature and within the range of 150 ° C. to 300 ° C.” when the second temperature is lower than the first temperature, the precursor composition layer is This is because it cannot be sufficiently softened (the plastic deformation ability of the precursor composition layer cannot be sufficiently increased), and as a result, it is difficult to obtain a sufficient embossing effect. Is less than 150 ° C., the precursor composition layer cannot be sufficiently softened (the plastic deformation capacity of the precursor composition layer cannot be sufficiently increased). This is because it becomes difficult to obtain the effect of processing, and when the second temperature exceeds 300 ° C., the solidification reaction of the precursor composition layer proceeds too much and the precursor composition layer becomes too hard. This is because the plastic deformation ability of the precursor composition layer is lowered again. From the above viewpoint, it is more preferable that the second temperature is in the range of 200 ° C to 300 ° C.

  In the method for manufacturing a ferroelectric material layer of the present invention, the first temperature and the second temperature may be constant temperatures or may vary within a predetermined temperature range. In the method for manufacturing a ferroelectric material layer according to the present invention, the “embossing” is performed when embossing is performed on a part of the ferroelectric material layer using a concavo-convex mold and when a flat mold is used. This includes both cases where the entire surface of the layer is embossed. In the method for manufacturing a ferroelectric material layer according to the present invention, the embossing process is performed on the ferroelectric material layer using an embossing processing apparatus that embosses the mold in a vertical direction with respect to a flat substrate. Processing may be applied, a mold is attached to the surface of the roller, and while the roller is rotated, an embossing apparatus for embossing on a flat substrate, or a substrate is attached to the surface of the roller, The ferroelectric material layer may be stamped using a stamping apparatus that presses the substrate against the substrate while rotating the roller. When attaching the mold to the surface of the roller, instead of attaching the mold to the surface of the roller, the mold may be formed on the surface of the roller itself. In the method for manufacturing a ferroelectric material layer of the present invention, “embossing” is sometimes called “nanoimprinting”.

In the manufacturing method of the ferroelectric material layer of the present invention, as the ferroelectric material, for example, PZT (Pb (Zr _x , Ti _1-x ) O ₃ ), BLT (Bi _4−x La _x Ti ₃ O _12). ), Nb-doped PZT, La-doped PZT, barium titanate (BaTiO ₃ ), lead titanate (PbTiO ₃ ), BTO (Bi ₄ Ti ₃ O ₁₂ ), SBT (SrBi ₂ Ta ₂ O ₉ ), BZN (Bi ₁ ) _0.5 Zn _1.0 Nb _1.5 O ₇ ) and bismuth ferrite (BiFeO ₃ ) can be preferably exemplified.

  In the method for producing a ferroelectric material layer of the present invention, in the fourth step, a mold heated to a fourth temperature that is higher than the first temperature and within a range of 150 ° C. to 300 ° C. is used. It is more preferable to apply a die pressing process.

  Here, the fourth temperature is “higher than the first temperature and within the range of 150 ° C. to 300 ° C.” when the fourth temperature is lower than the first temperature. However, the temperature of the precursor composition layer tends to be low at the contact surface between the precursor composition layer and the mold, and when the fourth temperature is less than 150 ° C., the precursor composition layer and the mold This is also because the temperature of the precursor composition layer tends to be low at the contact surface with the precursor composition, and when the fourth temperature exceeds 300 ° C., the precursor composition layer at the contact surface between the precursor composition layer and the mold is used. This is because the solidification reaction of the layer proceeds too much and the precursor composition layer becomes too hard, so that the plastic deformation ability of the precursor composition layer decreases again. From the above viewpoint, the fourth temperature is more preferably “higher than the first temperature and in the range of 200 ° C. to 300 ° C.”.

[2] In the method for manufacturing a ferroelectric material layer of the present invention, the first temperature is in a range of 120 ° C. to 200 ° C., the second temperature is higher than the first temperature, and It is preferable that it exists in the range of 175 degreeC-300 degreeC.

  According to the method for manufacturing a ferroelectric material layer of the present invention, the first temperature is in the range of 120 ° C. to 200 ° C., the second temperature is higher than the first temperature, and the range of 175 ° C. to 300 ° C. Therefore, as can be seen from Example 2 described later, the leakage current of the ferroelectric material layer can be further reduced. As can be seen from Example 2 described later, it is more preferable that the first temperature is in the range of 150 ° C. to 175 ° C. and the second temperature is in the range of 200 ° C. to 300 ° C.

  In the method for manufacturing a ferroelectric material layer of the present invention, in the fourth step, a mold heated to a fourth temperature that is higher than the first temperature and within a range of 175 ° C. to 300 ° C. is used. It is more preferable to apply a die pressing process.

  Here, the fourth temperature is “higher than the first temperature and within the range of 175 ° C. to 300 ° C.” when the fourth temperature is lower than the first temperature, the heat capacity of the mold However, the temperature of the precursor composition layer tends to be low at the contact surface between the precursor composition layer and the mold, and when the fourth temperature is less than 175 ° C., the precursor composition layer and the mold This is also because the temperature of the precursor composition layer tends to be low at the contact surface with the precursor composition, and when the fourth temperature exceeds 300 ° C., the precursor composition layer at the contact surface between the precursor composition layer and the mold is used. This is because the solidification reaction of the layer proceeds too much and the precursor composition layer becomes too hard, so that the plastic deformation ability of the precursor composition layer decreases again. From the above viewpoint, the fourth temperature is more preferably “higher than the first temperature and in the range of 200 ° C. to 300 ° C.”.

[3] In the method for manufacturing a ferroelectric material layer according to the present invention, it is preferable that the fourth step is embossed with a pressure within a range of 1 MPa to 20 MPa.

  According to the method for manufacturing a ferroelectric material layer of the present invention, as described above, the precursor composition layer is sufficiently softened (the plastic deformation capacity of the precursor composition layer is sufficiently increased). Since the stamping process is performed on the precursor composition layer, even if the pressure applied when the stamping process is performed is reduced to 1 MPa to 20 MPa, a desired electrical property improving effect (residual polarization is increased) Effect and / or effect of reducing leakage current).

  Here, the reason why the pressure is within the range of “1 MPa to 20 MPa” is that when the pressure is less than 1 MPa, the pressure is too low to sufficiently emboss the precursor composition. This is because the desired electrical property improving effect may not be obtained, and if the pressure is 20 MPa, the precursor composition can be sufficiently embossed. It is because it is not necessary to apply.

  Speaking from the above viewpoint, in the fourth step, it is more preferable to perform the embossing with a pressure in the range of 2 MPa to 10 MPa.

[4] A thin film transistor of the present invention includes a source electrode and a drain electrode, a channel layer positioned between the source electrode and the drain electrode, a gate electrode for controlling a conduction state of the channel layer, and the gate electrode A thin film transistor comprising a gate insulating layer made of a ferroelectric material formed between the channel region, wherein the gate insulating layer is formed using the method for manufacturing a ferroelectric material layer of the present invention It is characterized by being.

  According to the thin film transistor of the present invention, a gate insulating layer having “excellent electrical characteristics (for example, high remanent polarization characteristics, low leakage current characteristics, etc.)” formed by using the method for manufacturing a ferroelectric material layer of the present invention. Therefore, the thin film transistor is superior to the conventional thin film transistor.

[5] The thin film transistor of the present invention includes an oxide conductor layer including a source region, a drain region, and a channel region, a gate electrode for controlling a conduction state of the channel region, and between the gate electrode and the channel region. And a gate insulating layer made of a ferroelectric material, wherein the channel region is thinner than the source region and the drain region, and the gate insulating layer comprises: It is formed using the manufacturing method of the ferroelectric material layer of this invention.

  According to the thin film transistor of the present invention, a gate insulating layer having “excellent electrical characteristics (for example, high remanent polarization characteristics, low leakage current characteristics, etc.)” formed by using the method for manufacturing a ferroelectric material layer of the present invention. Therefore, the thin film transistor is superior to the conventional thin film transistor.

  In addition, according to the thin film transistor of the present invention, an oxide conductive material is used as a material constituting the channel region, so that the carrier concentration can be increased, and a ferroelectric material as a material constituting the gate insulating layer As a result, it is possible to perform high-speed switching with a low drive voltage, and as a result, as with conventional thin film transistors, it is possible to control a large current at high speed with a low drive voltage.

[6] In the thin film transistor of the present invention, the oxide conductor layer in which the channel region is thinner than the source region and the drain region is formed using an embossing technique. It is preferable that

  With such a configuration, a thin film transistor can be manufactured by simply forming an oxide conductor layer in which the layer thickness of the channel region is thinner than the layer thickness of the source region and the drain region. Unlike the conventional thin film transistor, the channel region, the source region, and the drain region do not need to be formed from different materials, and the above-described excellent thin film transistor is used with significantly less raw materials and manufacturing energy than the conventional thin film transistor. And it becomes possible to manufacture in a shorter process than before.

  In the thin film transistor of the present invention, it is preferable that the oxide conductor layer, the gate electrode, and the gate insulating layer are all formed using a liquid material.

  By adopting such a configuration, as will be understood from the embodiments described later, it becomes possible to manufacture a thin film transistor using an embossing technique, so that an excellent thin film transistor as described above can be obtained. It is possible to manufacture using a significantly smaller amount of raw materials and manufacturing energy and in a shorter process than before.

  In the thin film transistor of the present invention, it is preferable that the oxide conductor layer, the gate electrode, and the gate insulating layer are all formed without using a vacuum process.

  By adopting such a configuration, it becomes possible to manufacture a thin film transistor without using a vacuum process, so that an excellent thin film transistor as described above is used with much less production energy than the conventional one, and It becomes possible to manufacture in a shorter process than before.

  In the thin film transistor of the present invention, it is preferable that the oxide conductor layer, the gate electrode, and the gate insulating layer are all made of an oxide material.

  With such a structure, the oxide conductor layer, the gate electrode, and the gate insulating layer can all be formed using a liquid material. In addition, a highly reliable thin film transistor can be obtained.

  In the thin film transistor of the present invention, it is preferable that all of the oxide conductor layer, the gate electrode, and the gate insulating layer have a perovskite structure.

  With such a structure, the gate electrode and the gate insulating layer have the same crystal structure, whereby a high-quality thin film transistor with few lattice defects can be manufactured.

[7] In the thin film transistor of the present invention, it is preferable that the carrier concentration and the layer thickness of the channel region are set to such values that the entire channel region is depleted when the thin film transistor is in an off state.

With such a structure, even when the carrier concentration of the oxide conductor layer is increased, the amount of current that flows when the thin film transistor is in an off state can be sufficiently reduced, so that a large current is reduced while maintaining a required on / off ratio. It is possible to control with the driving voltage.
In this case, if the thin film transistor is an enhancement type transistor, the thin film transistor is turned off when a control voltage of 0 V is applied to the gate electrode. Therefore, in this case, the entire channel region is depleted. If the thin film transistor is a depletion type transistor, the thin film transistor is turned off when a negative control voltage is applied to the gate electrode. It only needs to be set to a value that depletes.

[8] In the thin film transistor of the present invention, the channel region has a carrier concentration in the range of 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ , and the channel region has a layer thickness of 5 nm to 100 nm. It is preferable to be within the range.

  With such a configuration, it is possible to control a large current with a low driving voltage while maintaining a necessary on / off ratio.

  In the thin film transistor of the present invention, the source region and the drain region preferably have a layer thickness in the range of 50 nm to 1000 nm.

[9] The piezoelectric inkjet head of the present invention is attached to the cavity member, one side of the cavity member, a piezoelectric plate on which the piezoelectric layer is formed, the other side of the cavity member, and a nozzle hole A piezoelectric ink jet head comprising a formed nozzle plate and an ink chamber defined by the cavity member, the vibration plate and the nozzle plate, wherein the piezoelectric layer is a ferroelectric material layer of the present invention It is formed using the manufacturing method of this.

  According to the piezoelectric ink jet head of the present invention, it is provided with “excellent electrical characteristics (for example, high remanent polarization characteristics, low leakage current characteristics, etc.) formed by using the manufacturing method of the ferroelectric material layer of the present invention. Since the piezoelectric layer is provided, the piezoelectric inkjet head is superior to the conventional piezoelectric inkjet head.

  In the piezoelectric inkjet head of the present invention, it is preferable that both the cavity member and the piezoelectric layer are formed using a liquid material.

  By adopting such a configuration, it becomes possible to manufacture a piezoelectric ink jet head using an embossing processing technique. And it becomes possible to manufacture using manufacturing energy.

  In the piezoelectric inkjet head of the present invention, it is preferable that both the cavity member and the piezoelectric layer are formed without using a vacuum process.

  With such a configuration, it becomes possible to manufacture a piezoelectric ink jet head without using a vacuum process. Therefore, the excellent piezoelectric ink jet head as described above can be manufactured with significantly less production energy than conventional ones. And can be manufactured in a shorter process than before.

FIG. 3 is a view for explaining a method for manufacturing the capacitor 12 according to the first embodiment. The figure shown in order to demonstrate the embossing processing apparatus 700. FIG. The figure shown in order to demonstrate the uneven | corrugated type | mold M1. The figure which shows a mode that the electrical property of the capacitor 12 which concerns on Embodiment 1 and the capacitor 14 which concerns on a comparative example is measured. The figure which shows the electrical property (residual polarization characteristic) of the capacitor 12 which concerns on Embodiment 1, and the capacitor 14 which concerns on a comparative example. The figure which shows the electrical characteristic (fatigue characteristic of remanent polarization) of the capacitor 12 which concerns on Embodiment 1, and the capacitor 14 which concerns on a comparative example. FIG. 3 is a diagram illustrating electrical characteristics (leakage current characteristics) of the capacitor 12 according to the first embodiment and the capacitor 14 according to the comparative example. FIG. 3 is a diagram illustrating surface states of a ferroelectric material layer 32 according to the first embodiment and a ferroelectric material layer 34 according to a comparative example. FIG. 3 is a diagram showing X-ray diffraction results of a ferroelectric material layer 32 according to Embodiment 1 and a ferroelectric material layer 34 according to a comparative example. FIG. 3 is a view for explaining a difference in leakage current between the ferroelectric material layer according to the first embodiment and the ferroelectric material layer according to the comparative example. The table | surface which shows the relationship between remanent polarization, 1st temperature, and 2nd temperature. The table | surface which shows the relationship between leakage current, 1st temperature, and 2nd temperature. It is a figure shown in order to demonstrate the plastic deformation capability of a precursor composition layer. FIG. 5 is a view for explaining a thin film transistor 100 according to Embodiment 2. FIG. 6 shows a method for manufacturing a thin film transistor according to the second embodiment. FIG. 6 shows a method for manufacturing a thin film transistor according to the second embodiment. FIG. 6 shows a method for manufacturing a thin film transistor according to the second embodiment. FIG. 9 is a diagram for explaining a thin film transistor 200 according to Embodiment 3. FIG. 5 shows a method for manufacturing a thin film transistor according to the third embodiment. FIG. 5 shows a method for manufacturing a thin film transistor according to the third embodiment. FIG. 6 is a view for explaining a piezoelectric inkjet head 300 according to a fourth embodiment. FIG. 5 is a view for explaining a method for manufacturing a piezoelectric inkjet head according to a fourth embodiment. FIG. 5 is a view for explaining a method for manufacturing a piezoelectric inkjet head according to a fourth embodiment. FIG. 5 is a view for explaining a method for manufacturing a piezoelectric inkjet head according to a fourth embodiment. FIG. 10 is a diagram illustrating a conventional thin film transistor 900. The figure shown in order to demonstrate the manufacturing method of the conventional thin-film transistor. FIG. 10 is a diagram shown for explaining electrical characteristics of a conventional thin film transistor 900.

  Hereinafter, a manufacturing method of a ferroelectric material layer and a thin film transistor of the present invention will be described based on embodiments shown in the drawings.

[Embodiment 1]
In the first embodiment, a method for manufacturing a ferroelectric material layer according to the present invention will be described using a capacitor having a ferroelectric material layer as an insulating layer.

FIG. 1 is a view for explaining the method for manufacturing the capacitor 12 according to the first embodiment. Fig.1 (a)-FIG.1 (h) are each process drawing.
FIG. 2 is a view shown for explaining the die-molding apparatus 700. In FIG. 2, reference numeral 710 is a lower mold, reference numeral 712 is a heat insulating plate, reference numeral 714 is a heater, reference numeral 716 is a placement section, reference numeral 718 is a suction section, reference numeral 720 is an upper mold, reference numeral 722 is a heater, reference numeral 724 is The fixed part, symbol M1, indicates an uneven shape.
FIG. 3 is a diagram for explaining the concave-convex mold M1. 3A is a plan view of the concavo-convex mold M1, and FIG. 3B is a cross-sectional view of the concavo-convex mold M1.

  As shown in FIG. 1, an embodiment is performed by performing the following “base material preparation step”, “ferroelectric material layer formation step”, “upper electrode formation step”, and “lower electrode exposure step” in this order. 1 was manufactured.

(1) Base material preparation step A base in which a lower electrode 24 made of “Ti (10 nm) and Pt (40 nm) laminated film” is formed on an insulating substrate 22 made of an Si substrate having a SiO ₂ layer formed on the surface. A material 20 is prepared (see FIG. 1A). The planar size of the substrate is 20 mm × 20 mm.

(2) Ferroelectric material layer forming step Prepare a PZT sol-gel solution that becomes a ferroelectric material layer (PZT layer) by heat treatment (8 wt% metal alkoxide type manufactured by Mitsubishi Materials Corporation) ( First step).

  Next, “the functional liquid material described above is applied onto the lower electrode 24 of the substrate 20 by using a spin coating method (for example, 2500 rpm · 25 seconds), and then the substrate 20 is placed on a hot plate 150. By repeating the operation of “drying at 5 ° C. for 5 minutes” three times, the precursor composition layer 30a (layer thickness 300 nm) of the ferroelectric material (PZT) is formed (second step to third step, FIG. 1B). )reference.).

  Next, an embossing process is performed on the precursor composition layer 30a by using an uneven mold M1 (difference in height of 500 μm) formed so that the center part is convex (fourth step, FIG. 1C to FIG. 1C). (See FIG. 1 (e)). For the embossing process, an embossing machine 700 (manufactured by Toshiba Machine, embossing machine ST50) shown in FIG. 2 is used. Further, as the concavo-convex mold M1, the concavo-convex mold M1 shown in FIG. 3 is used. In addition, as shown in FIG. 3, the uneven | corrugated type | mold M1 has a 10 mm x 10 mm convex part (height 500 micrometers) in the square-shaped center part of 20 mm x 20 mm. The pressure when embossing is set to a maximum of 5 MPa. Thereby, the precursor composition layer 30b in which only the 10 mm × 10 mm region at the center is embossed is formed. At this time, in the above step, the precursor composition layer 30a is heated to 225 ° C. and subjected to a pressing process using the concavo-convex mold M1 heated to 225 ° C.

  Finally, the precursor composition layer 30b is placed on a hot plate having a surface temperature of 400 ° C. for 10 minutes, and is then heat-treated at a high temperature (650 ° C., 30 minutes) using an RTA apparatus, whereby a ferroelectric material is obtained. The layer (PZT layer) 30 is completed (see the fifth step, FIG. 1 (f)). Hereinafter, the portion of the ferroelectric material layer that has been embossed is referred to as the ferroelectric material layer 32 according to the first embodiment, and the portion of the ferroelectric material layer that has not been embossed is used as a comparative example. Such a ferroelectric material layer 34 will be referred to.

(3) Upper Electrode Formation Step An upper electrode made of gold is formed on each of the central portion (ferroelectric material layer 32) and the peripheral portion 34 (ferroelectric material layer 34) of the ferroelectric material layer (PZT layer) 30. Each having a diameter of 400 μm).

(4) Lower electrode exposure step A part of the peripheral portion (ferroelectric material layer 34) of the ferroelectric material layer (PZT layer) 30 is removed using 1% hydrofluoric acid to expose the lower electrode 24.

  Through the steps described above, the capacitor 12 according to the first embodiment and the capacitor 14 according to the comparative example are completed (see FIG. 4A described later). At this time, the thickness of the ferroelectric material layer 32 according to the first embodiment (the central portion of the ferroelectric material layer 30) is 170 nm, and the ferroelectric material layer 34 according to the comparative example (the ferroelectric material layer 30). The thickness of the peripheral part) was 180 nm.

2. Measurement of Electrical Characteristics FIG. 4 is a diagram illustrating how electrical characteristics of the capacitor 12 according to the first embodiment and the capacitor 14 according to the comparative example are measured. FIG. 4A is a diagram illustrating a state of measuring the electrical characteristics of the capacitor 12 according to the first embodiment, and FIG. 4B is a diagram illustrating a state of measuring the electrical characteristics of the capacitor 14 according to the comparative example. .
FIG. 5 is a diagram illustrating electrical characteristics (residual polarization characteristics) of the capacitor 12 according to the first embodiment and the capacitor 14 according to the comparative example. FIG. 6 is a diagram illustrating the electrical characteristics (fatigue characteristics of remanent polarization) of the capacitor 14 according to the comparative example of the capacitor 12 according to the first embodiment. FIG. 7 is a diagram illustrating electrical characteristics (leakage current characteristics) of the capacitor 12 according to the first embodiment and the capacitor 14 according to the comparative example.

  As shown in FIG. 4, the electrical characteristics were measured using the capacitor 12 according to the first embodiment and the capacitor 14 according to the comparative example. The residual polarization characteristics and the fatigue characteristics of the residual polarization were performed by a ferroelectric characteristic evaluation system (manufactured by Toyo Corporation, FCE). The leak characteristics were measured by a semiconductor parameter analyzer (Agilent Technology Co., Ltd., 4155C). The fatigue characteristics of remanent polarization were measured under conditions of 500 MHz and ± 8V.

As a result, as can be seen from FIG. 5, the remanent polarization of the capacitor 14 according to the comparative example is 36 μC / cm ² , whereas the remanent polarization of the capacitor 12 according to the first embodiment is 48 μC / cm ^2. It was found that the ferroelectric material layer 32 according to Mode 1 had better remanent polarization characteristics.

Moreover, as can be seen from FIG. 6, the number of cycles the residual polarization of 80% of the value of the initial capacitor 14 according to the comparative example, a positive 4 × 10 ⁷ cycles when, 4 × 10 ⁷ cycles when the negative On the other hand, the number of cycles in which the residual polarization of the capacitor 12 according to the first embodiment is 80% of the initial value is 4 × 10 ⁸ cycles when positive, and 2 × 10 ⁹ cycles or more when negative. It has been found that the ferroelectric material layer 32 according to the first embodiment has excellent residual polarization fatigue characteristics.

  Further, as shown in FIG. 7, the leakage current of the capacitor 12 according to the first embodiment is 0.5 to 3 digits lower than the leakage current of the capacitor 14 according to the comparative example. It was found that the body material layer 32 has excellent low leakage current characteristics. In the capacitor 12 according to the first embodiment, since the dielectric breakdown phenomenon (about 17V) observed in the capacitor 14 according to the comparative example is not observed in the range of 0V to 20V, the ferroelectric according to the first embodiment. It was also found that the material layer 32 has better insulating properties.

  For the capacitor 12 according to the first embodiment and the capacitor 14 according to the comparative example, a plurality of samples are prepared under the same conditions, and the measurement of the remanent polarization characteristic in FIG. 5 and the remanent polarization fatigue characteristic in FIG. The measurement was performed using another sample. Therefore, the absolute values of the remanent polarization characteristics are slightly different.

3. Observation of Surface State of Ferroelectric Material Layer FIG. 8 is a diagram showing surface states of the ferroelectric material layer 32 according to the first embodiment and the ferroelectric material layer 34 according to the comparative example. FIG. 8A is a view showing the surface state of the ferroelectric material layer 32 according to the first embodiment, and FIG. 8B is a view showing the surface state of the ferroelectric material layer 34 according to the comparative example. .

  The observation of the surface state was performed with a scanning probe microscope (S-image manufactured by SII Nano Technology Co., Ltd.). As a result, as can be seen from FIG. 8, the size of the crystal grains in the ferroelectric material layer 32 according to the first embodiment is 50 nm to 400 nm, and the crystal grain size in the ferroelectric material layer 34 according to the comparative example. Is 30 nm to 200 nm, and it has been found that the crystal grains are larger in the ferroelectric material layer 32 according to the first embodiment.

4). Evaluation of Crystallinity by X-Ray Diffraction FIG. 9 is a diagram showing X-ray diffraction results of the ferroelectric material layer 32 according to the first embodiment and the ferroelectric material layer 34 according to the comparative example. In FIG. 9, the solid line indicates the X-ray diffraction result in the ferroelectric material layer 32 according to the first embodiment, and the broken line indicates the X-ray diffraction result in the ferroelectric material layer 34 according to the comparative example.

  The evaluation of crystallinity by X-ray diffraction was performed using an X-ray diffractometer (M18XHF, manufactured by Mac Science). As a result, when compared with the peak of PZT (111) (2θ = 39 °), the ferroelectric material layer 32 according to the first embodiment has a peak intensity of 1 compared with the ferroelectric material layer 34 according to the comparative example. It was found that the ferroelectric material layer 32 according to the first embodiment has higher crystallinity.

5. Discussion FIG. 10 is a diagram for explaining a difference in leakage current between the ferroelectric material layer 32 according to the first embodiment and the ferroelectric material layer 34 according to the comparative example.
As can be seen from “3. Observation of surface state of ferroelectric material layer” and “4. Evaluation of crystallinity by X-ray diffraction”, the ferroelectric material layer 32 according to the first embodiment is a comparative example. Since the crystal grain is larger than that of the ferroelectric material layer 34, there are few crystal grain boundaries, and furthermore, since it has high crystallinity, there are fewer leak paths than the ferroelectric material layer 34 according to the comparative example, and the leakage current It is presumed that the level of has decreased (see FIG. 10).

[Examples 1 and 2]
Example 1 is an example for clarifying what temperature range should be set between the first temperature and the second temperature from the viewpoint of increasing the remanent polarization. Example 2 is an example for clarifying what temperature range should be set between the first temperature and the second temperature from the viewpoint of reducing the leakage current. In Examples 1 and 2, the capacitor was produced by the same method as in the case of the capacitor manufacturing method according to Embodiment 1 under the conditions in which the first temperature and the second temperature were changed to various temperatures. Residual polarization and leakage current of the capacitor (ferroelectric material layer) were measured.

  FIG. 11 is a table showing the relationship between the remanent polarization, the first temperature, and the second temperature. In FIG. 11, “the residual polarization of the ferroelectric material layer manufactured from the precursor composition layer subjected to the stamping process” is “a ferroelectric material manufactured from the precursor composition layer not subjected to the stamping process”. When “larger than the residual polarization of the layer” is marked with “○”, “the residual polarization of the ferroelectric material layer manufactured from the precursor composition layer subjected to the stamping process” and “no stamping process” When the remanent polarization of the ferroelectric material layer manufactured from the precursor composition layer is almost the same size, “△” is given, and “manufactured from the precursor composition layer that has been embossed. When the “remanent polarization of the ferroelectric material layer” is smaller than the “residual polarization of the ferroelectric material layer manufactured from the precursor composition layer not subjected to the stamping process”, “x” is given. If no experiment was performed, the column was left blank.

  As a result, in Example 1, as can be seen from FIG. 11, the first temperature is in the range of 120 ° C. to 250 ° C., the second temperature is higher than the first temperature, and 150 ° C. to 300 ° C. It was found that the residual polarization of the ferroelectric material layer can be increased by setting the temperature within the range of ° C (more preferably 200 ° C to 300 ° C).

  FIG. 12 is a table showing the relationship between the first temperature and the second temperature in the leakage current. In FIG. 12, “a leak current of a ferroelectric material layer manufactured from a precursor composition layer subjected to a stamping process” is “a ferroelectric material manufactured from a precursor composition layer not subjected to a stamping process”. “○” when lower than the “layer leakage current”, and “the leakage current of the ferroelectric material layer manufactured from the precursor composition layer that has been embossed” and “not embossed” When the leakage current of the ferroelectric material layer manufactured from the precursor composition layer is substantially the same size, “△” is given, and “manufactured from the precursor composition layer that has been embossed. When the “leakage current of the ferroelectric material layer” is smaller than the “leakage current of the ferroelectric material layer manufactured from the precursor composition layer not subjected to the stamping process”, an “x” is given. If no experiment was performed, the column was left blank.

  As a result, in Example 2, as can be seen from FIG. 12, the first temperature is in the range of 120 ° C. to 200 ° C., the second temperature is higher than the first temperature, and 175 ° C. to 300 ° C. It was found that the leakage current of the ferroelectric material layer can be reduced by setting the temperature within the range of ° C (more preferably 200 ° C to 300 ° C).

FIG. 13 is a figure shown in order to demonstrate the plastic deformation capability of a precursor composition layer.
As can be understood from FIG. 13, when the precursor composition layer of the ferroelectric material layer is formed by applying the PZT sol-gel solution on the base material, at the initial time point when the precursor composition layer is formed. The precursor composition layer is too soft and the plastic deformation ability is low, and good stamping cannot be carried out (see reference S1). On the other hand, when the precursor composition layer is heated and dried, the solidification reaction of the precursor composition layer proceeds to some extent and the main solvent is removed, so the precursor composition layer Thus, the fluidity of the precursor composition layer becomes low, and the precursor composition layer has just the right hardness (see S2). However, when this precursor composition layer is embossed at room temperature, when the precursor composition layer is returned to room temperature, the precursor composition layer becomes too hard and the plastic deformation ability is reduced again (reference S3). reference.). Therefore, the precursor composition layer in which the solidification reaction has progressed to some extent is again heated to the second temperature in the above-described temperature range. Thereby, by sufficiently softening the precursor composition layer, the plastic deformation ability of the precursor composition layer can be increased again, and good stamping can be performed (see reference S4). At this time, as can be seen from FIG. 13, if the second temperature is too low (see reference A1) or the second temperature is too high (see reference A3), good stamping is performed. On the other hand, when the second temperature is within the above-described temperature range (see reference A2), it is possible to perform good stamping and to improve the desired electrical characteristics (for example, high residual Polarization characteristics and low leakage current characteristics).

  Thereafter, with reference to the above results, the precursor composition layer was actually embossed at various pressures at various pressures in the range of room temperature to 400 ° C. When the precursor composition layer is heated within the above-mentioned temperature range, it becomes possible to form a predetermined embossed structure in the precursor composition layer at a relatively low pressure of 1 MPa to 20 MP, thereby improving electrical characteristics. It was confirmed that an effect was obtained.

[Embodiment 2]
1. Thin film transistor 100 according to Embodiment 2
FIG. 14 is a diagram for explaining the thin film transistor 100 according to the second embodiment. 14A is a plan view of the thin film transistor 100, FIG. 14B is a cross-sectional view along A1-A1 in FIG. 14A, and FIG. 14C is a cross-sectional view along A2-A2 in FIG. FIG.

  As shown in FIGS. 14A and 14B, the thin film transistor 100 according to Embodiment 2 includes an oxide conductor layer 140 including a source region 144, a drain region 146, and a channel region 142; A gate electrode 120 for controlling a conduction state, and a gate insulating layer 130 formed between the gate electrode 120 and the channel region 142 and made of a ferroelectric material are provided. The channel region 142 is thinner than the source region 144 and the drain region 146. The layer thickness of the channel region 142 is preferably not more than ½ of the layer thickness of the source region 144 and the drain region 146. As shown in FIGS. 14A and 14C, the gate electrode 120 is connected to the gate pad 122 exposed to the outside through the through hole 150.

  In the thin film transistor 100 according to the second embodiment, the gate insulating layer 130 is formed by using the method for manufacturing a ferroelectric material layer of the present invention.

  In the thin film transistor 100 according to Embodiment 2, the oxide conductor layer 140 in which the channel region 142 is thinner than the source region 144 and the drain region 146 is formed using an embossing technique. It is a thing.

  In the thin film transistor 100 according to Embodiment 2, the oxide conductor layer 140, the gate electrode 120, and the gate insulating layer 130 are all formed using a liquid material.

  In the thin film transistor 100 according to Embodiment 2, the oxide conductor layer 140, the gate electrode 120, and the gate insulating layer 130 are all formed without using a vacuum process.

  In the thin film transistor 100 according to Embodiment 2, the oxide conductor layer 140, the gate electrode 120, and the gate insulating layer 130 are all made of an oxide material.

  In the thin film transistor 100 according to Embodiment 2, the oxide conductor layer 140, the gate electrode 120, and the gate insulating layer 130 all have a perovskite structure.

In the thin film transistor 100 according to the second embodiment, the carrier concentration and the layer thickness of the channel region 142 are set to values such that the channel region 142 is depleted when an off control voltage is applied to the gate electrode 120. . Specifically, the carrier concentration of the channel region 142 is in the range of 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ , and the layer thickness of the channel region 142 is in the range of 5 nm to 100 nm. .

  In the thin film transistor 100 according to the second embodiment, the layer thicknesses of the source region 144 and the drain region 146 are in the range of 50 nm to 1000 nm.

The oxide conductor layer 140 is made of, for example, indium tin oxide (ITO), the gate insulating layer 130 is made of, for example, PZT (Pb (Zr _x , Ti _1-x ) O ₃ ), and the gate electrode 120 is made of, for example, An insulating substrate 110 made of nickel lanthanum oxide (LNO (LaNiO ₃ )), which is a solid substrate, for example, is an insulating substrate in which an STO (SrTiO) layer is formed on the surface of a Si substrate via a SiO ₂ layer and a Ti layer. Become.

2. Method for Manufacturing Thin Film Transistor According to Embodiment 2 A thin film transistor 100 according to Embodiment 2 can be manufactured by a method for manufacturing a thin film transistor described below (a method for manufacturing a thin film transistor according to Embodiment 1). Hereinafter, it demonstrates in order of a process.

  15 to 17 are views for explaining the method of manufacturing the thin film transistor according to the second embodiment. FIGS. 15A to 15E, FIGS. 16A to 16E, and FIGS. 17A to 17E are process diagrams. In each process drawing, the figure shown on the left side is a figure corresponding to FIG. 14B, and the figure shown on the right side is a figure corresponding to FIG. 14C.

(1) Formation of the gate electrode 120 First, the functional liquid material used as the functional solid material which consists of metal oxide ceramics (nickel lanthanum oxide) is prepared by heat-processing. Specifically, a solution (solvent: 2-methoxyethanol) containing a metal inorganic salt (lanthanum nitrate (hexahydrate) and nickel acetate (tetrahydrate)) is prepared.

  Next, as shown in FIGS. 15A and 15B, a functional liquid material is applied to one surface of the insulating substrate 110 using a spin coating method (for example, 500 rpm for 25 seconds). Thereafter, the insulator substrate 110 is placed on a hot plate and dried at 60 ° C. for 1 minute to form a precursor composition layer 120 ′ (layer thickness 300 nm) of a functional solid material (nickel lanthanum oxide).

  Next, as shown in FIG. 15C and FIG. 15D, using a concavo-convex mold M2 (height difference of 300 nm) formed so that regions corresponding to the gate electrode 120 and the gate pad 122 are concave. The precursor composition layer 120 ′ is embossed at 150 ° C. to form an embossed structure (a convex layer thickness of 300 nm and a concave layer thickness of 50 nm) on the precursor composition layer 120 ′. . The pressure at the time of embossing is 5 MPa. Thus, since the precursor composition layer that has obtained high plastic deformation ability by heating to a second temperature within a range of 120 ° C. to 200 ° C. is subjected to a stamping process, a desired stamping process is performed. The structure can be formed with high accuracy.

  Next, the precursor composition layer 120 'is entirely etched to completely remove the precursor composition layer from the region other than the region corresponding to the gate electrode 120 (entire surface etching step). The entire surface etching step is performed without using a vacuum process by using a wet etching technique.

  Finally, the precursor composition layer 120 ′ is heat-treated at a high temperature (650 ° C., 10 minutes) using an RTA apparatus, so that the precursor composition layer 120 ′ can function from the precursor composition layer 120 ′ as shown in FIG. A gate electrode 120 and a gate pad 122 made of a conductive solid material layer (nickel lanthanum oxide) are formed.

(2) Formation of the gate insulating layer 130 First, the functional liquid material used as the functional solid material which consists of metal oxide ceramics (PZT) is prepared by heat-processing. Specifically, a solution containing a metal alkoxide (PZT sol-gel solution, manufactured by Mitsubishi Materials Corporation) is prepared as a functional liquid material (first step).

  Next, “the above-described functional liquid material is applied to one surface of the insulating substrate 110 by using a spin coating method (for example, 2500 rpm · 25 seconds), and then the insulating substrate 110 is placed on a hot plate. By repeating the “operation of drying at 150 ° C. for 5 minutes” three times, the precursor composition layer 130 ′ (layer thickness 300 nm) of the functional solid material (PZT) is formed as shown in FIG. (2nd process-3rd process).

  Next, as shown in FIG. 16B and FIG. 16C, using a concavo-convex mold M3 (height difference of 300 nm) formed so that the region corresponding to the through hole 150 is convex at 225 ° C. A stamping structure corresponding to the through hole 150 is formed in the precursor composition layer 130 ′ by performing a stamping process on the precursor composition layer 130 ′ (fourth step). The pressure at the time of embossing is 5 MPa. As a result, the precursor composition layer that has obtained a high plastic deformation ability by heating to 150 ° C. is subjected to embossing at 225 ° C., so that the desired electrical property improvement effect (for example, high remanent polarization) Characteristics and low leakage current characteristics).

  Finally, the precursor composition layer 130 ′ is heat-treated at a high temperature (650 ° C., 10 minutes) using an RTA apparatus, thereby forming a functional solid material layer (PZT) as shown in FIG. A gate insulating layer 130 is formed (fifth step).

(3) Formation of oxide conductor layer 140 First, a functional liquid material to be a functional solid material made of metal oxide ceramics (ITO) is prepared by heat treatment. Specifically, as a functional liquid material, a solution containing a metal carboxylate (functional liquid material (trade name: ITO-05C) manufactured by Kojundo Chemical Laboratory Co., Ltd.), stock solution: diluted solution = 1: 1 Prepare 5). Note that an impurity having a concentration such that the carrier concentration of the channel region 142 is in the range of 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ when completed is added to the functional liquid material.

  Next, as shown in FIG. 16 (e), the functional liquid material described above is applied to one surface of the insulating substrate 110 using a spin coating method (for example, 2000 rpm · 25 seconds), and then The insulator substrate 110 is placed on a hot plate and dried at 150 ° C. for 3 minutes to form a precursor composition layer 140 ′ (layer thickness 300 nm) of a functional solid material (ITO).

  Next, as shown in FIGS. 17A to 17C, the region corresponding to the channel region 142 is formed to be more convex than the region corresponding to the source region 144 and the region corresponding to the drain region 146. The precursor composition layer 140 ′ is embossed by using a concavo-convex mold M4 (difference in height of 350 nm), so that the precursor composition layer 140 ′ has an embossed structure (a layer thickness of 350 nm of convex portions, A recess thickness of 100 nm) is formed. Thereby, the layer thickness of the part which becomes the channel region 142 in the precursor composition layer 140 ′ becomes thinner than the other part.

  At this time, in the above-described process, the precursor composition layer 140 ′ is heated to 150 ° C. and subjected to a die pressing process using a mold heated to 150 ° C. In this case, the pressure when embossing is about 4 MPa.

  Note that the concavo-convex mold M4 has a structure in which a region corresponding to the element isolation region 160 and the through hole 150 is more convex than a region corresponding to the channel region 142, and one surface of the insulating substrate 110 is By performing wet etching on the entire surface, the precursor composition layer 140 ′ can be completely removed from the region corresponding to the element isolation region 160 and the through hole 150 while the portion to be the channel region 142 has a predetermined thickness. (See FIG. 17 (d)). The concavo-convex mold M4 may have a shape in which a region corresponding to the element isolation region is tapered.

  Finally, the precursor composition layer 140 ′ is subjected to a heat treatment (precursor composition layer 140 ′ is baked on a hot plate at 400 ° C. for 10 minutes, and then 650 ° C./30 using an RTA apparatus. The precursor composition layer 140 ′ is heated under the conditions of a minute (first 15 minutes oxygen atmosphere, second half 15 minutes nitrogen atmosphere)), whereby an oxide conductor layer including a source region 144, a drain region 146, and a channel region 142 is obtained. The thin film transistor 100 according to the second embodiment having the bottom gate structure as shown in FIG.

3. Effect of Thin Film Transistor 100 According to Embodiment 2 According to the thin film transistor 100 according to Embodiment 2, the precursor composition layer is dried at a first temperature in the range of 120 ° C. to 300 ° C., and the precursor composition layer is “Excellent electricity” formed by embossing the precursor composition layer in a state heated to a second temperature that is higher than the first temperature and within a range of 150 ° C. to 300 ° C. Since the gate insulating layer having characteristics (for example, high remanent polarization characteristics, low leakage current characteristics, etc.) is provided, the thin film transistor is superior to conventional thin film transistors.

  In addition, according to the thin film transistor 100 according to the second embodiment, it is possible to manufacture a thin film transistor only by forming an oxide conductor layer in which the channel region has a thinner layer thickness than the source region and the drain region. Therefore, unlike the conventional thin film transistor, the channel region, the source region, and the drain region do not have to be formed from different materials, and the excellent thin film transistor 900 as described above is obtained by using much less raw materials than the conventional one. And it becomes possible to manufacture using a manufacturing energy and a shorter process than before.

  Further, according to the thin film transistor 100 according to the second embodiment, an oxide conductive material is used as a material for forming the channel region 142, so that the carrier concentration can be increased, and a material for forming the gate insulating layer 130 is used. As a result, it is possible to perform high-speed switching with a low driving voltage, and as a result, as with the conventional thin film transistor 900, it is possible to control a large current at high speed with a low driving voltage. Become.

  In addition, according to the thin film transistor 100 according to the second embodiment, the thin film transistor is manufactured only by forming the oxide conductor layer 140 in which the channel region 142 is thinner than the source region 144 and the drain region 146. Therefore, unlike the conventional thin film transistor 900, the channel region, the source region, and the drain region do not have to be formed from different materials, and an excellent thin film transistor as described above can be obtained. It is possible to manufacture using a significantly smaller amount of raw materials and manufacturing energy and in a shorter process than before.

  In addition, according to the thin film transistor 100 according to the second embodiment, since the oxide conductor layer, the gate electrode, and the gate insulating layer are all formed using a functional liquid material, the embossing technique is used. Thus, a thin film transistor can be manufactured, and an excellent thin film transistor as described above can be manufactured using much less raw materials and manufacturing energy than in the past, and in a shorter process than in the past.

  In addition, according to the thin film transistor 100 according to the second embodiment, the oxide conductor layer, the gate electrode, and the gate insulating layer are all formed without using a vacuum process, and thus the thin film transistor without using a vacuum process. As described above, it is possible to manufacture a thin film transistor that is excellent as described above, using much less manufacturing energy than in the past, and in a shorter process than in the past.

  Further, according to the thin film transistor 100 according to the second embodiment, since the gate electrode and the gate insulating layer both have a perovskite structure, lattice defects are reduced at the interface between the gate electrode and the gate insulating layer, and a high quality thin film transistor is manufactured. Is possible.

  In the thin film transistor 100 according to the second embodiment, the carrier concentration and the layer thickness of the channel region 142 are set to values that cause the channel region 142 to be depleted when an off control voltage is applied to the gate electrode 120. Therefore, even when the carrier concentration of the oxide conductor layer is increased, the amount of current flowing at the time of off can be sufficiently reduced, and a large current can be controlled with a low driving voltage while maintaining a required on / off ratio. . In this case, if the thin film transistor is an enhancement type transistor, the thin film transistor is turned off when a control voltage of 0 V is applied to the gate electrode. Therefore, in this case, the entire channel region is depleted. If the thin film transistor is a depletion type transistor, the thin film transistor is turned off when a negative control voltage is applied to the gate electrode. It only needs to be set to a value that depletes.

Further, according to the thin film transistor 100 according to the second embodiment, the carrier concentration of the channel region 142 is in the range of 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ , and the layer thickness of the channel region 142 is Since it exists in the range of 5 nm-100 nm, it becomes possible to control a big electric current with a low drive voltage, maintaining a required on-off ratio.

[Embodiment 3]
1. Thin film transistor 200 according to Embodiment 3
FIG. 18 is a diagram for explaining the thin film transistor 200 according to the third embodiment. 18A is a plan view of the thin film transistor 200, FIG. 18B is a cross-sectional view taken along line A1-A1 in FIG. 18A, and FIG. 18C is a cross-sectional view taken along line A2-A2 in FIG. FIG.

  The thin film transistor 200 according to the third embodiment basically has the same configuration as the thin film transistor 100 according to the second embodiment, but differs from the thin film transistor 100 according to the second embodiment in that it has a top gate structure. That is, the thin film transistor 200 according to the third embodiment has a structure in which an oxide conductor layer 240, a gate insulating layer 230, and a gate electrode 220 are formed in this order above an insulating substrate 210, as shown in FIG. Have The source region 244 and the drain region 246 are exposed to the outside through the through holes 250 as shown in FIGS. 18A and 18B, respectively.

  As described above, the thin film transistor 200 according to the third embodiment is different from the thin film transistor 100 according to the second embodiment in having a top gate structure, but the precursor composition layer is in a range of 120 ° C. to 300 ° C. While drying at 1 temperature, the precursor composition layer is embossed against the precursor composition layer in a state where the precursor composition layer is heated to a second temperature higher than the first temperature and within a range of 150 ° C to 300 ° C. Since the gate insulating layer having “excellent electrical characteristics (for example, high remanent polarization characteristics, low leakage current characteristics, etc.)” formed by processing is provided, similarly to the thin film transistor 100 according to the second embodiment. Thus, the thin film transistor is superior to the conventional thin film transistor.

  Note that the thin film transistor 200 according to Embodiment 3 can be manufactured by the following thin film transistor manufacturing method. Hereinafter, it demonstrates in order of a process.

  19 and 20 are views for explaining the method of manufacturing the thin film transistor according to the third embodiment. FIG. 19A to FIG. 19F and FIG. 20A to FIG. 20E are process diagrams.

(1) Formation of oxide conductor layer 240 First, a functional liquid material to be a functional solid material made of metal oxide ceramics (ITO) is prepared by heat treatment. Specifically, a solution containing a metal carboxylate (functional liquid material (trade name: ITO-05C) manufactured by Kojundo Chemical Laboratory Co., Ltd.) is prepared as the functional liquid material. Note that the functional liquid material is doped with an impurity having a concentration such that the carrier concentration of the channel region 242 is in the range of 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ when completed.

  Next, as shown in FIG. 19A, the above-described functional liquid material is applied onto one surface of the insulating substrate 210 by using a spin coating method, and then the insulating substrate 210 is placed on a hot plate. The precursor composition layer 240 ′ (layer thickness 300 nm) of the functional solid material (ITO) is formed by drying at 150 ° C. for 3 minutes.

  Next, as shown in FIGS. 19B and 19C, the region corresponding to the channel region 242 is formed to be more convex than the region corresponding to the source region 244 and the region corresponding to the drain region 246. Using the uneven | corrugated type | mold M5 (height difference 350nm), by performing a stamping process with respect to precursor composition layer 240 ', the stamping structure (layer thickness of a convex part 350nm is given to precursor composition layer 240' , The layer thickness of the recesses is 100 nm). Thereby, the layer thickness of the part which becomes the channel region 242 in the precursor composition layer 240 ′ becomes thinner than the other part.

  At this time, in the above step, the stamping process is performed using a mold heated to 150 ° C. in a state where the precursor composition layer 240 ′ is heated to 150 ° C. In this case, the pressure when embossing is about 4 MPa.

  Note that the concavo-convex mold M5 has a structure in which the region corresponding to the element isolation region and the region corresponding to the gate pad 222 are more convex than the region corresponding to the channel region 242. By performing wet etching on the entire surface of one surface, the precursor composition layer 240 ′ is completely removed from the region corresponding to the element isolation region 260 and the gate pad 222 while the portion to be the channel region 242 has a predetermined thickness. Can be removed. The concavo-convex mold M5 may have a shape in which a region corresponding to the element isolation region is tapered.

  Finally, the precursor composition layer 240 ′ is subjected to heat treatment to form an oxide conductor layer 240 including a source region 244, a drain region 246, and a channel region 242 as shown in FIG.

(2) Formation of the gate insulating layer 230 First, the functional liquid material used as the functional solid material which consists of metal oxide ceramics (PZT) is prepared by heat-processing (1st process). Specifically, a solution containing a metal alkoxide (PZT sol-gel solution, manufactured by Mitsubishi Materials Corporation) is prepared as a functional liquid material.

  Next, “the above-described functional liquid material is applied on one surface of the insulating substrate 210 using a spin coating method (for example, 2500 rpm · 25 seconds), and then the insulating substrate 210 is placed on a hot plate. By repeating the “operation of drying at 150 ° C. for 5 minutes” three times, the precursor composition layer 230 ′ (layer thickness 300 nm) of the functional solid material (PZT) is formed (second step to third step).

  Next, as shown in FIG. 19 (e), the precursor composition layer 230 is formed at 225 ° C. using a concavo-convex mold M 6 (height difference of 300 nm) formed so that the region corresponding to the through hole 250 is convex. A stamping structure corresponding to the through hole 250 is formed in the precursor composition layer 230 ′ by performing a stamping process on “4” (fourth step). The pressure at the time of embossing is 5 MPa. Thereby, since the stamping process is performed on the precursor composition layer that has obtained a high plastic deformation ability by heating to 225 ° C., it is possible to obtain a desired electrical property improving effect.

  Finally, the precursor composition layer 230 ′ is heat-treated at a high temperature (650 ° C., 10 minutes) using an RTA apparatus, thereby forming a functional solid material layer (PZT) as shown in FIG. 19 (f). A gate insulating layer 230 is formed (fifth step).

(3) Formation of the gate electrode 220 First, the functional liquid material used as the functional solid material which consists of metal oxide ceramics (nickel lanthanum oxide) is prepared by heat-processing (1st process). Specifically, a solution (solvent: 2-methoxyethanol) containing a metal inorganic salt (lanthanum nitrate (hexahydrate) and nickel acetate (tetrahydrate)) is prepared.

  Next, as shown in FIGS. 20A and 20B, a functional liquid material is applied to one surface of the insulating substrate 210 using a spin coating method, and then the insulating substrate 210 is attached. It is placed on a hot plate and dried at 60 ° C. for 1 minute to form a precursor composition layer 220 ′ (layer thickness 300 nm) of a functional solid material (nickel lanthanum oxide) (second step to third step).

  Next, as shown in FIGS. 20 (c) and 20 (d), a concavo-convex M7 (height difference of 300 nm) formed so that the region corresponding to the gate electrode 220 and the region corresponding to the gate pad 222 are concave. ), The precursor composition layer 220 ′ is embossed at 150 ° C. to give the precursor composition layer 220 ′ an embossed structure (projection layer thickness of 300 nm, recess layer thickness of 50 nm). ) Is formed (fourth step). The pressure at the time of embossing is 5 MPa. Thus, since the precursor composition layer that has obtained high plastic deformation ability by heating to a second temperature within the range of 80 ° C. to 300 ° C. is subjected to a stamping process, a desired stamping process is performed. The structure can be formed with higher accuracy.

  Next, the precursor composition layer 220 ′ is entirely etched to remove the precursor composition layer 220 ′ completely from the region other than the region corresponding to the gate electrode 220 and the region corresponding to the gate pad 222 (entire surface). Etching process). The entire surface etching step is performed without using a vacuum process by using a wet etching technique.

  Finally, the precursor composition layer 220 ′ is heat-treated at a high temperature (650 ° C., 10 minutes) using an RTA apparatus, whereby the gate electrode 220 and the gate pad 222 made of a functional solid material layer (nickel lanthanum oxide) are formed. The thin film transistor 200 according to the third embodiment that has been formed (fifth step) and has a top gate structure as shown in FIG.

[Embodiment 4]
FIG. 21 is a diagram for explaining the piezoelectric inkjet head 300 according to the fourth embodiment. FIG. 21A is a cross-sectional view of the piezoelectric inkjet head 300, and FIGS. 21B and 21C are diagrams illustrating a state in which the piezoelectric inkjet head 300 ejects ink.

1. Configuration of Piezoelectric Inkjet Head 300 According to Embodiment 4 A piezoelectric inkjet head 300 according to Embodiment 4 is attached to one side of a cavity member 340 and a cavity member 340 as shown in FIG. A diaphragm 350 having a body element 320 formed thereon, a nozzle plate 330 attached to the other side of the cavity member 340 and having nozzle holes 332 formed therein, and defined by the cavity member 340, the diaphragm 350 and the nozzle plate 330. An ink chamber 360. The vibration plate 350 is provided with an ink supply port 352 that communicates with the ink chamber 360 and supplies ink to the ink chamber 360.

  According to the piezoelectric inkjet head 300 according to the fourth embodiment, as shown in FIGS. 21B and 21C, by applying an appropriate voltage to the piezoelectric element 320, the diaphragm 350 is temporarily moved upward. After the ink is supplied to the ink chamber 360 from a reservoir (not shown), the vibration plate 350 is bent downward, whereby the ink droplet i is ejected from the ink chamber 360 through the nozzle hole 332. Thereby, vivid printing can be performed on the substrate.

2. Method for Manufacturing Piezoelectric Inkjet Head According to Embodiment 4 A piezoelectric inkjet head 300 having such a structure includes a piezoelectric element 320 (first electrode layer 322, piezoelectric layer 324, and second electrode layer 326) and a cavity member. Both 340 are formed using an embossing technique. Hereinafter, the manufacturing method of the piezoelectric inkjet head 300 according to the fourth embodiment will be described in the order of steps.

  22 to 24 are views for explaining the method of manufacturing the piezoelectric inkjet head according to the fourth embodiment. FIG. 22A to FIG. 22F, FIG. 23A to FIG. 23D, and FIG. 24A to FIG.

(1) Formation of Piezoelectric Element 320 (1-1) Formation of First Electrode Layer 322 First, a functional liquid material that becomes a functional solid material made of metal oxide ceramics (nickel lanthanum oxide) is prepared by heat treatment. To do. Specifically, a solution (solvent: 2-methoxyethanol) containing a metal inorganic salt (lanthanum nitrate (hexahydrate) and nickel acetate (tetrahydrate)) is prepared.

  Next, as shown in FIG. 22A, a functional liquid material is applied to one surface of the dummy substrate 310 by using a spin coating method (for example, 500 rpm for 25 seconds), and then the dummy substrate 310 is mounted. By placing on a hot plate and drying at 60 ° C. for 1 minute, a precursor composition layer 322 ′ (layer thickness: 300 nm) of a functional solid material (nickel lanthanum oxide) is formed.

  Next, as shown in FIG. 22B, a precursor composition is used at 150 ° C. using a concavo-convex mold M8 (height difference of 300 nm) formed so that the region corresponding to the first electrode layer 322 is concave. By embossing the layer 322 ′, an embossed structure (the thickness of the convex portion is 300 nm and the thickness of the concave portion is 50 nm) is formed in the precursor composition layer 322 ′. The pressure at the time of embossing is 5 MPa.

  Next, the precursor composition layer 322 'is entirely etched to completely remove the precursor composition layer 322' from the region other than the region corresponding to the first electrode layer 322 (entire etching step). The entire surface etching step is performed without using a vacuum process by using a wet etching technique.

  Finally, the precursor composition layer 322 ′ is heat-treated at a high temperature (650 ° C., 10 minutes) using an RTA apparatus, so that the precursor composition layer 326 ′ has a function as shown in FIG. The first electrode layer 322 made of a conductive solid material layer (nickel lanthanum oxide) is formed.

(1-2) Formation of Piezoelectric Layer 324 First, a functional liquid material to be a functional solid material made of metal oxide ceramics (PZT) is prepared by heat treatment (first step). Specifically, a solution containing a metal alkoxide (PZT sol-gel solution, manufactured by Mitsubishi Materials Corporation) is prepared as a functional liquid material (first step).

  Next, as shown in FIG. 22D, “the functional liquid material described above is applied to one surface of the dummy substrate 310 using a spin coating method, and then the dummy substrate 310 is placed on the hot plate. The operation of drying at 150 ° C. for 5 minutes is repeated a plurality of times to form a precursor composition layer 324 ′ (for example, a thickness of 1 μm to 10 μm) of the functional solid material (PZT) (second step to third step). ).

  Next, as shown in FIG. 22 (e), a concavo-convex mold M9 (with a height difference of 500 nm) formed so that the region corresponding to the piezoelectric layer 324 is concave is used for the precursor composition layer 324 ′. On the other hand, an embossing structure (for example, a layer thickness of 1 μm to 10 μm of a convex portion and a layer thickness of 50 nm of a concave portion) is formed in the precursor composition layer 324 ′ by performing a die pressing process (fourth step).

  At this time, in the above-described process, the precursor composition layer 324 ′ is heated to 225 ° C. and subjected to a die pressing process using a mold heated to 225 ° C. The pressure at the time of embossing is about 4 MPa.

  Next, the precursor composition layer 324 'is entirely etched, thereby completely removing the precursor composition layer 324' from a region other than the region corresponding to the piezoelectric layer 324 (entire etching step). The entire surface etching step is performed without using a vacuum process by using a wet etching technique.

  Finally, the precursor composition layer 324 ′ is heat-treated at a high temperature (650 ° C., 10 minutes) using an RTA apparatus, so that the precursor composition layer 324 ′ has a function as shown in FIG. A piezoelectric layer 324 made of a conductive solid material layer (PZT) is formed (fifth step).

(1-3) Formation of the 2nd electrode layer 326 First, the functional liquid material used as the functional solid material which consists of metal oxide ceramics (nickel lanthanum oxide) is prepared by heat-processing. Specifically, a solution (solvent: 2-methoxyethanol) containing a metal inorganic salt (lanthanum nitrate (hexahydrate) and nickel acetate (tetrahydrate)) is prepared.

  Next, as shown in FIG. 23A, a functional liquid material is applied to one surface of the dummy substrate 310 by using a spin coating method (for example, 500 rpm · 25 seconds), and then the dummy substrate 310 is mounted. By placing on a hot plate and drying at 60 ° C. for 1 minute, a precursor composition layer 326 ′ (layer thickness: 300 nm) of a functional solid material (nickel lanthanum oxide) is formed.

  Next, as shown in FIG. 23 (b), a precursor composition is used at 150 ° C. using a concavo-convex mold M10 (height difference of 300 nm) formed so that the region corresponding to the second electrode layer 326 is concave. By embossing the layer 326 ′, an embossed structure (projection layer thickness of 300 nm, recess layer thickness of 50 nm) is formed in the precursor composition layer 326 ′. The pressure at the time of embossing is 5 MPa.

  Next, the precursor composition layer 326 'is entirely etched to remove the precursor composition layer 326' completely from a region other than the region corresponding to the second electrode layer 326 (entire etching step). The entire surface etching step is performed without using a vacuum process by using a wet etching technique.

  Finally, the precursor composition layer 326 ′ is heat-treated at a high temperature (650 ° C., 10 minutes) using an RTA apparatus, so that the precursor composition layer 326 ′ has a function from the precursor composition layer 326 ′ as shown in FIG. A second electrode layer 326 made of a conductive solid material layer (nickel lanthanum oxide) is formed. As a result, the piezoelectric element 320 including the first electrode layer 322, the piezoelectric layer 324, and the second electrode layer 326 is completed.

(2) Bonding of vibration plate 350 and piezoelectric element 320 As shown in FIG. 23 (d), the vibration plate 350 having the ink supply port 352 and the piezoelectric element 320 are bonded together using an adhesive.

(3) Formation of Cavity Member 340 First, a functional liquid material that becomes metal oxide ceramics (quartz glass) is prepared by heat treatment. Specifically, a solution containing metal alkoxide (isopropyl silicate (Si (OC ₃ H ₇ ) ₄ )) is prepared as a functional liquid material.

  Next, as shown in FIG. 24A, the functional liquid material described above is applied onto one surface of the diaphragm 350 by using a spin coating method, and then the dummy substrate 310 is placed on a hot plate. By drying at 150 ° C. for 5 minutes, a precursor composition layer 340 ′ (for example, a layer thickness of 10 μm to 20 μm) of a functional solid material (quartz glass) is formed.

  Next, as shown in FIG. 24 (b), the precursor composition layer 340 ′ is embossed using a concavo-convex mold M11 having a shape corresponding to the ink chamber 360 or the like, thereby providing a precursor. A stamping structure (for example, a layer thickness of 10 μm to 20 μm of a convex portion and a layer thickness of 50 nm of a concave portion) is formed on the composition layer 340 ′.

  At this time, in the above process, the precursor composition layer 340 ′ is heated to 150 ° C. and subjected to a die pressing process using a mold heated to 150 ° C. The pressure at the time of embossing is about 4 MPa.

  Finally, the precursor composition layer 340 ′ is heat-treated at a high temperature (650 ° C., 10 minutes) using an RTA apparatus, so that the precursor composition layer 340 ′ has a function from the precursor composition layer 340 ′ as shown in FIG. A cavity member 340 made of a conductive solid material layer (quartz glass) is formed.

(4) Bonding of Cavity Member 340 and Nozzle Plate 330 As shown in FIG. 24D, the cavity member 340 and the nozzle plate 330 having the nozzle holes 332 are bonded together using an adhesive.

(5) Removal of Dummy Substrate 310 As shown in FIG. 24 (e), the dummy substrate 310 is removed from the piezoelectric layer 320. Thereby, the piezoelectric inkjet head 300 according to the fourth embodiment is completed.

3. Effect of Piezoelectric Inkjet Head 300 According to Embodiment 4 According to the piezoelectric inkjet head 300 according to Embodiment 4, the precursor composition layer 324 ′ is dried at a first temperature in the range of 120 ° C. to 300 ° C. In addition, the precursor composition layer 324 ′ is heated to a second temperature higher than the first temperature and within the range of 150 ° C. to 300 ° C., and the precursor composition layer 324 ′ is embossed. A piezoelectric ink jet that is superior to conventional piezoelectric ink jet heads because it has a piezoelectric layer having excellent electrical characteristics (for example, high remanent polarization characteristics, low leakage current characteristics, etc.) formed by applying Become the head.

  According to the piezoelectric inkjet head 300 according to the fourth embodiment, the first electrode layer 322, the piezoelectric layer 324, the first electrode layer 326, and the cavity member 340 are all formed using a liquid material. Therefore, since it becomes possible to manufacture a piezoelectric ink jet head using an embossing processing technique, the above excellent piezoelectric ink jet head can be manufactured using significantly less raw materials and manufacturing energy than conventional ones. It can be manufactured.

  Also, according to the piezoelectric inkjet head 300 according to the fourth embodiment, the first electrode layer 322, the piezoelectric layer 324, the first electrode layer 326, and the cavity member 340 are all formed without using a vacuum process. Therefore, it is possible to manufacture the excellent piezoelectric inkjet head as described above by using much less manufacturing energy than in the past and in a shorter process than in the past.

  As described above, the manufacturing method of the ferroelectric material layer, the thin film transistor, and the piezoelectric ink jet head of the present invention have been described based on the above embodiment, but the present invention is not limited to this, and does not depart from the gist thereof. For example, the following modifications are possible.

(1) In Embodiments 1 to 4, PZT (Pb (Zr _x , Ti _1-x ) O ₃ ) is used as the ferroelectric material, but the present invention is not limited to this. For example, Nb-doped PZT, La-doped PZT, barium titanate (BaTiO ₃ ), lead titanate (PbTiO ₃ ), BTO (Bi ₄ Ti ₃ O ₁₂ ), BLT (Bi _4-x La _x Ti ₃ O ₁₂ ), SBT (SrBi ₂ Ta ₂ O ₉ ), BZN (Bi _1.5 Zn _1.0 Nb _1.5 O ₇ ) or bismuth ferrite (BiFeO ₃ ) can be used.

(2) In Embodiments 1 to 4 described above, in the method for manufacturing a ferroelectric material layer of the present invention, an embossing processing apparatus 700 for embossing a mold in a vertical direction with respect to a flat substrate. However, the present invention is not limited to this. For example, a die is attached to the surface of a roller, and the die is pressed against a flat substrate while rotating the roller. Thus, the ferroelectric material layer may be embossed using an embossing apparatus that embosses the substrate while rotating the roller. When attaching the mold to the surface of the roller, instead of attaching the mold to the surface of the roller, the mold may be formed on the surface of the roller itself.

(3) In Embodiments 2 and 3, indium tin oxide (ITO) was used as the oxide conductor material, but the present invention is not limited to this. For example, indium oxide (In ₂ O ₃ ), antimony-doped tin oxide (Sb—SnO ₂ ), zinc oxide (ZnO), aluminum-doped zinc oxide (Al—ZnO), gallium-doped zinc oxide (Ga—ZnO), ruthenium oxide An oxide conductor material such as (RuO ₂ ), iridium oxide (IrO ₂ ), tin oxide (SnO ₂ ), tin monoxide SnO, or niobium-doped titanium dioxide (Nb—TiO ₂ ) can be used. In addition, an amorphous conductive oxide such as indium gallium zinc composite oxide (IGZO), gallium-doped indium oxide (In-Ga-O (IGO)), or indium-doped zinc oxide (In-Zn-O (IZO)) is used. be able to. Also, strontium titanate (SrTiO ₃ ), niobium-doped strontium titanate (Nb—SrTiO ₃ ), strontium barium composite oxide (SrBaO ₃ ), strontium calcium composite oxide (SrCaO ₃ ), strontium ruthenate (SrRuO ₂ ), Nickel lanthanum oxide (LaNiO ₃ ), titanium lanthanum oxide (LaTiO ₃ ), copper lanthanum oxide (LaCuO ₃ ), nickel oxide neodymium (NdNiO ₃ ), nickel yttrium oxide (YNiO ₃ ), lanthanum calcium manganese oxide (LCMO) , Barium leadate (BaPbO ₃ ), LSCO (La _x Sr _1-x CuO ₃ ), LSMO (La _1-x Sr _x MnO ₃ ), YBCO (YBa ₂ Cu ₃ O _7-x ), LNTO ( _{La (NI 1-x Ti x} ) O 3), LSTO ((La 1-x, Sr x) TiO 3), STRO (Sr (Ti 1-x Ru x) O 3) other perovskite-type conductive oxide Alternatively, a pyrochlore type conductive oxide can be used.

(4) In Embodiments 2 and 3, nickel lanthanum oxide (LaNiO ₃ ) was used as the material used for the gate electrode, but the present invention is not limited to this. For example, Pt, Au, Ag, Al, Ti, ITO, In ₂ O ₃ , Sb—In ₂ O ₃ , Nb—TiO ₂ , ZnO, Al—ZnO, Ga—ZnO, IGZO, RuO ₂ and IrO ₂ and Nb _{-STO, SrRuO 2, LaNiO 3,} BaPbO 3, LSCO, LSMO, can be used YBCO other perovskite-type conductive oxide. A pyrochlore type conductive oxide and an amorphous conductive oxide can also be used.

(5) In Embodiments 2 and 3, an insulating substrate in which an STO (SrTiO) layer is formed on the surface of a Si substrate via an SiO ₂ layer and a Ti layer is used as the insulating substrate. Although a SiO ₂ ) substrate is used, the present invention is not limited to this. For example, a SiO2 / Si substrate, an alumina (Al ₂ O ₃ ) substrate, an STO (SrTiO) substrate, or an SRO (SrRuO ₃ ) substrate can be used.

(6) Although the present invention has been described with reference to the first embodiment as a capacitor, the second and third embodiments as thin film transistors, and the fourth embodiment as a piezoelectric inkjet head, the present invention is not limited to this. For example, the method for manufacturing a ferroelectric material layer of the present invention can be applied to manufacturing various functional devices other than these.

DESCRIPTION OF SYMBOLS 12 ... Capacitor (center part, Embodiment 1), 14 ... Capacitor (peripheral part, comparative example), 20 ... Base material, 22 ... Insulating substrate, 24 ... Lower electrode, 30 ... Ferroelectric material layer, 32 ... Strong Dielectric material layer (central portion, embodiment 1), 34 ... ferroelectric material layer (peripheral portion, comparative example), 30a, 30b, 30c ... precursor composition layer, 42,44 ... upper electrode, 100,200 900, thin film transistor, 110, 210, 910 ... insulating substrate, 120, 220, 920 ... gate electrode, 120 ', 220' ... precursor composition layer (gate electrode), 130, 230, 930 ... gate insulating layer, 130 ', 230' ... precursor composition layer (gate insulating layer), 140, 240 ... oxide conductor layer, 140 ', 240' ... precursor composition layer (oxide conductive layer), 142, 242, ... Channel region, 144, 2 4 ... Source region, 146, 246 ... Drain region, 300 ... Piezoelectric inkjet head, 310 ... Dummy substrate, 320 ... Piezoelectric element, 322 ... First electrode layer, 324 ... Piezoelectric layer, 326 ... Second electrode layer, 330 ... Nozzle plate, 332 ... Nozzle hole, 340 ... Cavity member, 350 ... Vibration plate, 352 ... Ink supply port, 360 ... Ink chamber, 940 ... Channel layer, 950 ... Source electrode, 960 ... Drain electrode, M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11.

Claims (8)

A first step of preparing a sol-gel solution to be a ferroelectric material by heat treatment;
A second step of forming a precursor composition layer of the ferroelectric material by applying the sol-gel solution on a substrate;
A third step of drying the precursor composition layer at a first temperature in the range of 120 ° C. to 250 ° C .;
A first embossing process is performed on the precursor composition layer in a state where the precursor composition layer is heated to a second temperature higher than the first temperature and within a range of 150 ° C. to 300 ° C. 4 steps,
And a fifth step of forming a ferroelectric material layer from the precursor composition layer by heat-treating the precursor composition layer at a third temperature higher than the second temperature in this order. A method for manufacturing a ferroelectric material layer. In the manufacturing method of the ferroelectric material layer according to claim 1,
The first temperature is within a range of 120 ° C to 200 ° C;
The method for manufacturing a ferroelectric material layer, wherein the second temperature is higher than the first temperature and is in a range of 175 ° C to 300 ° C. In the manufacturing method of the ferroelectric material layer according to claim 1 or 2,
In the fourth step, the method of manufacturing a ferroelectric material layer is characterized by performing an embossing process at a pressure within a range of 1 MPa to 20 MPa. A source electrode and a drain electrode;
A channel layer located between the source electrode and the drain electrode;
A gate electrode for controlling the conduction state of the channel layer;
A thin film transistor comprising a gate insulating layer formed between the gate electrode and the channel region and made of a ferroelectric material,
The thin film transistor according to claim 1, wherein the gate insulating layer is formed by using the method for manufacturing a ferroelectric material layer according to claim 1. An oxide conductor layer including a source region, a drain region, and a channel region, a gate electrode for controlling a conduction state of the channel region, and a gate made of a ferroelectric material formed between the gate electrode and the channel region An insulating layer, wherein the channel region has a layer thickness smaller than that of the source region and the drain region,
The thin film transistor according to claim 1, wherein the gate insulating layer is formed by using the method for manufacturing a ferroelectric material layer according to claim 1. The thin film transistor according to claim 5,
The oxide conductor layer in which the layer thickness of the channel region is smaller than the layer thickness of the source region and the layer thickness of the drain region is formed using an embossing technique. . The thin film transistor according to claim 5 or 6,
The carrier concentration and the layer thickness of the channel region are set to such values that the entire channel region is depleted when the thin film transistor is in an off state , and
The carrier concentration of the channel region is in the range of 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ ,
A thin film transistor , wherein the channel region has a layer thickness in a range of 5 nm to 100 nm . A cavity member;
A diaphragm attached to one side of the cavity member and having a piezoelectric layer formed thereon;
A nozzle plate attached to the other side of the cavity member and formed with nozzle holes;
A piezoelectric inkjet head comprising: an ink chamber defined by the cavity member, the diaphragm and the nozzle plate;
A piezoelectric ink jet head, wherein the piezoelectric layer is formed by using the method for manufacturing a ferroelectric material layer according to any one of claims 1 to 3.