JP5147448B2 - Image processing apparatus for semiconductor appearance inspection apparatus, semiconductor appearance inspection apparatus, and image processing method - Google Patents

Description

  The present invention relates to an image processing apparatus and an image processing method for processing a continuous image in parallel by a plurality of processors, and more particularly to a hardware memory of a processor element (PE) in a multiprocessor unit in an image processing apparatus for a semiconductor visual inspection apparatus. The present invention relates to a method for realizing defect determination processing by a plurality of image processing programs regardless of memory size limitations, even when the size is limited.

  A general semiconductor wafer appearance inspection apparatus is required to improve inspection sensitivity and speed up in order to cope with the miniaturization of the manufacturing process. Defects detected by detecting the image to be inspected with the sensor of the image detection unit and using digital images that have been digitally converted by the A / D converter, using image processing for alignment, defect determination, defect feature extraction, etc. Information is output.

In an image processing apparatus, an input image is subjected to defect determination processing at high speed and defect information is output. Therefore, in many cases, an image is distributed to a plurality of image processing units and processed in parallel.
One example is Patent Document 1 (USP 6,971,066 specification).
In recent years, a multiprocessor type image processing apparatus that includes a plurality of processor elements (PE) and performs parallel processing has been proposed in order to improve processor processing performance. In a multiprocessor image processing apparatus, an image is divided into small units, and each processor performs division processing, thereby realizing high-speed image processing. In such a processor system, alignment by image processing, defect determination, defect feature extraction processing, and the like are realized by software.
Examples thereof include Patent Document 2 (Japanese Patent Laid-Open No. 11-135054) and Patent Document 3 (Japanese Patent Laid-Open No. 10-162130).

USP 6,971,066 specification Japanese Patent Laid-Open No. 11-135054 JP-A-10-162130

  A semiconductor that performs defect determination between common pattern parts in an image using two-dimensional image data continuously detected by utilizing the fact that the shape of a chip is the same in an appearance inspection formed on a semiconductor substrate In an image processing apparatus for an appearance inspection apparatus, high-speed image distribution and real-time processing are realized by configuring a plurality of multiprocessor units including a plurality of processor elements (PE). When a defect determination processing function is installed in a multiprocessor unit, it is impossible to store an image processing program exceeding the memory size limitation due to the memory size limitation of the processor element (PE) hardware. There is a problem that it is difficult to realize the defect determination processing function in the processing program.

  In order to solve the above problems, the present invention has a plurality of image processing programs held in the overall control computer, and image processing is performed on the memory space of each processor element (PE) in the plurality of multiprocessor units. The image processing program is replaced by executing the program download, and each processor element (PE) performs a defect determination process using the downloaded image processing program by reading the initial value file from the overall control computer.

  According to the present invention, due to the limitation of the hardware memory size of the processor element (PE) in the multiprocessor unit, the overall control is performed even in a state where a plurality of types of image processing programs cannot be stored in the memory space of the processor element (PE). By downloading the image processing program to be stored in the processor element (PE) by the computer and replacing the image processing program, a plurality of image processing programs can be used regardless of restrictions on the memory size of the hardware of the processor element (PE). It becomes possible to execute a defect determination process.

Embodiments of the present invention will be described below with reference to the drawings.
<Example 1>
FIG. 1 is a block diagram showing an image processing apparatus based on a multiprocessor system that has already been disclosed. Reference numeral 102 denotes a sensor, 103 denotes an A / D conversion circuit, and 104 denotes an image processing apparatus. In the figure, a sensor 102 is a line sensor for obtaining an inspection image. The detected image is converted into a digital image by an A / D conversion circuit 103 and input to the image processing apparatus 104 as a continuous two-dimensional image.

  The image processing apparatus 104 has a multiprocessor configuration in which a plurality of processors are arranged, and includes a memory 105, a multiprocessor unit 106 and a multiprocessor unit 108 that are grouped into two groups according to an image processing function, and an overall control computer 107. Configure. The memory 105 has a memory space in which a plurality of chip images can be stored. The input image is temporarily stored and then a continuous image is output to the multiprocessor unit 106 at an arbitrary timing. An image of a rectangular area designated by the multiprocessor unit 108. And an image cutout function 109 for cutting out the image.

  The multiprocessor unit 106 and the multiprocessor unit 108 include a distribution processing unit 110 that assigns an image from the memory 105 to each processor element (PE), and four processor elements (PE). The distribution processing unit 110 has a function of dividing a continuous two-dimensional image into rectangular blocks, and a function of distributing an image of blocks to each processor, and performs image processing using images distributed by each processor. Repeat the test in real time. The multiprocessor unit 106 performs position correction and defect determination processing, and the multiprocessor unit 108 performs defect feature extraction processing.

The overall control computer 107 performs data exchange with each multiprocessor unit, control of the memory 105, parameter setting before inspection, collection and storage of inspection results, display, data exchange with other devices, etc. in real time. Perform an inspection.
FIG. 2 shows a processor element configuration inside the multiprocessor unit, which is composed of four processor elements 201, 202, 203, 204 (205, 206, 207, 208) connected to the image distribution circuit 200. Each processor element consists of a CPU and memory. The CPU performs defect determination calculation processing with the adjacent chip stored in advance one chip before storing the image transferred from the image distribution circuit 200 in the memory inside the multiprocessor. The image storage in the memory may be DMA transfer. The memory is used not only for image processing programs, storage of inspection parameters, calculation work, etc., but also as an image storage memory, and has a memory size that can store at least all images in one chip area in charge of one PE. Inspection parameters and input image size are preset from the overall control computer before inspection. Also, the processing result is notified to the overall control computer 209.

  Next, an example in which image distribution to the memory space in each processor element of the multiprocessor and downloading of the image processing program are executed will be described with reference to FIGS.

  FIG. 3 shows steps from the overall control computer 209 to image distribution to the memory space in each processor element and downloading of the image processing program, execution of inspection, and completion of inspection.

  FIG. 4 is a diagram showing the details of the internal control computer 209 and the internal portions of the processor elements 201 to 204 in the multiprocessor in FIG. 2. The image processing program A and the image processing program are stored in the memory unit of the overall control computer 209. Program initial value 400 for A, program initial value 401 for image processing program B and image processing program B, program initial value 402 for image processing program C and image processing program C, program initial value for image processing program D and image processing program D 403, inspection condition parameters 404 set in advance before inspection such as wafer size, chip size, number of inspection scans, image distribution setting table 405 calculated from inspection condition parameters, and defect determination processing from the multiprocessor The structure of the results inspection result 406, the configuration of the memory area for the internal configuration of the CPU and the image data area and an image processing program area and the other area in the processor element in a multiprocessor.

In FIG. 3, when the overall control computer recognizes the download step in step 300, the overall control computer shifts to the image distribution setting in step 301.
In the image distribution setting in step 301, an image distribution table in which assignment of processor elements in a multiprocessor element that distributes image data for each chip area and a corresponding image processing program from inspection condition parameters 404 set in advance prior to inspection is summarized. Referring to 405, the process proceeds to image processing program download in step 302.

  In the image processing program download in step 302, downloading of the image processing program and the program initial value file determined in the image distribution setting table to each processor element in the multiprocessor unit is started, and CPU in each processor element in step 303 is reset. Migrate to

  The CPU reset in each processor element in step 303 requires a reset in order to execute the image processing program downloaded in step 302 from the start address of the memory of the processor element (PE). After the CPU reset in each processor element in the multi-unit is performed, the process proceeds to the inspection start in step 304.

  At the start of inspection in step 304, the image distribution circuit from the image distribution setting table 405 distributes the input image data to each processor element in the multiprocessor, and executes defect determination processing according to each image processing program. When the execution is completed, the process proceeds to the end of the inspection in step 305.

  At the end of the inspection process in step 305, the defect determination process result is received from each processor element in the multi-unit in the inspection result storage 406 prepared in the memory space in the overall control computer of FIG. A summary process is executed and the inspection is terminated.

The above is an example in which the image distribution and the image processing program are downloaded to the memory space in each processor element of the multiprocessor.
Up to now, since the memory size of one processor element is finite, when executing the defect determination function in a plurality of image processing programs, execution is possible only within the memory size constraint of the processor element. By following the embodiment of the present invention, the image processing program stored in the memory space of each processor element is replaced by downloading, and the defect determination processing is performed by the downloaded image processing program, so that the multiprocessor unit There is provided an image processing apparatus for a semiconductor visual inspection apparatus, characterized by having means for realizing a defect determination function in a plurality of image processing programs regardless of hardware memory size restrictions of a processor element (PE) in be able to.
<Example 2>
In this embodiment, the image processing apparatus for a semiconductor visual inspection apparatus in the first embodiment is used, and the logic circuit area 503 and the memory cell area 504 in the memory LSI 502 are arranged on the chip 501 arranged on the semiconductor wafer 500 shown in FIG. A case where defect determination processing is performed using an image processing program that differs from region to region in other regions 504 will be described as an example.
The areas 503 to 505 in the memory LSI 502 are set in advance in the inspection condition parameter 404 shown in FIG. 4 before inspection, and the image distribution table 405 is created.
For example, the chip areas a and b in the image distribution setting table 405 are areas of the logic circuit 503, and the image processing program A is registered in the image processing program to be processed. Further, in the chip areas b to c in the image distribution setting table 405, the memory cell area 504 is set, and the image processing program B is registered in the image processing program to be processed. Similarly, other areas 504 are set in the chip areas c to d in the image distribution setting table 405, and the image processing program C is registered in the image processing program to be processed. By setting each area in the image distribution setting table 405 in this way, image distribution to each processor element in the multiprocessor for each area and execution of the image processing program are performed.
Further, the chip 511 arranged on the semiconductor wafer 510 is divided into a register group area 513, a memory area 514, a CPU core area 515, an input / output area 516, and other areas 516 in the microcomputer LSI 512. However, by setting the region in the inspection condition parameter 404 shown in FIG. 4 and using the image distribution setting table 405, each region is compared with the image region in the memory space of the processor element (PE) in each multiprocessor. Image data is stored, and the image processing program is stored in the image processing program area, so that image processing is performed for each in-chip area regardless of the hardware memory size limitation of the processor element (PE) in the multiprocessor unit. It is possible to switch programs, and defect determination processing It can be carried out.
<Example 3>
The third embodiment will be described with reference to FIGS. 6 and 7. In the second embodiment, the inspection method in the case where the inside of the chip is divided for each region is shown. In FIG. 6, in the inspection in which the shapes of the chip 601, the chip 602, and the chip 603 arranged on the semiconductor wafer 600 are the same, and the chip 604, the chip 605, and the chip 606 have the same shape, An example will be described in which defect determination processing is performed with a different image processing program for each chip combination in which 603 is one set and chips 604 to 606 are one set.
FIG. 7 shows a defect determination processing method in each processor element in the multiprocessor. FIG. 7 shows an inspection example for three chips, and the inspection is performed in the order of chip 1 700, chip 2 701, and chip 3 702. In addition, memory spaces 703 to 706 of the image areas of the processor elements 201 to 204 are shown. Reference numerals 707 to 710 denote memory spaces of image processing program areas of the processor elements 201 to 204, respectively. Each chip is divided into 12 blocks of image blocks 0 to 11. If the chip 601, chip 602, and chip 603 in FIG. 6 are regarded as chip 1 700, chip 2 701, and chip 3 702 in FIG. 7, a in FIG. 7 corresponding to .about.b and c.about.d are assigned to the processor element 201, blocks 3, 4, and 5 shown in FIG. 7 corresponding to c to d in FIG. 7 are assigned to the processor element 203, blocks 9, 10, and 11 in FIG. 7 corresponding to d to e in FIG. 6 are assigned to the processor element 204, and so on. By distributing in order, memory locations 703 to 706 of each processor element store the same location image in the chip as shown in FIG.
Correspondingly, since the defect determination function program notified from the overall control computer to the image distribution circuit has the same chip shape this time, the image processing program A is stored in the image processing program area 707 of the processor element 201, and the image processing of the processor element 202 is performed. The image processing program A is stored in the program area 708, the image processing program A is stored in the image processing program area 709 of the processor element 203, the image processing program A is stored in the image processing program area 710 of the processor element 204, and so on. Each processor performs defect determination processing by comparing the same blocks of adjacent chips using the distribution image and each image processing program, and detects defects. Similarly, in the chip 604, chip 605, and chip 606 in FIG. 6, the image data and the image processing program are stored in the processor elements 205 to 208 in the multiprocessor unit shown in FIG.
By performing the above processing, the inspection function program for each chip set is stored in the image processing program area of the memory space in the processor element in the multiprocessor, so that the processor element ( It is possible to switch the image processing program in each processor element for each same chip set regardless of the memory size limitation of the hardware of PE), and to perform defect determination processing by a different image processing program for each same chip set. be able to.
<Example 4>
Example 4 will be described. So far, switching of image processing programs stored in the memory space of the processor element (PE) in the multiprocessor in the chip area in Embodiment 2 and in units of chips in Embodiment 3 has been described with reference to the embodiment. This time, the image processing program stored in the memory space of all the processor elements (PE) in the plurality of multiprocessors shown in FIGS. 2 and 4 is downloaded using the download mechanism shown in FIG. 3 described in the first embodiment. By carrying out total replacement, it is possible to switch the defect determination function for each inspection, and so far a single semiconductor appearance inspection device where multiple image processing devices for semiconductor appearance inspection devices are used for each inspection. Inspection can be carried out with an image processing apparatus.

1 is a block diagram showing an image processing apparatus using a known multiprocessor system. The figure which shows the internal structure of a multiprocessor unit. The figure which shows the execution step of download. The figure which shows the internal structure of a general control computer and a multiprocessor unit. The figure which showed the chip | tip which has a some pattern inside arrange | positioned on a semiconductor wafer. The figure which showed the different same chip pattern group arrange | positioned on the same semiconductor wafer. The figure which shows the defect determination process inside a processor element.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Semiconductor wafer, 101 ... Chip, 102 ... Image detection sensor, 103 ... A / D converter, 104 ... Overall control computer, 105 ... Memory, 106 ... Processor element, 107 ... Overall control computer, 108 ... Multiprocessor unit, DESCRIPTION OF SYMBOLS 109 ... Image cropping, 110 ... Distribution processing part, 200 ... Image distribution circuit, 201, 202, 203, 204, 205, 206, 207, 208 ... Processor element, 209 ... Overall control computer, 300 ... Image block, 400, 401, 402, 403, 404 ... inspection condition parameter area, 405 ... image distribution setting table area, 406 ... inspection result storage area, 500 ... semiconductor wafer, 501 ... chip, 502 ... memory LSI, 503 ... logic circuit area, 504 ... Memory cell area, 505. Other regions, 510 ... semiconductor wafer, 511 ... chip, LSI, 513 ... register group area such as 512 ... microcontroller 514 ... memory unit area, 515 ... CPU core region, 516 ... and out area. 517: Other area, 600: Semiconductor wafer, 601: Chip 1, 602 ... Chip 2, 603 ... Chip 3, 604 ... Chip 4, 605 ... Chip 5, 606 ... Chip 6, 700 ... Chip 1, 701 ... Chip 2, 702: Chip 3, 703: Image area memory space, 704 ... Image area memory space, 705 ... Image area memory space, 706 ... Image area memory space, 707, 708, 709, 710 ... Memory of image processing program space.

Claims (12)

An image processing apparatus for a semiconductor appearance inspection apparatus that detects an image in a region to be inspected on a semiconductor wafer, compares and determines common patterns of detected images obtained by the detection, and performs an appearance inspection of the semiconductor wafer,
Image cutout means for cutting out the detected image into a predetermined image range;
Image processing means for inputting the clipped image and performing image processing;
The image processing means includes
A multiprocessor unit comprising: a plurality of processor elements; and an image distribution unit that divides the clipped image into blocks and distributes the divided block-unit images for each of the processor elements;
Overall control means for controlling at least the multiprocessor unit and the image distribution means, and summing up image processing results processed by the multiprocessor unit;
The overall control means has a plurality of image processing programs required for image processing performed in each of the processor elements,
When executing the image processing in units of divided blocks, an image processing program corresponding to the image processing performed by the processor element is extracted from the plurality of image processing programs and is already stored in the memory of the processor element. In the case of performing an appearance inspection of the semiconductor wafer by replacing with an image processing program,
When performing defect determination inspection on the semiconductor wafer using a different image processing program for each of the circuit regions having different functions provided in the chip on the semiconductor wafer,
An image processing program corresponding to a defect determination function for the circuit area is extracted from the plurality of image processing programs, and stored in the memory of the processor element.
An image processing apparatus for a semiconductor appearance inspection apparatus, wherein the defect determination inspection is executed after resetting a CPU in the processor element.   2. The image processing apparatus for a semiconductor visual inspection apparatus according to claim 1, wherein after the CPU is reset, the downloaded image processing program is executed from the start address of the memory of the processor element. A group of chips having one shape and a group of chips having another shape are provided on a semiconductor wafer, and a defect determination inspection is performed on each group of chips using different image processing programs. If
The semiconductor appearance according to claim 1, wherein an image processing program corresponding to a defect determination function for each group of chips is extracted from the plurality of image processing programs and stored in a memory of the processor element. Image processing apparatus for inspection apparatus.   The defect determination processing corresponding to each of the inspections is executed by switching an image processing program stored in a memory in the processor element for each appearance inspection of the semiconductor wafer. The image processing apparatus for semiconductor appearance inspection apparatuses as described. A semiconductor visual inspection apparatus for detecting an image in a region to be inspected on a semiconductor wafer, comparing and determining common patterns of detected images obtained by the detection, and performing visual inspection of the semiconductor wafer,
A detection device for detecting the image;
A memory device having storage means for storing the detected image and image cutout means for cutting out the detected image into a predetermined image range;
An image processing apparatus that inputs the cut image and performs image processing;
The image processing apparatus includes:
A multiprocessor unit comprising: a plurality of processor elements; and an image distribution unit that divides the clipped image into blocks and distributes the divided block-unit images for each of the processor elements;
An overall control device that controls at least the multiprocessor unit and the image distribution means, and totals image processing results processed by the multiprocessor unit;
The overall control apparatus has a plurality of image processing programs required for image processing performed in each of the processor elements,
In the image processing apparatus, when executing the image processing in units of divided blocks, an image processing program corresponding to the image processing performed by the processor element is extracted from the plurality of image processing programs and is already stored in the processor element. When replacing the stored image processing program to perform an appearance inspection of the semiconductor wafer,
When performing defect determination inspection on the semiconductor wafer using a different image processing program for each of the circuit regions having different functions provided in the chip on the semiconductor wafer,
An image processing program corresponding to a defect determination function for the circuit area is extracted from the plurality of image processing programs, and stored in the memory of the processor element.
The semiconductor appearance inspection apparatus, wherein the defect determination inspection is executed after resetting a CPU in the processor element. 6. The semiconductor appearance inspection apparatus according to claim 5, wherein after the CPU is reset, the downloaded image processing program is executed from the start address of the memory of the processor element. A group of chips having one shape and a group of chips having another shape are provided on a semiconductor wafer, and a defect determination inspection is performed on each group of chips using different image processing programs. If
6. The semiconductor appearance according to claim 5, wherein an image processing program corresponding to a defect determination function for each group of chips is extracted from the plurality of image processing programs and stored in a memory of the processor element. Inspection device.   6. The defect determination process corresponding to each of the inspections is executed by switching an image processing program stored in a memory in the processor element for each appearance inspection of the semiconductor wafer. The semiconductor appearance inspection apparatus as described. An image processing method in an image processing apparatus for a semiconductor appearance inspection apparatus for detecting an image in a region to be inspected on a semiconductor wafer, comparing and determining common patterns of detected images obtained by the detection, and performing an appearance inspection of the semiconductor wafer Because
A detection device for detecting the image;
An image cutout that cuts out the detected image into a predetermined image range, and an image processing device that inputs the cutout image and performs image processing;
The image processing apparatus includes a plurality of processor elements, and an image distribution unit that divides the cut-out image into blocks and distributes the divided block-by-block images into the processor elements. A multiprocessor unit
An overall control device that controls at least the multiprocessor unit and the image distribution means, and totals image processing results processed by the multiprocessor unit;
The overall control apparatus includes a plurality of image processing programs required for image processing performed by each of the processor elements, and also includes an image in units of blocks, a processor element to which the block images are allocated, and image processing to be stored in the processor elements. It has an image distribution table that summarizes the correspondence of each program,
Receiving a download command of an image processing program corresponding to the processor element from the overall control device;
Distributing and storing the block image to the processor element based on inspection condition parameters set in advance before inspection;
Downloading an image processing program and a program initial value file corresponding to the processor element to the processor element based on the image distribution table;
Resetting a CPU in the processor element;
Executing a defect determination process on the semiconductor wafer according to the downloaded image processing program;
Storing the result of defect determination processing from each of the processor elements in a memory in the overall control device,
When performing defect determination inspection on the semiconductor wafer using a different image processing program for each of the circuit regions having different functions provided in the chip on the semiconductor wafer,
An image processing program corresponding to a defect determination function for the circuit area is extracted from the plurality of image processing programs, and stored in the memory of the processor element.
An image processing method, wherein the defect determination inspection is executed after resetting the CPU in the processor element. The image processing method according to claim 9, wherein after the CPU is reset, the downloaded image processing program is executed from the start address of the memory of the processor element. A group of chips having one shape and a group of chips having another shape are provided on a semiconductor wafer, and a defect determination inspection is performed on each group of chips using different image processing programs. If
The image processing according to claim 9, wherein an image processing program corresponding to a defect determination function for each group of chips is extracted from the plurality of image processing programs and stored in a memory of the processor element. Method.   The defect determination process corresponding to each of the inspections is executed by switching an image processing program stored in a memory in the processor element for each appearance inspection of the semiconductor wafer. The image processing method as described.

Images