JP5116275B2 - Arithmetic processing apparatus, information processing apparatus, and control method for arithmetic processing apparatus - Google Patents

Description

The present invention relates to an arithmetic processing device, an information processing device, and a control method for the arithmetic processing device .

  Conventionally, in an information processing system in which data read from a main memory is processed by a processor, a high-speed cache memory is arranged between the processor and the main memory, and data that is frequently read and written is arranged in the cache memory. Cache technology that avoids memory access delay (memory latency) for data reading and writing has been used.

  With this cache technology, when data to be read (load target) exists in the cache memory (cache hit), data can be read at high speed by reading the necessary data from the cache memory, avoiding memory latency. To do. However, if the data to be loaded does not exist in the cache memory (cache miss), the necessary data is acquired from the main memory, so that memory latency cannot be avoided.

  By the way, according to recent research results, it has been found that most cache misses are caused by a relatively small number of load instructions. A relatively small number of load instructions that cause most cache misses are called Delinquent Load. For example, Non-Patent Document 1 reduces the influence of memory latency caused by access to the main memory due to a cache miss caused by a load instruction by executing an instruction sequence including this Delinquent Load as a separate thread in advance. Thus, a technique for improving the performance of the processor system has been devised.

Dynamic Speculative Pre-computation Jamison D. Collons, etc. In 34th International Symposium on Micro-architecture, December, 2001 JP 2001-290702 A

  However, in the prior art represented by the above Non-Patent Document 1, in order to execute Delinquent Load as a separate thread in advance, hardware and a multi-thread mechanism for assembling the thread are necessary. However, there is a problem that the circuit scale is complicated and the circuit scale becomes large.

The present invention has been made to solve the above problems (problems), and does not require special hardware such as a multi-thread mechanism. An object of the present invention is to provide an arithmetic processing device, an information processing device, and a control method for the arithmetic processing device capable of reducing the influence of memory latency caused by accessing the memory and improving the performance of the entire information processing system. .

  In order to solve the above-described problems and achieve the object, the present invention provides an information processing apparatus in which a cache device is arranged between a main storage device and the cache according to a load instruction for reading data from the main storage device. A load instruction storage unit for storing the load instruction in an identifiable manner when a cache miss occurs in the apparatus is provided.

  Further, the present invention is characterized in that, in the above-mentioned invention, the load instruction storage unit stores the number of times the cache miss has occurred for each load instruction in which a cache miss has occurred in the cache device.

  According to the present invention, in the above invention, when writing data to the main storage device in response to a store instruction for writing data to the main storage device, the load instruction corresponding to the store instruction is identified, and the load instruction is A load instruction storage determination unit that determines whether or not to be stored in the load instruction storage unit, and a load instruction that is determined to be stored in the load instruction storage unit by the load instruction storage determination unit has caused a cache miss A cache miss number determination unit that determines whether or not the number of times exceeds a predetermined threshold, and data to be read by a load instruction that is determined by the cache miss number determination unit that the number of occurrences of a cache miss exceeds a predetermined threshold, or And a data storage unit that caches a data identifier for identifying the data.

  The present invention also provides an instruction control mechanism for controlling a load instruction in an information processing device in which a cache device is arranged between the main storage device and the cache device according to a load instruction for reading data from the main storage device. A load instruction storage unit for storing the load instruction in an identifiable manner when a cache miss occurs is provided.

  The present invention also relates to an instruction control method for controlling a load instruction in an information processing device in which a cache device is arranged between the main storage device and the cache device according to a load instruction for reading data from the main storage device. A load instruction storing step of storing the load instruction in an identifiable manner when a cache miss occurs is included.

  According to the present invention, since the load instruction in which the cache miss has occurred is stored in the dedicated buffer in an identifiable manner, the load instruction in which the cache miss has occurred can be identified and the occurrence of the cache miss can be predicted in advance. Play.

  In addition, according to the present invention, since the load instruction in which a cache miss has occurred is stored in the dedicated buffer together with the number of times the cache miss has occurred, the load instruction that is more likely to cause a cache miss is grasped, and the occurrence of a cache miss has occurred. There is an effect that can be predicted in advance.

  Further, according to the present invention, the load instruction that is highly likely to cause a cache miss that is determined that the number of occurrences of the cache miss exceeds a predetermined threshold value or the data identifier that identifies the data is read. Since the data storage unit for storing is provided, the memory latency due to the occurrence of a cache miss of the load instruction can be suppressed by referring to the data storage unit.

With reference to the accompanying drawings, the processing unit of the present invention, an embodiment will be described in detail according to the method of controlling an information processing apparatus and the processing unit. Prior to the description of the first and second embodiments, problems of the prior art and features of the present invention, which are preconditions for the present invention, will be described. In the following, a case where the processor is a CPU (Central Processing Unit) is shown, but the present invention is not limited to this, and various processing devices such as an MPU (Micro Processing Unit) and MCU (Micro Controller Unit) may be used. Good.

First, the problems of the prior art, which is the premise that the present invention has been made, will be described. FIG. 1 is a diagram illustrating a problem of the prior art. As shown in the figure, Delinquent Load, a load instruction that is prone to cache misses, is applied to the cache memory, which is a high-speed memory that can primarily store data from the CPU core that is the processing subject of the CPU that is the information processing device. A data load is required. On the other hand, if the load instruction is Delinquent Load, a cache miss occurs in the cache memory. Since a cache miss has occurred, the cache memory requests the main memory to load the data. Note that data loading refers to reading data from the main memory or the cache memory.

  Since the cache memory has a high memory access speed, the memory access does not cause a delay compared to the processing of the CPU core. However, the main memory still has a slower memory access speed than the recent CPU core processing speed improvement, and cannot keep up with the CPU core processing speed, causing the memory access to delay due to the completion of data loading. End up. For this reason, in order to load certain data into the CPU core, loading from the cache memory is more advantageous than loading from the main memory from the viewpoint of processing efficiency of the CPU.

  Therefore, when data is loaded into the CPU core, the data read from the main memory is temporarily stored in the cache memory, and when the data is loaded again into the CPU core, the data is loaded from the cache memory instead of from the main memory. A technique for improving the speed of memory access by loading the memory is used.

  However, because the cache memory has a limited storage capacity, it is impossible to store all the data once loaded into the CPU core, such as FIFO (First In First Out), LIFO (Last In Last Out), Some data is erased in accordance with a predetermined algorithm such as LFU (Least Frequently Used method). For this reason, the erased data cannot be loaded from the cache memory by referring to the cache memory, and is loaded again from the main memory. This is called a cache miss.

  Among the data load instructions executed by the CPU core in the process of sequentially executing the processing procedure whose execution order is determined by the predetermined algorithm in the CPU, certain load instructions are once due to the characteristics of the predetermined algorithm. When the loaded data is reloaded, there is a load instruction that is erased from the cache memory and must be loaded from the main memory again. This is called Delinquent Load, but Delinquent Load is a load instruction that easily causes a cache miss.

  Therefore, when Delinquent Load tries to load data from the cache memory, a cache miss always occurs and the necessary data is accessed and acquired. For Delinquent Load, access to the main memory always occurs, resulting in memory latency and a reduction in CPU processing efficiency.

  The present invention has been made to solve the above-described problems (problems), and a Delinquent Load control mechanism and a Delinquent Load control in which memory latency is not caused by Delinquent Load and the processing efficiency of the CPU does not decrease. It aims to provide a method.

  Next, features of the present invention made to achieve the above object will be described. FIG. 2 is a diagram showing features of the present invention. As shown in the figure, a cache miss occurs when attempting to load data from cache memory by Delinquent Load. Here, a dedicated cache memory for Delinquent Load that can be accessed at high speed is provided in the same way as a normal cache memory. The data targeted for loading by the Delinquent Load is not erased from the Delinquent Load dedicated cache memory.

  Therefore, when data is loaded by Delinquent Load, data is loaded from the cache memory dedicated to Delinquent Load, so that a cache miss does not occur and a cache hit always occurs. By doing so, it is not necessary to access the main memory at the time of data loading for Delinquent Load, and it is possible to avoid occurrence of memory latency. As a result, it is possible to prevent a decrease in processing efficiency of the CPU.

  Embodiment 1 of the present invention will be described below with reference to FIGS. The first embodiment shows a case where a CSDB (Corresponding Store Data Buffer) is adopted as the above-described Delinquent Load dedicated cache memory. Corresponding Store is a store instruction corresponding to a load instruction. Therefore, CSDB is a data buffer that stores store data of a store instruction corresponding to a load instruction. Note that data loading means reading of data from the cache storage unit 102 that is a cache memory or an external main storage unit that is a main memory. The data store refers to data writing to the cache storage unit 102 or an external main storage unit.

  First, the configuration of the information processing apparatus according to the first embodiment will be described. FIG. 3 is a functional block diagram illustrating the configuration of the information processing apparatus according to the first embodiment. FIG. 4 is a diagram illustrating a table image of the Delinquent Load Table in the DLT unit of the information processing apparatus according to the first embodiment. FIG. 5 is a table image of the Corresponding Store Data Buffer in the CSDB unit of the information processing apparatus according to the first embodiment.

  As shown in FIG. 3, the information processing apparatus 100 includes a main processing unit 101 that is a CPU core, a cache storage unit 102 that is a cache memory, a CSDB unit 103, a DLT unit 104, and a CSI unit 105.

  The main processing unit 101 performs various calculations based on data loaded from the cache storage unit 102 or the external main storage device in the information processing apparatus 100, and stores the calculation results in the cache storage unit 102 and the external main storage device Execute.

As shown in FIG. 5, the CSDB unit 103 is a data buffer that stores an operand address V _ij (i and j are natural numbers) designated by a store instruction corresponding to Delinquent Load and data DATA _ij associated with the V _ij. is there. When the main processing unit 101 designates the operand address VA and executes the load instruction, the main processing unit 101 first checks whether or not there is an operand address VA _ij that matches the designated operand address with reference to the CSDB unit 103. To do. When an operand address matching the operand address VA _ij specified by the load instruction exists in the CSDB 103, the data DATA _ij corresponding to this operand address is loaded from the CSDB 103.

A DLT (Delinquent Load Table) unit 104 is a mechanism for identifying and holding a Delinquent Load. Specifically, as shown in FIG. 4, operand addresses VA ₁₁ , VA ₁₂ ,..., VA _1n and cache miss count N ₁ are stored in association with the program counter PC ₁ that is a Load identifier. Yes. Further, operand addresses VA _i1 ,..., VA _im (m is a natural number) and cache miss number N _i are stored in association with each other in a program identifier PC _i (i is a natural number) as a Load identifier. .

  When the DLT unit 104 is instructed to load data from the main processing unit 101 to the cache storage unit 102 by a load instruction, the load instruction is stored by the main processing unit 101 together with an operand address. Further, when a data load is instructed from the main processing unit 101 to the cache storage unit 102 by a load instruction, when a cache miss occurs in the cache storage unit 102, the main processing unit 101 adds 1 to the number of cache misses. Is done.

Note that the number of operand addresses VA _im stored in association with each program counter PC _i differs depending on the program counter PC _i . The number of cache misses N _i stored in association with each program counter PC _i is a variable that holds a numerical value counted up in units of program counter PC _i . That is, the number of cache misses is counted regardless of the operand address if the operand address is associated with the same Load identifier.

A CSI (Corresponding Store Identifier) unit 105 is a mechanism for identifying a store instruction (Corresponding Store) that generates memory data to be loaded by Delinquent Load. When the main processing unit 101 designates an operand address and a store instruction is instructed, the DLT unit 104 is referenced to determine whether or not the operand address is stored in the DLT unit 104. Further, when it is determined that the operand address is stored in the DLT unit 104, it is determined whether or not the number of cache misses associated with the operand address exceeds a given threshold M (M is a natural number). judge. The data targeted by the load instruction identified by the Load identifier corresponding to the operand address VA _ij determined to exceed the given threshold M is the CSDB unit 103 together with the operand address VA _ij as the data targeted by the Delinquent Load. Will be stored.

  Next, a logic circuit of the CSI unit of the information processing apparatus according to the first embodiment will be described. FIG. 6 is a circuit diagram illustrating a logic circuit of the CSI unit of the information processing apparatus according to the first embodiment. As shown in the figure, the CSI unit 105 includes a coincidence determination gate 105a, a comparison determination gate 105b, and an AND gate 105c.

When the store instruction Store VA specifying the operand address VA is output from the main processing unit 101 to the CSI unit 105, the match determination gate 105a first refers to the DLT unit 104 to store the operand address that matches VA. It is determined whether or not. When an operand address VA _ij that matches VA exists in the DLT unit 104, the comparison determination gate 105b determines the number of cache misses N _i stored in association with the operand address VA _ij and a given threshold value. Compare with M and determine whether N _i > M. The match determination operand address that matches the gate 105a is determined that there exists, and comparison determination if it is determined that N _i> M by the gate 105b, the operand address VA _ij and said operand address VA _ij by AND gate 105c DATA _ij , which is actual data specified by the above, is stored in the CSDB unit 103.

  Next, processing in the information processing apparatus according to the first embodiment will be described. FIG. 7 is a timing chart illustrating processing in the information processing apparatus according to the first embodiment. Each step shown in FIG. 7 represents one step in pipe processing. As shown in the figure, first, instruction fetch from the main processing unit 101 (step S101), instruction decode (step S102), address calculation (step S103), CSDB access (step S104), Cache access is executed (step S105).

  Subsequently, a Load command is added to the DLT 104 (step S106). Further, when a cache miss occurs in the cache access in step S105, main memory access is executed (step S107). When the main memory access in step S107 is completed, register write is executed in the main processing unit 101 (step S108). The processes in steps S101 to S108 are processes related to the first stage Load command as shown in the figure.

  When step S108 ends, the main processing unit 101 subsequently executes instruction fetch (step S109), instruction decode (step S110), address calculation (step S111), and DLT access (step S112). Is called. Subsequent to the end of address calculation in step S111, main memory access is executed (step S113), and after completion of DLT access in step S112, CSDB update is executed (step S114). In addition, the process of step S113 and the process of step S114 may be performed in parallel. The processes in steps S109 to S114 are processes related to the second stage Store instruction as shown in the figure.

  When step S114 ends, the main processing unit 101 executes instruction fetch (step S115), instruction decode (step S116), address calculation (step S117), CSDB, and the third stage Load instruction. Access execution (step S118) is executed. At the time of execution of step S118, since the data to be loaded by the Load instruction is already stored in the CSDB in step S114, the data is successfully read from the CSDB. Subsequently, the data successfully read from the CSDB is written to the register of the main processing unit 101 (step S119).

  As described above, in the first embodiment, a cache miss occurs once due to the load instruction, and the load target data stored in the CSDB is stored in the CSDB at the next execution of the same load instruction. Since the data stored in is read and loaded, it is possible to suppress the occurrence of memory latency in memory access due to a cast miss.

  A second embodiment of the present invention will be described below with reference to FIGS. The second embodiment is basically the same as the first embodiment, and in the following description of the second embodiment, differences from the first embodiment will be described. In the second embodiment, a case where a CAB (Corresponding Store Address Buffer) is adopted as the above-described Delinquent Load dedicated cache memory is shown. Corresponding Store is a store instruction corresponding to a load instruction. Accordingly, the CSAB is an address buffer that stores an address for specifying a load instruction corresponding to a store instruction corresponding to a Delinquent Load instruction.

  First, the configuration of the information processing apparatus according to the second embodiment will be described. FIG. 8 is a functional block diagram illustrating the configuration of the information processing apparatus according to the second embodiment. FIG. 9 is a diagram illustrating a table image of the Corresponding Store Address Buffer of the CTAB unit of the information processing apparatus according to the second embodiment. Note that the Delinquent Load Table of the DLT unit of the information processing apparatus of the second embodiment is the same as that of the first embodiment.

  As shown in FIG. 3, the information processing apparatus 100 includes a main processing unit 101 that is a CPU core, a cache storage unit 102 that is a cache memory, a CAB unit 106, a DLT unit 104, and a CSI unit 105.

As shown in FIG. 9, the CAB unit 106 includes a program counter PC _i (i is a natural number) that is a load identifier corresponding to a store instruction corresponding to a Delinquent Load and an operand address V _ij (j is a natural number) specified by the store instruction. ) Is stored. When the main processing unit 101 designates the program counter PC and executes the load instruction, the main processing unit 101 first determines whether or not a program counter matching the designated program counter PC is stored with reference to the CTAB unit 106. To do. If a matching program counter PC is detected here, it is determined that the re-execution of Delinquent Load is approaching.

Next, the CSDB unit 106 pre-fetches data specified by the operand address VA _ij associated with the program counter PC for which a match is detected previously from the main storage unit (main memory) ( (Cache memory) 102 is requested.

  Next, a logic circuit of the CSI unit of the information processing apparatus according to the second embodiment will be described. FIG. 10 is a circuit diagram illustrating a logic circuit of the CSI unit of the information processing apparatus according to the second embodiment. As shown in the figure, the CSI unit 105 includes a coincidence determination gate 105a, a comparison determination gate 105b, and an AND gate 105c.

The CSI unit 105 is a mechanism for identifying a store instruction (Corresponding Store) that generates memory data to be loaded by Delinquent Load. When the main processing unit 101 designates an operand address and a store instruction is instructed, the DLT unit 104 is referenced to determine whether or not the operand address is stored in the DLT unit 104. Further, when it is determined that the operand address is stored in the DLT unit 104, it is determined whether or not the number of cache misses associated with the operand address exceeds a given threshold M (M is a natural number). judge. The program counter PC _i is a Load identifier of the load instruction identified by the program counter PC _i is a Load identifier corresponding to the operand address VA _ij that is determined to exceed a given threshold M with operand address VA _ij as Delinquent Load It is stored in the CAB unit 106.

  Next, processing in the information processing apparatus according to the second embodiment will be described. FIG. 11 is a timing chart illustrating processing in the information processing apparatus according to the second embodiment. Each step shown in FIG. 11 represents one step in pipe processing. As shown in the figure, first, instruction fetch execution (step S201), instruction decode execution (step S202), address calculation execution (step S203), and cache access execution (step S204) from the main processing unit 101 are performed. Done.

  Subsequently, a Load command is added to the DLT 104 (step S205). Further, when a cache miss occurs in the cache access in step S204, main memory access is executed (step S206). When the main memory access in step S206 is completed, register write is executed in the main processing unit 101 (step S207). The processes in steps S201 to S207 are processes related to the first stage Load command as shown in the figure.

  When step S207 ends, the main processing unit 101 subsequently executes instruction fetch (step S208), instruction decode (step S209), address calculation (step S210), and DLT access (step S211). Is called. Subsequent to the end of address calculation in step S210, main memory access is executed (step S212), and following completion of DLT access in step S211, CTAB update is executed (step S213). In addition, the process of step S212 and the process of step S213 may be performed in parallel. The processes in steps S208 to S213 are processes related to the second stage Store instruction as shown in the figure.

  When step S213 is completed, the main processing unit 101 executes instruction fetch (step S214), instruction decode (step S215), address calculation (step S216), and cache in the third stage Load instruction. Access is executed (step S217).

  On the other hand, simultaneously with the instruction fetch in step S214, a CSAB access is executed (step S218), and the main memory access is executed following the end of step S218 (step S219).

  When the memory access in step S219 ends, the data is successfully read from the cache storage unit 102 based on the cache access in step S217. Subsequently, the data successfully read from the cache storage unit 102 is written to the register of the main processing unit 101 (step S220).

  As described above, in the second embodiment, a cache miss occurs once due to the load instruction, and the operand address that specifies the data to be loaded by the load instruction determined to be Delinquent Load is stored in the CTAB together with the program counter PC of the load instruction. . Then, since the prefetch of the required data is requested based on the operand address stored in the CSAB in parallel with the instruction fetch at the next execution of the same load instruction, it is predicted that the execution of Delinquent Load is approaching. Thus, necessary data can be stored in the cache memory in advance, and it is possible to suppress the occurrence of memory latency in memory access due to a miss.

  The method shown in the second embodiment exhibits superiority as the processing time of step S215 and step S216 is longer. Regardless of whether or not the processing of step S216 is completed, at the same time as the instruction fetch of step S214, the CAB access of step S218 is executed in advance to perform memory access, and the necessary data is cached in advance. This is because the memory can be prefetched.

  The main processing unit 101, the CSDB unit 103, the DLT unit 104, the CSI unit 105, and the CAB unit 106 corresponding to the CPU core shown in the first and second embodiments correspond to the instruction control mechanism, and the instruction control mechanism includes the cache storage unit 102. The information including the number corresponds to the information processing apparatus.

  As mentioned above, although the Example of this invention was described, this invention is not limited to this, In the range of the technical idea described in the claim, even if it implements in a various different Example, it is. It ’s good. Moreover, the effect described in the Example is not limited to this.

(Appendix 1) An information processing apparatus in which a cache device is arranged between the main storage device and
An information processing apparatus comprising: a load instruction storage unit for storing a load instruction in an identifiable manner when a cache miss occurs in the cache apparatus due to a load instruction for reading data from the main storage device.

(Supplementary note 2) The information processing apparatus according to supplementary note 1, wherein the load instruction storage unit stores the number of times a cache miss has occurred for each load instruction in which a cache miss has occurred in the cache apparatus.

(Supplementary Note 3) When writing data to the main storage device in response to a store instruction for writing data to the main storage device, the load instruction corresponding to the store instruction is identified, and the load instruction is stored in the load instruction storage unit. A load instruction storage determination unit for determining whether or not to be stored;
A cache miss number determination unit that determines whether or not the number of times that the load instruction determined to be stored in the load instruction storage unit by the load instruction storage determination unit has caused a cache miss exceeds a predetermined threshold;
A data storage unit that caches data to be read or a data identifier that identifies the load instruction that is determined by the cache miss number determination unit that the number of times that a cache miss has occurred exceeds a predetermined threshold. The information processing apparatus according to supplementary note 2, which is characterized.

(Supplementary note 4) The information processing apparatus according to supplementary note 3, wherein when the load instruction for reading data from the main storage device is executed, data to be read by the load instruction is read from the data storage unit.

(Supplementary Note 5) Before executing a load instruction for reading data from the main storage device, the data to be read by the load instruction from the data storage unit is read from the main storage device based on a data identifier for identifying the data. The information processing apparatus according to appendix 3, wherein the information is read out in advance to a cache apparatus.

(Appendix 6) An instruction control mechanism for controlling a load instruction in an information processing apparatus in which a cache device is arranged between the main storage device,
An instruction control mechanism comprising: a load instruction storage unit for storing a load instruction in an identifiable manner when a cache miss occurs in the cache device by a load instruction for reading data from the main storage device.

(Supplementary note 7) The instruction control mechanism according to supplementary note 6, wherein the load instruction storage unit stores the number of times a cache miss has occurred for each load instruction in which a cache miss has occurred in the cache device.

(Supplementary Note 8) When writing data to the main storage device in response to a store instruction for writing data to the main storage device, the load instruction corresponding to the store instruction is identified, and the load instruction is stored in the load instruction storage unit. A load instruction storage determination unit for determining whether or not to be stored;
A cache miss number determination unit that determines whether or not the number of times that the load instruction determined to be stored in the load instruction storage unit by the load instruction storage determination unit has caused a cache miss exceeds a predetermined threshold;
A data storage unit that caches data to be read or a data identifier that identifies the load instruction that is determined by the cache miss number determination unit that the number of times that a cache miss has occurred exceeds a predetermined threshold. The instruction control mechanism according to appendix 7, which is characterized in that.

(Supplementary note 9) An instruction control method for controlling a load instruction in an information processing device in which a cache device is arranged between the main storage device,
An instruction control method comprising a load instruction storing step of storing a load instruction in an identifiable manner when a cache miss occurs in the cache apparatus by a load instruction for reading data from the main storage device.

(Supplementary note 10) The instruction control method according to supplementary note 9, wherein the load instruction storing step stores the number of times the cache miss has occurred for each load instruction in which a cache miss has occurred in the cache device.

(Supplementary Note 11) When writing data to the main storage device in response to a store instruction for writing data to the main storage device, the load instruction corresponding to the store instruction is identified, and the load instruction is stored in the cache miss storage step. A load instruction storage determination step for determining whether or not it has been stored;
A cache miss number determination step of determining whether or not the number of times that the load instruction that has been determined to be stored in the cache miss storage step by the load instruction storage determination step causes a cache miss exceeds a predetermined threshold;
A data storage step for caching data to be read or a data identifier for identifying the data to be read by the load instruction determined that the number of occurrences of the cache miss exceeds a predetermined threshold in the cache miss number determination step. The instruction control method according to appendix 10, which is characterized by the following.

  The present invention is useful when it is desired to reduce the influence of memory latency caused by accessing a main memory due to a cache miss of a load instruction in a simple and small circuit without requiring special hardware, and in particular, Delinquent This is effective when you want to reduce the impact of memory latency due to Load cache misses.

It is a figure which shows the problem of a prior art. It is a figure which shows the feature point of this invention. 1 is a functional block diagram illustrating a configuration of an information processing apparatus according to a first embodiment. It is a figure which shows the table image of Delinquent Load Table of the DLT part of the information processing apparatus of Example 1. FIG. It is a figure which shows the table image of Corresponding Store Data Buffer of the CSDB part of the information processing apparatus of Example 1. FIG. 3 is a circuit diagram illustrating a logic circuit of a CSI unit of the information processing apparatus according to the first embodiment. 3 is a time chart illustrating processing in the information processing apparatus according to the first exemplary embodiment. FIG. 6 is a functional block diagram illustrating a configuration of an information processing apparatus according to a second embodiment. It is a figure which shows the table image of Corresponding Store Address Buffer of the CSAB part of the information processing apparatus of Example 2. FIG. 10 is a circuit diagram illustrating a logic circuit of a CSI unit of the information processing apparatus according to the second embodiment. 10 is a time chart illustrating processing in the information processing apparatus according to the second embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Information processing apparatus 101 Main processing part 102 Cache storage part 103 CSDB part 104 DLT part 105 CSI part 105a Match determination gate 105b Size determination gate 105c AND gate 106 CSAD part

Claims (5)

Cache memory to hold data,
An instruction processing unit for executing a load instruction for reading data from the cache memory;
When a cache miss occurs in the cache memory due to the load instruction executed by the instruction processing unit, program counter information for identifying a load instruction in which a cache miss has occurred, and one or more operands corresponding to the program counter information An instruction storage unit that stores an address and the number of cache misses in which a load instruction for the one or more operand addresses has caused a cache miss for each load instruction in which a cache miss has occurred ;
A storage determination unit that determines whether program counter information for identifying a load instruction corresponding to the store instruction is stored in the instruction storage unit when executing a store instruction to write data to the cache memory;
A cache miss number determination unit that determines whether or not the cache miss number corresponding to the program counter information determined by the storage determination unit to be stored in the instruction storage unit exceeds a predetermined value;
The cache miss number determination unit includes an operand address of a load instruction identified by program counter information determined that the cache miss number exceeds a predetermined value, and program counter information determined that the cache miss number exceeds a predetermined value. An arithmetic processing unit comprising: a data storage unit that holds a set of data to be written by a store instruction corresponding to an identified load instruction . Cache memory to hold data,
An instruction processing unit for executing a load instruction for reading data from the cache memory;
When a cache miss occurs in the cache memory due to the load instruction executed by the instruction processing unit, program counter information for identifying a load instruction in which a cache miss has occurred, and one or more operands corresponding to the program counter information An instruction storage unit that stores an address and the number of cache misses in which a load instruction for the one or more operand addresses has caused a cache miss for each load instruction in which a cache miss has occurred ;
A storage determination unit that determines whether program counter information for identifying a load instruction corresponding to the store instruction is stored in the instruction storage unit when executing a store instruction to write data to the cache memory;
A cache miss number determination unit that determines whether or not the cache miss number corresponding to the program counter information determined by the storage determination unit to be stored in the instruction storage unit exceeds a predetermined value;
The store corresponding to the load instruction identified by the program counter information determined by the cache miss number determination unit that the cache miss number exceeds a predetermined value and the program counter information determined that the cache miss number exceeds a predetermined value An arithmetic processing unit comprising: a data storage unit that holds a pair with an operand address of an instruction . In an information processing apparatus having a main storage device and an arithmetic processing device connected to the main storage device,
The arithmetic processing unit includes:
Cache memory to hold data,
When a load instruction for reading data from the main memory or the cache memory is executed and a cache miss occurs in the cache memory, program counter information for identifying the load instruction in which the cache miss has occurred, and corresponding to the program counter information An instruction storage unit that stores, for each load instruction in which a cache miss has occurred, and one or more operand addresses that perform, and a cache miss number in which the load instruction for the one or more operand addresses has generated a cache miss ;
A storage determination unit that determines whether program counter information for identifying a load instruction corresponding to the store instruction is stored in the instruction storage unit when executing a store instruction to write data to the cache memory;
A cache miss number determination unit that determines whether or not the cache miss number corresponding to the program counter information determined by the storage determination unit to be stored in the instruction storage unit exceeds a predetermined value;
The cache miss number determination unit includes an operand address of a load instruction identified by program counter information determined that the cache miss number exceeds a predetermined value, and program counter information determined that the cache miss number exceeds a predetermined value. An information processing apparatus comprising: a data storage unit that holds a pair with data to be written by a store instruction corresponding to an identified load instruction . In an information processing apparatus having a main storage device and an arithmetic processing device connected to the main storage device,
The arithmetic processing unit includes:
Cache memory to hold data,
When a load instruction for reading data from the main memory or the cache memory is executed and a cache miss occurs in the cache memory, program counter information for identifying the load instruction in which the cache miss has occurred, and corresponding to the program counter information An instruction storage unit that stores, for each load instruction in which a cache miss has occurred, and one or more operand addresses that perform, and a cache miss number in which the load instruction for the one or more operand addresses has generated a cache miss ;
A storage determination unit that determines whether program counter information for identifying a load instruction corresponding to the store instruction is stored in the instruction storage unit when executing a store instruction to write data to the cache memory;
A cache miss number determination unit that determines whether or not the cache miss number corresponding to the program counter information determined by the storage determination unit to be stored in the instruction storage unit exceeds a predetermined value;
The store corresponding to the load instruction identified by the program counter information determined by the cache miss number determination unit that the cache miss number exceeds a predetermined value and the program counter information determined that the cache miss number exceeds a predetermined value An information processing apparatus comprising: a data storage unit that holds a pair with an operand address of an instruction . In an arithmetic processing unit having a cache memory for holding data,
The instruction processing unit included in the arithmetic processing unit executes a load instruction for reading data from the cache memory,
When a cache miss occurs in the cache memory due to the load instruction executed by the instruction processing unit, program counter information for identifying a load instruction in which a cache miss has occurred, and one or more operands corresponding to the program counter information The instruction storage unit of the arithmetic processing unit stores the address and the number of cache misses in which the load instruction for the one or more operand addresses has caused a cache miss for each load instruction in which a cache miss has occurred ,
When the storage determination unit included in the arithmetic processing unit executes a store instruction that writes data to the cache memory, is program counter information that identifies a load instruction corresponding to the store instruction stored in the instruction storage unit? Determine
The cache miss number determination unit included in the arithmetic processing unit determines whether the cache miss number corresponding to the program counter information determined to be stored in the instruction storage unit exceeds a predetermined value,
The data storage unit of the arithmetic processing unit determines the operand address of the load instruction identified by the program counter information determined that the number of cache misses exceeds a predetermined value, and the program determined that the number of cache misses exceeds a predetermined value A control method for an arithmetic processing unit, characterized by holding a pair with data written by a store instruction corresponding to a load instruction identified by counter information .

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