JP5108578B2 - Image processing controller and image forming apparatus - Google Patents

Description

  The present invention relates to an image processing controller including a plurality of interfaces and an image forming apparatus including the image processing controller.

  In general, an image processing apparatus such as a printer or a copier is generally configured to connect an engine unit to a controller ASIC and perform image formation processing from a CPU connected to the controller ASIC via the controller ASIC. is there. For example, the controller ASIC and the engine unit are connected by a bus called a PCI interface, a CPU is connected to the controller ASIC, and print processing, copy processing, and the like are performed under the control of the CPU. The controller ASIC and the CPU are generally connected via a chipset since the recent CPU does not disclose the interface of the CPU itself. At that time, the chipset and the controller ASIC are connected to each other. Are connected by a PCI interface.

  The performance of the image forming apparatus as described above is determined by the data transfer speed in the PCI interface. However, the performance of the PCI interface via the chipset is low and the performance of the image forming apparatus such as a printer or a copier is lowered. .

  In recent years, a bus called a PCI-EXPRESS interface that enables high-speed data transfer compared to a PCI interface has become available. The use of PCI-EXPRESS makes it possible to improve the performance of image forming apparatuses such as printers and copiers.

  A technique related to an image forming apparatus configured by connecting a controller ASIC and an engine unit via a PCI interface and further connecting a controller ASIC and a CPU via a chip set is described in, for example, Patent Document 1 and the like. It has been.

JP 2003-309680 A

  The above-described prior art using PCI-EXPRESS requires that the controller ASIC be equipped with a PCI-EXPRESS interface, but if the controller ASIC is configured with only the PCI-EXPRESS interface, an engine (scanner) that supports the PCI interface. , Plotter, etc.) becomes impossible to use. In order to solve such a problem, it is preferable to provide a PCI interface and a PCI-EXPRESS interface in the controller ASIC. However, in this case, it is necessary to control the data transfer path in the controller ASIC. However, conventionally, a technique of providing a PCI interface and a PCI-EXPRESS interface in the controller ASIC and controlling a data transfer path in the controller ASIC is not known.

  An object of the present invention is to improve availability by providing a plurality of interfaces, a PCI interface (hereinafter simply referred to as PCI) and a PCI-EXPRESS interface (hereinafter simply referred to as PCI-EXPRESS), and to use data using both interfaces. An image processing controller and an image forming apparatus capable of controlling a transfer path are provided.

In order to achieve the above object, the first means of the image processing controller of the present invention is to connect an engine including a scanner and a plotter and a CPU connected via a chipset to transfer image data and image data. When an image processing controller that processes data is connected to a PCI-EXPRESS endpoint controller that controls communication with the chipset via a PCI-EXPRESS interface and the engine via a PCI-EXPRESS interface, A PCI-EXPRESS route complex controller that controls communication with the engine, and a PCI controller that controls communication with the engine when connected to the engine via a PCI interface. The EXPRESS endpoint controller is connected to the chipset from the CPU. The receiving access to the engine on behalf, to resources connected to the image processing controller, to suppress the reference from the CPU, the PCI controller and PCI-EXPRESS via image processing controller from the connected CPU via According to whether the engine is connected to any one of the root complex controllers, it has a function of suppressing reference from the engine to unnecessary resources .

The second means of the image processing controller of the present invention connects an engine including a scanner and a plotter and a CPU connected via a chipset to transfer image data and process image data. When the image processing controller is connected to a PCI-EXPRESS endpoint controller that controls communication with the chipset via the PCI-EXPRESS interface and the engine via the PCI-EXPRESS interface, PCI-EXPRESS end point controller comprising: a PCI-EXPRESS root complex controller that controls communication with a PCI controller that controls communication with the engine when connected to the engine via a PCI interface Is connected from the CPU via the chipset The access from the CPU to the engine via the image processing controller is received on behalf, the reference from the CPU to the resource connected to the image processing controller is suppressed, and the PCI-EXPRESS root complex controller and the PCI controller are: The memory access from the engine is converted into access to the memory connected to the chipset, and depending on whether the engine is connected to either the PCI controller or the PCI-EXPRESS root complex controller, an unnecessary resource is accessed. , Has a function of suppressing reference from the engine .

The third unit of the image processing controller of the present invention, in was first or second means, with respect to the PCI controller from the PCI-EXPRESS root complex controller, an address via the resources of a fixed address It has a bridge function for bridging.

According to a fourth means of the image processing controller of the present invention, in any one of the first to third means, a plurality of arbiter control sections that perform arbitration with different algorithms, and the PCI-EXPRESS route complex And a selection unit that selects the arbiter control unit that performs arbitration between the controller and the engine according to the number of lanes.

The image forming apparatus according to the present invention is an image processing controller that connects an engine including a scanner and a plotter and a CPU connected via a chipset to transfer image data and process image data. When the PCI-EXPRESS endpoint controller that controls communication with the chipset via the PCI-EXPRESS interface is connected to the engine via the PCI-EXPRESS interface, the communication between the engine is controlled. When connected to the PCI-EXPRESS root complex controller and the engine via a PCI interface, a PCI controller that controls communication with the engine , a plurality of arbiter controllers that perform arbitration using different algorithms, and the PCI -EXPRESS root complex controller and previous Between the engine according to the number of lanes, comprises a selector for selecting the arbiter control section for arbitration, said PCI-EXPRESS endpoint controller is connected via the chip set from the CPU An image processing controller is provided that accepts access to the engine from the CPU via the image processing controller by proxy, and suppresses reference from the CPU to resources connected to the image processing controller.

  According to the present invention, by providing PCI and PCI-EXPRESS, it is possible to improve availability and control the data transfer path using both interfaces.

  Hereinafter, embodiments of an image processing controller and an image forming apparatus according to the present invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing the configuration of the image forming apparatus according to the first embodiment, FIG. 2 is a block diagram showing the configuration of the controller ASIC, and FIG. 3 shows the registers, engines, and optional resources of the controller ASIC itself as PCI-EXPRESS and FIG. 4 is a diagram for explaining the contents of a dedicated register of the controller ASIC, and FIG. 5 is a base address on the PCI-EXPRESS root complex controller side of the controller ASIC. FIG. 6 is a diagram for explaining the relationship between offset values from two base addresses on the PCI side of the controller ASIC and resources to be arranged.

  In the image forming apparatus according to the first embodiment, as shown in FIG. 1, the controller ASIC 101 is an engine 106 such as a scanner or a plotter via a PCI-EXPRESS 108 and an external I / F such as IEEE1394 via a PCI 109. Are connected to the option 107, are connected to the HDD 105, and are connected to the chip set 102 via the PCI-EXPRESS 110. Further, the chip set 102 of the image forming apparatus is connected to the CPU 103 and the memory 104.

  As shown in FIG. 2, the controller ASIC 101 includes a PCI-EXPRESS end point controller 201 that connects the chipset 102 via the PCI-EXPRESS 110 and a PCI-EXPRESS root complex controller 217 that connects the engine 106 via the PCI-EXPRESS 108. And a PCI controller 221 for connecting the option 107 via the PCI 109 as main elements.

  The PCI-EXPRESS endpoint controller 201 includes a target circuit 202 including a configuration register 204 and a master circuit 203, and the engine via the controller ASIC from the CPU 103 connected from the CPU 103 via the chipset 102. 106, the access to the option 107 is accepted by proxy, and the resource connected to the controller ASIC 101 has a function of suppressing the reference from the CPU 103.

  The master circuit 203 performs data control with an external device (for example, the chipset 102) connected via the bus. Data transfer is realized when the master circuit 203 requests the target circuit of the external device to transfer data.

  The target circuit 202 includes a configuration register 204, receives a data transfer request from a master circuit of an external device (for example, the chip set 102), and performs control for performing data transfer. The configuration register 204 holds an accessible device address and the like.

  Similar to the controller 201, the PCI-EXPRESS root complex controller 217 includes a target circuit 218 including a configuration register 220 and a master circuit 219, and image data between the engine 106 connected via the PCI-EXPRESS 108. Give and receive.

  Similarly to the controllers 201 and 217, the PCI controller 221 includes a target circuit 222 including a configuration register 224 and a master circuit 223, and exchanges image data with an option 107 connected via the PCI 109. I do.

  The PCI-EXPRESS route complex controller 217 and the PCI controller 221 convert the memory access from the engine 106 and the option 107 into access to the memory 104 connected to the chipset 102, and from the engine and the option for unnecessary resources. It has a function to deter reference.

  The PCI-EXPRESS end point controller 201 described above accesses the memory 104 via the chipset 102 under the control of the CPU 103 to control the transfer of image data, and the PCI-EXPRESS root complex controller 217 and the PCI controller. The data transfer control and the data transfer path control with the 221 are executed jointly with the PCI-EXPRESS route complex controller 217 and the PCI controller 221, and connected to the PCI-EXPRESS route complex controller 217 and the PCI controller 221. The processing of the image data is realized by controlling the engine 106 and the option 107.

  The PCI-EXPRESS endpoint controller 201, the PCI-EXPRESS route complex controller 217, and the PCI controller 221 have an image input buffer 214, an image output, and the like for the above-described data transfer control and data transfer path control. Buffer 215, bridge transfer controller 216, target access address decoder 206, PCI-EXPRESS direct access controller 207, image input DMA controller 208, image output DMA controller 209 including decompressor 210, PCI direct access controller 211, HDD controller 212, DMA A controller 213 and an arbiter 205 are provided.

  Next, the operation in the first embodiment configured as described above will be described. The operations described below are common to image forming apparatuses according to second and third embodiments of the present invention described later.

Activation to Detection / Setting of Controller ASIC When the image forming apparatus shown in FIG. 1 is activated, BIOS software (not shown) first executes PCI device enumeration including PCI-EXPRESS. Specifically, the BIOS software assigns the bus number and the device number, reads the device / vendor ID register of the configuration register 220 in the PCI-EXPRESS route complex controller 217 and the configuration register 224 in the PCI controller 221, and this value is If it is other than 0xffffffff, it is recognized that the device exists (the engine 106 connected to the PCI-EXPRESS root complex controller 217 and the option 107 connected to the PCI controller 221 exist).

  Next, resources (capacities of memory space and I / O space) are allocated to the option 107 that is the PCI device detected as described above and the engine 106 that is the PCI-EXPRESS device. Specifically, the capacity of the memory space and I / O space required by this device is recognized from the configuration register 220 in the PCI-EXPRESS root complex controller 217 and the base address register of the configuration register 224 in the PCI controller 221. Cut out from the available memory space and set its address in this base address register. In the above, one device may have a plurality of base address registers.

  The controller ASIC 101 has one base address register, and the registers of the controller ASIC 101 and the engine and optional resources are mapped in this range as PCI-EXPRESS, PCI memory space, and I / O space. FIG. 3 shows the state of this mapping, and the PCI-EXPRESS memory space, PCI-EXPRESS I / O space, PCI memory space, PCI / O space, and register space are mapped to the memory area of the ASIC resource.

Settings on the engine / option side After the various settings of the controller ASIC are completed in the above-described processing from the startup to the detection / setting of the controller ASIC, PCI-EXPRESS and PCI settings on the engine side and the option side are set.

  The access to the configuration register 220 in the PCI-EXPRESS route complex controller 217 on the engine 106 side and the access to the configuration register 224 in the PCI controller 221 on the option 107 side are performed by the controller ASIC as shown in FIG. This is done via a dedicated register.

  As shown in Figure 4, by setting the bus number to BUS_NUM, device number to DEV_NUM, function number to FN_NUM, register number to REG_ADR for the address register (PCI-CONFIG ADDRESS), and reading the data register, Config write access is performed by writing to the data register.

  By reading the configuration register 220 in the PCI-EXPRESS root complex controller 217 and the configuration register 224 in the PCI controller 221 by the method described above, device detection and resource allocation to the base address register are performed.

  The PCI-EXPRESS route complex controller 217 of the controller ASIC 101 has one base address resource, and resources are arranged as shown in FIG. That is, the offset value from the base address is + 00h, + 08h, + 10h, + 18h, + 20h, + 30h, + 40h, and the image output channel 1, the image output channel 2, the image output channel 3, the image Output channel 4, image input channel, bridge write channel, bridge read channel are arranged

  The PCI controller 221 of the controller ASIC 101 has two base addresses, and resources are arranged as shown in FIG. That is, for one base address, as shown in FIG. 6, as in the case shown in FIG. 5, offset values from the base address are + 00h, + 08h, + 10h, + 18h, + 20h. The image output channel 1, the image output channel 2, the image output channel 3, the image output channel 4, and the image input channel are arranged at the positions.

  Both the PCI-EXPRESS route complex controller 217 and the PCI controller 221 have fixed address resources for image input and image output. However, the engine that requires the image input resource and the image output resource is connected to either the PCI-EXPRESS or the PCI, so which form is used to the controller ASIC 101 by an external terminal. In advance, the image input resource and the image output resource can be accessed only from the side to which the engine is connected.

Memory to image output path (including decompression)
Next, image output processing via an image output path (including decompression) will be described. The explanation here assumes that the output image or code is stored in the memory 104 connected to the chipset 102.

  The software is activated by setting the register of the image output DMA controller 209. The image output DMA controller 209 accesses the master circuit 203 of the PCI-EXPRESS endpoint controller 201 via the arbiter 205, generates a PCI-EXPRESS memory read transaction, and accesses the memory 104 in which the image is stored. .

  Data read from the memory 104 is stored in the image output buffer 215. When the image is encoded and stored in the memory 104, the image output DMA controller 209 expands the encoded data using the expander 210 and then stores it in the image output buffer 215.

  The separately started engine 106 accesses the image output resource to the target circuit 222 of the PCI controller of the controller ASIC 101 or the target circuit 218 of the PCI-EXPRESS root complex controller 217 via PCI or PCI-EXPRESS.

  By accessing the image output resource described above, data in the image output buffer 215 is extracted and returned to the engine 106 as response data.

Image Input-Memory Path Next, image input processing via the memory path will be described.

  The software is activated by setting the register of the image input DMA controller 208. The image input DMA controller 208 takes in the data input from the scanner by the engine 106 by performing write access to the image input resource of the PCI controller 221 of the controller ASIC 101 or the PCI-EXPRESS route complex controller 217, and transfers it to the image input resource. The data fetched by the write access is sequentially stored in the image input buffer 214.

  As long as there is data in the image input buffer 214, the image input DMA controller 208 reads it and writes it to a preset address (on the chip set side memory).

  For the write to the memory 104 connected to the chipset 102, the request is sent to the master circuit 203 of the PCI-EXPRESS endpoint controller 201 via the arbiter 205, and a PCI-EXPRESS transaction is generated. Writing to the memory 104 connected to the set 102 is performed.

PCI-EXPRESS Direct Access Path Next, an access process that does not correspond to an image input resource or an image output resource from the engine 106 connected by PCI-EXPRESS will be described.

  In the access from the engine 106 connected by PCI-EXPRESS to the controller ASIC 101, the access not corresponding to the image input resource and the image output resource is interpreted as the access to the chipset 102 side, and the PCI-EXPRESS direct access controller 207, As a master access from the PCI-EXPRESS endpoint controller 201 via the arbiter 205, a PCI-EXPRESS transaction for the chipset 102 is generated, and the memory 104 connected to the chipset 102 is accessed.

PCI Direct Access Path Next, direct memory access processing from options connected by PCI will be described.

  Access from the option 107 connected by PCI to the controller ASIC 101 is interpreted as access to the direct memory access resource as access to the chipset 102 side, and the PCI-EXPRESS end via the PCI direct access controller 211 and the arbiter 205 As a master access from the point controller 201, a PCI-EXPRESS transaction for the chipset 102 is generated, and the memory 104 connected to the chipset 102 is accessed.

  The above description from the startup to the process of detecting / setting the controller ASIC up to this point has been described as the same operation in the second and third embodiments described later. By the way, as described above, the image forming apparatus according to the first embodiment includes an engine 106 such as a scanner or a plotter via the PCI-EXPRESS 108 and an external I / F such as IEEE1394 via the PCI 109. Since an option 107 is connected, the engine is not connected via the PCI 109. That is, in the first embodiment, since the engine is not connected to the PCI controller 221 of the controller ASIC 101, the access request is rejected so that the image input resource and the image output resource on the PCI side cannot be accessed. , Reference to the base address from the software is suppressed. Specifically, a response indicating that the base address register of the configuration register 224 of the PCI controller 221 is not mounted is returned.

(Second Embodiment)
FIG. 7 is a block diagram illustrating a configuration of an image forming apparatus according to the second embodiment. As shown in FIG. 7, the image forming apparatus according to the second embodiment is connected to a controller ASIC 101 with two engines 106 and 111 such as a scanner and a plotter via a PCI 109, and an optional external controller 112, The FAX unit 113 is connected, the HDD 105 is connected to the controller ASIC 101, the chip set 102 is connected to the controller ASIC 101 via the PCI-EXPRESS 110, and the CPU 103 and the memory 104 are connected to the chip set 102. Configured. The configuration of the controller ASIC 101 in the second embodiment shown in FIG. 7 is the same as that in the first embodiment shown in FIG.

  The difference between the second embodiment described above and the first embodiment is that nothing is connected to the controller ASIC 101 via the PCI-EXPRESS 108, and the engine 106 such as a scanner or a plotter is connected via the PCI 109. 111, an optional external controller 112, and a FAX unit 113 are connected. That is, in the second embodiment, nothing is connected to the PCI-EXPRESS root complex controller 217 of the controller ASIC 101, so that the image input resources and image output resources on the PCI-EXPRESS side cannot be accessed. The access request is rejected, and the base address is inhibited from being referenced from software. Specifically, a response indicating that the base address register of the configuration register 220 of the PCI-EXPRESS root complex controller 217 is not mounted is returned.

(Third embodiment)
FIG. 8 is a block diagram showing the configuration of the image forming apparatus according to the third embodiment. In the image forming apparatus according to the third embodiment, as shown in FIG. 8, an engine 106 is connected to a controller ASIC 101 via a PCI-EXPRESS 108, and an option 107, an external controller 112, and a FAX unit 113 are connected via a PCI 109. In addition, the HDD 105 is connected to the controller ASIC 101, the chip set 102 is connected to the controller ASIC 101 via the PCI-EXPRESS 110, and the CPU 103 and the memory 104 are connected to the chip set 102. The configuration of the controller ASIC 101 in the third embodiment shown in FIG. 8 is the same as that in the first embodiment shown in FIG.

Bridge Transfer from PCI Express to PCI Next, a process for performing image transfer from the engine 106 to the external controller 112 in the third embodiment will be described.

  In order to perform image transfer from the engine 106 to the external controller 112, the base address of the PCI-EXPRESS route complex controller 217 of the controller ASIC 101 has a fixed address resource for bridge transfer. The bridge transfer controller 216 has an address converter for converting access to the above-described fixed address to an address where the actual resource of the external controller 112 is present.

  The aforementioned address converter has a conversion address register that can be set from software, and converts a fixed address accessed from the PCI-EXPRESS side into a fixed address set in the conversion address register. The master circuit 223 of the PCI controller 221 generates a PCI transaction using the fixed address converted as described above, and accesses the external controller 112 connected to the PCI 109. Thus, image transfer from the engine 106 to the external controller 112 can be performed via the bridge transfer controller 216.

  The controller ASIC 101 in the embodiment described above can transfer access to a resource to an appropriate destination, thereby requiring a resource connected to PCI and a resource connected to PCI-EXPRESS. Only the device can access it. Further, the controller ASIC 101 described above can appropriately switch the resource for image transfer when the engine is connected to either PCI-EXPRESS or PCI. Furthermore, the controller ASIC 101 described above can easily transfer image data and the like from the PCI-EXPRESS side to the PCI side with limited resources.

(Fourth embodiment)
FIG. 9 is a block diagram illustrating configurations of a controller ASIC and an engine ASIC according to the fourth embodiment. The controller ASIC 901 shown in FIG. 9 differs from the arbiter 205 in that the processing is changed to an arbiter 902 that is different in processing. In the following description, the same components as those in the first embodiment described above are denoted by the same reference numerals and description thereof is omitted. The configuration of the image forming apparatus is the same as that of the first embodiment, and a description thereof is omitted.

  The engine ASIC 951 includes a master circuit 952 and a target circuit 953, and is connected to the PCI-EXPRESS route complex controller 217 via the PCI-EXPRESS 108. The engine ASIC 951 has a function as a scanner for reading image data and a plotter for printing image data on a paper document.

  The master circuit 952 performs data control with the controller ASIC 901 connected via the bus. The master circuit 203 requests the target circuit 218 of the controller ASIC 901 to transfer data, thereby realizing data transfer.

  The target circuit 953 includes a configuration register 954, receives a data transfer request from the master circuit of the controller ASIC 901, and performs control for performing data transfer. The configuration register 204 holds an address of a device accessible from the controller ASIC 901 and the like.

  The engine ASIC 951 is connected to the root complex controller 217 via the PCI-EXPRESS bus.

  By the way, since PCI-EXPRESS can change the bandwidth by changing the number of lanes, the performance can be changed in a scalable manner. For example, when the same controller ASIC 901 is installed for different image forming apparatuses, 16 lanes are set for transferring a high-quality color image at a high speed, and 1 lane is set for a monochrome low speed, thereby forming an image. Data transfer with appropriate performance can be realized for each device. Further, when mounting in an image forming apparatus, power consumption can be reduced and board wiring can be facilitated by not connecting unnecessary lanes.

  The image forming apparatus processes various data such as FAX data and communication data in addition to image data from the engine ASIC regardless of whether the function is high or low. However, in the conventional image forming apparatus, regardless of the function, in the controller ASIC, the method of arbitration of a plurality of data transfer functions gives top priority to image transfer with the engine (scanner input / plotter output), and other than that A uniform method is generally used in which functions are given low priority.

  This is the arbitration suitable for the general method described above if the number of lanes of PCI-EXPRESS is one lane and there is no bandwidth. However, if PCI-EXPRESS has 16 lanes and a relatively large bandwidth, arbitration that secures a certain bandwidth for transfer functions with medium priority can achieve optimal performance. Conceivable. Therefore, the arbiter 902 of the ASIC 901 according to the present embodiment has the following configuration in order to achieve optimum performance.

  The arbiter 902 includes a control register 906, a selector 905, and a plurality of arbitration circuits such as a first arbitration circuit 903 and a second arbitration circuit 904, and performs arbitration using different arbitration algorithms depending on the situation.

  The first arbitration circuit 903 is a circuit that performs arbitration with the highest priority for scanner / plotter transfer and the lowest priority for other image processing transfer. Arbitration performed by the first arbitration circuit 903 is referred to as an engine top priority type.

  Normally, the image output function by the engine ASIC 951 cannot be stopped when the writing process by the engine ASIC 951 is started. For this reason, in this engine priority type arbitration, image transfer from the engine ASIC 951 is executed with the highest priority even when other data transfer functions are operating.

  The second arbitration circuit 904 guarantees a high bandwidth for high-priority transfer such as scanner / plotter transfer, and guarantees a constant bandwidth lower than scanner / plotter transfer for medium-priority transfer such as an HDD controller. A circuit that performs arbitration with the lowest priority for transfers other than high priority and medium priority. The arbitration performed by the second arbitration circuit 904 is called a bandwidth guarantee type.

  For example, since the PCI-EXPRESS has a large number of lanes and there is a sufficient bandwidth, even if a certain bandwidth is allocated to a transfer function other than image output transfer, there is no delay in scanner / plotter transfer. Therefore, the second arbitration circuit 904 executes the bandwidth guarantee type arbitration assuming the situation.

  Note that the number of arbitration circuits is not limited to two, and three or more arbitration circuits may be provided. Hereinafter, a configuration for performing control for switching between the first arbitration circuit 903 and the second arbitration 094 will be described.

  The control register 906 holds information for switching between the first arbitration circuit 903 and the second arbitration circuit 904 described above.

  FIG. 10 is a diagram illustrating a data structure of the control register 906 of the arbiter 902. As shown in FIG. 10, bits 02-00 of reference numeral 1002 hold a threshold value for the number of lanes for switching between the engine highest priority type and the bandwidth guarantee type. If the actual number of lanes is smaller than the threshold set in bit 02-00, arbitration is performed with the engine first priority type, and if the actual number of lanes is greater than the threshold set in bit 02-00, the bandwidth guarantee type Arbitration will be performed.

  Bit 08 of reference numeral 1001 in FIG. 10 holds the setting of engine priority fixed. When the initial value is set to ‘1’, arbitration is executed in the engine highest priority type regardless of the number of lanes.

  Returning to FIG. 9, the selector 905 refers to the control register 906, and any of the first arbitration circuit 903 and the second arbitration circuit 904 is a circuit that actually performs arbitration according to the number of lanes set in PCI-Express. Select one of them. The number of lanes set in PCI-Express is detected by the PCI-EXPRESS root complex controller 217 confirming the link width with the opposite device before link training. The detected number of lanes is input to the arbiter 902.

  In this embodiment, it is assumed that “8” is set as the threshold value of the number of lanes in the control register 906. Therefore, the selector 905 determines whether or not the input number of lanes is equal to or greater than the threshold value “8”. If it is determined that the threshold value is “8” or more, the second arbitration circuit 904 is selected as an arbitration execution circuit. On the other hand, when the selector 905 determines that the number of input lanes is smaller than the threshold value “8”, the selector 905 selects the first arbitration circuit 903 as an arbitration execution circuit.

  By the way, engine image output and input are normally executed exclusively, but when there is a margin in bandwidth, the performance of the image forming apparatus can be improved by executing them simultaneously. In order to perform this process, even if the threshold for the number of lanes is large, an engine top priority type arbitration circuit is selected, and as an arbitration algorithm, the engine image output and the input have the same priority, Simultaneous operation with the highest priority can be performed.

  Arbitration algorithms for a plurality of data transfer functions in the controller ASIC 901 can be changed according to the number of PCI-EXPRESS lanes between the controller ASIC 901 and the engine ASIC 951 according to the present embodiment. Thereby, the controller ASIC 901 according to the present embodiment can realize the arbitration control of the optimum data transfer function according to the number of PCI-EXPRESS lanes, that is, the processing performance. Accordingly, the controller ASIC 901 and the image forming apparatus including the controller ASIC 901 can realize appropriate processing performance.

(Fifth embodiment)
FIG. 11 is a block diagram illustrating configurations of a controller ASIC and an engine ASIC according to the fifth embodiment. A controller ASIC 901 shown in FIG. 11 has the same configuration as that of the fourth embodiment, and is different in that the engine ASIC 1151 is connected to the PCI controller 221 via a PCI bus. In the following description, the same components as those in the first embodiment described above are denoted by the same reference numerals and description thereof is omitted.

  The engine ASIC 1151 is an engine ASIC having a lower processing speed than the engine ASIC 951 of the fourth embodiment.

  The PCI-EXPRESS root complex controller 217 according to the present embodiment checks the link width with the opposite device before link training. This confirms that the link width is “0”, that is, no connection. At this time, the controller ASIC 901 considers that the engine ASIC 1151 is connected to the PCI side. Information indicating that the engine ASIC 151 is set on the PCI side is input from the controller ASIC 901 to the arbiter 205.

  In this case, the selector 905 of the arbiter 205 selects the first arbitration circuit 903 as an arbitration execution circuit regardless of the number of lanes.

  In the controller ASIC 901 according to the fourth and fifth embodiments, arbitration algorithms for a plurality of data transfer functions in the controller ASIC 901 can be changed according to the connection destination of the engine ASIC 951. Thereby, the controller ASIC 901 according to the present embodiment can realize the arbitration control of the optimum data transfer function according to the interface to which the engine ASIC 951 is connected. Accordingly, the controller ASIC 901 and the image forming apparatus including the controller ASIC 901 can realize appropriate processing performance.

1 is a block diagram illustrating a configuration of an image forming apparatus according to a first embodiment. It is a block diagram which shows the structure of controller ASIC. It is a figure explaining the situation where the register | resistor of the controller ASIC itself, the engine, and the option resource were mapped as the memory space of PCI-EXPRESS and PCI, and I / O space. It is a figure explaining the contents of the exclusive register of controller ASIC. It is a figure explaining the relationship between the offset value from the base address by the side of the PCI-EXPRESS route complex controller of controller ASIC, and the resource arrange | positioned. It is a figure explaining the relationship between the offset value from two base addresses on the PCI side of controller ASIC, and the resource arrange | positioned. It is a block diagram which shows the structure of the image forming apparatus by 2nd Embodiment. It is a block diagram which shows the structure of the image forming apparatus by 3rd Embodiment. It is a block diagram which shows the structure of the image forming apparatus by 4th Embodiment. It is the figure which showed the data structure of the control register with which an arbiter is provided. It is a block diagram which shows the structure of the image forming apparatus by 5th Embodiment.

Explanation of symbols

101,901 Controller ASIC
102 chipset 103 CPU
104 Memory 105 HDD
106, 111 Engine 107 Option 108, 110 PCI-EXPRESS interface 109 PCI interface 112 External controller 113 FAX unit 201 PCI-EXPRESS endpoint controller 202, 218, 222 Target circuit 203, 219, 223 Master circuit 204, 220, 224 Configuration register 205, 902 Arbiter 206 Target access access decoder 207 PCI-EXPRESS direct access controller 208 Image input DMA controller 209 Image output DMA controller 210 Decompressor 211 PCI direct access controller 212 HDD controller 213 DMA controller 214 Image input buffer 215 Image output buffer 216 Bridge Transfer controller La 903 First arbitration circuit 904 Second arbitration circuit 905 Selector 906 Control register 951 Engine ASIC
952 Master circuit 953 Target circuit 954 Configuration register

Claims (6)

In an image processing controller that connects an engine including a scanner and a plotter and a CPU connected via a chipset to transfer image data and process image data.
A PCI-EXPRESS endpoint controller that controls communication with the chipset via a PCI-EXPRESS interface;
A PCI-EXPRESS root complex controller that controls communication with the engine when connected to the engine via a PCI-EXPRESS interface;
A PCI controller that controls communication with the engine when connected to the engine via a PCI interface;
The PCI-EXPRESS endpoint controller accepts access to the engine from the CPU via the image processing controller from the CPU connected via the chipset as a proxy, and for resources connected to the image processing controller, Deter references from the CPU ,
According to whether the engine is connected to either the PCI controller or the PCI-EXPRESS root complex controller, it has a function of suppressing reference from the engine to unnecessary resources.
Images processing controller. In an image processing controller that connects an engine including a scanner and a plotter and a CPU connected via a chipset to transfer image data and process image data.
  A PCI-EXPRESS endpoint controller that controls communication with the chipset via a PCI-EXPRESS interface;
  A PCI-EXPRESS root complex controller that controls communication with the engine when connected to the engine via a PCI-EXPRESS interface;
  A PCI controller that controls communication with the engine when connected to the engine via a PCI interface;
  The PCI-EXPRESS endpoint controller accepts access to the engine from the CPU via the image processing controller from the CPU connected via the chipset as a proxy, and for resources connected to the image processing controller, Deter references from the CPU,
  The PCI-EXPRESS root complex controller and the PCI controller convert memory access from the engine into access to the memory connected to the chipset, and the PCI-EXPRESS root complex controller and the PCI-EXPRESS root complex controller According to whether the engine is connected, it has a function to suppress reference from the engine to unnecessary resources.
  Image processing controller. 3. The image processing controller according to claim 1, further comprising a bridge function that bridges an address from the PCI-EXPRESS root complex controller to the PCI controller via a fixed address resource. A plurality of arbiter control units that perform arbitration with different algorithms;
A selection unit that selects the arbiter control unit that performs arbitration according to the number of lanes between the PCI-EXPRESS route complex controller and the engine;
Image processing controller according to any one of claims 1 to 3, further comprising a. The selection unit selects a predetermined arbiter control unit regardless of the number of lanes when the engine is connected to the PCI controller via a PCI interface;
The image processing controller according to claim 4 . In an image processing controller for transferring image data and processing image data by mutually connecting an engine including a scanner and a plotter and a CPU connected via a chipset, the chip is connected via a PCI-EXPRESS interface. PCI-EXPRESS endpoint controller that controls communication with the set, PCI-EXPRESS root complex controller that controls communication with the engine when connected to the engine via the PCI-EXPRESS interface, and PCI interface A PCI controller that controls communication with the engine , a plurality of arbiter control units that perform arbitration with different algorithms, the PCI-EXPRESS route complex controller, and the engine. Depending on the number of lanes Te, comprising: a selector for selecting the arbiter control section for arbitration, said PCI-EXPRESS endpoint controller, via the image processing controller from the CPU from the CPU are connected via the chip set An image forming apparatus, comprising: an image processing controller that accepts access to the engine by proxy and deters reference from the CPU to a resource connected to the image processing controller.

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