JP5106977B2 - Liquid crystal display - Google Patents

Description

The present invention relates to a liquid crystal display equipment, can be applied to a liquid crystal display device for switching the operation between the analog driving method and memory system. The present invention, by creating a storage capacitor of an adjacent liquid crystal cell sandwiched between the shield layer in the lower layer of the pixel electrode, even if a small area can be arranged to hold capacity, the retention capacity required Ensure that it can be secured sufficiently.

  Conventionally, in a liquid crystal display device, a display unit is formed by arranging pixels of liquid crystal cells in a matrix. In the liquid crystal display device, each liquid crystal cell is provided with a TFT (Thin Film Transistor) for driving the liquid crystal cell, and the operation of the TFT is controlled by a horizontal drive unit and a vertical drive unit arranged around the display unit. A desired image is displayed on the display unit. Conventionally, a liquid crystal display device is produced by sandwiching a liquid crystal layer between a TFT substrate on which TFTs are arranged and a CF substrate on which color filters are arranged, and liquid crystal cells are arranged in a matrix by the layout of these TFT substrates and CF substrates, Further, a vertical driving unit and a horizontal driving unit are arranged around the display unit and on the TFT substrate.

  FIG. 19 is a plan view showing the layout of the TFT substrate. In the liquid crystal display device, the TFT substrate 1 and the CF substrate are laid out so that each of the liquid crystal cells is formed by a rectangular area AR2. Further, in the TFT substrate 1, for example, the corner area AR3 of each rectangular area AR2 is allocated to the area where the TFT is arranged, and all or part of the remaining area of each rectangular area AR2 is insufficient for each liquid crystal cell. A holding capacitor Cs that supplements the capacitance is provided.

  As shown in FIG. 20, in the TFT substrate 1, a gate layer 5 or the like is formed on a transparent insulating substrate 4 made of glass or the like to form a TFT, and then an insulating film 6 is formed. Subsequently, the TFT substrate 1 is formed with a wiring layer 7 made of polysilicon, and TFTs are wired. Subsequently, after the insulating film 8 is formed, a wiring layer 9 made of aluminum or the like is formed. Subsequently, after the insulating layer 10 is formed, the pixel electrode 11 is formed, and the pixel electrode 11 is connected to the TFT by the lower wiring layer 9. In the TFT substrate 1, an alignment film (not shown) is formed on the upper layer of the pixel electrode 11. The TFT substrate 1 has a common electrode disposed below the pixel electrode 11 in the ISP mode or the like.

  As shown in FIG. 21, the TFT substrate 1 conventionally has a gate layer 5 and a wiring layer 7 that each form a counter electrode constituting a storage capacitor Cs, and the counter electrode on the wiring layer 7 side is connected to the pixel electrode 11. The The gate layer 5 side electrode of the storage capacitor Cs is supplied with the drive signal CS related to the precharge process and is held at the potential of the drive signal CS.

  Conventionally, a liquid crystal display device sequentially switches the voltage of a signal line provided in a display unit to a gradation voltage indicating the gradation of each pixel, and controls each TFT by controlling the TFT of each liquid crystal cell in conjunction with this switching. The voltage of the electrode 11 is sequentially set to the voltage of the signal line, thereby setting the gradation of each pixel. Hereinafter, this driving method is referred to as an analog driving method.

  With regard to such a liquid crystal display device, Japanese Patent Application Laid-Open No. 9-243959 discloses a configuration in which each pixel is provided with a memory unit, and each pixel is driven in accordance with the recording in this memory unit. Hereinafter, this method is called a memory method. According to this memory system, once the gradation of each pixel is set, the gradation setting process for each pixel can be omitted, so that power consumption can be reduced.

  By the way, in a memory type liquid crystal display device, if the memory is shared by a plurality of adjacent pixels, the number of memories in the entire liquid crystal display device can be reduced, and the configuration can be simplified. However, if the memory is shared by a plurality of adjacent pixels, the layout of the TFT substrate is biased among the plurality of pixels, and the area in which a storage capacitor can be created in a specific pixel is reduced. As a result, the liquid crystal display device has a problem that it is difficult to provide a sufficient opening to secure a storage capacitor required for this specific pixel.

  In the liquid crystal display device, spacers are arranged at a predetermined pixel pitch, and a gap between the TFT substrate and the CF substrate is secured by the spacers. Therefore, in the liquid crystal display device, the layout of the TFT substrate is also biased by the arrangement of the spacers, and the area in which a storage capacitor can be created with a specific pixel in which the spacers are arranged becomes small. As a result, in this case, the liquid crystal display device has a problem that it becomes difficult to provide a sufficient opening and secure a storage capacitor necessary for this specific pixel due to high resolution or the like.

  As one method for solving this problem, it is conceivable that the storage capacitors of these specific pixels are created in adjacent pixels, and the storage capacitor layout is biased with respect to the continuous pixel arrangement. However, in this case, as shown in FIG. 22, in this adjacent pixel, the wiring layer 7 below the pixel electrode 11 is held at the pixel potential of the adjacent pixel, and the capacitive coupling between the pixel electrode 11 and the wiring layer 7 occurs. As a result, the pixel potential of the pixel changes, and there is a problem that gradation cannot be displayed correctly.

In the first place, even if there is no bias in the layout of the TFT substrate, the area in which the storage capacitor can be arranged in each pixel is reduced by increasing the resolution of the liquid crystal display device. There is a problem that it is difficult to secure the necessary storage capacity.
Japanese Patent Laid-Open No. 9-243995

  The present invention has been made in consideration of the above points, and a liquid crystal display device and a liquid crystal display device that can sufficiently secure a required storage capacity even when the area in which the storage capacity can be arranged is small. An image display method is proposed.

In order to solve the above problems, the invention of claim 1 is characterized in that a liquid crystal layer is sandwiched between a TFT substrate and a CF substrate, liquid crystal cells by the liquid crystal layer are arranged in a matrix to form a display portion, and the display portion image is applied to a liquid crystal display device for displaying the, on an insulating substrate, the TFT substrate is produced by placing at least the pixel electrode of the liquid crystal cell and the transistor to be subjected to the driving of the liquid crystal cell, the lower layer of the pixel electrode In addition, a part or all of the storage capacitor of the adjacent liquid crystal cell is created with the shield layer interposed therebetween, and the counter electrode of the storage capacitor is formed by the gate layer of the transistor and the wiring layer of the transistor, the shield layer, Ru is formed by a wiring layer for connecting the transistor to the pixel electrode.

According to the configuration of the first aspect, the influence of the pixel potential of the adjacent liquid crystal cell can be effectively avoided by the shield layer, and the storage capacitor of the adjacent liquid crystal cell can be disposed below the pixel electrode. Therefore, when the area in which the storage capacitor can be arranged in a specific liquid crystal cell is small due to a layout deviation or the like, the storage capacitor of this specific liquid crystal cell can be arranged in the adjacent liquid crystal cell to ensure the necessary storage capacitor. .

  According to the present invention, even if the area where the storage capacitor can be arranged is small, the required storage capacitor can be sufficiently secured.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings as appropriate.

(1) Configuration of Embodiment FIG. 2 is a block diagram showing a liquid crystal display device according to Embodiment 1 of the present invention. The liquid crystal display device 18 displays, for example, a moving image and a still image based on video data output from a tuner unit, an external device, etc. (not shown) on the display unit 13 by an analog drive method, and displays various menu images and the like by a memory method. This is displayed in part 13.

  In the liquid crystal display device 18, an interface (I / F) 12 inputs image data SDI by serial data sequentially indicating the gradation of each pixel and various timing signals synchronized with the image data SDI. Here, the image data SDI is image data displayed on the display unit 13 by an analog driving method. The interface 12 receives binary image data DV to be displayed on the display unit 13 from the controller 14 by a memory method, and outputs the input image data SDI, DV and various timing signals to each unit according to the control of the controller 14. .

  The timing generator (TG) 16 generates various timing signals necessary for the memory method and the analog driving method under the control of the controller 14 and outputs them to the horizontal driving unit 15 and the vertical driving unit 17. Further, the drive power supply VCOM for the common electrode of the liquid crystal cell is generated and output to the display unit 13. In this embodiment, the display unit 13 can be any of a reflection type, a transmission type, and a combination type of a reflection type and a transmission type.

  The horizontal drive unit 15 switches the operation between an analog drive method and a memory method under the control of the controller 14, and in the analog drive method, the image data SDI input from the interface 12 is sequentially distributed to each signal line SIG to perform digital-analog conversion processing. Then, the drive signal Ssig of each signal line SIG is generated by field inversion, frame inversion, line inversion, and the like. The horizontal drive unit 15 outputs this drive signal Ssig to each signal line SIG of the display unit 13 in the analog drive method.

  In the memory system, the horizontal driving unit 15 outputs a driving signal Sdv corresponding to the logical value of the binary image data DV output from the controller 14 to the corresponding signal line SIG, and then outputs a predetermined driving signal XCS. Output to line.

  The vertical drive unit 17 switches operation between an analog drive method and a memory method under the control of the controller 14 and outputs a predetermined drive signal to the scanning lines of the display unit 13.

  The display unit 13 operates in accordance with various signals output from the horizontal drive unit 15 and the vertical drive unit 17 and displays an image based on the image data SDI or DV. Here, FIG. 3 is a connection diagram showing a basic unit of the display unit 13. Here, the basic unit 21 is a structural unit of the display unit 13, and in this embodiment, is composed of red, green, and blue liquid crystal cells 22R, 22G, and 22B and peripheral circuits of these liquid crystal cells 22R, 22G, and 22B. Is done. The display unit 13 includes the basic unit 21 shown in FIG. 3 as a TFT substrate so that the red, green, and blue liquid crystal cells 22R, 22G, and 22B that constitute red, green, and blue pixels, respectively, are sequentially and continuously circulated. The liquid crystal cells 22R, 22G, and 22B are arranged in a matrix.

  In the basic unit 21, the storage capacitors CsR, CsG, and CsB of the red, green, and blue liquid crystal cells 22R, 22G, and 22B are supplied with a drive signal CS related to precharge processing at one end and correspond to the other ends, respectively. Connected to the pixel electrodes of the liquid crystal cells 22R, 22G, and 22B. The liquid crystal cells 22R, 22G, and 22B are supplied to the common electrode with a driving power source VCOM whose signal level is switched in conjunction with the driving signal CS.

  The liquid crystal cells 22R, 22G, and 22B have pixel electrodes connected to the NMOS transistor Q2 via NMOS transistors Q1R, Q1G, and Q1B that are turned on and off by gate signals GATER, GATEG, and GATEB, respectively. Here, the NMOS transistor Q2 is turned on / off by the blue gate signal GATEB, and the NMOS transistors Q1R, Q1G, Q1B are respectively connected via the NMOS transistors Q3 and Q4 that are turned on / off according to the output from the memory unit 23. Connect to the signal line SIG or the supply line of the drive signal CS.

  In the basic unit 21, the memory unit 23 includes an SRAM (CMOS (SRAM)) composed of a CMOS inverter composed of an NMOS transistor Q5 and a PMOS transistor Q6 whose gates and drains are commonly connected, and a CMOS inverter composed of the same NMOS transistor Q7 and PMOS transistor Q8. Static Random Access Memory), which outputs an output RAM corresponding to the logic level of the signal line SIG and an inverted output at a logic level opposite to this output RAM to the transistors Q3 and Q4, respectively, and complements these transistors Q3 and Q4. On / off control. The memory unit 23 is connected to the signal line SIG via the NMOS transistor Q11 that is turned on by the gate signal GATED.

  As shown in FIGS. 4 and 5, the basic unit 21 uses the memory unit 23 in advance so that the transistor Q3 is turned on by the horizontal driving unit 15 and the vertical driving unit 17 when the analog driving method is used. After being set (FIGS. 4D to 4E), the settings of the gate signals GATER, GATEG, and GATEB are sequentially switched (FIGS. 4B1 to B3), as shown in FIG. The liquid crystal cells 22R, 22G, and 22B are sequentially connected to the signal line SIG. Here, FIG. 5 is a diagram showing the configuration of the basic unit 21 in a simplified manner by comparison with FIG. 3 for explaining the connection between the signal line SIG and the liquid crystal cells 22R, 22G, and 22B.

  Further, in the case where the basic unit 21 is based on the analog drive method, the horizontal drive unit 15 applies the drive signal Ssig of the signal line SIG to the gradation voltages R, G, and B indicating the gradations of the liquid crystal cells 22R, 22G, and 22B, respectively. The gate signals GATER, GATEG, and GATEB are sequentially switched so as to correspond to the setting of the signal line SIG (FIG. 4A) (FIGS. 4B1 to 4B3). Accordingly, in the basic unit 21, the pixel electrode side potentials PIXR, PIXG, and PIXB of the liquid crystal cells 22R, 22G, and 22B are set to the gradation voltages R, G, and B based on the drive signal Ssig. Thereby, the basic unit 21 sets the gradation of the liquid crystal cells 22R, 22G, and 22B by an analog driving method. In the configuration of FIG. 3, with the transistor Q2 turned on, the red and green transistors Q1R and Q1G are alternately turned on, and the gray levels of the red and green liquid crystal cells 22R and 22G are sequentially changed. It may be set.

  On the other hand, when the memory unit 23 is set in advance in the analog drive system and when writing is performed in the memory system, the basic unit 21 uses the gate signals GATER, GATEG, and GATEB to generate transistors Q1R and Q1G as shown in FIGS. , Q1B is set to the off state (FIGS. 6B1 to B3 and C1 to C3), and the power supply voltage VRAM of the memory unit 23 is temporarily set to the voltage VDD corresponding to the H level of the signal line SIG. (FIGS. 6A and 6D), the transistor Q11 is turned on by the gate signal GATED, and the memory portion 23 is connected to the signal line SIG (FIG. 6E). Thereby, the basic unit 21 sets the logic level of the drive signal Sdv output to the signal line SIG (FIG. 6F). After that, in the basic unit 21, the power supply voltage VRAM is raised to the voltage VDD2 corresponding to the driving voltage of the liquid crystal cells 22R, 22G, and 22B (FIGS. 6D and 6F), and the transistors Q3 and Q4 are turned on and off. Set to be controllable. Here, FIG. 7 is a diagram showing the configuration of the basic unit 21 shown in FIG. 3 in a simplified manner for explaining the write operation of the memory unit 23.

  When the memory unit 23 is set in advance in the analog drive system, the basic unit 21 sets the signal line SIG to the H level by the horizontal drive unit 15 and executes these series of operations, thereby setting the transistor Q3 to the on state. Set to do. On the other hand, at the time of writing by the memory system, the signal line SIG is set to the logical value of the image data DV by the horizontal driving unit 15, and thereby the logical value of the image data DV is set to the memory unit 23. When this logic value is H level, the memory unit 23 is set so as to set the transistor Q3 to the on state, whereas when this logic value is L level, the transistor Q4 is set to the on state. The memory unit 23 is set.

  Here, at the time of display by the memory system, as shown in FIGS. 8 and 9, the basic unit 21 receives an inverted signal XCS of the drive signal CS whose signal level is complementarily switched from the horizontal drive unit 15 to the drive signal CS. Is supplied to the signal line SIG (FIGS. 8A and 8B). Further, gate signals GATER, GATEG, and GATEB are supplied from the horizontal drive unit 15 so as to turn on all the transistors Q1R, Q1G, Q1B, and Q2 (FIGS. 8C1 to 8C3). In the basic unit 21, the transistor Q3 or Q4 is selectively turned on according to the logic value set in the memory unit 23, whereby the inverted signal XCS or the drive signal CS is selectively transferred to the liquid crystal cells 22R, 22G, It is supplied to the pixel electrode 22B (FIG. 8 (D1) to (D3)). Accordingly, the liquid crystal cells 22R, 22G, and 22B are set to black gradation or white gradation corresponding to the logical value of the image data DV set in the memory unit 23. Here, FIG. 9 is a diagram showing the configuration of the basic unit 21 shown in FIG. 3 in a simplified manner for the explanation of the display by this memory system.

  FIGS. 10A and 10B are diagrams for explaining the layout of the basic unit 21 in the TFT substrate. Here, in the basic unit 21 shown in FIG. 3, the number of scanning lines is remarkably larger than the number of signal lines, and the liquid crystal cells 22R, 22G, and 22B are arranged side by side in the horizontal direction. It becomes complicated. Therefore, in this embodiment, the pixels by the liquid crystal cells 22R, 22G, and 22B by one basic unit 21 are arranged side by side in the signal line extending direction, and the display unit 13 is configured by so-called horizontal stripes. Further, scanning lines are arranged between the pixels formed by the liquid crystal cells 22R, 22G, and 22B and between the pixels formed by the adjacent basic units 21. Accordingly, in this embodiment, the TFT substrate is efficiently laid out to prevent the opening of the display unit 13 from being reduced.

  Further, as shown by an arrow in FIG. 10, among the three liquid crystal cells 22R, 22G, and 22B of red, green, and blue by the one basic unit 21, the memory unit 23, Transistors Q3, Q4, and Q11 are arranged. Further, the transistors Q1R, Q1G, Q1B, and Q2 and the storage capacitor CsR of the red liquid crystal cell 22R are arranged in a pixel formed by the red liquid crystal cell 22R. In addition, the storage capacitors CsG and CsB of the green liquid crystal cell 22G and the blue liquid crystal cell 22B are arranged in the pixel by the green liquid crystal cell 22G. Thus, in this embodiment, the transistors Q1 to Q11 are efficiently arranged to sufficiently secure the area of the opening that can be assigned to the red, green, and blue pixels, and the area of the opening in the red, green, and blue pixels. Make sure that is not biased.

  Further, as shown in FIG. 1, at least the storage capacitor CsB of the blue liquid crystal cell 22B disposed in the pixel of the green liquid crystal cell 22G is shielded between the electrode of the storage capacitor CsB formed by the wiring layer 7 and the pixel electrode 11. A layer 31 is provided. Here, in the liquid crystal display device 18, the shield layer 31 is formed by the wiring layer 9 that connects the pixel electrode 11 to the basic unit 21. In the basic unit 21, the shield layer 31 is connected to ground or a fixed potential.

(2) Operation of Embodiment In the above configuration, the liquid crystal display device 18 (FIG. 2) uses the controller 14 to display a moving image or a still image based on the image data SDI output from the tuner unit, an external device, or the like. Under the control of each unit, the image data SDI input to the interface 12 is input to the horizontal drive unit 15 where the image data SDI is subjected to digital-analog conversion processing to drive the signal line SIG by field inversion, frame inversion, line inversion, etc. A signal Ssig is generated. In the liquid crystal display device 18, the gradation of each pixel provided in the display unit 13 is set by the drive signal Ssig based on the analog signal, and a moving image and a still image are displayed by the analog drive method.

  On the other hand, when displaying a menu image or the like by the controller 14, binary image data DV output from the controller 14 is input to the horizontal driving unit 15 via the interface 12. In the liquid crystal display device 18, the logic level of the signal line SIG is sequentially set according to the logic level of the image data DV, and the logic level of the signal line SIG is stored in the memory unit 23 provided in the display unit 13 ( FIG. 3). In addition, the gradation of each pixel is set according to the logic level stored in the memory unit 23, whereby a menu image is displayed by the memory method.

  More specifically, in the display unit 13 (FIGS. 3, 6, and 7), in the case of display by an analog drive method, the logical level of each signal line SIG is set to H level by the horizontal drive unit 15 in advance processing. Then, in a state where the power supply VRAM of the memory unit 23 is lowered, the memory unit 23 is connected to the signal line SIG by the gate signal GATED, and thereby, the logic value of the signal line SIG is set in the memory unit 23. Further, by setting the logical value, the transistor Q3 is set to the on state, and the transistor Q2 is connected to the signal line SIG.

  Further, in the case of display by an analog drive method (FIGS. 3 to 6), the horizontal drive unit 15 sequentially indicates the gray levels of the liquid crystal cells 22R, 22G, and 22B in which the signal level of the signal line SIG is red, green, and blue. The transistors Q1R, Q1G, Q1B, and Q2 are sequentially turned on so as to correspond to the setting of the gradation voltage and the signal level of the signal line SIG, and the pixel electrodes of the liquid crystal cells 22R, 22G, and 22B. Is set to the gradation voltage of each pixel. In order to correspond to this setting, the drive signals VCOM and CS are supplied to the common electrodes of the liquid crystal cells 22R, 22G, and 22B and the holding capacitors CsR, CsG, and CsB.

  In the liquid crystal display device 18, the setting of the liquid crystal cells 22R, 22G, and 22B by the signal line SIG is repeated, for example, in units of frames, and thereby, moving images and still images can be displayed by an analog driving method.

  On the other hand, in the case of the memory system (FIGS. 3, 6, and 7), the signal level of the signal line SIG is set to a logic level corresponding to light emission and non-light emission of the liquid crystal cells 22R, 22G, and 22B, and analog driving is performed. The memory unit 23 is driven in the same manner as the prior processing based on the method, and the logic level of the image data DV is set in the memory unit 23.

  Subsequently, the transistor Q3 or Q4 is selectively turned on according to the logic value set in the memory unit 23 (FIGS. 3, 8, and 9), and the inverted signal XCS or the drive signal of the drive signal CS. CS is selected. In the liquid crystal display device 18, the selected inverted signal XCS or drive signal CS is supplied to the pixel electrodes of the liquid crystal cells 22R, 22G, and 22B via the transistors Q1R, Q1G, Q1B, and Q2, and thereby the signal line SIG. These liquid crystal cells 22R, 22G, and 22B are set to display or non-display according to the set logical value. As a result, the liquid crystal display device 18 can reduce the power consumption by displaying an image display that does not need to be updated at a frame period, such as a menu image, using a memory system.

  Further, in the liquid crystal display device 18, one memory unit 23 is allocated to the red, green, and blue liquid crystal cells 22R, 22G, and 22B and an image is displayed by a memory system, thereby reducing the number of memories provided in the display unit. Thus, the configuration can be simplified.

  Further, red, green, and blue liquid crystal cells 22R, 22G, and 22B to which one memory unit 23 is allocated are sequentially arranged in the extending direction of the signal line SIG, so that the display unit 13 is configured by so-called horizontal stripes. The substrate can be laid out to prevent a decrease in the opening in the display unit 13.

  However, if the memory unit 23 is shared by a plurality of adjacent pixels in this way, the TFT substrate layout is biased by the plurality of pixels, and the area in which a storage capacitor can be created by a specific pixel is reduced. That is, in this case, if the memory unit 23 is disposed in any pixel, it is difficult to allocate a sufficient area to the storage capacitor by securing a sufficient opening in the pixel in which the memory unit 23 is disposed.

  Therefore, in this embodiment, the memory unit 23, the transistors Q3, Q4, and the pixels formed by the blue liquid crystal cell 22B among the three liquid crystal cells 22R, 22G, and 22B of red, green, and blue by one basic unit 21 are provided. Q11 is disposed, and the transistors Q1R, Q1G, Q1B, and Q2 and the storage capacitor CsR of the red liquid crystal cell 22R are disposed in the pixel formed by the red liquid crystal cell 22R. In addition, the storage capacitors CsG and CsB of the green liquid crystal cell 22G and the blue liquid crystal cell 22B are arranged in the pixel by the green liquid crystal cell 22G. Thus, in this embodiment, the transistors Q1 to Q11 are efficiently arranged to sufficiently secure the area of the opening that can be assigned to the red, green, and blue pixels, and the area of the opening in the red, green, and blue pixels. Make sure that is not biased.

  However, when the storage capacitors CsG and CsB of the green liquid crystal cell 22G and the blue liquid crystal cell 22B are arranged in the pixels of the green liquid crystal cell 22G as described above, the storage capacitor CsB of the blue liquid crystal cell 22B is arranged below the green liquid crystal cell 22G. As a result, the green liquid crystal cell 22G may be affected by the pixel potential of the blue liquid crystal cell 22B, and a correct gradation may not be expressed.

  Therefore, in this embodiment (FIG. 1), at least for the storage capacitor CsB of the blue liquid crystal cell 22B arranged in the pixel of the green liquid crystal cell 22G, between the electrode of the storage capacitor CsB of the wiring layer 7 and the pixel electrode 11, A shield layer 31 is provided by the wiring layer 9, and this shield layer 31 is connected to the ground or a fixed potential.

  Thus, in this embodiment, the shield by the shield layer 31 can prevent the pixel potential of the green liquid crystal cell 22G from being affected by the pixel potential of the blue liquid crystal cell 22B, thereby making it possible to correct the green pixel to the correct level. Can be displayed in key. Thereby, in this embodiment, even if the area where the storage capacitor can be arranged is small, the required storage capacitor can be sufficiently secured.

(3) Effects of the embodiment According to the above configuration, the storage capacitor of the adjacent pixel is created in the lower layer of the pixel electrode, and the pixel potential side electrode and the pixel electrode that configure the storage capacitor of the adjacent pixel By providing a shield layer between the shields, the necessary storage capacity can be sufficiently ensured even when the area where the storage capacity can be arranged is small.

  In addition, by creating this shield layer with a wiring layer that connects the pixel electrode to the TFT, the shield layer can be provided by effectively using the existing process, and thereby an area where the storage capacitor can be arranged with a simple configuration. Even if it is small, a sufficient storage capacity can be secured.

  In addition, it is applied to a configuration in which one memory portion is assigned to a plurality of adjacent pixels and displayed by a memory method, and even if the layout of the TFT substrate is extremely biased, a sufficient storage capacity is ensured. Can do.

  In addition, by applying to a configuration in which an image is displayed by a memory method, an analog driving method, or the like, even if the layout of the TFT substrate is extremely biased, a necessary storage capacity can be sufficiently secured.

  FIG. 11 is a block diagram showing a liquid crystal display device according to Embodiment 2 of the present invention. The liquid crystal display device 41 displays a moving image and a still image based on the image data SDI on the display unit 42 by an analog driving method, and further displays a menu image based on the image data DV1. The selection of the menu displayed on the display unit 42 is detected by the controller 44, and the display on the display unit 42 is switched.

  Here, in the liquid crystal display device 41, an interface (I / F) 45 includes image data SDI output from a tuner unit, an external device, etc., various timing signals synchronized with the image data SDI, and an image output from the controller 44. Data DV1 is input, and the input image data SDI, DV1, and various timing signals are output to each unit under the control of the controller 44.

  The horizontal drive unit 46 distributes the image data SDI and DV1 output from the interface 45 to each signal line SIG provided in the display unit 42, and performs analog-digital conversion processing on the distributed image data, A drive signal Ssig is generated and output to the display unit 42. The vertical drive unit 47 generates a timing signal GATEL and drive signals VCOM, CS corresponding to the drive signal Ssig from the horizontal drive unit 46 and outputs them to the display unit 42.

  The display unit 42 is a transmissive or transflective liquid crystal display panel provided with a sensor circuit constituting a touch sensor at a predetermined pixel pitch. The display unit 42 is driven by the horizontal drive unit 46 and the vertical drive unit 47 according to image data SDI. A moving image, a still image, and a menu image based on the image data DV1 are displayed.

  The scan unit 48 generates and outputs various timing signals RST and SEL used for driving a sensor circuit provided in the display unit 42. The sensing unit 43 performs signal processing on the output signal SIGX of the sensor circuit output from the display unit 42, detects the coordinates X and Y of the location touched by the user, and sends the detected coordinates X and Y to the controller 44. Output.

  The controller 44 is a control unit that controls the operation of each unit, and controls the operation of the interface 45 to display a predetermined menu screen on the display unit 42. Further, the selection of the menu on this menu screen is detected based on the coordinates X and Y notified by the sensing unit 43, the display of the display unit 42 is switched in response to the selection of this menu, and further the source of the image data SDI. Switch etc.

  FIG. 12 is a block diagram showing a basic unit of the display unit 42. In this basic unit 51, the same components as those of the basic unit 21 in FIG. 3 are denoted by the corresponding reference numerals, and redundant description is omitted. Here, the basic unit 51 is a structural unit of the display unit 42, and in this embodiment, the basic unit 51 is composed of continuous red, green, and blue liquid crystal cells 22 R, 22 G, and 22 B and one sensor unit 52. In the display unit 42, the basic units 51 are arranged in a matrix on the TFT substrate so that the red, green, and blue liquid crystal cells 22R, 22G, and 22B are sequentially and continuously arranged, whereby the liquid crystal cells 22R, 22G are arranged. , 22B are arranged in a matrix.

  The basic unit 51 is red on the red, green, and blue signal lines SIGR, SIGG, and SIGB, respectively, via NMOS transistors Q12R, Q12G, and Q12B that are turned on and off by the gate signal GATEL output from the vertical drive unit 47. , Green and blue liquid crystal cells 22R, 22G, and 22B are connected, and the gradation of these liquid crystal cells 22R, 22G, and 22B is set by an analog driving method.

  Here, when a finger or the like approaches the display screen of the display unit 42, light emitted from the display unit 42 is reflected by the finger or the like, and return light to the display unit 42 is generated. The sensor unit 52 receives the return light and outputs an output signal corresponding to the amount of received light, an integration capacitor 54 for integrating the output signal of the sensor 53, and an amplification circuit for amplifying the integration result by the integration capacitor 54. 55, and a transistor Q13 which is turned on by the selection signal SEL and outputs the output signal of the amplifier circuit 55 to the signal line SIG for the sensor section.

  Here, FIG. 13 is a connection diagram showing a detailed configuration of the sensor unit 52 together with related configurations. In the sensor unit 52, a photosensor 56 that outputs a current corresponding to the amount of return light is applied to the sensor 53, and an output signal of the sensor 53 is supplied to one end of the integrating capacitor 54. In the sensor unit 52, the other end of the integration capacitor 54 is connected to a ground having a predetermined fixed potential, and one end of the integration capacitor 54 is connected to the power supply VDD via a PMOS transistor Q14 that is turned on by a reset signal RST. Is done.

  As shown in FIG. 14, the sensor unit 52 receives a reset signal RST from the scanning unit 48 in synchronization with the timing of gradation setting to the liquid crystal cells 22R, 22G, and 22B in the basic unit 51 provided with the sensor unit 52. In response to this reset signal RST, the transistor Q14 is turned on, and the voltage V1 (FIG. 14B) at one end of the integrating capacitor 54 is connected to the power supply voltage VDD. As a result, the accumulated charge in the integrating capacitor 54 is reset. Thereafter, the voltage V1 at one end of the integrating capacitor 54 gradually decreases in accordance with the amount of return light.

  The sensor unit 52 amplifies the voltage at one end of the integrating capacitor 54 with an amplifying circuit 55 using an NMOS transistor, and the output of the amplifying circuit 55 is output to the signal line SIG via the transistor Q13. Here, immediately before the voltage V1 at one end of the integrating capacitor 54 is reset to the power supply voltage VDD by the reset signal RST, the sensor unit 52 receives the selection signal SEL from the scan unit 48 (FIG. 14C), thereby The integration result by the integration capacitor 54 is output to the signal line SIG at the timing of the selection signal SEL.

  In this liquid crystal display device 41, as shown in FIG. 15, a reset signal RST () is sent to each basic unit 51 via a scanning line so as to sequentially select and reset the basic units 51 arranged along the signal line SIG. RST1, RST2,...) And a selection signal SEL (SEL1, SEL2,...) Are output. As a result, the measurement results OUT1, OUT2,... By the basic unit 51 arranged along the signal line SIG are output to the signal line SIG by time division.

  In this embodiment, the sensing unit 43 (FIG. 13) has a constant current source 57 connected to each signal line SIG, and converts the output signal SIGX of the sensor unit 52 detected at the input end of the constant current source 57 from analog to digital. The detection result by the basic unit 51 connected to the signal line SIG is acquired. The sensing unit 43 divides this analog-digital conversion result by the pixel value of the corresponding image data SDI, DV1, and normalizes the amount of return light. Further, the normalization result is determined by a predetermined threshold value, and the basic unit 51 in which the return light is received with a predetermined light amount or more is detected. The sensing unit 43 notifies the controller 44 of the detected coordinates X and Y of the basic unit 51.

  FIG. 16 is a plan view of the TFT substrate showing the layout of the basic unit 51. In this embodiment, the display unit 42 is configured by so-called vertical stripes in which pixels of the liquid crystal cells 22R, 22G, and 22B are arranged side by side in the extending direction of the scanning lines. In the display unit 42, transistors Q1R, Q1G, and Q1B are disposed in the liquid crystal cells 22R, 22G, and 22B, respectively. A sensor unit 52 is disposed in a pixel including green and blue liquid crystal cells 22G and 22B. Note that the sensor 53 of the sensor circuit is arranged in a pixel by the blue liquid crystal cell 22G. In addition, the storage capacitors CsR, CsG, and CsB of the liquid crystal cells 22R, 22G, and 22B are arranged in the pixels of the red liquid crystal cell 22R. However, the storage capacitor CsB of the blue liquid crystal cell 22B is arranged in the red liquid crystal cell 22R of the adjacent basic unit 51.

  Further, among the storage capacitors CsR, CsG, and CsB, at least the storage capacitors CsG and CsB of the green and blue liquid crystal cells 22G and 22B are provided with the shield layer 31 described above with reference to FIG. Connected to ground or fixed potential. Thus, in this embodiment, the influence of the pixel electrodes of the blue liquid crystal cell 22B and the green liquid crystal cell 22G in the red liquid crystal cell 22R is effectively avoided.

  According to this embodiment, the present invention can be applied to a configuration in which a sensor unit that detects the amount of return light is provided, and even if the layout of the TFT substrate is extremely biased, the necessary storage capacity can be sufficiently secured. it can.

  FIG. 17 is a plan view of a TFT substrate applied to the liquid crystal display device according to the third embodiment of the present invention in comparison with FIG. In this liquid crystal display device, spacers that secure a gap between the TFT substrate and the CF substrate are arranged at a predetermined pixel pitch. In this liquid crystal display device, due to the arrangement of the spacers, a space for creating a storage capacitor is insufficient in the pixels in which the spacers are arranged. Therefore, in this liquid crystal display device, the storage space is created by sequentially assigning the insufficient space to adjacent pixels.

That is, in the pixel of the blue liquid crystal cell 22B in FIG. 17, the storage capacitor CsB is disposed between the pixel of the blue liquid crystal cell 22B and the adjacent pixel of the green liquid crystal cell 22G. In the pixel of the adjacent green liquid crystal cell 22G, the storage capacitor CsG is disposed in the pixel of the green liquid crystal cell 22G and the pixel of the adjacent red liquid crystal cell 22R.

  In this way, with respect to the storage capacitors arranged in the adjacent pixels, correct gradation can be displayed by the arrangement of the shield layer 31 similar to that in the first embodiment or the second embodiment.

  According to this embodiment, even if the layout of the TFT substrate is biased by the arrangement of the spacers and the area where the storage capacitor can be created becomes small, the required storage capacitor can be sufficiently secured.

  FIG. 18 is a cross-sectional view of a TFT substrate applied to the liquid crystal display device of Example 4 of the present invention in comparison with FIG. In the liquid crystal display device of this embodiment, a counter electrode facing the pixel potential side electrode of the storage capacitor is formed by the wiring layer 9. The counter electrode is internally connected to the drive signal CS side electrode of the storage capacitor. As a result, in this embodiment, the capacity of the storage capacitor per unit area is set to almost twice that of the conventional configuration in which the storage capacitor is formed by the gate layer 5 and the wiring layer 7.

  In this liquid crystal display device, the storage capacitor is arranged in a lower layer of the liquid crystal cell related to the storage capacitor.

  According to this embodiment, by further creating a counter electrode between the pixel electrode and doubling the storage capacitor, the area where the storage capacitor can be arranged in each pixel has been reduced due to high resolution and the like. Even in this case, a sufficient storage capacity can be secured.

  In the first to third embodiments described above, the present invention is applied when the layout of the TFT substrate is biased by the arrangement of the memory portion, the sensor circuit, and the spacer, and the area in which a storage capacitor can be created in a specific pixel becomes small. Although the case where the present invention is applied is described, the present invention is not limited to this, and it is widely used when the layout of the TFT substrate is biased due to the arrangement of other configurations, and the area where a storage capacitor can be created in a specific pixel becomes small. Can be applied.

  In each of the above-described embodiments, the case where a desired image is displayed by switching between the memory method and the analog driving method or the analog driving method has been described. However, the present invention is not limited to this, and only the analog driving method is used. In this case, the present invention can be widely applied to the case where only the memory system is used.

  In each of the above-described embodiments, the case where a shield layer or a separate counter electrode is provided has been described. However, the present invention is not limited to this, and a liquid crystal display device may be configured by a combination thereof.

  In the above-described embodiments, the case where the shield layer and the like are formed using the wiring layer has been described. However, the present invention is not limited to this, and for example, the shield layer is formed using the common electrode layer in the FFS method and the ISP method. Or a shield layer or the like by laminating a metal film or the like.

  The present invention can be applied to, for example, a liquid crystal display device whose operation is switched between an analog drive method and a memory method.

It is sectional drawing which shows the structure of the TFT substrate which concerns on the liquid crystal display device of Example 1 of this invention. It is a block diagram which shows the liquid crystal display device of Example 1 of this invention. FIG. 3 is a connection diagram illustrating a basic unit of the liquid crystal display device of FIG. 2. 4 is a time chart for explaining the operation of the basic unit in FIG. 3. FIG. 4 is a connection diagram for explaining the operation of the analog drive system of the basic unit of FIG. 3. It is a time chart with which it uses for description of the setting of the memory part of the basic unit of FIG. FIG. 4 is a connection diagram for explaining setting of a memory unit of the basic unit in FIG. 3. It is a time chart with which it uses for description of the operation | movement by the memory system of the basic unit of FIG. FIG. 4 is a connection diagram for explaining an operation of the basic unit of FIG. 3 according to a memory system. FIG. 3 is a diagram for explaining a layout of a TFT substrate in the liquid crystal display device of FIG. 2. It is a block diagram which shows the liquid crystal display device of Example 2 of this invention. FIG. 12 is a connection diagram illustrating a basic unit of the liquid crystal display device of FIG. 11. It is a connection diagram with which it uses for description of operation | movement of the sensor part in the basic unit of FIG. It is a time chart with which it uses for description of operation | movement of the sensor part in the basic unit of FIG. 12 is a time chart for explaining the operation of a sensor unit in the liquid crystal display device of FIG. 11. FIG. 12 is a plan view showing a layout of a TFT substrate in the liquid crystal display device of FIG. 11. It is a top view which shows the layout of the TFT substrate in the liquid crystal display device of Example 3 of this invention. It is sectional drawing of the TFT substrate of FIG. It is a top view which shows the layout of the TFT substrate in the conventional liquid crystal display device. It is sectional drawing of the TFT substrate of FIG. It is sectional drawing which shows an auxiliary electrode. It is sectional drawing with which it uses for description of the influence by coupling | bonding with a pixel electrode.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... TFT substrate, 4 ... Transparent insulating substrate, 5 ... Gate layer, 6, 8, 10 ... Insulating film, 7, 9 ... Wiring layer, 11 ... Pixel electrode, 31 ... Shield layer, 13 ...... Display unit, 15, 36 ... Horizontal drive unit, 17, 47 ... Vertical drive unit, 18, 41 ... Liquid crystal display device, 21, 51 ... Basic unit, 22R, 22G, 22B ... Liquid crystal cell, 23... Memory section 52. Sensor section 53. Sensor 55 55 Amplifier circuit CsR, CsB, CsB Retention capacitance Q1 to Q13 Transistor

Claims (3)

In a liquid crystal display device in which a liquid crystal layer is sandwiched between a TFT substrate and a CF substrate, liquid crystal cells by the liquid crystal layer are arranged in a matrix to form a display unit, and a desired image is displayed by the display unit.
On an insulating substrate, the TFT substrate is produced by placing at least the pixel electrode of the liquid crystal cell and the transistor to be subjected to the driving of the liquid crystal cell,
A part or all of the storage capacitor of the adjacent liquid crystal cell is created under the pixel electrode with a shield layer interposed therebetween ,
A counter electrode of the storage capacitor is formed by a gate layer of the transistor and a wiring layer of the transistor;
The liquid crystal display device , wherein the shield layer is formed by a wiring layer that connects the transistor to the pixel electrode .   The transistor is
  A transistor of a memory unit that is assigned to a plurality of adjacent liquid crystal cells and records gradations of the plurality of adjacent liquid crystal cells;
  And a transistor for setting a gradation of the liquid crystal cell in accordance with recording in the memory unit.
  The liquid crystal display device according to claim 1.   The transistor is
  It is a transistor that switches the operation between a memory system and an analog drive system and sets the gradation of the liquid crystal cell.
  The liquid crystal display device according to claim 1.

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