JP5104874B2 - Lamination sequence inspection method and wiring board manufacturing method - Google Patents

Description

  The present invention relates to a stacking order inspection method and a wiring board manufacturing method for inspecting the stacking order of multilayer wiring boards.

  As electronic devices become more functional and denser, multilayer boards are required for wiring boards incorporated in these devices and mounted with components. The multilayer wiring board has a structure in which insulating layers and wiring layers are alternately stacked. There are mainly two methods for forming a multilayer wiring board. One is a method of forming a structure in which all the layers are laminated at once by performing pressing in a state where all the materials for the wiring layer and the insulating layer are stacked. The conductor patterns provided in each wiring layer are electrically coupled through a through hole formed through the wiring board after pressing. The other is to stack the wiring layers and insulating layers one by one, and then form vias in the stacked insulating layers to connect the conductor patterns on both sides of the insulating layers, and finally laminate all the layers. It is a method to do.

  In any of the methods, as the number of wiring boards increases, the number of sheets to be stacked increases in the process of stacking, and the work becomes complicated. Therefore, wiring boards stacked in the wrong order may be manufactured. For this reason, it is necessary to inspect whether or not the lamination is performed in a predetermined order.

  FIG. 1 is a plan view showing units constituting a wiring board to be inspected by a conventional stacking order inspection, and FIG. 2 is a plan view showing a state in which the units shown in FIG. 1 are stacked.

  The wiring board is formed by sequentially stacking n units 91L1,..., 91Ln-1, 91Ln from L1 to Ln shown in FIG. Each of the units 91L1 to 91Ln has a metal conductor pattern 913 and circuit patterns 914L1,..., 914Ln-1, 914Ln for forming a circuit wiring on the surface of an insulating plate 912 made of an insulating material. It is formed by etching or the like. In FIG. 1, the conductor pattern constituting the circuit wiring is shown in a simplified rectangular shape. The conductor patterns 914L1 to 914Ln for the stacking order inspection are formed in the vicinity of the edge of the insulating plate 912, and the positions of the units 91L1 to 91Ln are shifted along the above edge as they become the upper layer from the lower layer. Is arranged.

  The units 91L1 to 91Ln shown in FIG. 1 are stacked in order, and press and through-hole formation are performed, whereby the wiring board 90 shown in FIG. 2 is formed.

  In order to inspect the stacking order of the units 91L1 to 91Ln (see FIG. 2), the edge 912a of the wiring board is cut along a cutting line 93 passing through the conductor patterns 914L1 to 914Ln for stacking order inspection. The arrangement of the conductor patterns 914L1 to 914Ln is visually inspected.

  FIG. 3 is a diagram showing a cut surface obtained by cutting the wiring board of FIG. 2 along a cutting line. In FIG. 3, the positional relationship between the conductor patterns 914L1 to 914Ln is schematically shown.

  Since the conductive patterns 914L1 to 914Ln for stacking order inspection are arranged at positions shifted from each other along the edge 912a (see FIG. 1), when the units 91L1 to 91Ln are stacked in a predetermined order, As shown in FIG. 3, the conductor patterns 914L1 to 914Ln in FIG. That is, when the arrangement of the conductor patterns 914L1 to 914Ln is disturbed, it means that the stacking order is incorrect. According to this method, the stacking order can be inspected according to the arrangement state of the conductor patterns 914L1 to 914Ln appearing on the cut surface. However, in this method, there is a risk of inspection omission in visual inspection, and in particular, with the increase in the number of stacked units, the number of conductor patterns to be confirmed increases, and the risk of inspection omission increases. Therefore, a method for inspecting the stacking order by electrical measurement has been proposed.

  For example, in the method disclosed in Patent Document 1, for inspection of a wiring board composed of a first layer, a second layer, and a third layer, two wirings whose both ends are coupled to through-holes passing through the wiring board are connected at the center. It forms in a 2nd layer and a lower 3rd layer, respectively, and each resistance of these two wiring is measured. Each of the resistances of the two wirings is measured including through holes at both ends, and the magnitudes of the two resistance values are compared. According to this method, if there is an error in the stacking order, the distance between the through holes until reaching each wiring changes, so the magnitude relationship between the two measured values is reversed. Therefore, it is possible to determine whether or not the loading order is a predetermined order as planned.

Further, in Patent Document 2, vias for connecting conductor patterns on both sides of the insulating layer are formed in the stacked insulating layer while the wiring layer and the insulating layer are stacked one by one. Regarding a wiring board formed by a method of laminating layers, a method for inspecting the presence / absence of wiring by forming wiring for inspection via all wiring layers through vias and conductor patterns is shown. According to this method, if the stacking order is incorrect, the wiring is interrupted in the middle, so it is possible to determine whether or not the stacking order is as planned.
JP 59-172294 A (2nd page, lower left column, FIG. 3) JP-A-6-61652 (FIG. 2)

  However, in the method disclosed in Patent Document 1, it is necessary to measure the resistance of each wiring for each layer and compare the measured values at the time of measurement. Therefore, when the wiring layers are multi-layered, the measurement and comparison man-hours are required. Will increase. In addition, the wiring board of the type in which the conductor patterns of the respective layers are coupled with each other through holes does not necessarily interrupt conduction even if the stacking order is wrong. Therefore, the method disclosed in Patent Document 2 cannot be applied.

  In view of the above circumstances, the present invention provides a stacking order inspection method capable of easily inspecting the stacking order of conductor layers in a wiring board of a type in which conductors penetrating a plurality of insulating layers, such as through holes, are formed, And it aims at providing a wiring board manufacturing method.

The stacking order inspection method of the present invention that achieves the above object includes a plurality of insulating layers, a plurality of conductive layers alternately laminated with the plurality of insulating layers, each comprising a conductor pattern, and the plurality of insulating layers. Lamination for inspecting the laminating sequence of a multilayer wiring board that has a through conductor that penetrates and couples the conductor patterns of the plurality of conductor layers and that is planned to be laminated in a predetermined order. An order inspection method,
The electrical resistance value of a conductor path consisting of the conductor pattern and the through conductor and having both ends reaching one or both of the front and back surfaces of the multilayer wiring board through all of the plurality of conductor layers at least once. Measuring process to measure
A comparison process of comparing the electrical resistance value measured in the measurement process with a reference electrical resistance value of the conductor path when the plurality of conductor layers are stacked in the predetermined order. And

  In the stacking order inspection method of the present invention, if the conductor layers of the multilayer wiring board are not stacked in a predetermined order, the length of the portion that becomes a path for connecting the conductor patterns to each other among the through conductors is the predetermined predetermined length. It differs from the length when stacked in order. As a result, the electric resistance value of the conductor path including the through conductor is also different from the reference electric resistance value when the conductor layers are laminated in a predetermined order. Therefore, the stacking order in a wiring board of a type in which a conductor that penetrates a plurality of insulating layers, such as through holes, is formed, the electrical resistance value of the conductor path is measured once, and the measured electrical resistance value and the reference By comparing the electric resistance value, it can be easily inspected.

  Here, in the stacking order inspection method of the present invention, the measurement process is minimum when the plurality of conductor layers are stacked in the predetermined order among all possible stacking orders of the plurality of conductor layers. It is preferable to be a process of measuring the electrical resistance value or the electrical resistance value of the conductor path showing the maximum electrical resistance value.

  When the electrical resistance value is the minimum when laminated in a predetermined order, the measured electrical resistance value is necessarily larger than the reference electrical resistance value in a situation where the conductor layers are not laminated in the predetermined order. On the contrary, when the electrical resistance value is the maximum when laminated in a predetermined order, the measured electrical resistance value is higher than the reference electrical resistance value in a situation where the conductor layers are not laminated in the predetermined order. Be sure to get smaller. Therefore, in the comparison process, it is only necessary to compare whether the measured electrical resistance value is larger than the reference electrical resistance value or whether the measured electrical resistance value is smaller than the reference electrical resistance value. Well, the comparison process can be simplified.

  In the stacking order inspection method of the present invention, the measurement process is preferably a process of measuring an electrical resistance value of a conductor path having both ends reaching one of the front and back surfaces of the multilayer wiring board.

  When measuring the electrical resistance value of a conductor path having both ends reaching one of the front and back surfaces, a measurement probe can be connected to one of the front and back surfaces of the multilayer circuit board, so that the efficiency of the measurement work is improved. improves.

In addition, the wiring board manufacturing method of the present invention that achieves the above object includes a plurality of insulating layers, a plurality of conductor layers that are alternately laminated with the plurality of insulating layers, and each having a conductor pattern, and the plurality of insulating layers. A wiring board manufacturing method for manufacturing a multilayer wiring board having a through conductor that connects conductor patterns of the plurality of conductor layers through a layer,
Forming the multi-layer wiring board in which the plurality of conductor layers are scheduled to be laminated in a predetermined order; and
The electrical resistance value of a conductor path consisting of the conductor pattern and the through conductor and having both ends reaching one or both of the front and back surfaces of the multilayer wiring board through all of the plurality of conductor layers at least once. Measuring process to measure
A comparison process of comparing the electrical resistance value measured in the measurement process with a reference electrical resistance value of the conductor path when the plurality of conductor layers are stacked in the predetermined order. And

  In the wiring board manufacturing method of the present invention, for example, a stacking order inspection is performed on a wiring board of a type in which a conductor penetrating a plurality of insulating layers such as a through hole is formed, and an electrical resistance value of a conductor path is measured once. This can be done by comparing the measured electrical resistance value with a reference electrical resistance value. Therefore, wiring board manufacture becomes easy.

  Here, also in the wiring board manufacturing method, the measurement process includes a minimum electric resistance when the plurality of conductor layers are laminated in the predetermined order among all possible lamination orders of the plurality of conductor layers. Preferably, this is a process of measuring the value or the electric resistance value of the conductor path showing the maximum electric resistance value.

  In the wiring board manufacturing method, it is preferable that the measurement process is a process of measuring an electrical resistance value of a conductor path having both ends reaching one of the front and back surfaces of the multilayer wiring board.

  As described above, according to the present invention, a stacking order inspection method capable of easily inspecting a stacking order in a type of wiring board in which a conductor penetrating a plurality of insulating layers is formed, and wiring board manufacture The method is realized.

It is a top view which shows the unit which comprises the wiring board test | inspected by the lamination | stacking order test | inspection of a prior art. It is a top view which shows the state by which each unit shown in FIG. 1 was laminated | stacked. It is a figure which shows the cut surface which cut | disconnected the wiring board of FIG. 2 with the cutting line. It is a top view which shows the wiring board manufactured by 1st Embodiment of the wiring board manufacturing method of this invention. It is the sectional view on the AA line of the wiring board shown in FIG. It is a flowchart which shows one Embodiment of the wiring board manufacturing method of this invention. It is a figure explaining the formation process of the wiring board by which the some insulating layer and conductor layer were laminated | stacked alternately. It is sectional drawing which shows the structure of the wiring board loaded in the order different from a predetermined order. It is sectional drawing which shows the structure of the wiring board manufactured by 3rd Embodiment of the wiring board manufacturing method of this invention. It is a top view which shows the wiring board manufactured by the wiring board manufacturing method which is 3rd Embodiment of this invention. It is sectional drawing which shows the structure of the wiring board shown in FIG. It is sectional drawing which shows the structure of the wiring board manufactured by 4th Embodiment of the wiring board manufacturing method of this invention.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 4 is a plan view showing the multilayer wiring board manufactured by the first embodiment of the wiring board manufacturing method of the present invention, and FIG. 5 is a cross-sectional view taken along line AA of the wiring board shown in FIG. In FIG. 5, hatching is omitted to make it easy to see the shape of each part.

  A multilayer wiring board (hereinafter, simply referred to as a wiring board) 10 shown in FIGS. 4 and 5 has six conductor layers 11L1, 11L2, 11L3, 11L4, 11L5, and 11L6 each formed of a conductor pattern. . The conductor layers 11L1 to 11L6 are alternately stacked with five insulating layers 12L1, 12L2, 12L3, 12L4, and 12L5. As shown in FIG. 5, the conductor layers 11L1 to 11L6 include the first conductor layer 11L1, the second conductor layer 11L2, the third conductor layer 11L3, the fourth conductor layer 11L4, the fifth conductor layer 11L5, The sixth conductor layer 11L6 is scheduled to be laminated in a predetermined order. However, the conductor layers 11L1 to 11L6 may be stacked in an order different from the predetermined order by mistake. Of the front and back surfaces of the wiring board 10 shown in FIG. 5, the side of the sixth conductor layer 11L6 is the front surface, and the side of the first conductor layer 11L1 is the back surface. The description will be continued with the sixth conductor layer 11L6 as the lowermost layer and the first conductor layer 11L1 as the uppermost layer.

  Seven through holes 131, 132, 133, 134, 135, 136, and 137 are formed in the wiring board 10 through the insulating layers 12L1 to 12L5. Inner walls 131a to 137a of the respective through holes 131 to 137 are formed of a metal (for example, copper) layer formed by plating, and the inner walls 131a to 137a also penetrate the insulating layers 12L1 to 12L5. The inner walls 131a to 137a of the respective through holes 131 to 137 correspond to an example of the through conductor referred to in the present invention. In the following description, the through holes 131 to 137 will be described as having a concept including inner walls 131a to 137a made of metal.

  The sixth conductor layer 11L6 shown in the plan view of FIG. 4 includes six conductor patterns 141, 142, 143, 144, 145, and 146 from the first conductor pattern 141 to the sixth conductor pattern 146. Among the six conductor patterns 141 to 146, the sixth conductor pattern 146 is provided to extend from the opening portion of the through hole 137 to the opening portion of the through hole 136. The remaining conductor patterns 141 to 145 are formed around the respective opening portions of the through holes 131 to 135.

  Among the six conductor layers 11L1 to 11L6, the fifth conductor layer 11L5 arranged second from the top is composed of a conductor pattern 151 extending from the through hole 137 to the through hole 136. The fourth conductor layer 11L4 includes a conductor pattern 151 extending from the through hole 145 to the through hole 144, and the third conductor layer 11L3 includes a conductor pattern 152 extending from the through hole 144 to the through hole 143. The second conductor layer 11L2 includes a conductor pattern 153 extending from the through hole 143 to the through hole 142. The first conductor layer 11L1 includes six conductor patterns 161, 162, 163, 164, 165, and 166 from the first conductor pattern 161 to the sixth conductor pattern 166, and among these, the first conductor pattern 161 is included. Extends from the through hole 131 to the through hole 132. The remaining conductor patterns 162 to 166 of the first conductor layer 11L1 are provided around the openings of the through holes 133 to 137, respectively.

  In the wiring board 10 shown in FIG. 5, the through hole 132 electrically couples the first conductor pattern 161 of the first conductor layer 11L1 and the conductor pattern 154 of the second conductor layer 11L2. The through hole 133 electrically couples the conductor pattern 154 of the second conductor layer 11L2 and the conductor pattern 153 of the third conductor layer 11L3. In addition, the through hole 134 electrically couples the conductor pattern 153 of the third conductor layer 11L3 and the conductor pattern 152 of the fourth conductor layer 11L4. Further, the through hole 135 electrically couples the conductor pattern 152 of the fourth conductor layer 11L4 and the conductor pattern 151 of the fifth conductor layer 11L5. Further, the through hole 136 electrically couples the conductor pattern 151 of the fifth conductor layer 11L5 and the sixth conductor pattern 146 of the sixth conductor layer 11L6.

  As a result, through holes 131 to 136 and the first conductor layer are arranged between the sixth conductor pattern 146 and the first conductor pattern 141 of the sixth conductor layer 11L6 disposed on the surface of the wiring board 10. The first conductor pattern 161 of 11L1, the conductor pattern 154 of the second conductor layer 11L2, the conductor pattern 153 of the third conductor layer 11L3, the conductor pattern 152 of the fourth conductor layer 11L4, and the fifth conductor A conductor path P1 including the conductor pattern 151 of the layer 11L5 and the sixth conductor pattern 146 of the sixth conductor layer 11L6 is formed. The conductor path P1 passes through all the six conductor layers 11L1 to 11L6 once. Further, both ends E1, E2 of the conductor path P1 reach the front surface of the wiring board 10.

  The wiring board 10 has a structure in which the conductor patterns of the respective conductor layers are coupled by through holes 133 to 137 penetrating the insulating layers 12L1 to 12L5. For this reason, even if the six conductor layers 11L1 to 11L6 are stacked in a different order from the predetermined order shown in FIG. 5, the sixth conductor pattern 146 and the first conductor pattern 141 in the sixth conductor layer 11L6. Conduction between and. However, the distance of the path formed when the conductor layers 11L1 to 11L6 are stacked in an order different from the predetermined order is different from the distance of the path formed when the conductor layers 11L1 to 11L6 are stacked in the predetermined order. Will also be different. More specifically, the conductor path P1 is the shortest when the six conductor layers 11L1 to 11L6 are stacked in the predetermined order among all possible stacking orders, and therefore the electric resistance value of the conductor path P1 is When the layers are laminated in a predetermined order, the minimum value is indicated.

  The wiring board 10 shown in FIGS. 4 and 5 can be manufactured by a forming process in which the material to be the conductor layers 11L1 to 11L6 and the material to be the insulating layers 12L1 to 12L5 are alternately stacked. However, since the conductor layers 11L1 to 11L6 may be stacked in an order different from the predetermined order, it is necessary to inspect the stacking order of the formed wiring boards after the forming process.

  FIG. 6 is a flowchart showing an embodiment of the method for manufacturing a wiring board of the present invention.

  The wiring board manufacturing method shown in FIG. 6 includes a forming process (S1), a measuring process (S2), and a comparing process (S3) for forming a wiring board, and the measuring process (S2) and the comparing process (S3). Then, the stacking order of the formed wiring boards is inspected. Here, the measurement process (S2) and the comparison process (S3) for inspecting the stacking order correspond to an embodiment of the stacking order inspection method of the present invention. First, the formation process will be described, and then each process for inspecting the stacking order of the formed wiring boards will be described.

  FIG. 7 is a diagram for explaining a process of forming a wiring board in which a plurality of insulating layers and conductor layers are alternately laminated. FIG. 7 shows an example in which the conductor layers are generalized to n layers from the first conductor layer to the nth conductor layer.

  In the process of forming the wiring board (S1 in FIG. 6), first, based on the design data including the shape and arrangement information of the conductor pattern of each conductor layer, a photo film (AW film) used for photoetching is used for each conductor. Create for each layer. Illustrations of design data and photo film are omitted.

  Next, the laminated units 21_1 to 21_m to be laminated are created using a photo film. The laminated units 21_1 to 21_m are formed by performing photo-etching on a copper foil plate material in which a copper foil layer is formed on the entire front and back surfaces of a flat core material made of an insulating material such as a resin. Although illustration is omitted, in more detail, a photosensitizer is applied on the copper foil layer of the copper foil plate material, the back surface is exposed using a photo film corresponding to the second conductor layer, and the surface is exposed. Exposure is performed using a photo film corresponding to the third conductor layer. Thereafter, development, etching, and photosensitizer removal are performed to form a conductor pattern of each conductor layer. First, a first stacked unit 21_1 (see FIG. 7) is formed by photoetching. For example, if the wiring board to be manufactured is, for example, the six-layer wiring board 10 shown in FIG. 5, the core material 212 (FIG. 7) of the first stacked unit 21_1 is finally the second insulating layer 12L2. As shown in FIG. 5, the conductor patterns 211 and 213 formed on the front and back surfaces of the core material 212 are finally formed into the second conductor layer 11L2 and the third conductor layer 11L3, respectively. Moreover, the conductor pattern corresponding to the 4th conductor layer and the 5th conductor layer is formed in another board | plate material, and the 2nd lamination | stacking unit 21_2 is formed. The stacked units are formed up to m corresponding to the (n-1) th conductor layer.

  Next, the members are stacked as shown in FIG. First, the prepreg 23_1 is placed on the copper foil 22 serving as the lowermost conductor layer. At this point, no pattern is formed on the copper foil 22. The prepreg is a sheet-like insulating member made of a thermosetting resin or a thermoplastic resin. The first stacked unit 21_1 is stacked on the prepreg 23_1, and the prepreg 23_2 is stacked on the first stacked unit 21_1. In this way, the stacked units and the prepreg are alternately stacked up to the last stacked unit 21_m. For example, when the six-layer wiring board 10 shown in FIG. 5 is formed, the lowermost prepreg 23_1 (FIG. 7) becomes the first insulating layer 12L1 (FIG. 5), and the prepreg 23_2 (FIG. 7) thereon. Becomes the third insulating layer 12L3 (FIG. 5). The copper foil 24 on which no pattern is formed is overlaid on the last-prepared prepreg 23_m + 1. In this manner, the copper foil, the prepreg, and the laminated unit are stacked one by one. Since the prepreg is a flexible sheet and it is not easy to place it on a machine, the operation of placing the prepreg is generally performed manually.

  Next, the stacked ones are put on a press machine to apply pressure in the vertical direction, and are placed in a high-temperature atmosphere that melts the prepreg. As a result, the prepreg adheres to the upper and lower layers. After cooling at room temperature, a through hole to be a through hole is formed with a drill, and copper is deposited on the inner wall of the through hole by a copper plating process to form a through hole.

  Next, photoetching is performed on the lowermost copper foil 22 and the uppermost copper foil 24. More specifically, photoconductor coating, exposure, development, etching, and photosensitizer removal are performed to form a conductor pattern corresponding to each conductor layer. For example, when the six-layer wiring board 10 shown in FIG. 5 is formed, the lowermost copper foil 22 (FIG. 7) becomes the first conductor layer 11L1 (FIG. 5), and the uppermost copper foil 24 (FIG. 5). 7) becomes the sixth conductor layer 11L6 (FIG. 5).

  Finally, a solder resist is applied by printing on the lowermost copper foil 22 and the uppermost copper foil 24 on which the conductor pattern is formed, and a desired size is cut out to complete the wiring board formation process. The wiring board is complete. The wiring boards shown in FIGS. 4 and 5 described above are also formed by this formation process. In the formed wiring board, the conductor layers are scheduled to be laminated in the predetermined order shown in FIG. 5, but if there is an error in the order of stacking the laminated units in the formation process, the order is different from the predetermined order. May be stacked.

  Here, referring again to FIGS. 4 and 5, a stacking order inspection method for inspecting the stacking order of the formed wiring boards will be described.

In the stacking order inspection, first, in the measurement process (S2 in FIG. 6), the electrical resistance value of the conductor path P1 indicated by the one-dot chain line in FIG. 5 is measured. Both ends E1, E2 of the conductor path P1 reach the surface of the wiring board 10, and one end E1 of the sixth conductor pattern 146 formed in the sixth conductor layer 11L6 is a through hole 137. The other end E2 is located in the first conductor pattern 141 formed in the sixth conductor layer 11L6. Therefore, in the measurement process, the probe of the measuring instrument is brought into contact with the portion of the sixth conductor pattern 146 on the side of the through hole 137 and the first conductor pattern 141, and the electrical resistance value is measured. As a result, the electrical resistance value of the conductor path P1 passing through all of the conductor layers 11L1 to 11L6 at least once is measured. Next, in the comparison process (S3 in FIG. 6), the electrical resistance value measured in the measurement process. And a reference electric resistance value are compared. The reference electrical resistance value is an electrical resistance value that the conductor path P1 has when the conductor layers 11L1 to 11L6 are laminated in a predetermined order. The reference electrical resistance value is the electrical resistance between the first conductor pattern 141 and the through hole 137 side of the sixth conductor pattern 146 in the reference wiring board in which the conductor layers 11L1 to 11L6 are laminated in a predetermined order. It is obtained by measuring the resistance value in advance. Note that the reference wiring board stacking order can be confirmed over time such as destructive inspection.

  As a result of the comparison, if the measured electrical resistance value matches the reference electrical resistance value, it is determined that the measured wiring boards are laminated in a predetermined order. On the other hand, if the measured electrical resistance value and the reference electrical resistance value do not match, it is determined that the measured wiring board is in the wrong stacking order. The conductor path P1 of the wiring board 10 shown in FIG. 4 and FIG. 5 is the minimum electric current when the conductor layers are laminated in the predetermined order shown in FIG. 5 among all possible lamination orders for the conductor layers 11L1 to 11L6. Indicates the resistance value. That is, in the measurement process in the present embodiment, the electrical resistance value of the conductor path showing the minimum electrical resistance value is measured when a plurality of conductor layers are laminated in a predetermined order among all possible lamination orders. . In this case, in a situation where the conductor layers are not laminated in a predetermined order, the measured electric resistance value is necessarily larger than the reference electric resistance value. Therefore, in the comparison process, it is only necessary to compare whether or not the measured electric resistance value is larger than the reference electric resistance value.

  FIG. 8 is a cross-sectional view showing the structure of the wiring boards stacked in an order different from the predetermined order. In FIG. 8, hatching is omitted to make the conductor path easy to see, and the inner wall surface of the through hole is also omitted.

  The wiring board 30 shown in FIG. 8 is obtained by stacking the two laminated units in the reverse order in the formation process. As a result, the fourth conductor layer 31L4, the fifth conductor layer 31L5, the second conductor layer 11L1 are formed on the first conductor layer 11L1. The second conductor layer 31L2, the third conductor layer 31L3, and the sixth conductor layer 11L6 are sequentially stacked. That is, the first conductor layer 11L1 and the sixth conductor layer 11L6 are arranged at the same position as the wiring board 10 laminated in a predetermined order shown in FIG. 5, but the fourth conductor layer 31L4, the fifth conductor layer 11L6 The conductor layer 31L5, the second conductor layer 31L2, and the third conductor layer 31L3 are arranged at different positions. The conductor path P3 of the wiring board 30 in which the conductor layers are stacked in the wrong order passes through all of the conductor layers once, but has a different length from the conductor path P1 of the wiring board 10 shown in FIG. More specifically, it is longer than the conductor path P1 of the wiring board 10 shown in FIG.

  Therefore, when the electrical resistance value of the conductor path in the wiring board shown in FIG. 8 is measured in the measurement process, and the measured electrical resistance value is compared with the reference electrical resistance value in the comparison process, the comparison results are inconsistent. More specifically, the measured electrical resistance value is greater than the reference electrical resistance value. Therefore, it can be seen from the comparison results that the wiring board 30 whose electrical resistance value was measured in the measurement process was laminated in an incorrect order, unlike the predetermined order of the conductor layers.

  In order to obtain the reference electric resistance value, it has been explained that the conductor path of the reference wiring board is measured. Here, there is a slight machine difference in the electrical resistance value due to a dimensional tolerance or the like for the reference wiring board. For this reason, in the process of obtaining the reference electrical resistance value, measurement is performed on a plurality of reference wiring boards, and the maximum and minimum values of the obtained electrical resistance values are compared as reference electrical resistance values. Preferably used in the process. The electrical resistance value of the conductor path of the wiring board according to the present embodiment shows the minimum when a plurality of conductor layers are laminated in the predetermined order shown in FIG. 5 among all possible lamination orders. The maximum value among the electrical resistance values obtained for the wiring board is determined as the reference electrical resistance value. In the comparison process, when the electrical resistance value measured in the measurement process is larger than the reference electrical resistance value, it is determined that the stacking order of the conductor layers is different from the predetermined order, and conversely, the measured electrical resistance value is the reference electrical resistance value. When the electrical resistance value is less than or equal to, it is determined that the conductor layers are laminated in a predetermined order. As the reference electrical resistance value, a value including a margin in consideration of a deviation or the like can be used for the measurement result of the reference wiring board.

  Subsequently, a second embodiment of the present invention will be described. In the following description of the second embodiment, the same elements as those in the embodiments described so far are denoted by the same reference numerals or omitted, and differences from the above-described embodiments will be described. explain.

  FIG. 9 is a cross-sectional view showing the structure of the wiring board manufactured by the second embodiment of the wiring board manufacturing method of the present invention. In FIG. 9, hatching is omitted to make the shape of each part easy to see, and illustration of the inner wall surface of the through hole is also omitted.

  The wiring board 40 shown in FIG. 9 has conductor layers 41L1, 41L2, 41L3, 41L4, 41L5, and 41L6. The conductor layers 41L1 to 41L6 are, from the bottom, the first conductor layer 41L1, the second conductor layer 41L2, the third conductor layer 41L3, the fourth conductor layer 41L4, the fifth conductor layer 41L5, and the sixth conductor. The layers 41L6 are stacked in a predetermined order. In the wiring board 40 according to this embodiment, the distance of the conductor path P4 is maximized when the wiring boards 40 are laminated in a predetermined order shown in FIG. Therefore, the electrical resistance value of the conductor path P4 shows the maximum value when the conductor layers 41L1 to 41L6 are laminated in a predetermined order.

  In the measurement process in the present embodiment, the electrical resistance value of the conductor path P4 is measured. More specifically, the through hole 137 side portion of the sixth conductor pattern 446 in the sixth conductor layer 41L6, which is one end E1 of the conductor path P4, and the first end that is the other end E2. The electrical resistance value between the conductor pattern 441 is measured. In the comparison process, the electrical resistance value measured in the measurement process is compared with the reference electrical resistance value.

  In the present embodiment, when the conductor layers 41L1 to 41L6 are laminated in a different order from the predetermined order, the measured electrical resistance value is necessarily smaller than the reference electrical resistance value. Therefore, in the comparison process, it is compared whether or not the measured electric resistance value is smaller than the reference electric resistance value. If the measured electrical resistance value is equal to or greater than the reference electrical resistance value, it is determined that the wiring boards measured in the measurement process are laminated in a predetermined order.

  Subsequently, a third embodiment of the present invention will be described. In the following description of the third embodiment, the same elements as those in the embodiments described so far are denoted by the same reference numerals or omitted, and differences from the above-described embodiments will be described. explain.

  FIG. 10 is a plan view showing a wiring board manufactured by the third embodiment of the wiring board manufacturing method of the present invention. FIG. 11 is a cross-sectional view showing the structure of the wiring board shown in FIG. In FIG. 11, hatching is omitted to make the shape of each part easy to see, and the inner wall surface of the through hole is also omitted.

  A conductor path P5 is formed in the wiring board 50 shown in FIGS. The conductor path P5 has a configuration in which conductor paths P1 formed by the wiring board 10 shown in FIGS. 4 and 5 are arranged in three stages and electrically connected in series. The conductor path P5 passes through all of the six conductor layers 51L1 to 51L6 provided in the wiring board 50 three times.

  When the wiring boards 50 are stacked in an order different from the predetermined order shown in FIG. 11, the electrical resistance value of the conductor path P5 measured in the measurement process is different from the reference electrical resistance value. Here, the conductor path P5 in the wiring board 50 corresponds to three conductor paths P1 in the wiring board 10 of FIG. Therefore, the difference between the wiring paths formed when the conductor layers are laminated in a predetermined order and when the conductor layers are laminated in a different order from the predetermined order is three times as large as that of the wiring board 10 of FIG. As a result, the difference between the electrical resistance value measured in the measurement process and the reference electrical resistance value is also expanded three times as compared with the wiring board 10 of FIG. Therefore, it is possible to accurately compare the electrical resistance value measured in the measurement process in the comparison process with the reference electrical resistance value.

  In the above-described embodiment, an example of a configuration in which the wiring route illustrated in FIG. 5 is repeated has been described, but the pattern of the repeated wiring route is not limited to this example. Subsequently, a fourth embodiment of the present invention, which is different from the above-described third embodiment in a repeated pattern, will be described.

  FIG. 12 is a cross-sectional view showing the structure of the wiring board manufactured by the fourth embodiment of the wiring board manufacturing method of the present invention.

  The conductor path P6 formed in the wiring board 60 shown in FIG. 12 has a structure in which the conductor paths P4 formed in the wiring board 40 shown in FIG. Yes. The conductor path P6 passes through all of the six conductor layers 61L1 to 61L6 of the wiring board 60 three times. Also in the wiring board 60 according to the present embodiment, when the conductor layers 61L1 to 61L6 are stacked in an order different from the predetermined order, the difference between the electrical resistance value measured in the measurement process and the reference electrical resistance value is shown in FIG. Compared with the wiring board 40 shown in FIG. Therefore, the comparison in the comparison process can be performed with high accuracy.

  In the above-described embodiment, the example of the wiring board having six conductor layers has been described. However, the present invention is not limited to this, and for example, if there are a plurality of conductor layers, the number of layers is other than six. May be.

  In the above-described embodiment, the example in which the conductor path is minimum or maximum when stacked in a predetermined order has been described. However, the present invention is not limited to this, and the case where the conductor paths are stacked in a predetermined order is described. It is only necessary that the wiring is formed so that the electrical resistance value of the conductor path is different from the case where the electrical resistance values are laminated in a different order from the predetermined order.

  In the above-described embodiment, the example of the wiring board in which only the conductor pattern for inspecting the stacking order of the wiring layers is described, but the present invention is not limited to this, and the wiring board includes Naturally, a conductor pattern for electrically coupling the mounted electrical components may be formed.

  In addition, the conductor pattern constituting the conductor path for measuring the electrical resistance value may also be used as a conductor pattern for electrically coupling the mounted electrical components.

  In the above-described embodiment, the example of the inner wall of the through hole has been described as the through conductor. However, the present invention is not limited to this. For example, the metal is formed in the hole formed through the plurality of insulating layers. It may be an embedded via.

Claims (8)

A plurality of insulating layers, a plurality of conductor layers each of which is alternately laminated with the plurality of insulating layers, each composed of a conductor pattern, and the conductor patterns of the plurality of conductor layers are coupled through the plurality of insulating layers. A stacking order inspection method for inspecting a stacking order of a multilayer wiring board in which the plurality of conductor layers are scheduled to be stacked in a predetermined order.
Between the both ends of the conductor path consisting of the conductor pattern and the through conductor and having both ends reaching one or both of the front and back surfaces of the multilayer wiring board through all of the plurality of conductor layers at least once a measuring process of measuring an electrical resistance value in,
A comparison step of comparing the electrical resistance value measured in the measurement process with a reference electrical resistance value of the conductor path when the plurality of conductor layers are stacked in the predetermined order. A stacking order inspection method.   The measuring process measures an electrical resistance value of a conductor path that exhibits a minimum electrical resistance value when the plurality of conductor layers are stacked in the predetermined order among all possible stacking orders of the plurality of conductor layers. The stacking sequence inspection method according to claim 1, wherein the stacking sequence inspection method is a step of performing the steps.   The measuring process measures an electrical resistance value of a conductor path that exhibits a maximum electrical resistance value when the plurality of conductor layers are stacked in the predetermined order among all possible stacking orders of the plurality of conductor layers. The stacking sequence inspection method according to claim 1, wherein the stacking sequence inspection method is a step of performing the steps.   4. The method according to claim 1, wherein the measuring process is a process of measuring an electrical resistance value of a conductor path having both ends reaching one of the front and back surfaces of the multilayer wiring board. 5. Stacking order inspection method. A plurality of insulating layers, a plurality of conductor layers each of which is alternately laminated with the plurality of insulating layers, each composed of a conductor pattern, and the conductor patterns of the plurality of conductor layers are coupled through the plurality of insulating layers. A wiring board manufacturing method for manufacturing a multilayer wiring board having a penetrating conductor,
Forming the multilayer wiring board in which the plurality of conductor layers are scheduled to be laminated in a predetermined order; and
Between the both ends of the conductor path consisting of the conductor pattern and the through conductor and having both ends reaching one or both of the front and back surfaces of the multilayer wiring board through all of the plurality of conductor layers at least once a measuring process of measuring an electrical resistance value in,
A comparison step of comparing the electrical resistance value measured in the measurement process with a reference electrical resistance value of the conductor path when the plurality of conductor layers are stacked in the predetermined order. Wiring board manufacturing method.   The measuring process measures an electrical resistance value of a conductor path that exhibits a minimum electrical resistance value when the plurality of conductor layers are stacked in the predetermined order among all possible stacking orders of the plurality of conductor layers. The wiring board manufacturing method according to claim 5, wherein the wiring board manufacturing process is performed.   The measuring process measures an electrical resistance value of a conductor path that exhibits a maximum electrical resistance value when the plurality of conductor layers are stacked in the predetermined order among all possible stacking orders of the plurality of conductor layers. The wiring board manufacturing method according to claim 5, wherein the wiring board manufacturing process is performed.   The wiring according to any one of claims 5 to 7, wherein the measuring process is a process of measuring an electric resistance value of a conductor path having both ends reaching one of the front and back surfaces of the multilayer wiring board. Plate manufacturing method.

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