JP5089074B2 - Storage device - Google Patents

Description

The present invention relates to a memory device and a semiconductor device including the memory device.

In recent years, development of semiconductor devices having various functions in which a plurality of circuits are integrated on an insulating surface has been promoted. In addition, development of a semiconductor device capable of transmitting and receiving data wirelessly by providing an antenna is in progress. Such a semiconductor device is called a wireless chip (also referred to as an ID tag, an IC tag, an IC chip, an RF (Radio Frequency) tag, a wireless tag, an electronic tag, or an RFID (Radio Frequency Identification) tag). Has been introduced in the market.

Many of these semiconductor devices in practical use have a circuit (also referred to as an IC (Integrated Circuit) chip) using a semiconductor substrate such as Si and an antenna, and the IC chip is a memory circuit (also referred to as a memory). ) And a control circuit. In particular, by providing a memory circuit capable of storing a large amount of data, a semiconductor device with higher functions and higher added value can be provided. In addition, these semiconductor devices are required to be manufactured at low cost, and in recent years, development of organic TFTs and organic memories using organic compounds in control circuits, memory circuits, etc. has been actively carried out (for example, Patent Document 1).
JP 2002-26277 A

  The storage circuit, DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), FeRAM (Ferroelectric Random Access Memory), mask ROM (Read Only Memory), EPROM (Electrically Programmable Read Only Memory), EEPROM (Electrically Erasable and Programmable Read Only Memory), flash memory, and the like. Among these, DRAM and SRAM are volatile storage circuits, and data is erased when the power is turned off. Therefore, it is necessary to write data every time the power is turned on. FeRAM is a non-volatile memory circuit, but a manufacturing process increases because a capacitor element including a ferroelectric layer is used. Although the mask ROM has a simple structure, it is necessary to write data in the manufacturing process and cannot be additionally written. Although EPROM, EEPROM, and flash memory are non-volatile memory circuits, the number of manufacturing steps increases because an element including two gate electrodes is used.

  In view of the above problems, an object of the present invention is to provide a nonvolatile memory device capable of writing and erasing data other than at the time of manufacturing and a semiconductor device having the nonvolatile memory device. It is another object of the present invention to provide a small and inexpensive nonvolatile memory device and a semiconductor device including the nonvolatile memory device.

One embodiment of the present invention includes a memory element including a pair of conductive layers and an organic compound sandwiched between the pair of conductive layers. The organic compound has liquid crystallinity, and the first voltage is applied to the pair of conductive layers. Is applied to the organic compound, and the organic compound is heated to cause phase transition of the organic compound from the first phase to the second phase, thereby recording data.

Another embodiment of the present invention includes a memory cell array in which memory elements are arranged in a matrix and a writing circuit, and the memory element includes a pair of conductive layers and an organic compound sandwiched between the pair of conductive layers. The organic compound has liquid crystallinity, and the data is obtained by applying a first voltage to the pair of conductive layers and heating the organic compound to change the phase of the organic compound from the first phase to the second phase. Is a storage device.

Another embodiment of the present invention includes a memory cell array in which memory cells are arranged in a matrix and a writing circuit. The memory cell includes a transistor and a memory element. The memory element includes a pair of conductive layers and a pair of conductive layers. An organic compound sandwiched between the conductive layers, and the organic compound has liquid crystallinity, the first voltage is applied to the pair of conductive layers, the organic compound is heated, and the organic compound is converted into the first phase. The storage device is characterized in that data is recorded by performing phase transition from the first phase to the second phase.

Another embodiment of the present invention includes a memory cell array in which memory elements are arranged in a matrix, a writing circuit, and an erasing circuit, and the memory elements are sandwiched between a pair of conductive layers and a pair of conductive layers. The organic compound has liquid crystallinity, the first voltage is applied to the pair of conductive layers, the organic compound is heated, and the organic compound is phase-shifted from the first phase to the second phase. Data is recorded, and a second voltage is applied to the pair of conductive layers to heat the organic compound, and the data is erased by causing the organic compound to transition from the second phase to the first phase. And a storage device.

Another embodiment of the present invention includes a memory cell array in which memory cells are arranged in a matrix, a writing circuit, and an erasing circuit. The memory cell includes a transistor and a memory element. The memory element is a pair of conductive elements. The organic compound sandwiched between the pair of conductive layers, the organic compound has liquid crystallinity, the first voltage is applied to the pair of conductive layers to heat the organic compound, and the organic compound is Data is recorded by phase transition from the first phase to the second phase, a second voltage is applied to the pair of conductive layers, and the organic compound is heated to remove the organic compound from the second phase. A storage device is characterized in that data is erased by phase transition to one phase.

  The organic compound is an isotropic phase in the first temperature range, a smectic phase in the second temperature range, a crystalline phase in the third temperature range, and the first temperature range is greater than the second temperature range. The second temperature range is higher than the third temperature range.

  Note that when a first voltage is applied to the pair of conductive layers after the organic compound is heated to be a first phase and then rapidly cooled, the first phase is an isotropic phase and the second phase is It is a smectic phase. Alternatively, the first phase is an isotropic phase and the second phase is a crystalline phase. Alternatively, the first phase is a smectic phase and the second phase is a crystalline phase.

Another embodiment of the present invention includes a memory cell array in which memory elements are arranged in a matrix, a writing circuit, and an erasing circuit, and the memory elements are sandwiched between a pair of conductive layers and a pair of conductive layers. The organic compound has liquid crystallinity, the first voltage is applied to the pair of conductive layers, the organic compound is heated, and the organic compound is phase-shifted from the first phase to the second phase. Data is recorded, and after heating the organic compound, the heating is stopped, the organic compound is cooled, and the data is erased by causing a phase transition from the second phase to the first phase. Is a storage device.

Another embodiment of the present invention includes a memory cell array in which memory cells are arranged in a matrix, a writing circuit, and an erasing circuit. The memory cell includes a transistor and a memory element. The memory element is a pair of conductive elements. The organic compound sandwiched between the pair of conductive layers, the organic compound has liquid crystallinity, the first voltage is applied to the pair of conductive layers to heat the organic compound, and the organic compound is Data is recorded by phase transition from the first phase to the second phase, the organic compound is heated, then the heating is stopped, the organic compound is cooled, and the second phase is changed to the first phase. The storage device is characterized in that data is erased by causing phase transition to.

  The first phase is a crystal phase, and the second phase is a smectic phase. The first phase is a crystal phase, and the second phase is an isotropic phase. The first phase is a smectic phase, and the second phase is an isotropic phase.

  One embodiment of the present invention is the above memory element, a conductive layer functioning as an antenna, a first transistor connected to the first conductive layer or the second conductive layer of the memory element, and a conductive layer functioning as an antenna. And a second transistor connected to the semiconductor device.

The organic compound of the memory element is formed of an organic semiconductor that exhibits liquid crystallinity when heated. Typical examples of the organic semiconductor exhibiting liquid crystallinity include the following general formulas (1) to (13).

一般式（１）〜（１３）の式中のｍ及びｎはそれぞれ０〜５までの整数を表す。また、Ｒ_１又はＲ_２は、直鎖状又は分岐状のアルキル基、アルコキシ基、フェニル基、シクロヘキシル基、シアノ基、フルオロ基、又は下記の一般式（１４）（式中、Ｒ_３は水素原子又はメチル基、Ｂは−（ＣＨ_２）_ｌ−、−（ＣＨ_２）_ｌ−Ｏ−、−ＣＯ−Ｏ−（ＣＨ_２）_ｌ−、−ＣＯ−Ｏ−（ＣＨ_２）_ｌ−Ｏ−、Ｃ_６Ｈ_１４−ＣＨ_２−Ｏ−、−ＣＯ−、）を表す。

M and n in the formulas (1) to (13) each represent an integer of 0 to 5. R ₁ or R ₂ is a linear or branched alkyl group, alkoxy group, phenyl group, cyclohexyl group, cyano group, fluoro group, or the following general formula (14) (wherein R ₃ is hydrogen An atom or a methyl group, B represents — (CH ₂ ) ₁ —, — (CH ₂ ) ₁ —O—, —CO—O— (CH ₂ ) ₁ —, —CO—O— (CH ₂ ) ₁ —O—; _{, C 6 H 14 -CH 2 -O} -, - CO-,) represents a.

なお、Ｒ_１及びＲ_２は同一の基であっても良く、異なる基であっても良い。また、Ｂ中のｌは０〜５までの整数を表す。また、Ａ_１乃至Ａ_３は、下記一般式（１５）〜（２４）、のいずれか一つ又は複数を示す。なお、Ａ_１乃至Ａ_３は同一の基であっても良く、異なる基であっても良い。

R ₁ and R ₂ may be the same group or different groups. In addition, l in B represents an integer of 0 to 5. A _{1 to} A ₃ represent any one or more of the following general formulas (15) to (24). A _{1 to} A ₃ may be the same group or different groups.

  The memory device of the present invention can selectively record and erase data by applying a voltage to a pair of conductive layers. For this reason, it is possible to selectively heat an arbitrary storage element other than at the time of manufacture, and to write and erase data. In addition, since it is not necessary to provide a separate device for writing and erasing data, the storage device can be reduced in size and simplified. Further, by using the present invention, a semiconductor device can be manufactured in a small size and at low cost.

Embodiments of the present invention will be described below with reference to the drawings.
However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in all the drawings for describing the embodiments, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

(Embodiment 1)
In this embodiment, an example of a structure of a memory element included in the memory device of the present invention will be described with reference to drawings.

FIG. 1 shows an operation method of reading, writing, and erasing data of a memory element included in the memory device of the present invention, and FIGS. 2 to 4 show cross-sectional structures of the memory element included in the memory device of the present invention. .

As shown in FIG. 2A, the memory element 30 includes a first conductive layer 32 formed over a first substrate 31 and a second conductive layer 34 formed over a second substrate 33. And the first substrate 31 and the first conductive layer 32, and the organic compound layer 35 sandwiched between the second substrate 33 and the second conductive layer 34. Further, as shown in FIG. 2B, an alignment film that orients the organic compound layer on the surfaces of the first substrate 31 and the first conductive layer 32, and on the surfaces of the second substrate 33 and the second conductive layer 34, respectively. 36 and 37 may be provided. By providing the alignment films 36 and 37, the phase change of the organic compound layer can be easily performed.

The memory element of the present invention records, reads, and erases data by changing the mobility of the organic compound layer due to the phase transition of the organic compound layer. The organic compound layer 35 uses a liquid crystalline organic semiconductor that undergoes phase transition depending on temperature. In particular, an organic semiconductor that is a smectic liquid crystal having a smectic phase is preferable. For this reason, as shown in FIG. 1B, in the case of T1> T2> T3> T0, the organic compound layer 35 is isotropic phase (hereinafter referred to as Iso phase) at T1 or more, and at T2 or more and less than T1. When the smectic phase (hereinafter referred to as Sm phase), T3 or more and less than T2, a phase transition occurs depending on the temperature as in the crystal phase, and a different phase is exhibited. In addition, the Sm phase may have a plurality of Sm phases such as an SmA phase, an SmB phase, an SmC phase, an SmD phase, an SmE phase, an SmF phase, an SmG phase, and an SmH phase.

In addition, since the organic compound layer of the memory element of the present invention is formed of an organic semiconductor, the Iso phase has μ1 mobility, the Sm phase has μ2 mobility, and the crystal phase has μ3 mobility. Have Since the crystal phase has high crystallinity, the mobility is high, and in the Iso phase, the molecule is isotropic, so the mobility is low. Therefore, μ1 <μ2 <μ3.

Further, when the Sm phase has a plurality of phases of SmA phase to SmH phase, each has different mobility.

Next, an operation for writing data will be described with reference to FIGS. Note that the writing operation in FIGS. 1C to 1E shows a case where data is written by causing a phase transition of an organic compound layer having low mobility to an organic compound layer having high mobility. Hereinafter, such a write operation is referred to as a first write operation. The right arrow indicates writing, and the left arrow indicates erasing. 3 shows the memory element 30 formed of the first conductive layer 32, the organic compound layer 35, and the second conductive layer. In addition, a memory element 30b formed of the first conductive layer 32b, the organic compound layer 35, and the second conductive layer 34 is shown. In addition, a memory element 30c formed of the first conductive layer 32c, the organic compound layer 35, and the second conductive layer 34 is shown.

As shown in FIG. 1C, the case where the first writing operation is performed using the phase transition from the Iso phase (mobility μ1) to the crystal phase (mobility μ3) will be described. After applying a voltage of V2 or higher to the first conductive layer 32 and the second conductive layer 34 of the memory element to be written to generate Joule heat, the organic compound layer 35 is heated to T1 or higher to make the Iso phase, The organic compound layer 35 is rapidly cooled to T0. The organic compound layer at this time is an Iso phase and has a mobility of μ1. V2 is an erase voltage (see FIG. 3A).

  Here, after the organic compound layer 35 is heated to T1 or more to make the Iso phase, the organic compound layer 35 can be kept (fixed) in the Iso phase by rapidly cooling the organic compound layer 35 to T0. . As a cooling means for rapidly cooling the memory element, a cooling liquid or a cooling gas may be used. Examples of the cooling liquid include liquid nitrogen, and examples of the cooling gas include rare gases.

  Next, a voltage of V1 or more and less than V2 is applied to the first conductive layer 32 and the second conductive layer 34 to generate Joule heat, so that the organic compound layer 35a is T3 or more and less than T2. V1 is a write voltage. As a result, phase transition 1 occurs, the organic compound layer 35a becomes a crystalline phase, and the mobility of the organic compound layer 35a changes to μ3 (see FIGS. 1C and 3B). The memory element 30 in which the organic compound layer 35a has transitioned from the Iso phase to the crystal phase has a significantly smaller electrical resistance and a larger current value than the other memory elements 30b and 30c. In this manner, voltage is applied to the pair of conductive layers, and data is written using changes in electric resistance and current value of the memory element.

  Next, the first reading operation is described with reference to FIG. A voltage lower than V1 is applied to the first conductive layers 32, 32b, 32c and the second conductive layer 34, and a current is passed through the memory elements 30, 30b, 30c. Data is read based on the current value and electrical resistance of each memory element at this time. For example, the organic compound layers of the memory elements 30b and 30c that are not written are in the Iso phase. For this reason, the mobility of the organic compound layer 35 is low, the electric resistance of the memory elements 30b and 30c is high, and the current value is low. The storage elements 30b and 30c are set to “0” data. On the other hand, since the memory element 30 is written and the organic compound layer 35a is in a crystalline phase, the mobility of the organic compound layer 35a is high, the electric resistance of the memory element 30 is low, and the current value is high. Such a storage element 30 can be set to “1” data. In this manner, data is read by electrically reading the difference in electric resistance and current value of the memory element.

Next, an operation for performing first erasing will be described with reference to FIG. A voltage of V2 or higher is applied to the first conductive layer 32 and the second conductive layer 34 of the memory element 30 on which writing has been performed, and the organic compound layer 35a is heated to T1 or higher by Joule heat generated thereby. As a result, phase transition 2 occurs and the organic compound layer becomes the Iso phase. Next, the organic compound layer is rapidly cooled to T0 (see FIG. 3C). As a result, the mobility of the organic compound layer of the memory element 30 is μ1, and data can be erased.

  Note that, here, the organic compound layer 35a can be maintained (fixed) in the Iso phase by heating the organic compound layer 35a to T1 or more to obtain the Iso phase and then rapidly cooling it.

In addition, as shown in FIG. 1D, writing may be performed using a phase transition from the Iso phase (mobility μ1) to the Sm phase (mobility μ2). Similar to the first write operation, the organic compound layer 35 is in the Iso phase. Next, a voltage lower than the write voltage V1 and lower than the erase voltage V2 is applied to the first conductive layer 32 and the second conductive layer 34 of the selected memory element to generate Joule heat, so that the organic compound layer 35a is changed from T2 to T1. Less than. As a result, phase transition 3 occurs, the organic compound layer 35a becomes the Sm phase, and the mobility of the organic compound layer 35a changes to μ2. The memory element in which the organic compound layer 35a has transitioned from the Iso phase to the Sm phase has a significantly reduced electric resistance and an increased current value. In this manner, voltage is applied to the pair of conductive layers, and data is written using changes in electric resistance and current value of the memory element.

Next, an operation of performing reading is described with reference to FIG. A voltage lower than the write voltage V <b> 1 is applied to the first conductive layer 32 and the second conductive layer 34 to cause a current to flow through the memory element 30. Data is read by electrically reading a difference in current value and electric resistance before and after flowing a current by applying a voltage to the memory element at this time.

Next, an operation for erasing will be described with reference to FIG. A voltage equal to or higher than the erasing voltage V2 is applied to the first conductive layer 32 and the second conductive layer 34 on which writing has been performed, and the organic compound layer 35a is heated to T1 or higher by Joule heat generated thereby. As a result, phase transition 4 occurs, and the organic compound layer 35a becomes an Iso phase. Next, the organic compound layer 35a is rapidly cooled to T0 and fixed to the Iso phase. As a result, the mobility of the organic compound layer is μ1, and data can be erased.

Further, as shown in FIG. 1E, writing may be performed using a phase transition from the Sm phase (mobility μ2) to the crystal phase (mobility μ3). Similar to the first write operation, a voltage is applied to the first conductive layer 32 and the second conductive layer 34 of all the memory elements to generate Joule heat, and the organic compound layer 35 is heated to T2 or more and less than T1. After making the Sm phase, it is rapidly cooled to T0 and fixed to the Sm phase. At this time, the organic compound layer 35 is in the Sm phase and the mobility is μ2. Next, a voltage is applied to the first conductive layer 32 and the second conductive layer 34 of the selected memory element to generate Joule heat, so that the organic compound layer 35a is T3 or more and less than T2. As a result, phase transition 5 occurs, the organic compound layer 35a becomes a crystalline phase, and the mobility changes to μ3. The memory element in which the organic compound layer 35a has transitioned from the Sm phase to the crystal phase has a significantly reduced electric resistance and a large current value. In this manner, voltage is applied to the pair of conductive layers, and data is written using changes in electric resistance and current value of the memory element.

Next, an operation of performing reading will be described with reference to FIG. A voltage lower than the write voltage V <b> 1 is applied to the first conductive layer 32 and the second conductive layer 34 to cause a current to flow through the memory element 30. Data is read based on the current value and resistance value at this time.

Next, an operation for erasing will be described with reference to FIG. A voltage equal to or higher than the erasing voltage V2 is applied to the first conductive layer 32 and the second conductive layer 34 of the memory element to which writing has been performed, and the organic compound layer 35a is heated to T2 or higher and lower than T1 by Joule heat generated thereby. . As a result, phase transition 6 occurs and the organic compound layer becomes the Sm phase (see FIG. 1E). Next, the organic compound layer is quenched to T0 to fix the Sm phase. As a result, the mobility of the storage element 30 is μ2, and data can be erased.

Next, a second write operation different from the first write operation will be described with reference to FIGS. 1B and 1F. Note that FIGS. 1F to 1H illustrate the case where data is written by causing a phase transition of an organic compound layer having high mobility to an organic compound layer having low mobility. The right arrow indicates writing, and the left arrow indicates erasing.

As shown in FIG. 1F, a case where writing is performed using a phase transition from a crystal phase (mobility μ3) to an Sm phase (mobility μ2) will be described. A voltage is applied to the first conductive layer 32 and the second conductive layer 34 of the selected memory element to pass a current, the crystalline organic compound layer 35 is heated to T2 or more and less than T1, and then rapidly cooled to change the Sm phase. Fix it. As a result, phase transition 7 occurs, the organic compound layer 35a becomes the Sm phase, and the mobility changes to μ2. That is, the electrical resistance of the memory element to which writing has been performed increases and the current value decreases as compared with the memory element to which writing has not been performed. In this manner, voltage is applied to the pair of conductive layers, and data is written using changes in electric resistance and current value of the memory element.

In addition, an operation of reading data is described with reference to FIG. A voltage lower than the write voltage V <b> 1 is applied to the first conductive layer 32 and the second conductive layer 34 to cause a current to flow through the memory element 30. Data is read by electrically reading the difference in current value and electrical resistance of the memory element at this time.

In addition, in FIG. 1F, an operation for performing a second erase different from the first erase operation is described. The second erasing operation is performed by heating the organic compound layer 35a which is the Sm phase of the memory element to which writing has been performed to T2 or more and less than T1 to improve the fluidity of the organic compound layer 35a, and thereafter from T3 to less than T2. Slowly cool to fix the crystal phase. Specifically, the heating of the memory element is stopped, the organic compound layer 35a is cooled, and the organic compound layer 35a is changed from the Sm phase to the crystal phase. As a result, phase transition 8 occurs, the organic compound layer 35 becomes a crystalline phase, and the mobility of the memory element 30 becomes μ3. That is, the organic compound layer 35a has the same phase as the organic compound layer of the memory element that is not written, and data can be erased.

In addition, as shown in FIG. 1G, writing may be performed using a phase transition from a crystal phase (mobility μ3) to an Iso phase (mobility μ1). A voltage is applied to the first conductive layer 32 and the second conductive layer 34 of the selected memory element to pass a current, the organic compound layer 35 in the crystalline phase is heated to T1 or higher, and then rapidly cooled to fix the Iso phase. . As a result, phase transition 9 occurs, the organic compound layer 35a becomes the Iso phase, and the mobility of the memory element 30 changes to μ1. That is, the electrical resistance of the memory element to which writing has been performed increases and the current value decreases as compared with the memory element to which writing has not been performed. In this manner, voltage is applied to the pair of conductive layers, and data is written using changes in electric resistance and current value of the memory element.

In addition, an operation of reading data is described with reference to FIG. A voltage lower than the write voltage V1 is applied to the first conductive layer 32 and the second conductive layer 34 to pass a current through the memory element. Data is read by electrically reading the difference in current value and electrical resistance of the memory element at this time.

In FIG. 1G, the erasing operation is performed by heating the organic compound layer 35a which is the Iso phase of the memory element to which writing has been performed at T1 or more to increase the fluidity of the organic compound layer 35a. The crystal phase is fixed by gradually cooling to less than T2. Specifically, the heating of the memory element is stopped, the organic compound layer 35a is cooled, and the organic compound layer 35a is changed from the Iso phase to the crystal phase. As a result, the phase transition 10 occurs, the organic compound layer 35 becomes a crystalline phase, and the mobility of the memory element 30 becomes μ3. That is, the organic compound layer 35a has the same phase as the organic compound layer of the memory element that is not written, and data can be erased.

In addition, as shown in FIG. 1H, writing may be performed using phase transition from the Sm phase (mobility μ2) to the Iso phase (mobility μ1). A voltage is applied to the first conductive layer 32 and the second conductive layer 34 of the selected memory element to pass a current, and the Sm-phase organic compound layer 35 is heated to T1 or more and then rapidly cooled to fix the Iso phase. . As a result, the phase transition 11 occurs, the organic compound layer 35a becomes the Iso phase, and the mobility of the memory element 30 changes to μ1. That is, the electrical resistance of the memory element to which writing has been performed increases and the current value decreases as compared with the memory element to which writing has not been performed. In this manner, voltage is applied to the pair of conductive layers, and data is written using changes in electric resistance and current value of the memory element.

In addition, an operation of reading data is described with reference to FIG. A voltage lower than the write voltage V1 is applied to the first conductive layer 32 and the second conductive layer 34 to pass a current through the memory element. Data is read by electrically reading the difference in current value and electrical resistance of the memory element at this time.

In FIG. 1H, the erasing operation is performed by heating the organic compound layer 35a which is the Iso phase of the memory element to which writing has been performed at T1 or higher to improve the fluidity of the organic compound layer, and then at least T2 or higher. Slowly cool to below T1 to fix the Sm phase. Specifically, the heating of the memory element is stopped, the organic compound layer 35a is cooled, and the organic compound layer 35a is changed from the Iso phase to the Sm phase. As a result, the phase transition 12 occurs, the organic compound layer 35 becomes the Sm phase, and the mobility of the memory element 30 becomes μ2, that is, the organic compound layer 35 has the same phase as the organic compound layer of the memory element that is not written. Thus, the data can be erased.

Further, writing and erasing of the memory element may be performed using a change in mobility caused by phase transition in different smectic phases of SmA to SmH.

With the above structure, data can be written and erased by applying a voltage to the pair of conductive layers of the selected memory element to cause phase transition of the organic compound layer. For this reason, it is not necessary to have a separate writing and erasing device, so that the storage device can be reduced in size and simplified.

Next, the structure of the memory element will be described with reference to FIGS. As the first substrate 31 and the second substrate 33, a glass substrate, a flexible substrate, a quartz substrate, a silicon substrate, a metal substrate, a stainless steel substrate, or the like can be used. The flexible substrate is a substrate that can be bent (flexible), and examples thereof include a plastic substrate made of polycarbonate, polyarylate, polyethersulfone, or the like. A film having a thermoplastic resin layer (made of polypropylene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, or the like) can also be used. In addition to this, the memory element 30 may be provided above a field effect transistor (FET) formed on a semiconductor substrate such as Si or above a thin film transistor (TFT) formed on a substrate such as glass. it can. Further, since the first substrate 31 and the second substrate 33 may be light-transmitting or light-blocking, the selection range of the substrates is widened.

  For the first conductive layer 32 and the second conductive layer 34, a single layer or a stacked structure made of a highly conductive metal, alloy, compound, or the like can be used. Typically, a light-transmitting oxide conductive film such as indium tin oxide (hereinafter referred to as ITO), indium tin oxide containing silicon, or indium oxide containing 2 to 20% zinc oxide (ZnO) is used. Can be mentioned. Also, titanium (Ti), gold (Au), platinum (Pt), nickel (Ni), tungsten (W), chromium (Cr), molybdenum (Mo), iron (Fe), cobalt (Co), copper (Cu ), Palladium (Pd), or a nitride of the metal material (eg, titanium nitride (TiN), tungsten nitride (WN), molybdenum nitride (MoN)), or the like. In addition, alkali metals such as lithium (Li) and cesium (Cs), alkaline earth metals such as magnesium (Mg), calcium (Ca), and strontium (Sr), and alloys containing any of these (MgAg, AlLi ), Rare earth metals such as europium (Er) and ytterbium (Yb), and alloys containing these.

The organic compound layer 35 is an organic compound (organic semiconductor) that exhibits semiconductor behavior, and uses a compound that exhibits liquid crystallinity. Typically, it is a compound represented by the general formulas (1) to (13). In any case, m and n are integers from 1 to 5. R ₁ or R ₂ represents a linear or branched alkyl group, an alkoxy group, or a group having an unsaturated bond represented by the general formula (14). The alkyl group has 1 to 18 carbon atoms, and specifically includes a methyl group, an ethyl group, a butyl group, a pentyl group, a hexyl group, an octyl group, a dodecyl group, a pentadecyl group, an octadecyl group, and the like.

R ₁ and R ₂ may be the same group or different groups.

In the formulas of the compounds represented by the general formulas (1) to (13), A _{1 to} A ₃ represent one or more of the general formulas (15) to (24). A _{1 to} A ₃ may be the same group or different groups.

Further, typical representative examples of compounds that can be used for the organic compound layer 35 include the following general formulas (25) to (29).

The organic compound layer 35 can be formed by a known liquid crystal injection method, liquid crystal dropping method, or the like. At this time, the thickness of the organic compound layer, that is, the distance between the first conductive layer and the second conductive layer is 0.5 to 6 μm, preferably 1 to 2 μm.

Further, as shown in FIG. 4A, the memory element 30 does not have the second conductive layer formed over the second substrate as compared with FIG. You may have the 1st conductive layer 32, the organic compound layer 35 which covers the 1st conductive layer 32, and the 2nd conductive layer 34 which covers the organic compound layer 35. Here, an insulating layer 38 functioning as a protective film is provided so as to cover the second conductive layer 34. A memory element having such a structure does not require a plurality of substrates and can reduce costs. In addition, since the memory element can be formed without bonding the first substrate and the second substrate, the manufacturing process can be simplified.

In the memory element having such a structure, the organic compound layer 35 and the second conductive layer 34 can be formed by an evaporation method, an electron beam evaporation method, or the like. For this reason, it is preferable that the thickness of the organic compound layer is 10 to 300 nm, desirably 50 to 200 nm. When the thickness of the organic compound layer is thinner than the above range, the uniformity of the organic compound layer is lowered, and the writing / erasing characteristics of the memory element are likely to vary.

The organic compound layer 35 formed by a vapor deposition method, an electron beam vapor deposition method, or the like is an organic semiconductor having liquid crystallinity as described above, and in the compound exhibiting liquid crystallinity, an organic compound having a molecular weight of 2000 or less, preferably a molecular weight of 1000 or less is used. be able to.

  The insulating layer 38 functioning as a protective film is preferably formed of silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, DLC (diamond-like carbon), or the like.

  In the memory element 30 illustrated in FIG. 4A, a rectifying element may be provided on the side opposite to the organic compound layer 35 with the first conductive layer 32 interposed therebetween (FIG. 4B). The element having a rectifying property is a transistor or a diode in which a gate electrode and a drain electrode are connected. Here, a diode 44 including the third conductive layer 41 and the semiconductor layer 42 is provided in contact with the first conductive layer 32. Note that a rectifying element may be provided on the side opposite to the organic compound layer 35 with the second conductive layer 34 interposed therebetween. Further, the rectifying element may be provided between the organic compound layer 35 and the first conductive layer 32. Further, a rectifying element may be provided between the organic compound layer 35 and the second conductive layer 34. Typical examples of the diode include a PN junction diode, a diode having a PIN junction, an avalanche diode, and the like. Moreover, you may use the diode of another structure. Thus, by providing a rectifying element, current flows only in one direction, so that a read error is reduced and a read margin is improved.

  In addition, when there is a concern about the influence of a horizontal electric field between adjacent memory elements, each organic compound provided in each memory element is separated in order to separate each organic compound layer provided in each memory element. A partition wall (insulating layer) may be provided between the layers. In other words, an organic compound layer may be selectively provided for each memory element.

  In addition, as shown in FIG. 4C, when the organic compound layer 35 covering the first conductive layer 32 is provided, the organic compound layer 35 is disconnected due to the step of the first conductive layer 32 or each memory cell. A partition wall (insulating layer) 39 may be provided between the first conductive layers 32 of each memory element in order to prevent the influence of the electric field in the lateral direction between them. Note that in the cross section of the partition wall (insulating layer) 39, the side surface of the partition wall (insulating layer) 39 is 10 to 60 degrees, more preferably 25 to 45 degrees with respect to the surface of the first conductive layer 32. It is preferable to have an inclination angle. Furthermore, the surface of the partition wall (insulating layer) 39 is preferably curved. Thereafter, an organic compound layer 35 and a second conductive layer 34 are formed so as to cover the first conductive layer 32 and the partition wall (insulating layer) 39.

Further, as shown in FIG. 4D, an interlayer covering a part of the first conductive layer 32 is formed on the first conductive layer 32 on the first substrate 31 instead of the partition wall (insulating layer) 39. You may provide the insulating layer 40a and the partition (insulating layer) 40b provided on the interlayer insulating layer. In the memory element having such an interlayer insulating layer 40a and the partition (insulating layer) 40b, the first conductive layer 32 extends in the first direction, and the second conductive layer 34 is the second perpendicular to the first direction. The structure extending in the direction of is particularly preferable.

The interlayer insulating layer 40 a covering a part of the first conductive layer 32 has an opening for each memory element 30. The partition (insulating layer) 40b is provided in a region where no opening is formed on the interlayer insulating layer. Further, the partition wall (insulating layer) 40 b extends in the second direction in the same manner as the second conductive layer 34. In addition, the partition wall (insulating layer) 40b has an inclination angle of 95 degrees or more and 135 degrees or less with respect to the interlayer insulating layer surface.

The partition wall (insulating layer) 40b is formed by using a positive photosensitive resin in which an unexposed portion remains, and adjusting the exposure amount or the development time so that the lower part of the pattern is etched more in accordance with a photolithography method. The height of the partition wall (insulating layer) 40 b is set to be larger than the thickness of the organic compound layer 35 and the second conductive layer 34. As a result, the organic compound layer 35 and the second conductive layer 34 are electrically connected to each other only by depositing the organic compound layer 35 and the second conductive layer 34 on the entire surface of the first substrate 31. The stripe-shaped organic compound layer 35 and the second conductive layer 34 which are separated into a plurality of independent regions and extend in a direction crossing the first direction can be formed. For this reason, the number of processes can be reduced. The organic compound layer 35a and the conductive layer 34a are also formed on the partition wall (insulating layer) 40b, but are separated from the organic compound layer 35 and the second conductive layer 34.

The memory device of this embodiment can record and erase data by applying a voltage to a selected pair of conductive layers. Therefore, it is possible to write and erase data by selectively heating an arbitrary storage element other than during manufacturing. In addition, since it is not necessary to provide a separate device for writing and erasing data, the storage device can be reduced in size and simplified. Further, by forming a memory element using a flexible substrate, a flexible memory device can be manufactured.

(Embodiment 2)
In this embodiment, structural examples of memory elements included in the memory device of the present invention will be described with reference to drawings. More specifically, the case of a passive matrix memory device will be described.

  FIG. 5A shows an example of the structure of the memory device 16 of this embodiment. A memory cell array 22 in which memory cells 21 are provided in a matrix, a column decoder 26a, a read circuit 26b, and a selector 26c are provided. It has a bit line driving circuit 26 having a word line driving circuit 24 having a row decoder 24a and a level shifter 24b, a writing circuit 25, an erasing circuit 27, etc., and an interface 23 for exchanging with the outside. The write circuit 25 and the erase circuit 27 are each composed of a booster circuit, a control circuit, and the like. Note that the structure of the memory device 16 shown here is just an example, and other circuits such as a sense amplifier, an output circuit, and a buffer may be included, and a write circuit may be provided in the bit line driver circuit.

  The memory cell 21 includes a first conductive layer connected to the bit line Bx (1 ≦ x ≦ m), a second conductive layer connected to the word line Wy (1 ≦ y ≦ n), and an organic compound layer. Have. The organic compound layer is provided between the first conductive layer and the second conductive layer.

  An example of a top surface structure and a cross-sectional structure of the memory cell array 22 is shown in FIG. Note that FIG. 6A illustrates a top structure of the memory cell array 22, and a cross-sectional structure between A and B in FIG. 6A corresponds to FIG. In FIG. 6A, the organic compound layer 35 and the second substrate 33 are omitted.

Memory cells 21 are provided in a matrix in the memory cell array 22 (see FIG. 6A). The memory cell 21 includes a memory element 30 (see FIG. 6B). The memory element 30 includes a first conductive layer 32 extending in the first direction on the first substrate 31, and a second direction extending in the second direction perpendicular to the first direction on the second substrate. The conductive layer 34 includes an organic compound layer 35 sandwiched between the first conductive layer 32 and the second conductive layer 34.

As the memory element 30, the memory element 30 described in Embodiment 1 can be used as appropriate.

  Next, an operation when data is written to the organic memory will be described (see FIGS. 5 and 6). Writing is performed by changing the electrical characteristics of the memory cell. The initial state of the memory cell (the state where no electrical action is applied) is data “0”, and the state where the electrical characteristic is changed is “1”. To do.

  When writing data, when writing data “1” in the memory cell 21, the memory cell 21 is selected by the column decoder 26a, the selector 26c, the row decoder 24a, and the level shifter 24b. Specifically, a predetermined voltage V2 is applied to the word line W3 connected to the memory cell 21 by the row decoder 24a and the level shifter 24b. Further, the bit line B3 connected to the memory cell 21 is connected to the write circuit 25 by the column decoder 26a and the selector 26c. Then, the write voltage V1 is output from the write circuit 25 to the bit line B3. Thus, the voltage Vw = V1−V2 is applied between the first conductive layer and the second conductive layer constituting the memory cell 21. When a first voltage is applied between the first conductive layer 32 and the second conductive layer 34 of the memory cell, the organic compound layer between the first conductive layer 32 and the second conductive layer 34 has Joule heat. Is heated. As a result, the organic compound layer undergoes a phase transition from the first phase to the second phase, and the mobility of the organic compound layer changes. As a result, the memory element is electrically changed, and data “1” is written. (See FIG. 5A).

  In the case where the first writing operation method of Embodiment 1 is used, a memory element in which the organic compound layer undergoes a phase transition from the first phase having low mobility to the second phase having high mobility is compared with other memory elements. The electrical resistance is significantly reduced and the current value is increased. In this manner, data is written by utilizing a change in electric resistance of the memory element by applying a voltage. For example, in the case where an organic compound layer to which no first voltage is applied is “0” data, when writing “1” data, a voltage is applied to a pair of conductive layers of a desired storage element, The phase transition of the compound layer is caused to reduce the electrical resistance of the memory element and increase the current value.

Note that in the case where the second writing operation of Embodiment 1 is used, a memory element in which the organic compound layer is phase-shifted from the first phase with high mobility to the second phase with low mobility is different from other memory elements. In comparison, the electrical resistance increases and the current value decreases. Data may be written by applying this.

Note that data “1” is controlled not to be written in the memory cell connected to the non-selected word line and the non-selected bit line. For example, unselected word lines and unselected bit lines may be set in a floating state. The first conductive layer and the second conductive layer constituting the memory cell must have characteristics such as diode characteristics that can ensure selectivity.

On the other hand, when data “0” is written in the memory cell 21, it is not necessary to apply an electrical action to the memory cell 21. In terms of circuit operation, for example, as in the case of writing “1”, the memory cell 21 is selected by the column decoder 26a, selector 26c, row decoder 24a, and level shifter 24b, but the output potential from the write circuit 26b to the bit line B3. Is approximately equal to the potential of the selected word line W3 or the potential of the non-selected word line, and the electrical characteristics of the memory cell 21 are changed between the first conductive layer and the second conductive layer constituting the memory cell 21. What is necessary is just to apply the voltage of the grade which is not changed.

  Next, an operation when erasing data in the organic memory will be described. When data is erased using the first erase operation method of the first embodiment, one memory element 30 is selected by the row decoder 24a, the column decoder 26a, and the selector 26c, and then an erase circuit is used. Data in the memory cell 21 is erased. When a second voltage is applied between the first conductive layer 32 and the second conductive layer 34 of the memory cell, the organic compound layer between the first conductive layer 32 and the second conductive layer 34 has Joule heat. Is heated. As a result, the organic compound layer undergoes a phase transition from the second phase with high mobility to the first phase with low mobility, and the mobility of the organic compound layer changes. As a result, the electrical resistance of the memory element changes.

Note that in the case where data is erased using the first erase operation method of Embodiment 1, the organic compound layer undergoes phase transition from the first phase having low mobility to the second phase having high mobility by writing. In the memory element, when the organic compound layer is gradually cooled after being heated once, the organic compound layer undergoes a phase transition from the second phase having low mobility to the first phase having high mobility, and the mobility of the organic compound layer changes. . Data may be erased by applying this.

  The memory element in which the organic compound layer has phase-shifted from the second phase to the first phase has the same electrical resistance as the memory element before writing. In this manner, data is erased by applying a voltage and utilizing a change in electrical resistance of the memory element.

  Next, an operation when reading data from the organic memory will be described. Here, the read circuit 26 b includes a resistance element 46 and a sense amplifier 47. However, the configuration of the readout circuit 26b is not limited to the above configuration, and may have any configuration.

  Data is read by applying a voltage between the first conductive layer 32 and the second conductive layer 34 and reading the electrical resistance of the organic compound layer 35. For example, as described above, when data is written by applying a voltage, the resistance value Ra1 when no voltage is applied and the resistance value Rb1 when the organic compound undergoes phase transition by applying a voltage are Ra1> Rb1. Meet. Data is read by electrically reading such a difference in resistance value.

  For example, when reading data from the memory cell 21 arranged in the xth column and the yth row from the plurality of memory cells 21 included in the memory cell array 22, first, the row decoder 24a, the column decoder 26a, and the selector 26c The bit line Bx in the column and the word line Wy in the y row are selected. Then, the organic compound layer included in the memory cell 21 and the resistance element 46 are connected in series. In this way, when a voltage is applied across the two resistance elements connected in series, the potential of the node P becomes a resistance-divided potential according to the resistance value Ra or Rb of the organic compound layer 35. Then, the potential of the node P is supplied to the sense amplifier 47, and it is determined whether the sense amplifier 47 has “0” or “1” data. Thereafter, a signal including data “0” and “1” determined by the sense amplifier 47 is supplied to the outside, and the data can be read.

  According to the above method, the state of the electrical resistance of the organic compound layer 35 is read as a voltage value using the difference in resistance value and resistance division. However, a method of comparing current values may be used. For example, the current value Ia1 when no voltage is applied to the organic compound layer and the current value Ib1 when the organic compound layer is phase-shifted by applying a voltage satisfy that Ia1 <Ib1. It is.

In the memory device of this embodiment, data can be recorded and erased by applying a voltage to a pair of conductive layers. Therefore, it is possible to write and erase data by selectively heating an arbitrary storage element other than during manufacturing. In addition, since it is not necessary to provide a separate device for writing and erasing data, the storage device can be reduced in size and simplified. Further, by forming a memory element using a flexible substrate, a flexible memory device can be manufactured.

(Embodiment 3)
In this embodiment, a memory device having a structure different from that in Embodiment 2 is described. Specifically, the case of an active matrix memory device is described.

  FIG. 7A illustrates an example of a structure of the memory device described in this embodiment. A memory cell array 222 in which memory cells 221 are provided in a matrix, a column decoder 226a, a reading circuit 226b, and a selector 226c are included. A bit line driving circuit 226 having a row decoder 224a, a word line driving circuit 224 having a row decoder 224a and a level shifter 224b, a writing circuit 227, an erasing circuit 228, and the like, and an interface 223 for exchanging with the outside. The writing circuit 227 and the erasing circuit 228 are each composed of a booster circuit, a control circuit, and the like. Note that the structure of the memory device 216 shown here is merely an example, and other circuits such as a sense amplifier, an output circuit, and a buffer may be included, and a writing circuit may be provided in the bit line driver circuit.

  The memory cell 221 includes a first wiring connected to the bit line Bx (1 ≦ x ≦ m), a second wiring connected to the word line Wy (1 ≦ y ≦ n), a transistor 240, and a memory element 241. And have. The memory element 241 has a structure in which an organic compound layer is sandwiched between a pair of conductive layers.

  Next, an example of a top view and a cross-sectional view of the memory cell array 222 having the above structure is described with reference to FIGS. Note that FIG. 8A illustrates an example of a top view of the memory cell array 222, and FIG. 8B illustrates a cross-sectional view taken along a line AB in FIG. 8A. In FIG. 8A, the second substrate and the second conductive layer formed thereon are omitted. Further, part of the first conductive layer connected to the source wiring or the drain wiring of the transistor 240 is omitted.

  In the memory cell array 222, a plurality of memory cells 221 are provided in a matrix. The memory cell 221 includes a transistor 240 functioning as a switching element over the first substrate 230 and a memory element 241 connected to the transistor 240. The memory element 241 is formed over the insulating layer 249 that covers the transistor 240 and is connected to a source wiring or a drain wiring of the transistor 240 and a second conductive layer 243 formed over the second substrate 242. The conductive layer 245 and the organic compound layer 244 sandwiched between the first conductive layer 243 and the second conductive layer 245 are formed. Further, in order to make the distance (cell gap) between the first substrate 230 over which the transistor and the first conductive layer are formed and the second substrate 242 constant, the insulating layer 249 and the second conductive layer 245 A spacer 250 may be provided therebetween. Note that here, the insulating layer 105, the transistor 240, the insulating layer 249 that covers the transistor 240, and the first conductive layer 243 are referred to as an element formation layer 253 (see FIGS. 8A and 8B).

For the first conductive layer 243 and the second conductive layer 245, the materials and formation methods of the first conductive layer 32 and the second conductive layer 34 described in Embodiment 1 can be used as appropriate. A thin film transistor is used as the transistor 240.

One mode of a thin film transistor that can be used for the transistor 240 is described with reference to FIGS. FIG. 15A illustrates an example in which a top-gate thin film transistor is applied. An insulating layer 105 is provided over the first substrate 230, and a thin film transistor is provided over the insulating layer 105. In the thin film transistor, a semiconductor layer 1302 and an insulating layer 1303 which can function as a gate insulating layer are provided over the insulating layer 105. Over the insulating layer 1303, a gate electrode 1304 is formed corresponding to the semiconductor layer 1302, and an insulating layer 1305 functioning as a protective layer and an insulating layer 248 functioning as an interlayer insulating layer are provided thereover. In addition, source wirings or drain wirings 1306 connected to the source region and the drain region of the semiconductor layer are formed. Further, an insulating layer functioning as a protective layer may be formed thereon.

  The semiconductor layer 1302 is a layer formed of a semiconductor having a crystal structure, and a non-single-crystal semiconductor or a single-crystal semiconductor can be used. In particular, an amorphous or microcrystalline semiconductor is crystallized by combining a crystalline semiconductor crystallized by laser light irradiation, a crystalline semiconductor crystallized by heat treatment, and heat treatment and laser light irradiation. It is preferable to apply a crystalline semiconductor. In the heat treatment, a crystallization method using a metal element such as nickel which has an action of promoting crystallization of a silicon semiconductor can be applied.

In the case of crystallization by irradiating with laser light, high repetition frequency with continuous wave laser light irradiation or repetition frequency of 10 MHz or more and pulse width of 1 nanosecond or less, preferably 1 to 100 picoseconds. By irradiating with ultrashort pulse light, crystallization can be performed while continuously moving the molten zone in which the crystalline semiconductor is melted in the irradiation direction of the laser light. By such a crystallization method, a crystalline semiconductor having a large particle diameter and a crystal grain boundary extending in one direction can be obtained. By adjusting the carrier drift direction to the direction in which the crystal grain boundary extends, the field-effect mobility in the transistor can be increased. For example, a mobility of 400 cm ² / V · sec or more can be realized.

When the crystallization process is performed using a crystallization process at a heat resistant temperature (about 600 ° C.) or lower of the glass substrate, a large-area glass substrate can be used. Therefore, a large amount of semiconductor devices can be manufactured per substrate, and the cost can be reduced.

Alternatively, the semiconductor layer 1302 may be formed by performing a crystallization step by heating at a temperature equal to or higher than the heat resistant temperature of the glass substrate. Typically, a quartz substrate is used as the insulating substrate, and the semiconductor layer 1302 is formed by heating an amorphous or microcrystalline semiconductor at 700 ° C. or higher. As a result, a semiconductor with high crystallinity can be formed. Therefore, a thin film transistor that has favorable characteristics such as response speed and mobility and can operate at high speed can be provided.

  The gate electrode 1304 can be formed using a metal or a polycrystalline semiconductor to which an impurity of one conductivity type is added. In the case of using a metal, tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), aluminum (Al), or the like can be used. Further, a metal nitride obtained by nitriding the above metal can be used. Or it is good also as a structure which laminated | stacked the 1st layer which consists of the said metal nitride, and the 2nd layer which consists of the said metal. In the case of a laminated structure, the end of the first layer may protrude outward from the end of the second layer. At this time, a barrier metal can be formed by using a metal nitride for the first layer. That is, the second layer metal can be prevented from diffusing into the insulating layer 1303 and the semiconductor layer 1302 below the insulating layer 1303.

Sidewalls (sidewall spacers) 1308 are formed on the side surfaces of the gate electrode 1304. Each sidewall can be formed by forming an insulating layer made of silicon oxide on a substrate by a CVD method, and anisotropically etching the insulating layer by a RIE (Reactive ion etching) method.

  Various structures such as a single drain structure, an LDD (lightly doped drain) structure, and a gate overlap drain structure can be applied to a transistor including the semiconductor layer 1302, the insulating layer 1303, the gate electrode 1304, and the like. Here, a thin film transistor having an LDD structure in which a low concentration impurity region 1310 is formed in a semiconductor layer where sidewalls overlap is shown. It is also possible to apply a single gate structure, equivalently a multi-gate structure in which transistors to which a gate voltage of the same potential is applied are connected in series, or a dual gate structure in which a semiconductor layer is sandwiched between gate electrodes. it can.

  The insulating layer 248 is formed using an inorganic insulating material such as silicon oxide or silicon oxynitride, or an organic insulating material such as an acrylic resin or a polyimide resin. In the case where the insulating layer is formed using a coating method such as spin coating or roll coater, the insulating layer can be formed of silicon oxide by heat treatment after coating an insulating film material dissolved in an organic solvent. For example, a film containing a siloxane bond can be formed by a coating method, and an insulating layer can be formed using silicon oxide by heat treatment at 200 to 400 degrees. By using an insulating layer formed by a coating method or an insulating layer flattened by reflow as the insulating layer 248, disconnection of wiring formed over the layer can be prevented. It can also be used effectively when forming multilayer wiring.

  A source wiring or a drain wiring 1306 formed over the insulating layer 248 can be provided so as to intersect with a wiring formed in the same layer as the gate electrode 1304 and forms a multilayer wiring structure. A multilayer wiring structure can be formed by stacking a plurality of insulating layers having the same function as the insulating layer 248 and forming wirings on the insulating layers. The source wiring or the drain wiring 1306 includes a low resistance material such as aluminum (Al), such as a laminated structure of titanium (Ti) and aluminum (Al), a laminated structure of molybdenum (Mo) and aluminum (Al), and titanium (Ti And a barrier metal using a refractory metal material such as molybdenum (Mo).

  FIG. 15B illustrates an example in which a bottom-gate thin film transistor is applied. The insulating layer 105 is formed over the first substrate 230, and a thin film transistor is provided thereover. The thin film transistor is provided with a gate electrode 1304, an insulating layer 1303 functioning as a gate insulating layer, a semiconductor layer 1302, a channel protective layer 1309, an insulating layer 1305 functioning as a protective layer, and an insulating layer 248 functioning as an interlayer insulating layer. . Further, an insulating layer functioning as a protective layer may be formed thereon. The source wiring or the drain wiring 1306 can be formed over the insulating layer 1305 or the insulating layer 248. Note that in the case of a bottom-gate thin film transistor, the insulating layer 105 is not necessarily formed.

In the case where the first substrate 230 is a flexible substrate, the heat resistant temperature of the substrate is lower than that of a non-flexible substrate such as a glass substrate. For this reason, the thin film transistor is preferably formed using an organic semiconductor.

Here, a structure of a thin film transistor using an organic semiconductor is described with reference to FIGS. FIG. 15C illustrates an example of applying a staggered organic semiconductor transistor. An organic semiconductor transistor is provided over a flexible substrate 1401. The organic semiconductor transistor includes a gate electrode 1402, an insulating layer 1403 functioning as a gate insulating film, a semiconductor layer 1404 overlapping with the insulating layer functioning as the gate electrode and the gate insulating film, and a source wiring or a drain wiring 1306 connected to the semiconductor layer 1404. Is formed. Note that the semiconductor layer is partly sandwiched between the insulating layer 1403 functioning as a gate insulating film and the source and drain wirings 1306.

The gate electrode 1402 can be formed using a material and a method similar to those of the gate electrode 1304. Alternatively, the gate electrode 1402 can be formed by drying and baking using a droplet discharge method. Alternatively, the gate electrode 1402 can be formed by printing a paste containing fine particles over a flexible substrate by a printing method, followed by drying and baking. As typical examples of the fine particles, fine particles mainly containing any of gold, copper, an alloy of gold and silver, an alloy of gold and copper, an alloy of silver and copper, and an alloy of gold, silver, and copper may be used. Further, fine particles mainly containing a conductive oxide such as indium tin oxide (ITO) may be used.

The insulating layer 1403 functioning as a gate insulating film can be formed using a material and a method similar to those of the insulating layer 1303. However, when an insulating layer is formed by heat treatment after applying an insulating film material dissolved in an organic solvent, the heat treatment temperature is lower than the heat resistance temperature of the flexible substrate.

Examples of the material of the semiconductor layer 1404 of the organic semiconductor transistor include polycyclic aromatic compounds, conjugated double bond compounds, phthalocyanines, and charge transfer complexes. For example, anthracene, tetracene, pentacene, 6T (hexathiophene), TCNQ (tetracyanoquinodimethane), PTCDA (perylene carboxylic acid anhydride), NTCDA (naphthalene carboxylic acid anhydride) and the like can be used. Examples of the material for the semiconductor layer 1404 of the organic semiconductor transistor include π-conjugated polymers such as organic polymer compounds, carbon nanotubes, polyvinyl pyridine, and phthalocyanine metal complexes. In particular, polyacetylene, polyaniline, polypyrrole, polythienylene, polythiophene derivatives, poly (3-alkylthiophene), polyparaphenylene derivatives, or polyparaphenylene vinylene derivatives, which are π-conjugated polymers whose skeleton is composed of conjugated double bonds, are used. And preferred.

  As a method for forming the semiconductor layer of the organic semiconductor transistor, a method that can form a film having a uniform thickness on the substrate may be used. The thickness is 1 nm to 1000 nm, preferably 10 nm to 100 nm. As a specific method, an evaporation method, a coating method, a spin coating method, a bar coating method, a solution casting method, a dip method, a screen printing method, a roll coater method, or a droplet discharge method can be used.

FIG. 15D illustrates an example in which a coplanar organic semiconductor transistor is used. An organic semiconductor transistor is provided over a flexible substrate 1401. In the organic semiconductor transistor, a gate electrode 1402, an insulating layer 1403 functioning as a gate insulating film, a source wiring or drain wiring 1306, and a semiconductor layer 1404 overlapping with an insulating layer functioning as a gate electrode and a gate insulating layer are formed. Further, the source wiring or the drain wiring 1306 is partly sandwiched between an insulating layer functioning as a gate insulating layer and a semiconductor layer.

Further, the thin film transistor and the organic semiconductor transistor may be provided in any configuration as long as they can function as a switching element.

  Alternatively, the transistor 240 may be formed using a single crystal substrate or an SOI substrate, and a memory element may be provided thereover. The SOI substrate may be formed using a method called wafer bonding or a method called SIMOX in which an insulating layer is formed inside by implanting oxygen ions into the Si substrate. Since a transistor formed using such a single crystal semiconductor has favorable characteristics such as response speed and mobility, a transistor that can operate at high speed can be provided. In addition, since the transistor has less variation in characteristics, a semiconductor device that achieves high reliability can be provided.

  The insulating layer 249 is preferably formed by applying an insulating film material dissolved in an organic solvent using a coating method such as spin coating or a roll coater, and then performing a heat treatment. As a result, the flatness of the surface of the insulating layer 249 can be improved. In addition, the first conductive layer 243 can be freely provided regardless of the position of the source wiring or the drain wiring 1306 of the transistor. As a result, the memory element and the transistor can be more highly integrated.

  A material and a formation method of the first conductive layer 243 and the second conductive layer 245 can be similarly performed using any of the materials and the formation method described in Embodiment Mode 1.

  The organic compound layer 244 can be provided using a material and a formation method similar to those of the organic compound layer 35 described in Embodiment Mode 1.

  Further, a rectifying element may be provided between the first conductive layer 243 and the organic compound layer 244. The element having a rectifying property is a transistor or a diode in which a gate electrode and a drain electrode are connected. Note that the element having a rectifying property may be provided between the organic compound layer 244 and the second conductive layer 245.

As the spacer 250, a spherical or columnar spacer can be used as appropriate. Here, spherical spacers are dispersed, but a columnar spacer may be formed over the insulating layer 249 or the second conductive layer 245 using an organic resin or the like.

Further, instead of the memory element 241, the second conductive layer of the memory element as shown in FIG. 4 of Embodiment 1 is not formed over the second substrate, and an organic compound is formed over the first conductive layer. A memory element in which a layer and a second conductive layer are stacked can be used as appropriate.

In addition, a separation layer is provided over the first substrate 230, the element formation layer 253 is formed over the separation layer, the element formation layer 253 is separated from the separation layer, and the adhesive layer 462 is interposed over the third substrate 461. Alternatively, the element formation layer 253 may be attached (see FIG. 10). Note that as a peeling method, (1) a metal oxide layer is provided as a peeling layer between the first substrate having high heat resistance and the element formation layer 253, and the metal oxide layer is weakened by crystallization. (2) An amorphous silicon film containing hydrogen is provided as a separation layer between the first substrate having high heat resistance and the element formation layer 253, and amorphous silicon is irradiated by laser light irradiation. The element formation layer 253 is formed by releasing hydrogen gas from the film to peel off the substrate having high heat resistance, or by providing an amorphous silicon film on the peeling layer and removing the amorphous silicon film by etching. (3) Mechanically removing the first substrate with high heat resistance on which the element formation layer 253 is formed, or etching with a solution or a halogen fluoride gas such as NF ₃ , BrF ₃ , or ClF ₃ How to remove, (4) heat resistance High metal layer and metal oxide layer is provided as a first release layer between the substrate and the element formation layer 253, the metal oxide layer is weakened by crystallization, a part of the solution and NF 3 in the metal _layer, BrF _3. After removing by etching with a halogen fluoride gas such as ₃ or ClF ₃ , a method of physically peeling the weakened metal oxide layer may be used.

  Further, as the third substrate 461, the flexible substrate shown in the first substrate 31 shown in Embodiment Mode 1, a film having a thermoplastic resin layer, or the like can be used, so that the memory device can be downsized. It is possible to reduce the thickness and weight.

  Next, an operation when data is written to the storage device 216 will be described (see FIGS. 7 and 8).

  First, an operation when data is written by voltage application will be described. Here, a case where data is written to the memory cell 221 in the x-th column and the y-th row will be described. In this case, the row decoder 224a, the column decoder 226a, and the selector 226c select the bit line Bx in the xth column and the word line Wy in the yth row, and the transistor 240 included in the memory cell 221 in the xth column and the yth row Turns on. Subsequently, a predetermined voltage is applied to the bit line Bx in the x-th column by the writing circuit. The voltage applied to the bit line Bx in the x-th column is connected to the first conductive layer 243 of the selected memory element, and there is a potential difference between the first conductive layer 243 and the second conductive layer 245. Occurs. Then, the organic compound layer 244 is heated with Joule heat. As a result, phase transition of the organic compound layer occurs, and the mobility of the organic compound layer changes. As a result, the electrical resistance of the memory element changes.

  In the case where the first writing operation method of Embodiment 1 is used, a memory element in which the organic compound layer is phase-shifted from the first phase having low mobility to the second phase having high mobility is compared with other memory elements. As a result, the electrical resistance is significantly reduced and the current value is increased. In this manner, data is written by utilizing a change in electric resistance of the memory element by applying a voltage. For example, in the case where an organic compound layer to which no first voltage is applied is “0” data, when writing “1” data, a voltage is applied to a pair of conductive layers of a desired storage element, The phase transition of the compound layer is caused to reduce the electrical resistance of the memory element and increase the current value.

Note that in the case where the second writing operation of Embodiment 1 is used, the memory element in which the organic compound layer has undergone a phase transition from the first phase with high mobility to the second phase with low mobility is different from other memory elements. In comparison, the electrical resistance increases and the current value decreases. Data may be written by applying this.

Next, an operation when data is erased by applying a voltage will be described. When data is erased using the first erase operation method of Embodiment 1, the row decoder 224a, the column decoder 226a, and the selector 226c cause the bit line Bx in the xth column and the word line Wy in the yth row to be The selected transistor 240 included in the memory cell 221 in the xth column and the yth row is turned on. Subsequently, a predetermined voltage is applied to the bit line Bx in the x-th column by the erasing circuit. The voltage applied to the bit line Bx in the x-th column is connected to the first conductive layer 243 of the selected memory element, and there is a potential difference between the first conductive layer 243 and the second conductive layer 245. Occurs. Then, the organic compound layer 244 is heated with Joule heat. As a result, the organic compound layer undergoes a phase transition from the second phase with high mobility to the first phase with low mobility, and the mobility of the organic compound layer changes. As a result, the electrical resistance of the memory element changes.

Note that in the case where data is erased using the second erase operation method of Embodiment 1, the organic compound layer undergoes phase transition from the first phase having high mobility to the second phase having low mobility by writing. In the memory element, the organic compound layer undergoes phase cooling from the second phase having low mobility to the first phase having high mobility by slowly cooling after heating, and the mobility of the organic compound layer changes. Data may be erased by applying this.

  The memory element in which the organic compound layer has phase-shifted from the second phase to the first phase has the same electrical resistance as the memory element before writing. In this manner, data is erased by applying a voltage and utilizing a change in electrical resistance of the memory element.

  Next, an operation when data is read by applying a voltage will be described. Here, the reading circuit 226b includes a resistance element 246 and a sense amplifier 247. However, the structure of the reading circuit 226b is not limited to the above structure, and may have any structure.

  Data is read by applying a voltage between the first conductive layer 243 and the second conductive layer 245 to read the phase state of the organic compound layer 244. Specifically, data is read by electrically reading the resistance value of the organic compound layer 244. For example, when data is read from a plurality of memory cells 221 included in the memory cell array 222 to the memory cell 221 in the xth column and the yth row, first, the row decoder 224a, the column decoder 226a, and the selector 226c are used to read the data in the xth column. The bit line Bx and the y-th word line Wy are selected. Then, the transistor 240 included in the memory cell 221 arranged in the xth column and the yth row is turned on.

  After that, the memory element 241 included in the memory cell 221 and the resistance element 246 are connected in series. At this time, the memory element 241 can be regarded as one resistance element. Thus, when a voltage is applied to both ends of two resistance elements connected in series, the potential of the node P becomes equal to that of the memory element 241. The potential is divided by resistance according to the resistance value Ra or Rb. Then, the potential of the node P is supplied to the sense amplifier 247, and it is determined whether the sense amplifier 247 has data “0” or “1”. Thereafter, a signal including data of “0” and “1” determined by the sense amplifier 247 is supplied to the outside.

  Next, in the case where a transistor is used as the resistance element, an operation when data is read from the memory element by voltage application will be described with reference to a specific example in FIG.

  FIG. 11 shows a current-voltage characteristic 951 of a memory element to which data has not been written, that is, a memory element with data “0”, a current-voltage characteristic 952 of a memory element to which data “1” has been written, and a resistance element 246. In this example, a transistor is used as the resistance element 246.

  In FIG. 11, in a memory cell having a storage element of data “0”, an intersection 954 between the current-voltage characteristic 951 of the storage element and the current-voltage characteristic 953 of the transistor serves as an operating point, and the potential of the node P at this time is V2 (V). The potential of the node P is supplied to the sense amplifier 247, and the data stored in the memory cell is determined as “0” in the sense amplifier 247.

  On the other hand, in a memory cell having a memory element in which data of “1” is written, an intersection 955 between the current-voltage characteristic 952 of the memory element and the current-voltage characteristic 953 of the transistor serves as an operating point. The potential is V1 (V) (V1 <V2). The potential of the node P is supplied to the sense amplifier 247. In the sense amplifier 247, the data stored in the memory cell is determined as “1”.

  As described above, the data stored in the memory cell can be determined by reading the resistance-divided potential in accordance with the resistance value of the memory element 241.

  According to the above method, data is read as a voltage value by utilizing the difference in resistance value of the memory element 241 and resistance division. However, the data included in the memory element 241 may be read using a current value.

Note that this embodiment mode can be freely combined with the above embodiment modes.

In the memory device of this embodiment, data can be recorded and erased by applying a voltage to a pair of conductive layers. Therefore, it is possible to write and erase data by selectively heating an arbitrary storage element other than during manufacturing. In addition, since it is not necessary to provide a separate device for writing and erasing data, the storage device can be reduced in size and simplified. Further, by forming a memory element using a flexible substrate, a flexible memory device can be manufactured.

(Embodiment 4)
In this embodiment, an example of a semiconductor device including the memory device described in the above embodiment will be described with reference to drawings.

  The semiconductor device described in this embodiment is characterized in that data can be read and written in a non-contact manner. A data transmission format is an electromagnetic which performs communication by mutual induction with a pair of coils arranged opposite to each other. There are roughly divided into a coupling system, an electromagnetic induction system that communicates using an induction electromagnetic field, and a radio system that communicates using radio waves, but any system may be used.

  An example of a structure of a semiconductor device in the case where an antenna is provided over a substrate provided with a plurality of elements and memory elements will be described with reference to FIGS.

  FIG. 9A illustrates a semiconductor device having a memory circuit formed of a passive matrix type. The semiconductor device includes transistors 451 and 452 formed over a first substrate 230, an insulating layer 249 covering the transistor, first conductive layers 371a to 371c of a memory element formed over the insulating layer 249 and connected to the transistor 452, And an element formation layer 351 having a conductive layer 353 functioning as an antenna, a second conductive layer 363 formed over the second substrate 242, and sandwiched between the first conductive layers 371 a to 371 c and the second conductive layer 363. The organic compound layer 364 is formed. The memory element is formed of the first conductive layers 371a to 371c, the second conductive layer 363, and the organic compound layer 364 sandwiched between the first conductive layers 371a to 371c and the second conductive layer 363. . Further, a spacer 250 may be provided between the insulating layer 249 and the second conductive layer 363.

  Note that the transistor 451 constitutes any of a power supply circuit, a clock generation circuit, a data demodulation / modulation circuit, a control circuit, and an interface circuit of the semiconductor device, and the transistor 452 has a potential of the first conductive layers 371a to 371c of the memory element. Control.

The conductive layer 353 functioning as an antenna is formed using the same layer as the source wiring and the drain wiring of the transistor. Note that the conductive layer 353 functioning as an antenna is not limited to this structure, and may be formed below or above the transistor. In this case, the material of the conductive layer 353 functioning as an antenna includes gold (Au), platinum (Pt), nickel (Ni), tungsten (W), molybdenum (Mo), cobalt (Co), copper (Cu), A kind of element selected from aluminum (Al), manganese (Mn), titanium (Ti), or the like, or an alloy containing a plurality of such elements can be used. As a method for forming the conductive layer 353 functioning as an antenna, various printing methods such as vapor deposition, sputtering, CVD, screen printing, and gravure printing, a droplet discharge method, or the like can be used.

  The memory element portion 352 includes a plurality of memory elements 352a to 352c. In addition, the memory element 352a includes a first conductive layer 371a formed over the insulating layer 249, an organic compound layer 364, and a second conductive layer 363 formed over the second substrate 242. The memory element 352b includes a first conductive layer 371b formed over the insulating layer 249, an organic compound layer 364, and a second conductive layer 363 formed over the second substrate 242. In addition, the memory element 352 c includes a first conductive layer 371 c formed over the insulating layer 249, an organic compound layer 364, and a second conductive layer 363 formed over the second substrate 242. The first conductive layers 371 a to 371 c are connected to the source wiring or the drain wiring of the transistor 452.

The memory element portion 352 can be formed as appropriate by using a structure, a material, and a manufacturing method similar to those of the memory element described in the above embodiment.

  Further, in the memory element portion 352, as described in the above embodiment, between the first conductive layers 371a to 371c and the organic compound layer 364 or between the organic compound layer 364 and the second conductive layer 363. An element having a rectifying property may be provided. As the rectifying element, the element described above in Embodiment Mode 1 can be used.

As the transistors 451 and 452 included in the element formation layer 351, the transistor 240 described in Embodiment 3 can be used as appropriate.

  Further, a peeling layer and an element formation layer 351 are formed over the first substrate 230, the element formation layer 351 is peeled off appropriately using the peeling method described in Embodiment 3, and attached to the substrate with an adhesive layer. May be. As the first substrate, a flexible substrate, a film having a thermoplastic resin layer, or the like shown in the first substrate 31 of Embodiment 1 is used, so that the memory device can be reduced in size, thickness, and weight. Is possible.

Further, a sensor connected to the transistor may be provided. Examples of the sensor include an element that detects temperature, humidity, illuminance, gas (gas), gravity, pressure, sound (vibration), or acceleration by physical or chemical means. The sensor is typically formed of a semiconductor element such as a resistance element, a capacitive coupling element, an inductive coupling element, a photovoltaic element, a photoelectric conversion element, a thermoelectric element, a transistor, a thermistor, or a diode.

  FIG. 9B illustrates an example of a semiconductor device including an active matrix memory circuit. Note that FIG. 9B will be described with respect to portions different from those in FIG.

  The semiconductor device illustrated in FIG. 9B includes transistors 451 to 453 formed over the first substrate 230, an insulating layer 249 covering the transistor, and a memory element 356a formed over the insulating layer 249 and connected to the transistor 452. A first conductive layer 371a, a first conductive layer 371b of a memory element 356b connected to the transistor 453, an insulating layer 249 covering the transistors 451 to 453, and an element formation layer 351 including a conductive layer 353 functioning as an antenna; The second conductive layer 363 formed on the substrate 242 and the organic compound layer 364 sandwiched between the first conductive layers 371a and 371b and the second conductive layer 363 are formed. The memory element unit 356 includes memory elements 356a and 356b. The memory element 356a is formed of a first conductive layer 371a, a second conductive layer 363, and an organic compound layer 364 sandwiched between the first conductive layer 371a and the second conductive layer 363. The memory element 356b is formed of a first conductive layer 371b, a second conductive layer 363, and an organic compound layer 364 sandwiched between the first conductive layer 371b and the second conductive layer 363. Further, a spacer 250 may be provided between the insulating layer 249 and the second conductive layer 363.

  Note that the first conductive layer 371a and the first conductive layer 371b are each connected to a source wiring or a drain wiring of the transistor. That is, a transistor is provided for each memory element.

The memory elements 356a and 356b can be formed as appropriate by using the structure, material, and manufacturing method described in the above embodiment modes. In the memory elements 356a and 356b, as described above, rectification is performed between the first conductive layers 371a and 371b and the organic compound layer 364 or between the organic compound layer 364 and the second conductive layer 363. You may provide the element which has.

  A peeling layer and an element formation layer 351 are formed over the first substrate 230, the element formation layer 351 is peeled off appropriately using the peeling method described in Embodiment 3, and an adhesive layer is used over the flexible substrate. You may paste.

Note that a sensor connected to the transistor may be provided. Examples of the sensor include an element that detects temperature, humidity, illuminance, gas (gas), gravity, pressure, sound (vibration), acceleration, and other characteristics by physical or chemical means. The sensor is typically formed of a semiconductor element such as a resistance element, a capacitive coupling element, an inductive coupling element, a photovoltaic element, a photoelectric conversion element, a thermoelectric element, a transistor, a thermistor, or a diode.

Note that this embodiment can be freely combined with the above embodiment.

According to this embodiment, an inexpensive semiconductor device can be provided. In addition, by forming a memory element using a flexible substrate, a flexible semiconductor device can be manufactured.

Here, the structure of the semiconductor device of the present invention will be described with reference to FIG. As shown in FIG. 12A, the semiconductor device 20 of the present invention has a function of communicating data without contact, and includes a power supply circuit 11, a clock generation circuit 12, a data demodulation / modulation circuit 13, and other circuits. A control circuit 14 to be controlled, an interface circuit 15, a storage device 16, a bus 17, and an antenna 18 are included.

Further, as shown in FIG. 12B, the semiconductor device 20 of the present invention has a function of communicating data without contact, and includes a power supply circuit 11, a clock generation circuit 12, a data demodulation / modulation circuit 13, and the like. In addition to the control circuit 14, the interface circuit 15, the storage device 16, the bus 17, and the antenna 18, the central processing unit 1 may be included.

Further, as shown in FIG. 12C, the semiconductor device 20 of the present invention has a function of communicating data without contact, and includes a power supply circuit 11, a clock generation circuit 12, a data demodulation / modulation circuit 13, and the like. In addition to the control circuit 14 for controlling the circuit, the interface circuit 15, the storage device 16, the bus 17, the antenna 18, and the central processing unit 1, the detection unit 2 including the detection element 3 and the detection control circuit 4 may be provided.

The semiconductor device of this embodiment includes a power supply circuit 11, a clock generation circuit 12, a data demodulation / modulation circuit 13, a control circuit 14 for controlling other circuits, an interface circuit 15, a storage device 16, and a transistor in an element formation layer. In addition to the bus 17, the antenna 18, and the central processing unit 1, the detection unit 2 including the detection element 3 and the detection control circuit 4 constitutes a small semiconductor having a sensing function and capable of transmitting and receiving radio waves. It is possible to form a device.

  The power supply circuit 11 is a circuit that generates electric power to be supplied to each circuit inside the semiconductor device 20 based on the AC signal input from the antenna 18. The clock generation circuit 12 is a circuit that generates various clock signals to be supplied to each circuit inside the semiconductor device 20 based on the AC signal input from the antenna 18. The data demodulation / modulation circuit 13 has a function of demodulating / modulating data communicated with the reader / writer 19. The control circuit 14 has a function of controlling the storage device 16. The antenna 18 has a function of transmitting and receiving electromagnetic waves. The reader / writer 19 controls communication with the semiconductor device and processing related to the data. The semiconductor device is not limited to the above-described configuration, and may be a configuration in which other elements such as a power supply voltage limiter circuit and hardware dedicated to cryptographic processing are added.

  The storage device 16 has one or more selected from the storage elements shown in the first to third embodiments. Since a memory element having an organic compound layer can simultaneously achieve downsizing, thinning, and increase in capacity, providing the memory device 16 as a memory element having an organic compound layer reduces the size and weight of a semiconductor device. Can be achieved.

The detection unit 2 can detect temperature, pressure, flow rate, light, magnetism, sound (vibration), acceleration, humidity, illuminance, gas component, liquid component, and other characteristics by physical or chemical means. The detection unit 2 includes a detection element 3 that detects a physical quantity or a chemical quantity, and a detection control circuit 4 that converts the physical quantity or the chemical quantity detected by the detection element 3 into an appropriate signal such as an electrical signal. Yes. Examples of the detection element 3 include resistance elements, capacitive coupling elements, inductive coupling elements, photovoltaic elements, photoelectric conversion elements, thermoelectromotive elements, transistors, thermistors, diodes, capacitive elements, piezoelectric elements, and the like. Can be formed. A plurality of detection units 2 may be provided. In this case, a plurality of physical quantities or chemical quantities can be detected simultaneously.

The physical quantity here refers to temperature, pressure, flow rate, light, magnetism, sound (vibration), acceleration, humidity, illuminance, etc., and the chemical quantity is a gas component such as gas or a liquid component such as ion. Refers to chemical substances. In addition, the chemical amount includes organic compounds such as specific biological substances (for example, blood glucose level contained in blood) contained in blood, sweat, urine and the like. In particular, when a chemical amount is to be detected, a specific substance is necessarily selectively detected. Therefore, a substance that selectively reacts with a substance to be detected is provided in advance in the detection element 3. . For example, in the case of detecting a biological substance, it is preferable that an enzyme, an antibody molecule, a microbial cell, or the like that selectively reacts with the biological substance to be detected by the detection element 3 is fixed to a polymer compound or the like. .

  According to the present invention, a semiconductor device 9210 functioning as a wireless chip can be formed. The wireless chip has a wide range of uses. For example, the semiconductor device 9210 can be used for banknotes, coins, securities, bearer bonds, certificates (driver's license, resident's card, etc., see FIG. 13A), recording medium (DVD Software, videotape, etc., see FIG. 13B), packaging containers (wrapping paper, bottles, etc., see FIG. 13C), vehicles (bicycles, etc., see FIG. 13D), personal items ( (Such as bags and glasses), foods, plants, clothing, daily necessities, electronic products, etc. and goods such as luggage tags (see FIGS. 13E and 13F). Can do. In addition, the semiconductor device 9210 can be provided on an animal or a human body. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (also simply referred to as televisions, television receivers, television receivers), mobile phones, and the like.

  The semiconductor device 9210 of the present invention is fixed to an article by being mounted on a printed board, pasted on a surface, or embedded. For example, the semiconductor device 9210 is fixed to each article by being embedded in paper for a book or embedded in an organic resin for a package made of an organic resin. Since the semiconductor device 9210 of the present invention is small, thin, and lightweight, it does not impair the design of the article itself even after being fixed to the article. In addition, by providing the semiconductor device 9210 of the present invention for bills, coins, securities, bearer bonds, certificates, etc., an authentication function can be provided, and forgery can be prevented by using this authentication function. Can do. In addition, by providing the semiconductor device of the present invention in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., the efficiency of a system such as an inspection system can be improved.

Next, one mode of an electronic device in which the semiconductor device 9210 of the present invention is mounted is described with reference to drawings. The electronic device illustrated here is a mobile phone, which includes housings 2700 and 2706, a panel 2701, a housing 2702, a printed wiring board 2703, operation buttons 2704, and a battery 2705 (see FIG. 14). The panel 2701 is detachably incorporated in the housing 2702, and the housing 2702 is fitted on the printed wiring board 2703. The shape and dimensions of the housing 2702 are changed as appropriate in accordance with the electronic device in which the panel 2701 is incorporated. A plurality of packaged semiconductor devices are mounted on the printed wiring board 2703, and the semiconductor device 9210 of the present invention can be used as one of them. The semiconductor device of the present invention mounted on the printed wiring board 2703 has a plurality of functions such as a controller, a central processing unit (CPU), a memory, a power supply circuit, an audio processing circuit, and a transmission / reception circuit.

The panel 2701 is connected to the printed wiring board 2703 through the connection film 2708. The panel 2701, the housing 2702, and the printed wiring board 2703 are housed in the housings 2700 and 2706 together with the operation buttons 2704 and the battery 2705. A pixel region 2709 included in the panel 2701 is arranged so as to be visible from an opening window provided in the housing 2700.

  Note that the housings 2700 and 2706 are examples of the appearance of a mobile phone, and the electronic device according to the present embodiment can be transformed into various modes depending on the function and application.

  As described above, the semiconductor device of the present invention is characterized in that it is small, thin, and lightweight, and the limited space inside the housings 2700 and 2706 of the electronic device can be effectively used due to the above characteristics. . Furthermore, the electronic device can be reduced in size.

  In this embodiment, FIG. 16 shows voltage-current characteristics when data is written by applying a voltage to the memory element of the present invention.

  In the sample manufactured in this example, an insulating layer is formed on a substrate, the first conductive layer formed on the insulating layer, the organic compound layer formed on the first conductive layer, and the organic compound layer A memory element including the formed second conductive layer is included.

  In this embodiment, a glass substrate is used as a substrate, a 100 nm-thick titanium layer formed by a sputtering method is used as a first conductive layer, and a 100-nm-thick 4-cyano formed by an evaporation method as an organic compound layer. Using -4'-n-octyloxybiphenyl, an aluminum layer having a thickness of 200 nm formed by a vapor deposition method was used as the second conductive layer. In addition, the upper surface shape where the first conductive layer and the second conductive layer of the memory element overlap was a square, and the length of one side was 10 μm. As a writing method at this time, sweep measurement was performed to measure the current value of the sample at each voltage while increasing the voltage from 0 V to 0.01 V. Moreover, the application time of each voltage was 100 msec.

  FIG. 16 shows the writing characteristics of the sample used in this example. The horizontal axis represents the write voltage, and the vertical axis represents the write current value. A plot surrounded by a broken line 90 indicates a current value with respect to an applied voltage of the memory element before writing, and a plot surrounded by a broken line 91 indicates a current value with respect to the applied voltage of the memory element after writing. It can be seen that writing is possible at about 1.5V. That is, since writing can be performed with a low voltage, the semiconductor device including the memory element shown in this embodiment can reduce power consumption. In addition, since it is possible to write at a low voltage, in a semiconductor device capable of transmitting and receiving information wirelessly, such as an RFID tag, even with power generated based on an AC signal input from an antenna, Data can be written, erased, and rewritten.

  In this embodiment, FIG. 17 shows voltage-current characteristics when data is written by applying a voltage to the memory element of the present invention.

  In the sample manufactured in this example, an insulating layer is formed on a substrate, the first conductive layer formed on the insulating layer, the organic compound layer formed on the first conductive layer, and the organic compound layer A memory element including the formed second conductive layer is included.

  In this example, a glass substrate is used as a substrate, a titanium layer with a thickness of 100 nm formed by a sputtering method is used as a first conductive layer, and a 4-cyanophenyl with a thickness of 100 nm formed by an evaporation method in an organic compound layer. Using -4′-n-octyloxyphenylbenzoate, an aluminum layer having a thickness of 200 nm formed by a vapor deposition method was used as the second conductive layer. In addition, the upper surface shape where the first conductive layer and the second conductive layer of the memory element overlap was a square, and the length of one side was 10 μm. As a writing method at this time, sweep measurement was performed to measure the current value of the sample at each voltage while increasing the voltage from 0 V to 0.01 V. Moreover, the application time of each voltage was 100 msec.

  FIG. 17 shows the writing characteristics of the sample used in this example. The horizontal axis represents the write voltage, and the vertical axis represents the write current value. A plot surrounded by a broken line 92 indicates a current value with respect to an applied voltage of the memory element before writing, and a plot surrounded by a broken line 93 indicates a current value with respect to the applied voltage of the memory element after writing. It can be seen that writing is possible at about 2V. That is, since writing can be performed with a low voltage, the semiconductor device including the memory element shown in this embodiment can reduce power consumption. In addition, since it is possible to write at a low voltage, in a semiconductor device capable of transmitting and receiving information wirelessly typified by a wireless chip, power generated based on an AC signal input from an antenna In addition, data can be written, erased, and rewritten.

It is a figure explaining the read operation of the memory | storage device of this invention, the write operation, and the erase operation. It is sectional drawing explaining the memory element of this invention. It is sectional drawing explaining the memory element of this invention. It is sectional drawing explaining the memory element of this invention. It is a figure explaining the memory | storage device of this invention. 4A and 4B are a top view and a cross-sectional view illustrating a memory device of the present invention. It is a figure explaining the semiconductor device of the present invention. 4A and 4B are a top view and a cross-sectional view illustrating a memory device of the present invention. It is sectional drawing explaining the semiconductor device of this invention. It is sectional drawing explaining the semiconductor device of this invention. It is a figure explaining the current-voltage characteristic of the memory element and resistive element which can be applied to this invention. It is a figure explaining the structural example of the semiconductor device of this invention. It is a figure explaining the usage pattern of the semiconductor device of this invention. FIG. 11 illustrates an electronic device including a semiconductor device of the present invention. FIG. 10 is a cross-sectional view illustrating a transistor that can be applied to the present invention. It is a figure explaining the current-voltage characteristic when writing in the memory element of this invention. It is a figure explaining the current-voltage characteristic when writing in the memory element of this invention.

Claims (3)

A storage element including a first conductive layer, a second conductive layer on the first conductive layer, and an organic compound sandwiched between the first conductive layer and the second conductive layer;
The organic compound has liquid crystallinity,
By applying a first voltage between the first conductive layer and the second conductive layer, the mobility records data by phase transition to a different crystal phases the organic compound from the isotropic phase A storage device. A storage element including a first conductive layer, a second conductive layer on the first conductive layer, and an organic compound sandwiched between the first conductive layer and the second conductive layer;
The organic compound has liquid crystallinity,
By applying a first voltage between the first conductive layer and the second conductive layer, mobility is a phase transition to a different smectic phase to record data of the organic compound from the isotropic phase A storage device. A storage element including a first conductive layer, a second conductive layer on the first conductive layer, and an organic compound sandwiched between the first conductive layer and the second conductive layer;
The organic compound has liquid crystallinity,
By applying a first voltage between the first conductive layer and the second conductive layer, to record data mobility by phase transition to a different crystal phases the organic compound from the smectic phase A storage device.

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