JP5085463B2 - Information transfer circuit, information processing apparatus, information transfer circuit control method, control program, and recording medium - Google Patents

Description

  The present invention relates to an information transfer circuit, an information processing apparatus, a control method for an information transfer circuit, a control program, and a recording medium, and more particularly, a plurality of virtually independent multiple physical buffers shared by a plurality of buffers. The present invention relates to effective use of buffers when used as a communication bus.

In information transfer using serial communication such as the PCI Express standard, information transfer is performed using a VC (Virtual Channel: virtual communication bus). The VC realizes a plurality of virtually independent information communication buses by sharing a single physical communication bus with a plurality of buffers (see, for example, Patent Document 1). The number of VC channels, that is, the number of virtual communication buses, is determined by the number of buffers (hereinafter referred to as VC buffers) for realizing VC.
JP 2005-332316 A

  In conventional information transfer by VC, the number of VC channels is adjusted to the smaller number of VC buffers mounted in two devices that perform information transfer, respectively. For this reason, when the number of VC buffers mounted on two devices is different, an extra VC buffer of a device on which many VC buffers are mounted has not been used. As a result, resources included in the apparatus are wasted.

  The present invention has been made in consideration of the above circumstances, and effectively uses an information transfer buffer in information transfer that realizes a virtual communication bus by sharing a single physical serial communication bus with a plurality of buffers. For the purpose.

In order to solve the above problem, the invention described in claim 1 is a plurality of information communication buses virtually independent by sharing a single physical serial communication bus with a plurality of virtual communication buffer areas. An information transfer circuit for realizing a virtual communication bus, the counter buffer number recognition unit for recognizing the number of virtual communication buffer areas included in a counter device connected via the serial communication bus as the counter buffer number, When the number of recognized counter buffers is smaller than the number of virtual communication buffer areas included in the information transfer circuit, the same number of virtual buffers for virtual communication as the number of counter buffers in the virtual communication buffer areas included in the information transfer circuit A used buffer determining unit that determines a buffer area as a used buffer area to be used for the virtual communication bus; and a virtual buffer included in the information transfer circuit. Extra buffer region other than the use buffer area of the credit buffer area, have a and extra buffer space allocation unit for allocating a region for expanding the information transfer buffer area used when the information transfer circuit to perform the information transfer A plurality of virtual communication buffer areas included in the information transfer circuit are subjected to a negotiation process for each virtual communication buffer area in a negotiation process with a plurality of virtual communication buffer areas included in the opposite device, The extra buffer area allocating unit is an area that extends a virtual communication buffer area other than the virtual communication buffer area in which a negotiation process is first executed among a plurality of virtual communication buffer areas included in the information transfer circuit. , and allocating the extra buffer area
The invention according to claim 2 realizes a virtual communication bus which is a plurality of virtually independent information communication buses by sharing a single physical serial communication bus with a plurality of virtual communication buffer areas. An information transfer circuit, a counter buffer number recognition unit for recognizing the number of virtual communication buffer areas included in a counter device connected via the serial communication bus as a counter buffer number, and the number of counter buffers recognized Is smaller than the number of virtual communication buffer areas included in the information transfer circuit, the virtual communication buffer areas equal in number to the counter buffers are included in the virtual communication buffer areas included in the information transfer circuit. A used buffer determining unit for determining a used buffer area for the bus, and a virtual communication buffer area included in the information transfer circuit. An extra buffer area allocation unit that allocates an extra buffer area other than the used buffer area as an area for expanding the information transfer buffer area used when the information transfer circuit performs information transfer, and the information transfer circuit. A negotiation processing unit that executes negotiation processing between the plurality of virtual communication buffer areas and the plurality of virtual communication buffer areas included in the opposite device, and the negotiation processing unit is included in the information transfer circuit The negotiation processing is executed by transmitting negotiation information including information related to a virtual communication buffer area, and the negotiation information includes information on the number of virtual communication buffer areas included in the information transfer circuit. To do.
The invention according to claim 3 realizes a virtual communication bus which is a plurality of virtually independent information communication buses by sharing a single physical serial communication bus with a plurality of virtual communication buffer areas. An information transfer circuit, a counter buffer number recognition unit for recognizing the number of virtual communication buffer areas included in a counter device connected via the serial communication bus as a counter buffer number, and the number of counter buffers recognized Is smaller than the number of virtual communication buffer areas included in the information transfer circuit, the virtual communication buffer areas equal in number to the counter buffers are included in the virtual communication buffer areas included in the information transfer circuit. A used buffer determining unit for determining a used buffer area for the bus, and a virtual communication buffer area included in the information transfer circuit. An extra buffer area allocating unit that allocates an extra buffer area other than the used buffer area as an area for expanding an information transfer buffer area used when the information transfer circuit executes information transfer. A plurality of virtual communication buffer areas included in the circuit are negotiated with each of the virtual communication buffer areas in the negotiation process with the plurality of virtual communication buffer areas included in the opposite device, and the information transfer circuit A buffer area initialization unit that initializes a virtual communication buffer area that is initially negotiated after the negotiation process among the plurality of virtual communication buffer areas included in Unit is used as the used buffer area As an area where the negotiation process of the credit buffer area extends the first virtual communication buffer area including a virtual communication buffer area is performed, and allocates the extra buffer area.
The invention according to claim 4 realizes a virtual communication bus which is a plurality of virtually independent information communication buses by sharing a single physical serial communication bus with a plurality of virtual communication buffer areas. An information transfer circuit, a counter buffer number recognition unit for recognizing the number of virtual communication buffer areas included in a counter device connected via the serial communication bus as a counter buffer number, and the number of counter buffers recognized Is smaller than the number of virtual communication buffer areas included in the information transfer circuit, the virtual communication buffer areas equal in number to the counter buffers are included in the virtual communication buffer areas included in the information transfer circuit. A used buffer determining unit for determining a used buffer area for the bus, and a virtual communication buffer area included in the information transfer circuit. An extra buffer area allocating unit that allocates an extra buffer area other than the used buffer area as an area for expanding an information transfer buffer area used when the information transfer circuit executes information transfer. The area allocation unit allocates the extra buffer area as an area for expanding the information transfer buffer area by generating information associating the extra buffer area with the information transfer buffer area.
The invention according to claim 5 realizes a virtual communication bus which is a plurality of virtually independent information communication buses by sharing a single physical serial communication bus with a plurality of virtual communication buffer areas. An information transfer circuit, a counter buffer number recognition unit for recognizing the number of virtual communication buffer areas included in a counter device connected via the serial communication bus as a counter buffer number, and the number of counter buffers recognized Is smaller than the number of virtual communication buffer areas included in the information transfer circuit, the virtual communication buffer areas equal in number to the counter buffers are included in the virtual communication buffer areas included in the information transfer circuit. A used buffer determining unit for determining a used buffer area for the bus, and a virtual communication buffer area included in the information transfer circuit. An extra buffer area allocating unit that allocates an extra buffer area other than the used buffer area as an area for expanding an information transfer buffer area used when the information transfer circuit executes information transfer. The area allocation unit allocates the extra buffer area as an area for expanding the information transfer buffer area by switching the connection between the information transfer buffer area and the extra buffer area.
The invention according to claim 6 realizes a virtual communication bus which is a plurality of virtually independent information communication buses by sharing a single physical serial communication bus with a plurality of virtual communication buffer areas. An information transfer circuit, a counter buffer number recognition unit for recognizing the number of virtual communication buffer areas included in a counter device connected via the serial communication bus as a counter buffer number, and the number of counter buffers recognized Is smaller than the number of virtual communication buffer areas included in the information transfer circuit, the virtual communication buffer areas equal in number to the counter buffers are included in the virtual communication buffer areas included in the information transfer circuit. A used buffer determining unit for determining a used buffer area for the bus, and a virtual communication buffer area included in the information transfer circuit. An extra buffer area allocating unit that allocates an extra buffer area other than the used buffer area as an area for expanding an information transfer buffer area used when the information transfer circuit executes information transfer. A method information storage unit that stores information on a method of information when the circuit transfers information to and from the opposite device, and the method information according to the allocation result of the extra buffer area by the extra buffer allocation unit And a method information updating unit for updating information stored in the storage unit.
Further, the invention according to claim 7 is the information transfer circuit according to claim 6, wherein the method information includes capacity information relating to an information capacity that can be included in one packet, and the method information update unit includes: The capacity information is updated.
The invention according to claim 8 is the information transfer circuit according to claim 7, wherein the extra buffer area allocating unit is configured to transfer information to the used buffer area or the information transfer circuit. The extra buffer area is allocated as an area that expands at least one of the retry buffer areas used for retry when executing the process, and the method information update unit is configured to use the extra buffer area and the retry buffer area. When the extra buffer area is allocated as an area for extending both, the capacity information is updated so as to increase the information capacity that can be included in the one packet.

The invention according to claim 9 is the information transfer circuit according to any one of claims 1 to 8 , wherein the extra buffer area allocating unit uses the extra buffer area as an area for expanding the used buffer area. An area is allocated.

According to a tenth aspect of the present invention, in the information transfer circuit according to any one of the first to ninth aspects, the extra buffer area allocating unit performs a retry when the information transfer circuit executes information transfer. The extra buffer area is allocated as an area for expanding a buffer area to be used.

Further, an invention according to claim 1 1, in the information transfer circuit according to any one of claims 1 to 1 0, wherein the additional buffer area allocation unit, depending on the execution of the information transfer according to the information transfer circuit The extra buffer area is dynamically allocated.

The invention described in Claim 1 2 is an information processing apparatus, characterized in that it comprises a information transfer circuit according to any one of claims 1 to 1 1.
The invention according to claim 13 realizes a virtual communication bus which is a plurality of virtually independent information communication buses by sharing a single physical serial communication bus with a plurality of virtual communication buffer areas. A method of controlling an information transfer circuit, wherein the number of virtual communication buffer areas included in a counter device connected via the serial communication bus is recognized as a counter buffer number, and the recognized counter buffer number is the information When the number of virtual communication buffer areas included in the transfer circuit is smaller than the number of virtual communication buffer areas included in the information transfer circuit, the same number of virtual communication buffer areas as the counter buffer are included in the virtual communication bus. Used as a buffer area to be used for the virtual communication, and the virtual communication buffer area included in the information transfer circuit is an extra buffer area other than the buffer area to be used By generating information associating a buffer area with the information transfer buffer area, the extra buffer area is allocated as an area for expanding the information transfer buffer area used when the information transfer circuit executes information transfer. It is characterized by.

The invention according to claim 14 realizes a virtual communication bus which is a plurality of virtually independent information communication buses by sharing a single physical serial communication bus with a plurality of virtual communication buffer areas. A method of controlling an information transfer circuit, wherein the number of virtual communication buffer areas included in a counter device connected via the serial communication bus is recognized as a counter buffer number, and the recognized counter buffer number is the information When the number of virtual communication buffer areas included in the transfer circuit is smaller than the number of virtual communication buffer areas included in the information transfer circuit, the same number of virtual communication buffer areas as the counter buffer are included in the virtual communication bus. Used as a buffer area to be used for the virtual communication, and the virtual communication buffer area included in the information transfer circuit is an extra buffer area other than the buffer area to be used The Ffa area, said information transfer circuit allocated as an area for expanding the information transfer buffer area used for executing the information transfer, the information when the information transfer circuit to transfer information to and from the opposite device the information stored in the system information storage unit that stores information about the system, characterized that you updated according to the allocation result of the extra buffer area by the extra buffer allocation unit.

The invention described in claim 15 is a control program, characterized by causing an information processing apparatus to execute the method for controlling an information transfer circuit according to claim 13 or 14.

  The invention according to claim 16 is a recording medium, wherein the control program according to claim 15 is recorded in a format readable by the information processing apparatus.

  According to the present invention, a buffer can be effectively used in information transfer for realizing a virtual communication bus by sharing a single physical serial communication bus with a plurality of buffers.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
Embodiment 1 FIG.
In the present embodiment, an image processing apparatus 1 including an information transfer circuit that implements a virtual communication bus will be described as an example. The image processing apparatus 1 according to the present embodiment is configured as a multifunction machine having functions as a scanner, a printer, and a copier.

  FIG. 1 is a block diagram illustrating a hardware configuration of an image processing apparatus 1 in which the information transfer circuit according to the present embodiment is used. As shown in FIG. 1, the image processing apparatus 1 according to the present embodiment includes the same configuration as an information processing terminal such as a general server or a PC (Personal Computer). That is, the information transfer circuit according to the present embodiment can be applied to a general information processing apparatus such as a PC.

  That is, the image processing apparatus 1 according to the present embodiment includes a CPU (Central Processing Unit) 10, a RAM (Random Access Memory) 20, an engine 30, an HDD (Hard Disk Drive) 40, a ROM (Read Only Memory) 50, and an NVRAM (Non-volatile Memory). Non-Volatile Random Access Memory) 60 and I / F 70 are connected via a bus B. Further, an LCD (Liquid Crystal Display) 80 and an operation unit 90 are connected to the I / F 70.

  The CPU 10 is a calculation unit and controls the operation of the information processing apparatus 1 as a whole. The RAM 20 is a volatile storage medium capable of reading and writing information at high speed, and is used as a work area when the CPU 10 processes information. The engine 30 is an image processing engine that executes an image processing function such as a scanner or a printer. The HDD 40 is a mass storage device using a magnetic recording medium. The ROM 50 is a read-only nonvolatile storage medium, and stores programs such as firmware.

  The NVRAM 60 is a non-volatile storage medium capable of reading and writing information, and stores an OS (Operating System), various control programs, application programs, information on operation parameters of the application programs, and the like. The I / F 70 connects and controls the bus B and various hardware and networks. The information transfer circuit according to the present embodiment is included in the I / F 70. The LCD 80 is a visual user interface for the user to check the state of the image processing apparatus 1. The operation unit 90 is a user interface such as a keyboard and a mouse for a user to input information to the image processing apparatus 1.

  Next, the information transfer circuit included in the I / F 70 according to the present embodiment will be described in detail. FIG. 2 is a diagram showing a connection portion with the LCD 80 in the I / F 70 according to the present embodiment. As shown in FIG. 2, the I / F 70 according to the present embodiment includes an information transfer circuit 100 and a VGA (Video Graphics Array) 200. The information transfer circuit 100 and the VGA 200 according to the present embodiment perform transmission / reception of information according to PCI Express, which is a standard for high-speed serial communication.

  The information transfer circuit 100 includes a controller 101, a transaction layer control unit 102, a data link layer control unit 103, a physical layer control unit 104, and a connection unit 105. The VGA 200 includes a controller 201, a transaction layer control unit 202, a data link layer control unit 203, a physical layer control unit 204, and a connection unit 205. In the information transfer circuit 100 and the VGA 200, configurations having the same names bear the same or corresponding functions. Therefore, in the following description, only the information transfer circuit 100 will be described, but the same applies to the VGA 200.

  The controller 101 has the highest configuration in the information transfer circuit 100, and is configured by a combination of software and hardware. Specifically, the controller 101 is configured by a control program read into a RAM or the like operating according to the CPU. The controller 101 executes exchange with the CPU 10 via the bus B in the information transfer circuit 101. Connection unit 105 includes a connection terminal that actually connects information transfer circuit 100 and VGA 200.

  The core of the PCI Express standard architecture as in this embodiment is the transaction layer, the data link layer, and the physical layer. The transaction layer control unit 102, the data link layer control unit 103, and the physical layer control unit 104 control operations of the transaction layer, the data link layer, and the physical layer, respectively.

  The transaction layer control unit 102 assembles and disassembles a TLP (Transaction Layer Packet). The TLP is a packet used for transmission of information such as information transmission / reception or an event in communication of the PCI Express standard. Further, the transaction layer control unit 102 includes a configuration for controlling the VC that is the gist of the present embodiment.

  The data link layer control unit 103 executes error detection, error correction, or retry processing for information transfer. As a result, the data link layer control unit 103 ensures the integrity of the TLP. The data link layer control unit 103 performs link management. That is, the data link layer control unit 103 exchanges packets for link management and flow control. A packet processed by the data link control unit 103 is a DLLP (Data Link Layer Packet).

  The physical layer control unit 104 includes a circuit necessary for interface operation. Circuits included in the physical layer control unit 104 include a driver, an input buffer, a parallel / serial converter, a PLL (Phase-Locked Loop), an impedance matching circuit, and the like. The physical layer control unit 104 has interface initialization and maintenance functions. Further, the physical layer control unit 104 has a function of making the data link layer control unit 103 and the transaction layer control unit 102 independent of the signal technology used in the actual link.

  In such an information transfer circuit 100, as described above, the configuration and operation of controlling the VC included in the transaction layer control unit 102 is the gist of the present embodiment. Details of the transaction layer control unit 102 will be described with reference to FIG. FIG. 3 is a block diagram showing a configuration of the transaction layer control unit 102 according to the present embodiment. As shown in FIG. 3, the transaction layer control unit 02 includes a VC controller 120, VC buffers 21 to 27, and a signal distributor / mixer 125. Further, the VC controller 120 includes an information transfer control unit 121, a VC establishment unit 122, and a used buffer recognition unit 123 VC buffer management unit 124.

  The VC controller 120 controls the VC in the transaction layer control unit 102 to transfer information. The VC controller 120 and each element included in the VC controller 120 are realized by a combination of software and hardware. Specifically, the VC controller 120 is configured by a control program read to a RAM or the like operating according to a calculation unit such as a CPU. The information transfer control unit 121 generates a TLP and sends it out through the VC buffers 21 to 27. In addition, the information transfer control unit 121 decomposes the TLP received via the VC buffers 21 to 27.

  The VC establishment unit 122 establishes a VC with the opposite device (VGA 200 in the present embodiment) connected via the connection unit 105. The used buffer recognition unit 123 recognizes the number of VCs according to the VC establishment result by the VC establishment unit 122. The VC buffer management unit 124 manages the VC buffers 21 to 27 according to the recognition result of the number of VCs by the used buffer recognition unit 123. The function of the VC buffer management unit 124 is one of the gist of the present embodiment.

  The VC buffers 21 to 27 are information transfer buffers provided for realizing VC. The VC buffers 21 to 27 are connected to one serial communication bus via the signal distributor / mixer 125. Since the VC buffers 21 to 27 operate independently, a plurality of independent communication buses can be virtually realized by one serial communication bus.

  The VC buffers 21 to 27 correspond to the channels VC0 to VC6, respectively. The signal distributor / mixer 125 distributes the signal of one serial communication bus to the VC buffers 21 to 27, respectively. Further, the signal distributor / mixer 125 mixes the signals of the VC buffers 21 to 27 and inputs them to one serial communication bus.

  Next, an initialization process of the information transfer circuit 100 according to the present embodiment will be described. FIG. 4 is a flowchart showing the initialization operation of the information transfer circuit 100 according to the present embodiment. The initialization operation shown in FIG. 4 is executed as part of the power-on reset process of the I / F 70 after the information processing apparatus 1 is powered on.

  As shown in FIG. 4, in the initialization process of the information transfer circuit 100, first, the data link layer control unit 103 executes the negotiation process of VC0 (S401). That is, the data link layer control unit 103 functions as a negotiation processing unit. The negotiation process is a process for mutually recognizing the number of VCs between the information transfer circuit 100 and the VGA 200.

  The process of S401 will be described with reference to FIG. FIG. 5 is a diagram schematically showing an aspect of the negotiation process. As shown in FIG. 5, the VC0 negotiation process is executed upon link-up by the data link control unit 103. As shown in FIG. 5, in the negotiation process, a packet called InitFC (Initialize Flow Control) is exchanged. That is, InitFC is used as negotiation information. In the present embodiment, the negotiation is completed by exchanging InitFC1 and InitFC2.

  As shown in FIG. 5, the data link layer control unit 203 of the VGA 200 that has received InitFC1 refers to the VC buffer of VC0 included in the transaction layer control unit 202. If VC0 is valid, the data link layer control unit 203 returns InitFC1. After that, negotiation of VC0 is completed by the exchange of InitFC2.

  InitFC1 and InitFC2 packets include information on the capacity of the VC buffer. As a result, the VC establishment unit 122 recognizes the capacity of the VC buffer (here, the buffer of VC0) included in the VGA 200. The VC establishment unit 122 stores information regarding the capacity of the recognized VC buffer of the VGA 200 in the VC buffer management unit 124. Thereby, information transfer by VC0 becomes possible.

  When the negotiation of VC0 is completed, the VC establishment unit 122 of the transaction layer control unit 102 executes configuration read / write processing based on the control of the controller 101 (S402). In S <b> 402, the VC establishment unit 122 transmits configuration information to the VGA 200 via the VC <b> 0 that has already been negotiated, and reads the configuration information from the VGA 200.

  The configuration information exchanged in S402 includes, for example, information on the number of VC buffers included in the information transfer circuit 100 and the VGA 200 (hereinafter referred to as mounting VC information). Thereby, the VC establishment unit 122 can recognize the number of VC buffers included in the VGA 200. That is, the VC establishment unit 122 functions as a counter buffer number recognition unit. Also, the VGA 200 validates the VC buffer of the transaction layer control unit 202 by receiving the configuration information from the information transfer circuit 100.

  When the configuration read / write processing is completed, the used buffer recognition unit 123 and the VC buffer management unit 124 work together to allocate an unused buffer (S403). FIG. 6 shows details of the processing in S403. As shown in FIG. 6, first, the use buffer recognition unit 123 recognizes the number of mounted VCs based on the mounted VC information (S601). The number of mounted VCs referred to here is the number of VC buffers mounted on the information transfer circuit 100 and the VGA 200, respectively.

  Next, the used buffer recognition unit 123 determines a buffer to be used among the VC buffers 21 to 27 (S602). In step S <b> 602, the used buffer recognition unit 123 determines a buffer to be used (hereinafter referred to as a used buffer) based on the number of VC buffers mounted on the VGA 200. Specifically, the used buffer recognizing unit 123 determines the same number of VC buffers in the lower diagram as the used buffers as the number of VC buffers mounted on the VGA 200. That is, the use buffer recognition unit 123 functions as a use buffer determination unit.

  In determining the use buffer, a VC buffer having a smaller number, such as VC0, VC1, VC2,. When the use buffer recognition unit 123 determines the use buffer, the use buffer recognition unit 123 stores the information in the VC buffer management unit 124.

  After storing the information on the number of used buffers, the VC buffer management unit 124 determines whether there is an unused buffer (S603). If there is an unused buffer as a result of the determination in S603 (S603 / Yes), the VC buffer management unit 124 allocates the storage area of the unused buffer as the storage area of the used buffer (S604), and ends the process. That is, the VC buffer management unit 124 functions as an extra buffer area allocation unit. As shown in FIG. 3, the VC buffers 21 to 27 according to the present embodiment are provided as separate storage media. In the unused buffer allocation process in S604, the VC buffer management unit 124 generates information (buffer allocation information) for managing the address of the storage area of the unused buffer.

  FIG. 7 shows an example of buffer allocation information generated by the VC buffer management unit 124. In the example of FIG. 7, the VC0 to VC2 buffers, that is, the VC buffers 21 to 23 are used buffers, and the VC3 and later buffers, that is, the VC buffer 24 and later are unused buffers. As shown in FIG. 7, the buffer allocation information includes an unused buffer, address information for specifying a storage area of the unused buffer, and information on a buffer to which the storage area is allocated.

  In the example of FIG. 7, for example, the buffer of “VC3”, that is, the area of addresses “*** to ##” of the VC buffer 24 is allocated as an area for expanding the storage area of VC1. The buffer allocation information shown in FIG. 7 is generated by the VC buffer management unit 124 and stored in a storage area included in the information transfer control unit 121. As shown in FIG. 7, in the present embodiment, VC0 is not an allocation destination buffer. This will be described in detail later.

  On the other hand, when there is no unused buffer (S603 / NO), the VC controller 120 ends the initialization process as it is. Such processing makes it possible to effectively use a VC buffer that cannot be used in relation to the VGA 200 that is the opposite device.

  Returning to the description of FIG. When the unused buffer allocation processing is completed, the data link layer control unit 103 sets “1” in the variable n (S404), and executes negotiation for VCn (S405). If n = 1, the negotiation process for VC1 is performed. As shown in FIG. 5, the negotiation process for VC1 is completed by exchanging InitFC1 and InitFC2 as in the negotiation process for VC0.

  In the exchange of InitFC in S405, the data link layer control unit 103 exchanges information on the capacity of the corresponding VC buffer as described above. Here, in the negotiation process after VC1, the data link layer control unit 103 exchanges the total capacity after the unused buffers are allocated by the VC buffer management unit 124. For example, in the example of FIG. 7, when performing VC1 negotiation, the data link layer control unit 103 determines the total capacity of the VC1 VC buffer 22, the VC3 VC buffer 24, and the VC4 VC buffer 25 as follows. Include in InitFC packet.

  In the negotiation process for VC1, if VC1 is valid (S406 / No), VC1 is validated and the negotiation process is completed (S408). Here, when the negotiation for all the VC buffers included in the transaction layer control unit 102 is completed, that is, when n = the number of all VC buffers (S409 / Yes), the data link layer control unit 103 performs the negotiation. Is finished (S407). Further, when the VCn to be negotiated is invalid (S406 / Yes), the negotiation is also terminated (S407).

  On the other hand, if the negotiation has not been completed for all the VC buffers yet (S409 / No), the data link layer control unit 203 sets n to n + 1 (S410) and repeats the processing from S405. In the present embodiment, as described above, VC0 to VC2 are effective. In this case, as shown in FIG. 5, when InitFC is executed for VC3, VGA200 does not return InitFC because VC3 is invalid in VGA200. Thereby, in the case of n = 3, it is judged that VC3 is invalid (S406 / Yes), and the negotiation process ends (S407). Note that the number of VC buffers is determined by the configuration read & write process (S402). Therefore, the information transfer circuit 100 may end the process without transmitting the VC3 InitFC1. Thereby, unnecessary signal transmission can be omitted and the processing efficiency can be improved.

  By such processing, the negotiation processing according to the present embodiment is completed. As described with reference to FIG. 4, in the present embodiment, configuration read / write is performed after negotiation for VC0 is completed. At this time, since information is transmitted and received through VC0, it is necessary to determine a buffer area for VC0 first. Specifically, it is necessary to register the storage capacity of the VC buffer of VC0 in the VC buffer management unit 124.

  For this reason, a VC buffer storage area is allocated to a VC other than VC0. This makes it possible to easily implement the effective use function of the unused buffer according to the present embodiment. In the present embodiment, it is referred to as “VC0”, but this is a name according to the present embodiment. That is, “VC0” indicates a channel on which negotiation is first executed in the negotiation process shown in FIG.

  As described above, by using the information transfer circuit 100 according to the present embodiment, a buffer is effectively used in information transfer for realizing a virtual communication bus by sharing a single physical communication bus with a plurality of buffers. It becomes possible to do.

  Note that the storage area of the used buffer is virtually expanded by the processing described above. Therefore, the amount of information that can be held is increased, and the transfer speed can be improved. This is an effect due to an increase in the number of packets that can be held. However, when the number of packets increases, the overhead capacity increases correspondingly and becomes inefficient. On the other hand, as shown in FIG. 8, it is conceivable to extend the Max Payload Size of the TLP handled by the transaction layer control unit 102. As a result, the amount of information to be transferred can be increased without increasing the number of packets.

  In FIG. 8, TLP is information generated in the transaction layer control unit 102. TLP is an information method used when the transaction layer control unit 102 transfers information to and from the opposite device. Information for generating the TLP (hereinafter referred to as method information) is stored in a storage medium provided in the VC controller 120. That is, the VC controller 120 functions as a method information storage unit.

  In addition, when the Max Payload Size is extended as shown in FIG. 8, it is necessary to update the method information. This update process is executed by the VC buffer management unit 124 in accordance with, for example, an unused buffer allocation result. That is, the VC buffer management unit 124 functions as a method information update unit.

  In the above description, as described with reference to FIG. 5, the example has been described in which the unused buffer area and the used buffer are fixedly associated with each other. In addition, the buffer area may be dynamically allocated according to the transfer status by the information transfer control unit 121. For example, an unused buffer may be used as an extension area of VC1 while information transfer is being performed via VC1.

  In such a case, the InitFC packet exchanged in S405 of FIG. 4 includes the total capacity of the target VC buffer and all unused buffers as buffer capacity information. As a result, the VC buffer management unit 124 recognizes the original capacity of the VC buffer and the total capacity of all unused buffers as the capacity of the target VC buffer. When information transfer is executed, the information transfer control unit 121 executes information transfer by dynamically switching the connection with the VC buffers 21 to 27.

  Further, in the above description, as shown in FIG. 5, a mode has been described in which unused buffers are allocated to used buffers among VC buffers. However, the destination to which the unused buffer is allocated is not limited to the VC buffer. For example, it can be assigned to a retry buffer. In other words, the unused buffer, that is, the extra buffer area can be used as a buffer area used when the information transfer circuit 100 executes information transfer, that is, an area for expanding the information transfer buffer area.

  By using the unused buffer as an extension area of the retry buffer, the amount of information that can be held by the retry buffer increases when a retry occurs. Therefore, it is possible to reduce the transfer speed drop and execute the retry appropriately. The retry buffer is originally provided in the data link layer control unit 103. When an unused buffer is used as a retry buffer, the information transfer control unit 121 executes retry processing control.

  As shown in FIG. 8, it is preferable to extend the TLP Max Payload Size when both the VC buffer area and the retry buffer area are expanded by unused buffers. When Max Payload Size is expanded, the size of one packet inevitably increases. Therefore, if the buffer size is not expanded, the number of packets that can be held by the buffer decreases. As a result, performance may be degraded. If both the VC buffer and the retry buffer are expanded, such a problem can be avoided.

  In the above description, the example in which the VC controller 120 is realized by a combination of software and hardware has been described. In addition, the VC controller 120 can be configured entirely by hardware. In this case, the unused buffer is not allocated by managing the address information as shown in FIG. 5, but by switching the connection between the storage element included in the VC buffers 21 to 27 and the information transfer control unit 121 by the switching element. Execute.

  In the above description, an example in which the VC establishment unit 122, the used buffer recognition unit 123, and the VC buffer management unit 124 are provided in the VC controller 120 inside the transaction control unit 102 has been described. These functions can also be provided in the controller 101. Alternatively, the program loaded in the RAM 20 shown in FIG. 1 can be realized by operating under the control of the CPU 10.

Embodiment 2. FIG.
In the first embodiment, the mode in which an unused buffer is not allocated to VC0 has been described for the sake of easy implementation. However, in order to improve the transfer rate, it is preferable to allocate an unused buffer to VC0. In the present embodiment, an example in which an unused buffer is allocated to VC0 will be described. In addition, about the structure which attaches | subjects the code | symbol similar to Embodiment 1, the same or an equivalent part is shown and description is abbreviate | omitted.

  The information processing apparatus 1 and the information transfer circuit 100 according to the present embodiment have substantially the same configuration as the aspect of the first embodiment described with reference to FIGS. The information transfer circuit 100 according to the present embodiment is different from the first embodiment in the unused buffer allocation process. As described above, it is difficult to allocate an unused buffer to VC0 because there are restrictions in the negotiation process. In order to eliminate this restriction, the information transfer circuit 100 according to the present embodiment executes an initialization process different from that of the first embodiment.

  FIG. 9 is a flowchart showing the operation of the negotiation process according to the present embodiment. As shown in FIG. 9, the processing in S901 and S902 is executed in the same manner as S601 and S602 described in FIG. In the configuration read / write process (S902) according to the present embodiment, the VC establishment unit 122 stores the acquired mounted VC number information in the VC buffer management unit 124. In addition, when the configuration read / write processing is completed, the VC establishment unit 122 sets a configuration read completed flag in the VC buffer management unit 124.

  When the configuration read / write processing ends (S902), the information transfer circuit 100 resets the register (S903). In step S903, at least information on the capacity of the VC buffer 21, that is, the capacity of VC0, stored in the VC buffer management unit 124 is reset. These resets are executed by the VC controller 120, for example. That is, the VC controller 120 functions as a buffer area initialization unit. FIG. 10 shows an example of information stored in the VC buffer management unit 124. As shown in FIG. 10, the register provided in the VC buffer management unit 124 stores the number of mounted VCs, the config read flag, the used buffer information, the buffer allocation information, and the VC buffer capacity information.

  As described above, the mounted VC number information and the config read flag are information acquired by the VC establishing unit 122 and stored in the VC buffer management unit 124 in the configuration read / write process (S902). The used buffer information is information determined by the used buffer recognition unit 123 as described in the first embodiment. The buffer allocation information is information generated by the VC buffer management unit 124 as described in the first embodiment. The VC buffer capacity information is information stored by exchange of InitFC.

  In the processing of S903, the information transfer circuit 100 executes a reset so as to erase other information while retaining the information indicated by the double line in FIG. 10, that is, the mounted VC number information and the config read completed flag. When the reset is completed, the used buffer recognition unit 123 and the VC buffer management unit 124 allocate unused buffers (S904). The VC controller 120 checks the config read completion flag stored in the VC buffer management unit 124, and then proceeds to the allocation process (S904) after the reset process (S903).

  In S904, processing is executed in substantially the same manner as the processing described in FIG. Here, in the present embodiment, the VC buffer capacity information shown in FIG. 10 is reset. Therefore, the capacity information of VC0 is not stored. This makes it possible to allocate an unused buffer to VC0 in S504 of FIG. When the unused buffer allocation process is completed, the data link layer control unit 103 sets “0” to the variable n (S905), and executes the negotiation process from VC0 (S906). Thereafter, the processing after S906 is executed in the same manner as the processing after S405 in FIG.

  As described above, in the information transfer circuit 100 according to the present embodiment, VC0 is reset after the configuration read / write is completed. As a result, an unused buffer can be allocated to VC0. As a result, it becomes possible to effectively use the invalidated VC buffer and improve the transfer efficiency.

Embodiment 3 FIG.
In the second embodiment, an example has been described in which an unused buffer can be allocated to a VC by executing a reset as described with reference to FIG. 10 after the negotiation process is completed. In this case, a new configuration for executing the reset as described above is required. Therefore, it is necessary to change the circuit for mounting. In the present embodiment, a method for more easily realizing the allocation of unused buffers to VC0 will be described. In addition, about the structure which attaches | subjects the code | symbol similar to Embodiment 1, 2, the same or an equivalent part is shown and description is abbreviate | omitted.

  FIG. 11 is a flowchart showing the operation of the negotiation process according to the present embodiment. As shown in FIG. 11, also in this embodiment, the data link layer control unit 103 first performs negotiation for VC0 (S1101). Here, in the negotiation process according to the present embodiment, information included in the InitFC exchanged by the data link layer control unit 103 is different. FIG. 12 shows the DLLP format of InitFC according to the present embodiment.

  As illustrated in FIG. 12, the InitFC according to the present embodiment includes information on a command, a VCID (Virtual Channel IDentification), a buffer area capacity, the number of VC implementations, and a CRC (Cyclic Redundancy Check). In the present embodiment, as shown in FIG. 12, the point is that information on the number of mounted VCs is included in the InitFC packet. That is, the conventional InitFC does not include information on the number of mounted VCs among the pieces of information shown in FIG. The data link control unit 103 generates an InitFC packet. Therefore, the format as shown in FIG. 12 can be realized by improving the data link control unit 103.

  By including information on the number of VC implementations in the InitFC packet, the information transfer circuit 100 and the VGA 200 can recognize the number of VC implementations of the opposite apparatus through the InitFC exchange shown in FIG. As a result, the information transfer circuit 100 and the VGA 200 can enable the VC buffer 20 without the configuration read / write processing. Since the configuration read / write processing is unnecessary, it is not necessary to determine the buffer area of VC0 during the negotiation operation shown in FIG. Therefore, in S403 of FIG. 4, the VC buffer management unit 124 can allocate an unused buffer to the VC buffer 21 of VC0 as well as other VC buffers.

It is a block diagram which shows the hardware constitutions of the information processing apparatus which concerns on embodiment of this invention. It is a block diagram which shows the function structure of I / F which concerns on embodiment of this invention. It is a block diagram which shows the function structure of the transaction layer control part which concerns on embodiment of this invention. It is a flowchart which shows the operation | movement of the initialization process which concerns on embodiment of this invention. It is a figure which shows the aspect of the negotiation process which concerns on embodiment of this invention. It is a flowchart which shows the allocation operation | movement of the unused buffer which concerns on embodiment of this invention. It is a figure which shows the example of the information contained in the buffer allocation information which concerns on embodiment of this invention. It is a figure which shows the expansion aspect of Max Payload Size which concerns on embodiment of this invention. It is a flowchart which shows the operation | movement of the initialization process which concerns on other embodiment of this invention. It is a figure which shows the example of the information which the VC buffer management part which concerns on other embodiment of this invention has memorize | stored. It is a flowchart which shows the operation | movement of the initialization process which concerns on other embodiment of this invention. It is a figure which shows the format of the packet of InitFC which concerns on other embodiment of this invention.

Explanation of symbols

1 Information processing device 10 CPU
20 RAM
21-27 VC buffer 30 Engine 40 HDD
50 ROM
60 NVRAM
70 I / F
80 LCD
DESCRIPTION OF SYMBOLS 90 Operation part 100 Information transfer circuit 101 Controller 102 Transaction layer control part 103 Data link layer control part 104 Physical layer control part 105 Connection part 120 VC controller 121 Information transfer control part 122 VC establishment part 123 Use buffer recognition part 124 VC buffer management part 125 Signal distributor / mixer 200 VGA
201 Controller 202 Transaction Layer Control Unit 203 Data Link Layer Control Unit 204 Physical Layer Control Unit 205 Connection Unit

Claims (16)

An information transfer circuit for realizing a virtual communication bus that is a plurality of virtually independent information communication buses by sharing a single physical serial communication bus with a plurality of virtual communication buffer areas,
A counter buffer number recognition unit for recognizing the number of virtual communication buffer areas included in the counter device connected via the serial communication bus as the counter buffer number;
When the recognized number of counter buffers is smaller than the number of virtual communication buffer areas included in the information transfer circuit, the same number of virtual communications as the number of counter buffers in the virtual communication buffer areas included in the information transfer circuit A use buffer determining unit that determines a buffer area as a use buffer area to be used for the virtual communication bus;
Of the virtual communication buffer area included in the information transfer circuit, an extra buffer area other than the used buffer area is allocated as an area for expanding the information transfer buffer area used when the information transfer circuit performs information transfer. possess a surplus buffer area allocation unit,
A plurality of virtual communication buffer areas included in the information transfer circuit are subjected to a negotiation process for each virtual communication buffer area in a negotiation process with a plurality of virtual communication buffer areas included in the opposite device,
The extra buffer area allocating unit is an area that extends a virtual communication buffer area other than the virtual communication buffer area in which a negotiation process is first executed among a plurality of virtual communication buffer areas included in the information transfer circuit. An information transfer circuit , wherein the extra buffer area is allocated . An information transfer circuit for realizing a virtual communication bus that is a plurality of virtually independent information communication buses by sharing a single physical serial communication bus with a plurality of virtual communication buffer areas,
A counter buffer number recognition unit for recognizing the number of virtual communication buffer areas included in the counter device connected via the serial communication bus as the counter buffer number;
When the recognized number of counter buffers is smaller than the number of virtual communication buffer areas included in the information transfer circuit, the same number of virtual communications as the number of counter buffers in the virtual communication buffer areas included in the information transfer circuit A use buffer determining unit that determines a buffer area as a use buffer area to be used for the virtual communication bus;
Of the virtual communication buffer area included in the information transfer circuit, an extra buffer area other than the used buffer area is allocated as an area for expanding the information transfer buffer area used when the information transfer circuit performs information transfer. An extra buffer area allocation unit;
A negotiation processing unit for performing negotiation processing between a plurality of virtual communication buffer areas included in the information transfer circuit and a plurality of virtual communication buffer areas included in the opposite device;
The negotiation processing unit executes the negotiation processing by transmitting negotiation information including information related to a virtual communication buffer area included in the information transfer circuit,
The negotiation information, characterized in that it comprises a number of information of the virtual communication buffer area included in the information transfer circuit, information transfer circuit. An information transfer circuit for realizing a virtual communication bus that is a plurality of virtually independent information communication buses by sharing a single physical serial communication bus with a plurality of virtual communication buffer areas,
A counter buffer number recognition unit for recognizing the number of virtual communication buffer areas included in the counter device connected via the serial communication bus as the counter buffer number;
When the recognized number of counter buffers is smaller than the number of virtual communication buffer areas included in the information transfer circuit, the same number of virtual communications as the number of counter buffers in the virtual communication buffer areas included in the information transfer circuit A use buffer determining unit that determines a buffer area as a use buffer area to be used for the virtual communication bus;
Of the virtual communication buffer area included in the information transfer circuit, an extra buffer area other than the used buffer area is allocated as an area for expanding the information transfer buffer area used when the information transfer circuit performs information transfer. An extra buffer area allocation unit,
A plurality of virtual communication buffer areas included in the information transfer circuit are subjected to a negotiation process for each virtual communication buffer area in a negotiation process with a plurality of virtual communication buffer areas included in the opposite device,
Among the plurality of virtual communication buffer areas included in the information transfer circuit, further includes a buffer area initialization unit that initializes the virtual communication buffer area in which the negotiation process is first executed after the negotiation process,
The extra buffer area allocation unit is an area that extends a virtual communication buffer area including a virtual communication buffer area in which the negotiation process is first executed among the virtual communication buffer areas used as the used buffer area . and allocating the extra buffer region, information transfer circuit. An information transfer circuit for realizing a virtual communication bus that is a plurality of virtually independent information communication buses by sharing a single physical serial communication bus with a plurality of virtual communication buffer areas,
A counter buffer number recognition unit for recognizing the number of virtual communication buffer areas included in the counter device connected via the serial communication bus as the counter buffer number;
When the recognized number of counter buffers is smaller than the number of virtual communication buffer areas included in the information transfer circuit, the same number of virtual communications as the number of counter buffers in the virtual communication buffer areas included in the information transfer circuit A use buffer determining unit that determines a buffer area as a use buffer area to be used for the virtual communication bus;
Of the virtual communication buffer area included in the information transfer circuit, an extra buffer area other than the used buffer area is allocated as an area for expanding the information transfer buffer area used when the information transfer circuit performs information transfer. An extra buffer area allocation unit,
The extra buffer area allocating unit allocates the extra buffer area as an area for expanding the information transfer buffer area by generating information that associates the extra buffer area with the information transfer buffer area. to, information transfer circuit. An information transfer circuit for realizing a virtual communication bus that is a plurality of virtually independent information communication buses by sharing a single physical serial communication bus with a plurality of virtual communication buffer areas,
A counter buffer number recognition unit for recognizing the number of virtual communication buffer areas included in the counter device connected via the serial communication bus as the counter buffer number;
When the recognized number of counter buffers is smaller than the number of virtual communication buffer areas included in the information transfer circuit, the same number of virtual communications as the number of counter buffers in the virtual communication buffer areas included in the information transfer circuit A use buffer determining unit that determines a buffer area as a use buffer area to be used for the virtual communication bus;
Of the virtual communication buffer area included in the information transfer circuit, an extra buffer area other than the used buffer area is allocated as an area for expanding the information transfer buffer area used when the information transfer circuit performs information transfer. An extra buffer area allocation unit,
The extra buffer area allocation unit, by switching the connection between the extra buffer region and the information transfer buffer area, and allocates the extra buffer region as a region for expanding the information transfer buffer region, information transfer circuit An information transfer circuit for realizing a virtual communication bus that is a plurality of virtually independent information communication buses by sharing a single physical serial communication bus with a plurality of virtual communication buffer areas,
A counter buffer number recognition unit for recognizing the number of virtual communication buffer areas included in the counter device connected via the serial communication bus as the counter buffer number;
When the recognized number of counter buffers is smaller than the number of virtual communication buffer areas included in the information transfer circuit, the same number of virtual communications as the number of counter buffers in the virtual communication buffer areas included in the information transfer circuit A use buffer determining unit that determines a buffer area as a use buffer area to be used for the virtual communication bus;
Of the virtual communication buffer area included in the information transfer circuit, an extra buffer area other than the used buffer area is allocated as an area for expanding the information transfer buffer area used when the information transfer circuit performs information transfer. An extra buffer area allocation unit,
A method information storage unit that stores information about a method of information when the information transfer circuit transfers information to and from the opposite device;
And further comprising a system information update unit for updating the information stored in the system information storage unit in accordance with the assignment result of the extra buffer area by the extra buffer allocation unit, information transfer circuit. The scheme information includes capacity information related to information capacity that can be included in one packet,
The information transfer circuit according to claim 6 , wherein the method information update unit updates the capacity information . The extra buffer area allocation unit allocates the extra buffer area as an area that extends at least one of the used buffer area or a retry buffer area used for retry when the information transfer circuit executes information transfer,
The method information update unit may include information that can be included in the one packet when the extra buffer area allocation unit allocates the extra buffer area as an area that extends both the used buffer area and the retry buffer area. The information transfer circuit according to claim 7 , wherein the capacity information is updated so as to increase a capacity . 9. The information transfer circuit according to claim 1, wherein the extra buffer area allocation unit allocates the extra buffer area as an area for expanding the used buffer area . 10. The extra buffer area allocating section allocates the extra buffer area as an area that extends a buffer area used for retry when the information transfer circuit executes information transfer . 2. The information transfer circuit according to item 1 . The extra buffer area allocation unit is characterized dynamically allocating the extra buffer region in response to the execution of the information transfer by said information transfer circuit, information transfer circuit according to any one of claims 1 to 10 . An information processing apparatus comprising the information transfer circuit according to claim 1.   An information transfer circuit control method for realizing a virtual communication bus that is a plurality of virtually independent information communication buses by sharing a single physical serial communication bus with a plurality of virtual communication buffer areas,
  Recognizing the number of virtual communication buffer areas included in the opposite device connected via the serial communication bus as the number of opposite buffers,
  When the recognized number of counter buffers is smaller than the number of virtual communication buffer areas included in the information transfer circuit, the same number of virtual communications as the number of counter buffers in the virtual communication buffer areas included in the information transfer circuit A buffer area for use as a buffer area to be used for the virtual communication bus,
  By generating information associating the information transfer buffer area with an extra buffer area other than the used buffer area in the virtual communication buffer area included in the information transfer circuit, the information transfer circuit A method for controlling an information transfer circuit, wherein an information transfer buffer area used for executing information transfer is allocated as an area for expansion. An information transfer circuit control method for realizing a virtual communication bus that is a plurality of virtually independent information communication buses by sharing a single physical serial communication bus with a plurality of virtual communication buffer areas,
Recognizing the number of virtual communication buffer areas included in the opposite device connected via the serial communication bus as the number of opposite buffers,
When the recognized number of counter buffers is smaller than the number of virtual communication buffer areas included in the information transfer circuit, the same number of virtual communications as the number of counter buffers in the virtual communication buffer areas included in the information transfer circuit A buffer area for use as a buffer area to be used for the virtual communication bus,
Of the buffer area for virtual communication included in the information transfer circuit, an extra buffer area other than the used buffer area is allocated as an area for expanding the information transfer buffer area used when the information transfer circuit performs information transfer ,
Information stored in a method information storage unit that stores information on a method of information when the information transfer circuit transfers information to and from the opposite device is stored in the extra buffer area by the extra buffer allocation unit. A method for controlling an information transfer circuit, wherein the information transfer circuit is updated according to a result of assignment of the information transfer circuit. 15. A control program for causing an information processing apparatus to execute the information transfer circuit control method according to claim 13 or 14.   16. A storage medium storing the control program according to claim 15 in a format readable by an information processing apparatus.

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