JP5073624B2 - Method for growing zinc oxide based semiconductor and method for manufacturing semiconductor light emitting device - Google Patents

Description

  The present invention relates to a method for growing a zinc oxide based semiconductor and a method for manufacturing a semiconductor element, and more particularly to a method for growing a zinc oxide based semiconductor layer by MOCVD and a method for manufacturing a semiconductor light emitting element using the same.

  Zinc oxide (ZnO) is a direct transition type semiconductor having a band gap energy of 3.37 eV at room temperature, and is expected as a material for optical elements in the blue or ultraviolet region. In particular, the exciton binding energy is 60 meV and the refractive index n = 2.0, which is very suitable for a semiconductor light emitting device. Further, the present invention can be widely applied not only to light emitting elements and light receiving elements but also to surface acoustic wave (SAW) devices, piezoelectric elements, and the like. In addition, the raw material is inexpensive and harmless to the environment and the human body.

  In general, MOCVD (Metal Organic Chemical Vapor Deposition) method, MBE (Molecular Beam Epitaxy) method, and the like are used as crystal growth methods for zinc oxide compound semiconductors. The MBE method is a crystal growth method under an ultra-high vacuum, and has problems such as expensive equipment and low productivity. On the other hand, the MOCVD method has the advantages that the apparatus is relatively inexpensive, allows large area growth and simultaneous growth of a large number of sheets, has high throughput, and is excellent in mass productivity and cost. .

  As a crystal growth method of zinc oxide using the MBE method, for example, a low-temperature ZnO layer having a single crystal characteristic is grown on a sapphire substrate, and then flattened by heat treatment at a high temperature, and then a high-temperature ZnO layer is grown. A method for obtaining a ZnO layer with good crystallinity is disclosed (Patent Document 1). More specifically, a low-temperature grown ZnO single crystal layer formed by using a growth temperature lower than the crystal growth temperature for growing a ZnO single crystal is disclosed. However, the method disclosed in this document is a growth condition / method effective only for the MBE method, and such a method cannot be applied to the MOCVD method. That is, as is well known (for example, Patent Document 2), the growth conditions of the MBE method capable of crystal growth under non-stoichiometric (non-stoichiometric composition) conditions cannot be directly applied to the MOCVD method. Therefore, a method for growing a single crystal layer of a zinc oxide based semiconductor using MOCVD has been actively studied.

Various methods for crystal growth of zinc oxide (ZnO) or a zinc oxide based semiconductor on a different material substrate such as sapphire (Al ₂ O ₃ ) by MOCVD have been disclosed so far (for example, Patent Documents 2 and 3). . For example, in Patent Document 2, MgZnO microcrystals are formed on an A-plane sapphire substrate or C-plane silicon carbide substrate using O ₂ as an oxygen source as a reserve buffer layer, and the microcrystal serves as a seed crystal to serve as a buffer layer body. It is disclosed that an MgZnO crystal is formed on the entire surface of a substrate. Patent Document 3 discloses that a polycrystalline or amorphous laminate formed at a low temperature is annealed at a high temperature to form a buffer layer. However, in such a method, a defect remains between adjacent crystal grain boundaries when the polycrystal is converted into a single crystal by heat treatment. In addition, defects remain in the grain boundary coalescence at the stage where the buffer layer main body grows crystallites. Therefore, it is difficult to greatly reduce crystal defects. Thus, conventionally, attempts have been made to improve the crystallinity by forming a buffer layer made of polycrystal, microcrystal, or amorphous. However, the method for improving the crystallinity by MOCVD is complicated, and it is difficult to remove the crystal on the substrate. It was difficult to grow high quality ZnO-based crystals.

  As described above, although many methods for growing a ZnO-based single crystal on a sapphire substrate or the like by the MOCVD method have been proposed, there are many problems as a method for growing a simple and high-quality ZnO-based single crystal.

  In addition, in the case of MOCVD, when grown in an environment where crystallinity is improved (about 600 ° C. or higher), it tends to become (hexagonal) columnar crystals, network crystals, and (hexagonal) disk-like crystals oriented in the c-axis direction. There is. In such a polycrystal or imperfect single crystal that is strongly oriented in the crystal axis direction, the grain interface and transition cause leakage current and local current concentration of the semiconductor element, leading to deterioration of element characteristics and element life. In particular, in a semiconductor light emitting device, characteristics such as light emission efficiency and device life are deteriorated due to leakage current and current concentration. Furthermore, when the crystal surface is not flat, it leads to a decrease in process accuracy and a manufacturing yield in a semiconductor process such as lithography and etching. In addition, the production yield is reduced in cleavage and braking.

Thus, conventionally, it has been difficult to grow a flat ZnO-based semiconductor single crystal with few grain interfaces and transitions on a heterogeneous substrate such as a sapphire substrate by MOCVD. In order to achieve high performance and high reliability of a semiconductor device, particularly a semiconductor light emitting device having a large operating current density, it is extremely important to develop a crystal growth method with few crystal defects and close to a flat ideal crystal.
Japanese Patent No. 3424814 JP 2005-340370 A Japanese Patent No. 3859148

  The present invention has been made in view of the above-described points, and an object of the present invention is to provide a method for growing a zinc oxide based semiconductor crystal having few single crystal defects and excellent single crystallinity and flatness on a substrate. is there. Another object of the present invention is to provide a high-performance and high-reliability semiconductor device, particularly a high-performance semiconductor light-emitting device excellent in light emission efficiency and device lifetime. It is another object of the present invention to provide a semiconductor light emitting device with a high manufacturing yield and excellent mass productivity.

  The present invention is a method for crystal growth of a zinc oxide based semiconductor layer on a substrate by MOCVD, using an organic metal compound not containing oxygen and water vapor, (a) at a low growth temperature and within a range of 1 kPa to 30 kPa. Performing a crystal growth at a low growth pressure to form a first single crystal layer; and (b) performing a crystal growth at a high growth temperature and a pressure higher than the low growth pressure to form the first single crystal layer on the first single crystal layer. And a step of forming a second single crystal layer.

  The present invention also relates to a method of manufacturing a semiconductor light emitting device by laminating a zinc oxide based semiconductor layer on a substrate by MOCVD, using an organometallic compound not containing oxygen and water vapor, (a) a low growth temperature And a step of crystal growth at a low growth pressure within a range of 1 kPa to 30 kPa to form a first single crystal layer; and (b) a crystal growth at a high growth temperature and a pressure higher than the low growth pressure. Forming a second single crystal layer on the first single crystal layer; and (c) performing crystal growth at a high growth temperature and a pressure higher than the low growth pressure to form the second single crystal layer on the second single crystal layer. And a step of forming a light emitting layer.

  The low growth temperature can be a temperature in the range of 250 ° C to 450 ° C.

  The high growth temperature can be set to a temperature in the range of 700 ° C to 850 ° C.

  Moreover, the pressure higher than the said low growth pressure can be made into the pressure in the range of 40 kPa-120 kPa.

  Hereinafter, a method for growing a zinc oxide-based semiconductor crystal layer having excellent single crystallinity and flatness on a substrate by MOCVD will be described in detail with reference to the drawings. Further, a semiconductor light emitting element (LED: Light Emitting Diode) will be described as an example of the semiconductor element formed by the growth method.

  The “low growth temperature” defined in the present specification is, for example, about 200 ° C. to 650 ° C., generally 50 ° C. to 500 ° C. than the temperature of crystal growth for growing a ZnO single crystal. This is a low temperature. The “high growth temperature” is generally a growth temperature suitable for growing a ZnO single crystal, and is a temperature higher than the above “low growth temperature” and about 850 ° C. or less.

FIG. 1 is a cross-sectional view showing a zinc oxide based semiconductor crystal layer (hereinafter referred to as a ZnO based semiconductor layer) grown on a substrate 10 according to the present invention. More specifically, the ZnO layer 11 and the ZnO-based semiconductor layer 12 are grown on the sapphire substrate using MOCVD. In the following, a case where Mg _x Zn _{(1-x) 2} O (0 ≦ x ≦ 0.68) is grown as the ZnO-based semiconductor layer 12 will be described as an example.

  In the following, the ZnO-based semiconductor may be another compound crystal based on ZnO. For example, a ZnO-based compound crystal in which a part of Zn (zinc) is replaced with calcium (Ca) may be used. Alternatively, a ZnO-based compound crystal in which part of O (oxygen) is replaced with selenium (Se), sulfur (S), tellurium (Te), or the like may be used.

  An MOCVD apparatus (not shown) used for crystal growth has a reaction vessel (chamber), and in the reaction vessel, a susceptor that holds the substrate 10, a heater that heats the susceptor, and a shower head that blows material gas onto the substrate. Is provided. Further, a pressure adjusting device for adjusting the exhaust pump and the pressure in the container is provided.

As the substrate 10, an α-sapphire single crystal sapphire (Al ₂ O ₃ ) substrate having a corundum structure is used. In the present embodiment, the ZnO layer 11 is grown on the sapphire A plane using the sapphire A plane ({11-20} plane) as a crystal growth plane. Hereinafter, a substrate having a sapphire A plane ({11-20} plane) as a principal plane (crystal growth plane) is also referred to as an A-plane sapphire substrate. Here, the Miller index {} indicates a representative value of an equivalent surface.

  In this example, a material containing no oxygen was used as the organometallic compound material (or organometallic material). That is, a material that does not contain oxygen atoms in its constituent molecules and a material that does not contain oxygen molecules were used.

More specifically, DMZn (dimethylzinc) was used as the zinc (Zn) source, Cp2Mg (biscyclopentadienylmagnesium) was used as the magnesium (Mg) source, and TEGa (triethylgallium) was used as the gallium (Ga) source. In addition to the above materials, DEZn (diethyl zinc), TMGa (trimethyl gallium), or the like can be used. An organometallic material that does not contain oxygen is easily pyrolyzed at a low temperature, and reacts with O ₂ (oxygen) or H ₂ O (water vapor) even at room temperature, which is suitable for crystal growth at a low temperature.

H ₂ O (water vapor) was used as a liquid material as an oxygen source. H ₂ O is suitable for low-temperature growth of ZnO crystals because it has high reactivity with an organometallic material that does not contain oxygen in the molecule even at room temperature. Further, the H ₂ O molecule has a large polarization in the molecule, and has two lone electron pairs, and is excellent in the adsorption ability to the crystal surface and the like.

TMGa (trimethylgallium) was used as the n-type impurity source, and NH ₃ (ammonia) gas was used as the p-type impurity source. Note that these gases may be diluted with an inert gas such as nitrogen or Ar (argon).

  Further, nitrogen was used as a transport (carrier) gas. Liquid or solid material vapor and gaseous material (hereinafter referred to as material gas) are fed into the showerhead by the carrier gas and supplied to the substrate.

  FIG. 2 shows a crystal growth sequence used for crystal growth by the MOCVD method. First, the A-plane sapphire substrate 10 was set on the susceptor in the MOCVD apparatus, and the reaction vessel pressure was adjusted to 10 kPa (kilopascal) (time T = T1).

Next, supply of H ₂ O (water vapor) as an oxygen source from the shower head to the substrate 10 at a flow rate of 640 μmol / min was started (T = T2). The substrate 10 was heated from room temperature (RT) to 900 ° C. with a heater, and the substrate 10 was degassed for 10 minutes (T = T3 to T4). Thereafter, H ₂ O (water vapor) was kept flowing at the same flow rate until the growth was completed.

After the degassing treatment, the substrate temperature was lowered to 400 ° C., and DMZn (dimethylzinc) as a zinc raw material was supplied to the substrate 10 at a flow rate of 1 μmol / min for about 15 minutes (T = T5 to T6: Growth period of the ZnO layer 11) , Period G1A in FIG. At this time, the water vapor flow rate and the flow rate ratio of the organic metal (DMZn) (F _H2O / F _DMZn ratio), so-called VI / II ratio, is 640.

  Thus, a ZnO layer (low temperature growth single crystal layer, hereinafter referred to as a growth temperature (Tg) of 400 ° C. under a reduced pressure growth condition (growth pressure Pg = 10 kPa), a growth rate of 1.7 nm / min, and a layer thickness of 25 nm. Simply referred to as a first single crystal layer).

  After the growth of the ZnO layer 11, the substrate temperature was raised to 800 ° C. and heat treatment (annealing) was performed for 10 minutes (T = T7 to T8). As will be described later, the crystallinity and flatness of the ZnO layer 11 were further improved by this heat treatment.

After the heat treatment (annealing) was completed, the ZnO-based semiconductor layer 12 was grown at a higher temperature and higher pressure than in the case of the ZnO layer (low temperature growth single crystal layer) 11. The reaction vessel pressure was increased from 10 kPa to 80 kPa. After the substrate temperature was stabilized, DMZn was supplied from the shower head onto the ZnO layer 11 at a flow rate of 10 μmol / min (T = T9 to T10: growth period of the ZnO-based semiconductor layer 12, period G2 in FIG. 2). The flow rate ratio _(F H2O _/ F _MO ratio) of water vapor flow rate and organometallic this time (DMZn), so-called VI / II ratio is 64. DMZn was supplied to the substrate 10 for about 60 minutes to form a ZnO-based semiconductor layer (ZnO layer) 12 having a layer thickness of about 1 μm.

  Note that the waiting time until the substrate temperature is stabilized before the growth of the ZnO-based semiconductor layer 12 can also be used as the heat treatment of the ZnO layer 11.

Thus, a ZnO-based semiconductor having a growth temperature (Tg) of a high growth temperature (800 ° C.) at a pressure (80 kPa) higher than the growth pressure of the ZnO layer 11, a growth rate of 17 nm / min, and a layer thickness of about 1 μm. Layer 12 (a high-temperature grown single crystal layer, hereinafter also simply referred to as a second single crystal layer) was formed. In this embodiment, the case where ZnO is grown as the ZnO-based semiconductor layer 12 will be described as an example, but the present invention is not limited to this. In addition to DMZn, for example, Mg _x Zn _(1-x) O crystal that is a ternary crystal is grown by using Cp2Mg (biscyclopentadienylmagnesium) that is an organometallic compound that does not contain an oxygen atom. be able to.

  After the growth of the ZnO-based semiconductor layer 12 was completed, it was cooled while flowing water vapor. After the substrate temperature became 300 ° C. or lower, the supply of water vapor was stopped (T = T11).

As described above, a substrate with a crystal growth layer (hereinafter simply referred to as growth) on which a ZnO layer (first single crystal layer) 11 and a ZnO-based semiconductor layer (second single crystal layer) 12 are grown on a substrate. 15) was manufactured.
[Crystallinity of ZnO layer (low-temperature grown single crystal layer, first single crystal layer) 11]
The ZnO layer 11 obtained by the above-described growth step (T = T5 to T6) is a single crystal layer that is c-axis oriented on an A-plane ({11-20} plane) sapphire substrate. That is, a {0001} plane of zinc oxide is laminated on a substrate having a {11-20} plane of α-sapphire single crystal as a main surface. The single crystallinity and flatness of the ZnO layer 11 were examined by RHEED (reflection high-energy electron diffraction) and AFM (atomic force microscope) measurements.

FIG. 3A is a diagram showing an RHEED diffraction image of the grown ZnO layer 11 when heat treatment (annealing) is not performed after the growth step (T = T5 to T6) is completed. As shown in FIG. 3A, streak-like RHEED diffraction images arranged at equal intervals were obtained. This shows that the surface crystal arrangement is single and smooth. Further, it was found by RFM (atomic force microscope) measurement that Rms (root mean square roughness) of 1 μm ² area was 0.62 nm (nanometer). Since the c-axis length (lattice constant) of the ZnO crystal was c = 5.207 Å, the surface roughness was equivalent to the c-axis length of the ZnO crystal, and it was found that the crystal layer surface was flat. From these results, it was confirmed that the ZnO layer 11 was a single crystal layer with good flatness.

FIG. 3B shows an RHEED diffraction image when the ZnO layer 11 is grown and then subjected to a heat treatment at a temperature of 800 ° C. for 3 minutes. In this example, the pressure Pa during the heat treatment was set to a low pressure (the same as in crystal growth, Pa = Pg = 10 kPa). Further, as described above, heat treatment was performed while supplying H ₂ O (water vapor) to the substrate 10, that is, in a water vapor atmosphere.

  As shown in FIG. 3 (b), it was confirmed that the RHEED diffraction image was more clearly streaked by the heat treatment than when the heat treatment was not performed (FIG. 3 (a)). . In addition, in AFM measurement, it was found that Rms (root mean square roughness) was 0.5 nm or less, which was less than the c-axis length of the ZnO crystal. Therefore, it was confirmed that the single crystallinity and flatness were improved by the heat treatment. That is, the first single crystal layer 11 is a single crystal layer grown at a low temperature, which is a thin film but flat at the sub-nano level.

  Thus, the ZnO layer 11 already has good flatness and a single crystal layer at the stage where crystal growth is completed, and further improves the single crystallinity by heat treatment, and is equal to or less than the c-axis length of the ZnO crystal. It was confirmed to have a flatness of

Note that the case where a ZnO layer is grown as the first single crystal layer 11 has been described as an example, but other compound crystals based on ZnO may be used.
[Growth conditions for low-temperature grown single crystal layer (first single crystal layer) 11]
In this example, an A-plane sapphire substrate which is the {11-20} plane of α sapphire (α-Al ₂ O ₃ ) is used as the substrate 10, DMZ is used as the organometallic compound material not containing oxygen, and the growth temperature is set. The case where the ZnO layer (first single crystal layer) 11 is grown at 400 ° C. and a growth pressure of 10 kPa has been described as an example. Further, the case where the growth rate is 1.7 nm / min and the growth layer thickness is 25 nm has been described as an example.

However, the conditions such as the substrate, the material gas, the growth temperature, the growth pressure, the growth rate, the growth layer thickness and the like shown in the above embodiments are merely examples, and are not limited thereto. The growth conditions including the heat treatment conditions were changed, the ZnO layer 11 was grown, and the conditions for growing a single crystal layer with high flatness were examined. Hereinafter, the growth conditions of the ZnO layer (first single crystal layer) 11 will be described in detail.
<Board>
An A-plane sapphire substrate is optimal. This is because the lattice mismatch between the A plane of the sapphire crystal and the C plane of the ZnO crystal is small. That is, the lattice mismatch between the sapphire <0001> direction (oxygen atom) and the ZnO <11-20> direction (zinc atom) is 0.07%, and the sapphire <10-10> direction (oxygen atom) and ZnO <10- The lattice mismatch in the 10> direction (zinc atom) is 2.46%. Here, since the ZnO <11-20> direction is locked to the sapphire <0001> direction, the ZnO crystal can grow a single crystal without forming a 30 ° rotation domain during growth.

In addition, as a usable substrate, in the case of a ZnO crystal with c-axis orientation on the substrate surface, the substrate surface has lattice matching points at rotationally symmetric positions of 60 °, 120 °, and 180 °. Any crystal substrate may be used. Further, in the case of an a-axis or m-axis oriented ZnO crystal, any crystal substrate in which a lattice matching point exists at a rotationally symmetric position of 180 ° may be used. For example, an R-plane sapphire substrate, an M-plane sapphire substrate, a SiC (silicon carbide) substrate, a GaN (gallium nitride) substrate, a Ga ₂ O ₃ (gallium oxide) substrate, a Si (silicon) substrate, or the like can be used.
<Growth temperature>
It is appropriate that the growth temperature is generally lower than a crystal growth temperature (referred to as “high growth temperature”) for growing a ZnO single crystal (referred to as “low growth temperature”). This is because at the high growth temperature, island-like growth is easy and layered single crystals are hardly formed.

More specifically, the growth temperature is preferably in the range of 250 ° C to 450 ° C. Furthermore, it is more preferable that it exists in the temperature range of 300 to 400 degreeC. At 250 ° C. or lower, the migration length becomes short, so that it becomes easy to be amorphous or polycrystallized. Further, as described above, when the temperature is higher than 450 ° C., island-shaped growth is likely to occur, and flatness is likely to be lowered (Rms value is increased).
<Growth pressure>
For single crystal growth, the migration length of reactive chemical species (DMZn, H ₂ O, intermediate products, Zn atoms before crystallization, O atoms before crystallization, etc.) on the substrate surface should be large. . Therefore, the reduced pressure growth is suitable, and specifically, the growth pressure is preferably 1 kPa to 30 kPa, more preferably 5 kPa to 20 kPa. When the growth pressure is 1 kPa or less, the growth rate is remarkably slowed.
<Material gas>
In order to form a ZnO single crystal layer under a low growth pressure and a low growth temperature, it is necessary to select a material having high mutual reactivity. This is because if the mutual reactivity is low, the crystal does not grow, or becomes amorphous or polycrystallized. As the Zn source, an organometallic compound that does not contain oxygen in the constituent molecules and has high reactivity with the oxygen source material is suitable. In addition to the DMZn described above, for example, there is DEZn (diethyl zinc). As the oxygen source, H ₂ O (water vapor) having a large intramolecular polarization and high reactivity with the organometallic compound material is suitable.
<Growth rate>
The growth rate is preferably in the range of 0.4 nm / min to 9 nm / min. Furthermore, it is more preferable to be within the range of 0.8 nm / min to 4 nm / min. When the growth rate is 9 nm / min or more, the surface irregularities become large, and sufficient flatness may not be obtained.
<Growth layer thickness>
The growth layer thickness is preferably in the range of 5 nm to 60 nm, and preferably in the range of 10 nm to 40 nm. Furthermore, it is more preferably 15 nm to 30 nm. That is, when the layer thickness is less than 5 nm, the crystal layer may not sufficiently cover the substrate surface. On the other hand, when the thickness is 60 nm or more, the unevenness of the surface becomes large and sufficient flatness may not be obtained.
<VI / II ratio (F _H2O / F _MO ratio)>
The water vapor flow rate and the organometallic (DMZn) flow rate ratio (F _H2O / F _DMZn ratio) may be about 2 or more. Specifically, about 2000 is sufficient. The water vapor flow rate is preferably about 70% of the saturated water vapor amount in which water vapor does not aggregate in the shower head.
<Heat treatment conditions>
As described above, the ZnO layer 11 already has good flatness and single crystal layer at the stage where crystal growth is completed. However, the single crystallinity and flatness can be further improved by performing heat treatment. it can. Further, it is preferable to perform the heat treatment under a low pressure where the migration length becomes long. Note that the pressure range suitable for the heat treatment is the same as the growth pressure range of the ZnO layer 11.

Specifically, the heat treatment temperature of the grown ZnO layer 11 is suitably 700 ° C. to 1100 ° C. The processing time is suitably in the range of 1 to 60 minutes. More preferably, the treatment temperature is 800 ° C. to 1000 ° C., and the treatment time is 3 minutes to 10 minutes. If the treatment temperature is less than 700 ° C., the effect is low, and if it is 1100 ° C. or more, the layer surface becomes rough. In addition, when the processing time is 60 minutes or more, film defects may occur due to film evaporation.
[Growth conditions of ZnO-based semiconductor layer (high temperature grown single crystal layer, second single crystal layer) 12]
Using conditions under which growth is performed in a two-dimensional crystal growth mode (lateral growth mode) on a ZnO layer (first single crystal layer) 11 that is flat at the sub-nano level and has excellent single crystallinity, ZnO A system semiconductor layer (second single crystal layer) 12 is grown.

Here, in this embodiment, an organic metal compound material (DMZn) not containing oxygen and water vapor are used on the ZnO layer 11 to achieve high temperature growth (800 ° C.), and the growth pressure is higher than the growth pressure of the ZnO layer 11. As an example, the case where the Mg _x Zn _(1-x) 2 O crystal layer (second crystal layer) 12 is grown on the ZnO layer 11 is described as an example. Further, the case where the growth rate is 17 nm / min and the growth layer thickness is 1 μm has been described as an example.

However, the growth conditions of the ZnO-based semiconductor layer 12 on the ZnO layer 11 shown in the above embodiment are merely examples, and are not limited to these. The growth conditions were changed to grow a ZnO-based semiconductor layer, and the conditions for growing the ZnO-based semiconductor layer 12 excellent in flatness and single crystal were examined. As a result, it was found that the above-described ZnO layer 11 has a slight degree of crystallinity fluctuation, but there are optimum conditions for crystal growth on the ZnO layer 11. Hereinafter, the growth conditions when the ZnO-based semiconductor layer (second single crystal layer) 12 is grown on the ZnO layer (first single crystal layer) 11 will be described in detail.
<Growth pressure>
The relationship between the growth pressure and the crystallinity and flatness of the growth layer was evaluated. From the full width at half maximum (FWHM) (FIG. 4) of the X-ray diffraction (10-10) ω rocking curve of the ZnO layer (second single crystal layer) 12 when the growth layer thickness (TH) is 0.125 μm, the growth pressure It has been found that the crystallinity is improved by increasing the value. It was also found that when the growth pressure is increased, lateral growth (two-dimensional growth mode) is promoted, and the plane (C plane) perpendicular to the c-axis is flattened. It has been found that a high growth pressure is desirable to obtain a flat crystal growth surface with good crystallinity and no irregularities or pits on the surface of the ZnO-based semiconductor layer (second single crystal layer). Specifically, the growth pressure is preferably 40 kPa or more. Moreover, 60 kPa or more is preferable and it is further more preferable that it is 80 kPa or more. As an upper limit, about 120 kPa is appropriate. This upper limit value is an upper limit value of the airtightness of the MOCVD apparatus and is not a film forming condition.
<Growth temperature>
The relationship between the growth temperature and the crystallinity and flatness of the growth layer was evaluated. When the growth layer thickness (TH) is 0.125 μm, the full width at half maximum (FWHM) of the X-ray diffraction (10-10) ω rocking curve of the ZnO layer 12 becomes narrower as the growth temperature becomes higher (FIG. 5). It has been found that the flatness is improved as the density is reduced and the crystallinity is improved. Specifically, 700 ° C. or higher at which a flat surface is formed in the c-axis direction is preferable. The upper limit is about 850 ° C. where growth becomes difficult with H ₂ O (water vapor). A temperature range of 740 ° C. to 810 ° C. is preferable, and 780 ° C. to 810 ° C. is most preferable.
<Growth layer thickness>
The relationship between the growth layer thickness and the crystallinity and flatness of the growth layer was evaluated. FIG. 6 is a diagram showing the half width (FWHM) of the X-ray diffraction (0002) ω rocking curve of the growth layer with respect to the growth layer thickness. The ZnO-based semiconductor layer (second single-crystal layer) 12 formed on the ZnO layer (first single-crystal layer) 11 first grows in an island shape, and the single-crystal islands merge with time to form a layered ZnO-based layer. It becomes a semiconductor layer.

  FIG. 7 shows scanning electron microscope (SEM) images of the growth layer surface of the ZnO layer 12 when the growth pressure (Pg) is 10 kPa (FIG. 7A) and 80 kPa (FIG. 7B), respectively. ing. The growth layer thickness is 1.0 μm. It can be seen that when crystal growth is performed at a growth pressure of 80 kPa, a crystal layer with good surface morphology and excellent flatness is obtained. Moreover, it was found from the X-ray diffraction rocking curve and electron microscope (SEM) evaluation that a layer thickness of 1.5 μm or more is more preferable in order to obtain a crystal plane having extremely good single crystallinity and flatness.

In order to grow a thick film on the order of microns required for manufacturing the device, a method of proceeding in the direction of improving the crystallinity in the thickening process is preferable. In this regard, from FIGS. 6 and 7, the present invention is an excellent two-dimensional mode crystal growth method in which both crystallinity and flatness are improved in the thickening process.
<Growth rate>
The growth rate is preferably in the range of 5 nm / min to 60 nm / min. When the growth rate is 60 nm / min or more, abnormal growth tends to occur.
<Crystal composition>
As the ZnO-based semiconductor layer 12, for example, Mg _x Zn _{(1-x) 2} O (0 ≦ x ≦ 0.43) crystal can be used. However, as the Mg composition x increases, the lattice constant difference in the a-axis direction increases and the defect density of the deposited semiconductor crystal layer increases. Therefore, the range of 0 ≦ x ≦ 0.3 is more preferable.

Further, as described above, the ZnO-based semiconductor layer 12 may be another compound crystal based on ZnO. For example, a ZnO-based compound crystal in which a part of Zn (zinc) is replaced by Ca may be used, or a ZnO-based compound crystal in which a part of O (oxygen) is replaced by Se, S, Te, or the like. There may be.
<Material gas>
Growth at a high temperature makes it possible to obtain a high-quality ZnO crystal by sufficiently obtaining the migration length of the reactive chemical species on the crystal growth surface. On the other hand, it becomes difficult for the gaseous material to be an oxygen source to adhere to the substrate surface, and growth is hindered. As the oxygen source, H ₂ O (water vapor) that has a large polarization in the molecule and is adsorbed on the substrate surface even at a high temperature is suitable.

As the Zn source, an organometallic compound that does not contain oxygen and has high reactivity with the oxygen source material is suitable. In addition to the DMZn described above, for example, there is DEZn (diethyl zinc). As the Mg source, there is Cp2Mg (biscyclopentadienylmagnesium).
<How to start growth>
FIG. 8 schematically shows a method for starting the growth of the ZnO-based semiconductor layer 12. FIG. 8A shows a case where the growth is performed with the DMZn flow rate F _DMZn kept constant from the growth start point (FIG. 2, T = T9) to the growth end point (FIG. 2, T = T10). . The case where the DMZn flow rate is 10 μmol / min is shown as an example.

  FIG. 8B shows a case where growth is performed by increasing the DMZn flow rate to 10 μmol / min stepwise. Specifically, a ZnO-based semiconductor layer having a layer thickness of about 1 μm (same as shown in FIG. 8A) is set at 5 μm at 3 μmol / min, 5 minutes at 6 μmol / min, and finally 10 μmol / min. ZnO layer) 12 is formed.

FIG. 8C shows a case where the DMZn flow rate is linearly increased to 10 μmol / min in 10 minutes from the start of growth, and then growth is performed at a constant flow rate. Also in this case, the ZnO-based semiconductor layer (ZnO layer) 12 having a layer thickness of about 1 μm is formed. When crystal growth of Mg _x Zn _{(1-x) 2} O 3 or the like is performed, the flow rate of the organometallic gas (Cp 2 Mg or the like) may be changed similarly to the flow rate of DMZn.

By performing the growth by increasing the DMZn flow rate stepwise or linearly at the start of growth, the density of island crystals in the initial growth stage of the ZnO-based semiconductor layer 12 can be reduced. As a result, there is an effect that the flattened thick film of the growth layer can be thinned (for example, 1.5 μm or less).
<Dopant>
To adjust the conductivity type (n-type) of the ZnO-based semiconductor layer 12, any one of TMGa (trimethylgallium), TEGa (triethylgallium), TMAl (trimethylaluminum), TMIn (trimethylindium), and TEIn (triethylindium) is used. What is necessary is just to add more than a kind. However, if it is added before the island-like crystals are combined and the crystal plane (C plane) in the c-axis vertical direction is flattened, the flattening may be hindered. It is preferred that Specifically, it is more preferable to add it after the layer thickness of 1.0 μm. That is, the ZnO-based semiconductor layer 12 is preferably an undoped layer having a layer thickness of at least 1.0 μm.

  As described above in detail, if the above growth conditions are used, ZnO having high flatness and crystallinity is formed on the first single crystal layer 11 which is a thin film but excellent in flatness and single crystallinity. The system semiconductor layer 12 can be grown. That is, the ZnO-based semiconductor layer (second single crystal layer) 12 can be grown so as to have a layer thickness sufficient for application to element manufacturing while having higher flatness and crystallinity. It can be widely applied to device manufacturing. For example, a light emitting layer (active layer), an LED light emitting operation layer, a cladding layer in a semiconductor laser element, or an element operation layer such as an electronic device can be directly grown on the ZnO-based semiconductor layer 12. Alternatively, the ZnO-based semiconductor layer 12 grown under the above-described growth conditions may be grown as a part of the LED light emitting operation layer, the cladding layer, or the element operation layer.

Here, in this specification, an operation layer or an element operation layer refers to a layer composed of a semiconductor to be included in order for a semiconductor element to perform its function. For example, a simple transistor includes a structural layer formed by a pn junction of an n-type semiconductor, a p-type semiconductor, and an n-type semiconductor (or a p-type semiconductor, an n-type semiconductor, and a p-type semiconductor). Note that a semiconductor layer that includes a p-type semiconductor layer, a light-emitting layer, and an n-type semiconductor layer (or a p-type semiconductor layer and an n-type semiconductor layer) and emits light by recombination of injected carriers, particularly, emits light. This is called the operation layer.
[Growth layered substrate 15]
The substrate with a growth layer 15 obtained by the above process can be used for the manufacture of semiconductor elements in the MOCVD apparatus without cooling. Alternatively, after cooling, a semiconductor element can be manufactured using an MOCVD apparatus or another crystal growth apparatus.

  That is, if the substrate with growth layer 15 is used, a single crystal is grown directly on the single crystal layer (ZnO-based semiconductor layer 12) having excellent single crystallinity and flatness using an MOCVD apparatus or another crystal growth apparatus. Can be done. Therefore, a high-quality ZnO-based semiconductor layer having few crystal defects and excellent single crystallinity and flatness can be formed.

  Further, using the substrate 15 with a growth layer, optical semiconductor elements, various electronic devices, and the like are formed by various methods other than MOCVD, such as MBE, plasma CVD, PLD (Pulsed Laser Deposition), and hydride VPE. It is also possible.

  As described above, according to the present invention, a growth in which a high-quality single crystal layer with few crystal defects, excellent single crystal properties and flatness, which can be applied to manufacture of optical semiconductor elements and various electronic devices is formed. A layered substrate can be provided.

  FIG. 9 shows a cross-sectional view of a semiconductor light emitting device structure grown on a substrate 10 according to the present invention. More specifically, the n-type ZnO-based semiconductor layer 21, the ZnO-based semiconductor active layer 22, and the p-type ZnO-based semiconductor are formed on the substrate 15 with the growth layer on which the ZnO layer 11 and the ZnO-based semiconductor layer 12 are formed according to the above-described embodiment. A light emitting operation layer (hereinafter also referred to as an LED operation layer) 20 composed of the layer 23 was formed. The crystal growth conditions of the LED operation layer 20 were the same as the growth conditions of the ZnO-based semiconductor layer 12 unless otherwise specified below. That is, the crystal growth sequence is the same as that shown in FIG. 2, and the same growth temperature, growth pressure, material gas, etc. as the period (G2) from T = T9 to T10 are used. An n-type ZnO-based semiconductor layer 21, a ZnO-based semiconductor active layer 22, and a p-type ZnO-based semiconductor layer 23 were sequentially grown. The growth conditions such as the growth temperature and the growth pressure of the LED operation layer 20 do not necessarily have to be the same as the growth conditions of the ZnO-based semiconductor layer 12. That is, the crystal growth conditions of the LED operation layer 20 are preferably within the range of the crystal growth conditions of the ZnO-based semiconductor layer 12.

As described above, the LED operation layer is grown on the ZnO-based semiconductor layer 12 having good flatness and single crystallinity under the growth conditions similar to those of the ZnO-based semiconductor layer 12, thereby obtaining a flat and excellent crystallinity LED. It is possible to form an operating layer. In the following, a case where Mg _x Zn _{(1-x) 2} O is used as the ZnO-based semiconductor will be described as an example.

  After growing the undoped ZnO-based semiconductor layer 12, the n-type ZnO-based semiconductor layer 21 was grown while maintaining the growth temperature and pressure (growth temperature 800 ° C., pressure 80 kPa). As described above, the undoped ZnO-based semiconductor layer 12 preferably has a layer thickness of at least 1.0 μm.

H ₂ O (water vapor) was kept at 640 μmol / min, and the DMZn flow rate was increased from 10 μmol / min to 30 μmol / min to grow a Ga-doped Mg _x Zn _(1-x) O crystal having a layer thickness of 3 μm. The flow rate of the Mg material gas (Cp2Mg) may be adjusted according to the Mg crystal composition x.

Further, since the conductivity type (n-type) _{control, Mg x Zn (1-x} ) simultaneously TEGa crystal growth of _{O Mg x Zn (1-x} ) concentration of O in the crystal 5 × ¹⁰ 18 ^{(cm -3} ).

Next, the DMZn flow rate was reduced to 1 μmol / min to grow an active layer 22 (Mg _x Zn _(1-x) O crystal) having a layer thickness of 30 nm. Here, the H ₂ O (water vapor) flow rate ratio (VI / II ratio) with respect to the DMZn flow rate was increased from 21 to 640 by reducing the flow rate of DMZn. Thereby, oxygen vacancies and the like in the growth layer can be reduced, so that high luminous efficiency can be obtained.

Next, the p-type ZnO-based semiconductor layer 23 was grown. Specifically, N (nitrogen) -doped Mg _x Zn _(1-x) O crystal having a layer thickness of 100 nm was grown at a DMZn flow rate of 1 μmol / min. Here, simultaneously with the crystal growth of Mg _x Zn _(1-x) O, NH ₃ (ammonia) is supplied as a p-type impurity material (dopant) at a flow rate of 180 μmol / min, and the nitrogen impurity concentration Na (N) = 8. Crystal growth was performed so as to be × 10 ¹⁹ (cm ⁻³ ).

  After the above steps were completed, the pressure of 80 kPa was maintained while flowing water vapor until the substrate temperature reached 300 ° C. After the substrate temperature became 300 ° C. or lower, the water vapor was stopped and the substrate was waited until the substrate temperature reached room temperature, and then taken out from the reaction vessel.

Incidentally, it has been described a case of using the _{Mg x Zn (1-x)} O crystals as n-type ZnO based semiconductor layer 21, active layer 22 and p-type ZnO based semiconductor layer 23. in this case,
n-type ZnO-based semiconductor layer 21: Mg _x Zn _{(1-x) 2} O (0 ≦ x ≦ 0.43),
p-type ZnO-based semiconductor layer 23: Mg _x Zn _{(1-x) 2} O (0 ≦ x ≦ 0.43),
Active layer 22: Mg _x Zn _(1-x) O / Mg _y Zn _(1-y) O
(0 ≦ (x, y) ≦ 0.43: y <x)
Can be used.

  Here, the Mg crystal composition x may be 0.63 or less if the layer thickness is about 0.5 μm or less, and 0.43 or less if the layer thickness is 0.5 μm or more. This is because MgO in the MgZnO crystal causes phase separation when the Mg composition increases.

  In addition, each of the n-type ZnO-based semiconductor layer 21, the active layer 22, and the p-type ZnO-based semiconductor layer 23 may have a multilayer structure in accordance with the light emitting element characteristics. Further, an MQW (Multi quantum well) structure may be adopted as the active layer 22. In particular, in the case of an MQW active layer, fluctuations in the layer thickness of the crystal layer (well layer, barrier layer) change the quantum level energy, quantum level density, etc., greatly affecting the emission wavelength, internal quantum efficiency, etc. Further, the effect of using the ZnO-based semiconductor layer 12 having excellent flatness and single crystallinity is further remarkable.

The board | substrate 25 with an LED operation layer manufactured at the said process was evaluated with the differential interference microscope and the scanning electron microscope (SEM). As a result, no irregularities and pits were observed on the surface, and it was confirmed that the surface was extremely flat from the macroscopic region to the microscopic region.
[Manufacture of semiconductor light emitting devices]
A semiconductor light emitting element (LED) is manufactured by the following steps using the substrate 25 with an LED operation layer manufactured in the above process. FIG. 10 is an element top view of the semiconductor light emitting element (LED) 30, and FIG. 11 is a cross-sectional view of the LED 30. FIG. 11 shows that two LEDs 30 and an element partitioning groove 32 for separating them by braking are formed.

  First, using a photolithography technique, a resist mask having a shape covering the region (element region) in the element section 31 was formed. Next, using wet etching, the p-type ZnO-based semiconductor layer 23, the active layer 22, and the n-type ZnO-based semiconductor layer 21 in the opening outside the element section 31 were partially removed to a predetermined depth. Finally, the resist was removed by washing, and element partition grooves 32 were formed.

  Since the surface of the substrate with LED operation layer 25 of the present invention is flat and mirror-like on the entire substrate (for example, a 2-inch substrate), the resist can be applied and formed with a uniform thickness. Further, since there is no unevenness on the surface, there is no exposure blur of the transfer pattern in the photolithography process, and transfer can be performed with high accuracy.

  Next, the p-side electrode 33 was formed using photolithography, EB (electron beam) deposition, or the like. The p-side electrode 33 is formed by depositing Ni (nickel) with a thickness of 0.3 to 10 nm and Au (gold) with a thickness of 5 to 20 nm, and using an RTA (rapid thermal annealer) in an oxygen 10% atmosphere. A translucent electrode was formed by treatment at 500 ° C. for 30 seconds.

  Next, a Ni / Pt / Au electrode pad material was laminated in this order with a thickness of 3 to 10 nm / 100 nm / 1000 nm on the p-side electrode 33 by EB vapor deposition to form a p-side connection electrode 34.

  Further, by using photolithography, Ti / Au was laminated on the exposed surface of the n-type ZnO-based semiconductor layer 21 in this order by EB deposition in a thickness of 10 to 100 nm / 1000 nm, respectively, to form the n-side connection electrode 35. .

  After the electrodes were formed in this way, the LED operation layer side was attached to a protective substrate, the back side was ground and polished, and formed into a 100 μm thick wafer. Next, after a protective sheet was pasted on the surface side on which the electrodes were formed, a scribe groove 36 perpendicular to each other was formed on the back surface corresponding to the central portion of the element partition groove 32 using a scribe device.

  In braking, the knife edge 37 was applied from the element partitioning groove 32 side of the opposing surface of the scribe groove 36, loaded with the knife edge 37, and cleaved in the scribe groove direction. Similarly, the substrate was rotated 90 ° and cleaved in the direction of the scribe groove 36 perpendicular to the substrate.

  Since the surface of the substrate with LED operation layer 25 of the present invention has no unevenness, the bottom of the element partition groove 32 can be formed extremely flat, and the bottom surface of the partition groove can be accurately pressed by the knife edge 37. Accordingly, since stress is applied evenly during the pressure cleavage, the occurrence of cleavage failure due to chipping of the element sections, displacement of the cleavage surface, etc. can be reduced, and the cleavage yield is improved. In addition, there were no potential crystal grain boundaries (domains) existing in the crystal plane, chipping of the crystal layer originating from the grain boundaries was reduced during cleavage, and the separation yield was improved.

  When the element was formed using the substrate 25 with LED operation layer of the present invention, the yield of resist pattern formation was about 98%. Also, the cleavage yield was very good, about 98%.

  As described above, the LED operation layer is grown on the ZnO-based semiconductor layer 12 on which a high-quality single crystal layer with few crystal defects and excellent single crystallinity and flatness is formed. It is possible to form a high-performance LED that can form an excellent LED operating layer, has high emission efficiency with suppressed leakage current and current concentration, and has excellent device life. In addition, high process accuracy can be obtained in lithography and etching semiconductor processes, and the manufacturing yield in cleavage and braking is also high.

  In the above-described embodiments, the case where the present invention is applied to a semiconductor light emitting element (LED) has been described as an example, but the present invention is not limited thereto. For example, the present invention can be applied to an optical semiconductor element and an electronic device that can be formed using a ZnO-based semiconductor layer, such as a semiconductor laser (LD), a surface acoustic wave device, or a MOSFET.

As described above in detail, according to the present invention, H ₂ having high reactivity between an organometallic compound material not containing oxygen and the organometallic compound material on a different material substrate such as an A-plane sapphire substrate. Using O (water vapor), crystal growth can be performed at a low growth temperature and a low growth pressure, and a zinc oxide single crystal layer (first single crystal layer) can be grown. Further, the single crystallinity and flatness of the growth layer can be further improved by performing the heat treatment under a low pressure (reduced pressure) and in a water vapor atmosphere. The single crystal layer is excellent in flatness and single crystallinity and has few crystal defects. Furthermore, since the MOCVD method is used, large area growth and large number growth are possible. Therefore, it is excellent in mass productivity and manufacturing cost.

  In addition, a ZnO-based compound semiconductor layer having higher flatness and crystallinity can be grown on the ZnO layer (first single crystal layer) 11 having excellent flatness and single crystallinity. The ZnO-based compound semiconductor layer (second single crystal layer) 12 can be grown so as to have not only high flatness and crystallinity but also a layer thickness sufficient for application to device manufacturing. Therefore, an LED light emitting operation layer, a cladding layer in a semiconductor laser element, an element layer of an electronic device, and the like can be directly grown on the ZnO-based semiconductor layer 12.

  By growing an LED operation layer on the ZnO-based semiconductor layer 12, an LED operation layer that is flat and excellent in crystallinity can be formed, and the light emission efficiency with high leakage current and current concentration is suppressed, and the output is high. High performance LED can be provided. Furthermore, it is possible to manufacture an LED having an excellent element lifetime. Furthermore, high accuracy can be obtained also in the semiconductor process, and the manufacturing yield in cleavage and braking is also high.

It is sectional drawing which shows the low growth temperature crystal layer and ZnO-type semiconductor layer which were grown on the board | substrate by this invention. It is a figure which shows the crystal growth sequence used for the crystal growth by MOCVD method. It is a figure which shows the RHEED diffraction image when not heat-processing after the growth of a ZnO layer, and when heat-processing is performed. It is a figure which shows the half value width (FWHM) of the X-ray diffraction (10-10) omega rocking curve with respect to the growth pressure of a ZnO layer (2nd single crystal layer). It is a figure which shows the half value width (FWHM) of the X-ray diffraction (10-10) omega rocking curve with respect to the growth temperature of a ZnO layer (2nd single crystal layer). It is a figure which shows the half value width (FWHM) of a X-ray diffraction (0002) (omega) rocking curve with respect to the growth layer thickness of a ZnO type semiconductor layer (high temperature growth single crystal layer). Scanning electron microscope (SEM) images of the ZnO layer (second single crystal layer) surface (growth layer thickness 1.0 μm) are shown for growth pressures of 10 kPa ((a)) and 80 kPa ((b)). FIG. It is a figure which shows typically the growth start method of a ZnO type semiconductor layer (high temperature growth single crystal layer). It is a figure which shows typically the cross-sectional view of the semiconductor light-emitting device structure grown on the board | substrate by this invention. It is an element top view of a semiconductor light emitting element (LED). It is sectional drawing of a semiconductor light emitting element (LED).

Explanation of symbols

10 Substrate 11 ZnO layer (low temperature growth single crystal layer)
12 ZnO-based semiconductor layer (high temperature grown single crystal layer)
15 substrate with crystal growth layer 20 LED operation layer 21 n-type semiconductor layer 22 active layer 23 p-type semiconductor layer 25 substrate with LED operation layer

Claims (15)

A method for crystal growth of a zinc oxide based semiconductor layer on a substrate by MOCVD,
Using oxygen-free organometallic compound and water vapor,
(A) performing crystal growth at a temperature within a range of 250 ° C. to 450 ° C. and a low growth pressure within a range of 1 kPa to 30 kPa to form a first single crystal layer;
(B) performing crystal growth at a temperature in the range of 700 ° C. to 850 ° C. and higher than the low growth pressure to form a second single crystal layer on the first single crystal layer;
A method characterized by comprising:   The method according to claim 1, wherein the pressure higher than the low growth pressure is a pressure within a range of 40 kPa to 120 kPa.   2. The method according to claim 1, wherein the step of forming the second single crystal layer includes performing a heat treatment of the first single crystal layer prior to the growth of the second single crystal layer. The substrate is α- sapphire single crystal, the method according to any one of claims 1 to 3, wherein the crystal growth surface is {11-20} plane. The first single crystal layer is a zinc oxide (ZnO) layer, and the second single crystal layer is a Mg _x Zn _{(1-x) 2} O (0 ≦ x ≦ 0.43) layer. The method according to any one of claims 1 to 4 . The thickness of the first single crystal layer method according to any one of claims 1 to 5, characterized in that in the range of 5 nm to 60 nm. The method according to any one of claims 1 to 6, characterized in that the layer thickness of the second single crystal layer is 1.5μm or more. The method according to claim 6 , wherein the growth rate of the first single crystal layer is 9 nm / min or less. The method according to claim 7 , wherein the growth rate of the second single crystal layer is 60 nm / min or less. The second step of forming a single crystal layer, the method according to any one of claims 5 to 9, characterized in that doping impurities after the growth layer thickness exceeds 1 [mu] m. The substrate according to any one of claims 1 to 3 , and 5 to 9 , wherein the substrate is any one of sapphire, gallium oxide (Ga ₂ O ₃ ), silicon carbide (SiC), gallium nitride (GaN), and a silicon substrate. The method according to any one of the above. A method of manufacturing a semiconductor light emitting device by stacking a zinc oxide based semiconductor layer on a substrate by MOCVD,
Using oxygen-free organometallic compound and water vapor,
(A) performing crystal growth at a temperature within a range of 250 ° C. to 450 ° C. and a low growth pressure within a range of 1 kPa to 30 kPa to form a first single crystal layer;
(B) performing crystal growth at a temperature in the range of 700 ° C. to 850 ° C. and higher than the low growth pressure to form a second single crystal layer on the first single crystal layer;
(C) forming a light emitting layer on the second single crystal layer by performing crystal growth at a temperature within a range of 700 ° C. to 850 ° C. and higher than the low growth pressure;
A method characterized by comprising: The method according to claim 12 , wherein the pressure higher than the low growth pressure is a pressure within a range of 40 kPa to 120 kPa. 14. The method according to claim 12, wherein the second single crystal layer includes an undoped layer having a layer thickness of at least 1.0 [mu] m formed on the first single crystal layer. The substrate is an A-plane sapphire substrate, and the first single crystal layer and the second single crystal layer are Mg _x Zn _(1-x) O (0 ≦ x ≦ 0.43) layers. 15. A method according to any one of claims 12 to 14 , characterized in that: